https://github.com/rust-lang/rust http://git.dreamy.place/mirrors/rust/atom?h=perf-tmp 2025-09-22T14:35:46+00:00 2025-09-22T14:35:46+00:00 bors bors@rust-lang.org 2025-09-22T14:35:46+00:00 urn:sha1:ce4beebecb77821734079cff47d8af08f9f27f11 Mark float intrinsics with no preconditions as safe Note: for ease of reviewing, the list of safe intrinsics is sorted in the first commit, and then safe intrinsics are added in the second commit. All *recently added* float intrinsics have been correctly marked as safe to call due to the fact that they have no preconditions. This adds the remaining float intrinsics which are safe to call to the safe intrinsic list, and removes the unsafe blocks around their calls. --- Side note: this may want a try run before being added to the queue, since I'm not sure if there's any tier-2 code that uses these intrinsics that might not be tested on the usual PR flow. We've already uncovered a few places in subtrees that do this, and it's worth double-checking before clogging up the queue. 2025-09-22T00:37:51+00:00 ltdk usr@ltdk.xyz 2025-09-17T18:07:23+00:00 urn:sha1:055e05a338af00751ffccc992feeda227b8436b1 2025-09-15T18:39:49+00:00 Sayantan Chakraborty 142906350+sayantn@users.noreply.github.com 2025-09-15T18:39:49+00:00 urn:sha1:c1242fab74e942ff252da5d6b8ccadc5f4af1208 RISC-V: Improvements of inline assembly uses 2025-09-15T08:18:20+00:00 Folkert de Vries flokkievids@gmail.com 2025-09-15T08:18:20+00:00 urn:sha1:5dd0fdcd67b3c938dbf010f97e5a1d0ff656d13d Remove big-endian swizzles from `vreinterpret` 2025-09-14T05:08:19+00:00 Tsukasa OI floss_rust@irq.a4lg.com 2025-09-13T21:59:39+00:00 urn:sha1:8df078a3f0071b311be2449407ae523f89ca6a33 This commit performs various improvements (better register allocation, less register clobbering on the worst case and better readability) of RISC-V inline assembly use cases. Note that it does not change the `p` module (which defines the "P" extension draft instructions but very likely to change). 1. Use `lateout` as possible. Unlike `out(reg)` and `in(reg)` pair, `lateout(reg)` and `in(reg)` can share the same register because they state that the late-output register is written after all the reads are performed. It can improve register allocation. 2. Add `preserves_flags` option as possible. While RISC-V doesn't have _regular_ condition codes, RISC-V inline assembly in the Rust language assumes that some registers (mainly vector state registers) may be overwritten by default. By adding `preserves_flags` to the intrinsics corresponding instructions without overwriting them, it can minimize register clobbering on the worst case. 3. Use trailing semicolon. As `asm!` declares an action and it doesn't return a value by itself, it would be better to have trailing semicolon to denote that an `asm!` call is effectively a statement. 4. Make most of `asm!` calls multi-lined. `rustfmt` makes some simple (yet long) `asm!` calls multi-lined but it does not perform formatting of complex `asm!` calls with inputs and/or outputs. To keep consistency, it makes most of the `asm!` calls multi-lined. 2025-09-12T11:51:38+00:00 Tsukasa OI floss_rust@irq.a4lg.com 2025-09-12T11:51:38+00:00 urn:sha1:05133f2115940aa581df8831031ea77c2c7c99c8 2025-09-12T11:50:51+00:00 Tsukasa OI floss_rust@irq.a4lg.com 2025-09-12T11:50:51+00:00 urn:sha1:a3b7aad20f6ff2a4af0e96c543ac300650c97d5e 2025-09-12T11:50:25+00:00 Tsukasa OI floss_rust@irq.a4lg.com 2025-09-12T11:50:25+00:00 urn:sha1:221eb1f0d51a97ec6ccb67427635370797d37225 2025-09-11T19:59:18+00:00 Sayantan Chakraborty 142906350+sayantn@users.noreply.github.com 2025-09-11T19:59:18+00:00 urn:sha1:269cecc91c2d8d37213a5a015513d584e0af7283 RISC-V: "Lower" requirements of `aes64im` 2025-09-11T19:50:34+00:00 sayantn sayantn05@gmail.com 2025-09-11T19:50:34+00:00 urn:sha1:bb31725e679c48e75e54c8ec88c7e654c5509d37