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<title>rust/src/rustllvm/PassWrapper.cpp, branch 1.22.0</title>
<subtitle>https://github.com/rust-lang/rust
</subtitle>
<id>http://git.dreamy.place/mirrors/rust/atom?h=1.22.0</id>
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<updated>2017-10-07T15:17:52+00:00</updated>
<entry>
<title>rustc: Implement ThinLTO</title>
<updated>2017-10-07T15:17:52+00:00</updated>
<author>
<name>Alex Crichton</name>
<email>alex@alexcrichton.com</email>
</author>
<published>2017-07-23T15:14:38+00:00</published>
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<id>urn:sha1:4ca1b19fde0c4fcdeba24a8e6135577e86c69f49</id>
<content type='text'>
This commit is an implementation of LLVM's ThinLTO for consumption in rustc
itself. Currently today LTO works by merging all relevant LLVM modules into one
and then running optimization passes. "Thin" LTO operates differently by having
more sharded work and allowing parallelism opportunities between optimizing
codegen units. Further down the road Thin LTO also allows *incremental* LTO
which should enable even faster release builds without compromising on the
performance we have today.

This commit uses a `-Z thinlto` flag to gate whether ThinLTO is enabled. It then
also implements two forms of ThinLTO:

* In one mode we'll *only* perform ThinLTO over the codegen units produced in a
  single compilation. That is, we won't load upstream rlibs, but we'll instead
  just perform ThinLTO amongst all codegen units produced by the compiler for
  the local crate. This is intended to emulate a desired end point where we have
  codegen units turned on by default for all crates and ThinLTO allows us to do
  this without performance loss.

* In anther mode, like full LTO today, we'll optimize all upstream dependencies
  in "thin" mode. Unlike today, however, this LTO step is fully parallelized so
  should finish much more quickly.

There's a good bit of comments about what the implementation is doing and where
it came from, but the tl;dr; is that currently most of the support here is
copied from upstream LLVM. This code duplication is done for a number of
reasons:

* Controlling parallelism means we can use the existing jobserver support to
  avoid overloading machines.
* We will likely want a slightly different form of incremental caching which
  integrates with our own incremental strategy, but this is yet to be
  determined.
* This buys us some flexibility about when/where we run ThinLTO, as well as
  having it tailored to fit our needs for the time being.
* Finally this allows us to reuse some artifacts such as our `TargetMachine`
  creation, where all our options we used today aren't necessarily supported by
  upstream LLVM yet.

My hope is that we can get some experience with this copy/paste in tree and then
eventually upstream some work to LLVM itself to avoid the duplication while
still ensuring our needs are met. Otherwise I fear that maintaining these
bindings may be quite costly over the years with LLVM updates!
</content>
</entry>
<entry>
<title>Add 'native' to -C target-cpu=help</title>
<updated>2017-09-15T05:32:59+00:00</updated>
<author>
<name>Matt Ickstadt</name>
<email>mattico8@gmail.com</email>
</author>
<published>2017-09-08T01:07:16+00:00</published>
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<id>urn:sha1:824fb3817c0cbcb3a31a705d02a77219c8331608</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Fix covered-switch-default warnings in PassWrapper</title>
<updated>2017-08-08T08:17:33+00:00</updated>
<author>
<name>kennytm</name>
<email>kennytm@gmail.com</email>
</author>
<published>2017-08-08T08:17:33+00:00</published>
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<id>urn:sha1:15e8b0fd3decd6c3ceca1986a422ac5a8fc640f2</id>
<content type='text'>
(See #39063 for explanation)
</content>
</entry>
<entry>
<title>Gate LLVMRustHasFeature on LLVM_RUSTLLVM</title>
<updated>2017-08-01T01:10:01+00:00</updated>
<author>
<name>Josh Stone</name>
<email>jistone@redhat.com</email>
</author>
<published>2017-08-01T01:10:01+00:00</published>
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<id>urn:sha1:881a7246606cb6ced8ba63a8d58b7e54fed90b7c</id>
<content type='text'>
Commit c4710203c098b in #43492 make `LLVMRustHasFeature` "more robust"
by using `getFeatureTable()`.  However, this function is specific to
Rust's own LLVM fork, not upstream LLVM-4.0, so we need to use
`#if LLVM_RUSTLLVM` to guard this call.
</content>
</entry>
<entry>
<title>Make LLVMRustHasFeature more robust</title>
<updated>2017-07-28T14:30:06+00:00</updated>
<author>
<name>Luca Barbato</name>
<email>lu_zero@gentoo.org</email>
</author>
<published>2017-07-28T02:03:23+00:00</published>
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<id>urn:sha1:c4710203c098b68b5f80b1507e889ad894855729</id>
<content type='text'>
The function should accept feature strings that old LLVM might not
support.

Simplify the code using the same approach used by
LLVMRustPrintTargetFeatures.

Dummify the function for non 4.0 LLVM and update the tests accordingly.
</content>
</entry>
<entry>
<title>When writing LLVM IR output demangled fn name in comments</title>
<updated>2017-07-01T00:16:43+00:00</updated>
<author>
<name>Stepan Koltsov</name>
<email>stepan.koltsov@gmail.com</email>
</author>
<published>2017-06-29T14:52:43+00:00</published>
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<id>urn:sha1:b62bdaafe038b8933fac5df5fa0fa5ddbaf176b7</id>
<content type='text'>
`--emit=llvm-ir` looks like this now:

```
; &lt;alloc::vec::Vec&lt;T&gt; as core::ops::index::IndexMut&lt;core::ops::range::RangeFull&gt;&gt;::index_mut
; Function Attrs: inlinehint uwtable
define internal { i8*, i64 } @"_ZN106_$LT$alloc..vec..Vec$LT$T$GT$$u20$as$u20$core..ops..index..IndexMut$LT$core..ops..range..RangeFull$GT$$GT$9index_mut17h7f7b576609f30262E"(%"alloc::vec::Vec&lt;u8&gt;"* dereferenceable(24)) unnamed_addr #0 {
start:
  ...
```

cc https://github.com/integer32llc/rust-playground/issues/15
</content>
</entry>
<entry>
<title>Auto merge of #41560 - alevy:rwpi-ropi, r=eddyb</title>
<updated>2017-05-01T17:23:09+00:00</updated>
<author>
<name>bors</name>
<email>bors@rust-lang.org</email>
</author>
<published>2017-05-01T17:23:09+00:00</published>
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<id>urn:sha1:4cb396c68088f38e517ac8890030d17a969e57ba</id>
<content type='text'>
Add RWPI/ROPI relocation model support

This PR adds support for using LLVM 4's ROPI and RWPI relocation models for ARM.

ROPI (Read-Only Position Independence) and RWPI (Read-Write Position Independence) are two new relocation models in LLVM for the ARM backend ([LLVM changset](https://reviews.llvm.org/rL278015)). The motivation is that these are the specific strategies we use in userspace [Tock](https://www.tockos.org) apps, so supporting this is an important step (perhaps the final step, but can't confirm yet) in enabling userspace Rust processes.

## Explanation

ROPI makes all code and immutable accesses PC relative, but not assumed to be overriden at runtime (so for example, jumps are always relative).

RWPI uses a base register (`r9`) that stores the addresses of the GOT in memory so the runtime (e.g. a kernel) only adjusts r9 tell running code where the GOT is.

## Complications adding support in Rust

While this landed in LLVM master back in August, the header files in `llvm-c` have not been updated yet to reflect it. Rust replicates that header file's version of the `LLVMRelocMode` enum as the Rust enum `llvm::RelocMode` and uses an implicit cast in the ffi to translate from Rust's notion of the relocation model to the LLVM library's notion.

My workaround for this currently is to replace the `LLVMRelocMode` argument to `LLVMTargetMachineRef` with an int and using the hardcoded int representation of the `RelocMode` enum. This is A Bad Idea(tm), but I think very nearly the right thing.

Would a better alternative be to patch rust-llvm to support these enum variants (also a fairly trivial change)?
</content>
</entry>
<entry>
<title>Added LLVMRustRelocMode</title>
<updated>2017-04-28T22:33:56+00:00</updated>
<author>
<name>Amit Aryeh Levy</name>
<email>amit@amitlevy.com</email>
</author>
<published>2017-04-28T22:21:59+00:00</published>
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<id>urn:sha1:0f00f27e0d4743b14f7c0d0fca9731a45eae487a</id>
<content type='text'>
Replaces the llvm-c exposed LLVMRelocMode, which does not include all
relocation model variants, with a LLVMRustRelocMode modeled after
LLVMRustCodeMode.
</content>
</entry>
<entry>
<title>Add RWPI/ROPI relocation model support</title>
<updated>2017-04-26T20:25:14+00:00</updated>
<author>
<name>Amit Aryeh Levy</name>
<email>amit@amitlevy.com</email>
</author>
<published>2017-04-26T00:05:51+00:00</published>
<link rel='alternate' type='text/html' href='http://git.dreamy.place/mirrors/rust/commit/?id=32b92669e4ec83005eff2641b092f25be09373b8'/>
<id>urn:sha1:32b92669e4ec83005eff2641b092f25be09373b8</id>
<content type='text'>
Adds support for using LLVM 4's ROPI and RWPI relocation models for ARM
</content>
</entry>
<entry>
<title>Add Hexagon support</title>
<updated>2017-04-25T05:56:44+00:00</updated>
<author>
<name>Michael Wu</name>
<email>mwu.code@gmail.com</email>
</author>
<published>2017-04-09T06:03:31+00:00</published>
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<id>urn:sha1:c558a2ae37052dc1f12aa4e40578eb4ae9aca3b9</id>
<content type='text'>
This requires an updated LLVM with D31999 and D32000 to build libcore.

A basic hello world builds and runs successfully on the hexagon simulator.
</content>
</entry>
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