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<title>rust/src/rustllvm/RustWrapper.cpp, branch 1.9.0</title>
<subtitle>https://github.com/rust-lang/rust
</subtitle>
<id>http://git.dreamy.place/mirrors/rust/atom?h=1.9.0</id>
<link rel='self' href='http://git.dreamy.place/mirrors/rust/atom?h=1.9.0'/>
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<updated>2016-03-29T14:44:54+00:00</updated>
<entry>
<title>Use weak_odr linkage when reusing definitions across codegen units</title>
<updated>2016-03-29T14:44:54+00:00</updated>
<author>
<name>Björn Steinbrink</name>
<email>bsteinbr@gmail.com</email>
</author>
<published>2016-03-28T15:57:31+00:00</published>
<link rel='alternate' type='text/html' href='http://git.dreamy.place/mirrors/rust/commit/?id=22f458758652d309b7c65fa904d44f090214456c'/>
<id>urn:sha1:22f458758652d309b7c65fa904d44f090214456c</id>
<content type='text'>
When reuing a definition across codegen units, we obviously cannot use
internal linkage, but using external linkage means that we can end up
with multiple conflicting definitions of a single symbol across
multiple crates. Since the definitions should all be equal
semantically, we can use weak_odr linkage to resolve the situation.

Fixes #32518
</content>
</entry>
<entry>
<title>Fix removal of function attributes on ARM</title>
<updated>2016-03-26T12:02:54+00:00</updated>
<author>
<name>Björn Steinbrink</name>
<email>bsteinbr@gmail.com</email>
</author>
<published>2016-03-26T11:27:33+00:00</published>
<link rel='alternate' type='text/html' href='http://git.dreamy.place/mirrors/rust/commit/?id=95697a83955c03d42eaaac6ecedcae04bd6986c9'/>
<id>urn:sha1:95697a83955c03d42eaaac6ecedcae04bd6986c9</id>
<content type='text'>
We use a 64bit integer to pass the set of attributes that is to be
removed, but the called C function expects a 32bit integer. On most
platforms this doesn't cause any problems other than being unable to
unset some attributes, but on  ARM even the lower 32bit aren't handled
correctly because the 64bit value is passed in different registers, so
the C function actually sees random garbage.

So we need to fix the relevant functions to use 32bit integers instead.
Additionally we need an implementation that actually accepts 64bit
integers because some attributes can only be unset that way.

Fixes #32360
</content>
</entry>
<entry>
<title>Fix LLVMRustSetHasUnsafeAlgebra to only have effect on instructions</title>
<updated>2016-03-19T21:35:28+00:00</updated>
<author>
<name>Ulrik Sverdrup</name>
<email>bluss@users.noreply.github.com</email>
</author>
<published>2016-03-19T21:02:33+00:00</published>
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<id>urn:sha1:e22d6d569fcbcf960261d71f67d554a7859fdfeb</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Add intrinsics for float arithmetic with `fast` flag enabled</title>
<updated>2016-03-18T16:31:41+00:00</updated>
<author>
<name>Ulrik Sverdrup</name>
<email>bluss@users.noreply.github.com</email>
</author>
<published>2016-03-14T23:01:12+00:00</published>
<link rel='alternate' type='text/html' href='http://git.dreamy.place/mirrors/rust/commit/?id=2dbac1fb8ed43cbcd160855803d50a51c38b8cee'/>
<id>urn:sha1:2dbac1fb8ed43cbcd160855803d50a51c38b8cee</id>
<content type='text'>
`fast` a.k.a UnsafeAlgebra is the flag for enabling all "unsafe"
(according to llvm) float optimizations.

See LangRef for more information http://llvm.org/docs/LangRef.html#fast-math-flags

Providing these operations with less precise associativity rules (for
example) is useful to numerical applications.

For example, the summation loop:

    let sum = 0.;
    for element in data {
        sum += *element;
    }

Using the default floating point semantics, this loop expresses the
floats must be added in a sequence, one after another. This constraint
is usually completely unintended, and it means that no autovectorization
is possible.
</content>
</entry>
<entry>
<title>Implement filling drop in MIR</title>
<updated>2016-02-24T19:05:21+00:00</updated>
<author>
<name>Simonas Kazlauskas</name>
<email>git@kazlauskas.me</email>
</author>
<published>2016-02-04T17:40:28+00:00</published>
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<id>urn:sha1:ba26efb60c9e11ab058a1c31b9816147c55ab417</id>
<content type='text'>
Hopefully the author caught all the cases. For the mir_dynamic_drops_3 test case the ratio of
memsets to other instructions is 12%. On the other hand we actually do not double drop for at least
the test cases provided anymore in MIR.
</content>
</entry>
<entry>
<title>Add intrinsics for compare_exchange and compare_exchange_weak</title>
<updated>2016-02-18T19:07:05+00:00</updated>
<author>
<name>Amanieu d'Antras</name>
<email>amanieu@gmail.com</email>
</author>
<published>2016-01-16T23:40:11+00:00</published>
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<id>urn:sha1:64ddcb33f431be554449116706eb0d6af2666a11</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Auto merge of #30962 - Amanieu:non_volatile_atomic, r=alexcrichton</title>
<updated>2016-02-04T02:46:44+00:00</updated>
<author>
<name>bors</name>
<email>bors@rust-lang.org</email>
</author>
<published>2016-02-04T02:46:44+00:00</published>
<link rel='alternate' type='text/html' href='http://git.dreamy.place/mirrors/rust/commit/?id=1096e7ab7afb14257798da82a1dd6aeadcb30100'/>
<id>urn:sha1:1096e7ab7afb14257798da82a1dd6aeadcb30100</id>
<content type='text'>
Rust currently emits atomic loads and stores with the LLVM `volatile` qualifier. This is unnecessary and prevents LLVM from performing optimization on these atomic operations.
</content>
</entry>
<entry>
<title>trans: Reimplement unwinding on MSVC</title>
<updated>2016-01-30T00:25:20+00:00</updated>
<author>
<name>Alex Crichton</name>
<email>alex@alexcrichton.com</email>
</author>
<published>2015-10-24T01:18:44+00:00</published>
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<id>urn:sha1:3e9589c0f43af69544b042f50b886005613540f2</id>
<content type='text'>
This commit transitions the compiler to using the new exception handling
instructions in LLVM for implementing unwinding for MSVC. This affects both 32
and 64-bit MSVC as they're both now using SEH-based strategies. In terms of
standard library support, lots more details about how SEH unwinding is
implemented can be found in the commits.

In terms of trans, this change necessitated a few modifications:

* Branches were added to detect when the old landingpad instruction is used or
  the new cleanuppad instruction is used to `trans::cleanup`.
* The return value from `cleanuppad` is not stored in an `alloca` (because it
  cannot be).
* Each block in trans now has an `Option&lt;LandingPad&gt;` instead of `is_lpad: bool`
  for indicating whether it's in a landing pad or not. The new exception
  handling intrinsics require that on MSVC each `call` inside of a landing pad
  is annotated with which landing pad that it's in. This change to the basic
  block means that whenever a `call` or `invoke` instruction is generated we
  know whether to annotate it as part of a cleanuppad or not.
* Lots of modifications were made to the instruction builders to construct the
  new instructions as well as pass the tagging information for the call/invoke
  instructions.
* The translation of the `try` intrinsics for MSVC has been overhauled to use
  the new `catchpad` instruction. The filter function is now also a
  rustc-generated function instead of a purely libstd-defined function. The
  libstd definition still exists, it just has a stable ABI across architectures
  and leaves some of the really weird implementation details to the compiler
  (e.g. the `localescape` and `localrecover` intrinsics).
</content>
</entry>
<entry>
<title>trans: Upgrade LLVM</title>
<updated>2016-01-30T00:25:20+00:00</updated>
<author>
<name>Alex Crichton</name>
<email>alex@alexcrichton.com</email>
</author>
<published>2015-10-23T05:07:19+00:00</published>
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<id>urn:sha1:d1cace17af31ddb21aeb8a3d94cb3eda934047d9</id>
<content type='text'>
This brings some routine upgrades to the bundled LLVM that we're using, the most
notable of which is a bug fix to the way we handle range asserts when loading
the discriminant of an enum. This fix ended up being very similar to f9d4149c
where we basically can't have a range assert when loading a discriminant due to
filling drop, and appropriate flags were added to communicate this to
`trans::adt`.
</content>
</entry>
<entry>
<title>Don't make atomic loads and stores volatile</title>
<updated>2016-01-16T20:16:10+00:00</updated>
<author>
<name>Amanieu d'Antras</name>
<email>amanieu@gmail.com</email>
</author>
<published>2016-01-16T20:16:10+00:00</published>
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<id>urn:sha1:01112d1ac496b3e8cf63459a6647b66baa8b5a26</id>
<content type='text'>
</content>
</entry>
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