https://github.com/rust-lang/rust http://git.dreamy.place/mirrors/rust/atom?h=automation/bors/try 2025-09-22T10:25:14+00:00 2025-09-22T10:25:14+00:00 Stuart Cook Zalathar@users.noreply.github.com 2025-09-22T10:25:14+00:00 urn:sha1:46be365a602495076171adeb603a682079e6c2eb Support ctr and lr as clobber-only registers in PowerPC inline assembly Follow-up to rust-lang/rust#131341. CTR and LR are marked as volatile in all ABIs, but I skipped them in rust-lang/rust#131341 due to they are currently marked as reserved. https://github.com/rust-lang/rust/blob/dd7fda570040e8a736f7d8bc28ddd1b444aabc82/compiler/rustc_target/src/asm/powerpc.rs#L209-L212 However, they are actually only unusable as input/output of inline assembly, and should be fine to support as clobber-only registers as discussed in [#t-compiler > ppc/ppc64 inline asm support](https://rust-lang.zulipchat.com/#narrow/channel/131828-t-compiler/topic/ppc.2Fppc64.20inline.20asm.20support/with/540413845). r? ````@Amanieu```` or ````@workingjubilee```` cc ````@programmerjake```` ````@rustbot```` label +O-PowerPC +A-inline-assembly 2025-09-21T19:16:06+00:00 Folkert de Vries folkert@folkertdev.nl 2025-09-19T18:39:47+00:00 urn:sha1:3565b0699d6830dc31732afa96272bcbd1f83606 2025-09-21T04:48:22+00:00 Taiki Endo te316e89@gmail.com 2025-09-21T04:48:22+00:00 urn:sha1:f4b876867d609404be8a78220c0d5117303bb0f8 2025-09-15T02:16:34+00:00 Tsukasa OI floss_rust@irq.a4lg.com 2025-09-15T02:16:34+00:00 urn:sha1:5ebdec5ac2908b0bae42adbe451beeadbe8fa5de Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register in the reference, it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it. 2025-07-22T12:28:48+00:00 Guillaume Gomez guillaume1.gomez@gmail.com 2025-07-21T12:34:12+00:00 urn:sha1:a27f3e3fd1e4d16160f8885b6b06665b5319f56c