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| author | Simon Sapin <simon.sapin@exyr.org> | 2022-06-21 12:31:42 +0200 |
|---|---|---|
| committer | Simon Sapin <simon.sapin@exyr.org> | 2022-06-21 12:31:42 +0200 |
| commit | 20bd0c377163f384ae66943674ed2e397dd1c73a (patch) | |
| tree | 89c7d2a6247411337973251c0800dee07672864e | |
| parent | abace0a1f17986d89aedf610819deab2b4afee56 (diff) | |
| download | rust-20bd0c377163f384ae66943674ed2e397dd1c73a.tar.gz rust-20bd0c377163f384ae66943674ed2e397dd1c73a.zip | |
Re-enable atomic loads and stores for all RISC-V targets
This roughly reverts PR https://github.com/rust-lang/rust/pull/66548 Atomic "CAS" are still disabled for targets without the *“A” Standard Extension for Atomic Instructions*. However this extension only adds instructions for operations more complex than simple loads and stores, which are always atomic when aligned. In the [Unprivileged Spec v. 20191213](https://riscv.org/technical/specifications/) section 2.6 *Load and Store Instructions* of chapter 2 *RV32I Base Integer Instruction Set* (emphasis mine): > Even when misaligned loads and stores complete successfully, > these accesses might run extremely slowly depending on the implementation > (e.g., when implemented via an invisible trap). Further-more, whereas > **naturally aligned loads and stores are guaranteed to execute atomically**, > misaligned loads and stores might not, and hence require > additional synchronization to ensure atomicity. Unfortunately PR https://github.com/rust-lang/rust/pull/66548 did not provide much details on the bug that motivated it, but https://github.com/rust-lang/rust/issues/66240 and https://github.com/rust-lang/rust/issues/85736 appear related and happen with targets that do have the A extension.
3 files changed, 3 insertions, 3 deletions
diff --git a/compiler/rustc_target/src/spec/riscv32i_unknown_none_elf.rs b/compiler/rustc_target/src/spec/riscv32i_unknown_none_elf.rs index 7124e2df9b3..c07029a4be7 100644 --- a/compiler/rustc_target/src/spec/riscv32i_unknown_none_elf.rs +++ b/compiler/rustc_target/src/spec/riscv32i_unknown_none_elf.rs @@ -12,7 +12,7 @@ pub fn target() -> Target { linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld), linker: Some("rust-lld".into()), cpu: "generic-rv32".into(), - max_atomic_width: Some(0), + max_atomic_width: Some(32), atomic_cas: false, executables: true, panic_strategy: PanicStrategy::Abort, diff --git a/compiler/rustc_target/src/spec/riscv32im_unknown_none_elf.rs b/compiler/rustc_target/src/spec/riscv32im_unknown_none_elf.rs index 508982eed68..849acf29b9b 100644 --- a/compiler/rustc_target/src/spec/riscv32im_unknown_none_elf.rs +++ b/compiler/rustc_target/src/spec/riscv32im_unknown_none_elf.rs @@ -12,7 +12,7 @@ pub fn target() -> Target { linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld), linker: Some("rust-lld".into()), cpu: "generic-rv32".into(), - max_atomic_width: Some(0), + max_atomic_width: Some(32), atomic_cas: false, features: "+m".into(), executables: true, diff --git a/compiler/rustc_target/src/spec/riscv32imc_unknown_none_elf.rs b/compiler/rustc_target/src/spec/riscv32imc_unknown_none_elf.rs index 4216968cb77..c88b8592d45 100644 --- a/compiler/rustc_target/src/spec/riscv32imc_unknown_none_elf.rs +++ b/compiler/rustc_target/src/spec/riscv32imc_unknown_none_elf.rs @@ -12,7 +12,7 @@ pub fn target() -> Target { linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld), linker: Some("rust-lld".into()), cpu: "generic-rv32".into(), - max_atomic_width: Some(0), + max_atomic_width: Some(32), atomic_cas: false, features: "+m,+c".into(), executables: true, |