Fix interleave/deinterleave for vectors with only one lane

2 files changed, 24 insertions, 2 deletions

diff --git a/crates/core_simd/src/swizzle.rs b/crates/core_simd/src/swizzle.rs
index 22999d24950..02567252a63 100644
--- a/crates/core_simd/src/swizzle.rs
+++ b/crates/core_simd/src/swizzle.rs
@@ -325,7 +325,11 @@ where
             const INDEX: [Which; LANES] = hi::<LANES>();
         }
 
-        (Lo::swizzle2(self, other), Hi::swizzle2(self, other))
+        if LANES == 1 {
+            (self, other)
+        } else {
+            (Lo::swizzle2(self, other), Hi::swizzle2(self, other))
+        }
     }
 
     /// Deinterleave two vectors.
@@ -380,6 +384,10 @@ where
             const INDEX: [Which; LANES] = odd::<LANES>();
         }
 
-        (Even::swizzle2(self, other), Odd::swizzle2(self, other))
+        if LANES == 1 {
+            (self, other)
+        } else {
+            (Even::swizzle2(self, other), Odd::swizzle2(self, other))
+        }
     }
 }
diff --git a/crates/core_simd/tests/swizzle.rs b/crates/core_simd/tests/swizzle.rs
index 51c63611aba..33a7becb421 100644
--- a/crates/core_simd/tests/swizzle.rs
+++ b/crates/core_simd/tests/swizzle.rs
@@ -60,3 +60,17 @@ fn interleave() {
     assert_eq!(even, a);
     assert_eq!(odd, b);
 }
+
+// portable-simd#298
+#[test]
+#[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+fn interleave_one() {
+    let a = Simd::from_array([0]);
+    let b = Simd::from_array([1]);
+    let (lo, hi) = a.interleave(b);
+    assert_eq!(lo.to_array(), [0]);
+    assert_eq!(hi.to_array(), [1]);
+    let (even, odd) = lo.deinterleave(hi);
+    assert_eq!(even, a);
+    assert_eq!(odd, b);
+}