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authorYuki Okushi <jtitor@2k36.org>2023-04-11 12:18:50 +0900
committerGitHub <noreply@github.com>2023-04-11 12:18:50 +0900
commit5af6385f9f0d33c4aa611db5efd80f9ab1b4ffde (patch)
treec32d6a26fddf27c7b69d4c3e71062ebbb99fa3db
parenta69cc45d8265e37646be24158137de5a428099ca (diff)
parent48be303272e8eb620665b73a7bd87cdb6508f6f1 (diff)
downloadrust-5af6385f9f0d33c4aa611db5efd80f9ab1b4ffde.tar.gz
rust-5af6385f9f0d33c4aa611db5efd80f9ab1b4ffde.zip
Rollup merge of #109860 - zyedidia:riscv-relax, r=petrochenkov
Add support for RISC-V relax target feature

This adds `relax` as an allowed RISC-V target feature. The relax feature in LLVM enables [linker relaxation](https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain), an optimization specific to RISC-V that allows global variable accesses to be resolved by the linker by using the global pointer (`gp`) register (rather than constructing the addresses from scratch for each access). Enabling `relax` will cause LLVM to emit relocations in the object file that support this. The feature can be enabled in rustc with `-C target-feature=+relax`.

Currently this feature is disabled by default, but maybe it should be enabled by default since it is an easy performance improvement (but requires the `gp` register to be set up properly). GCC/Clang enable this feature by default (for both hosted/bare-metal targets), and include the `-mno-relax` flag to disable it (see [here](https://github.com/llvm/llvm-project/blob/466d554dcab39c3d42fe0c5b588b795e0e4b9d0d/clang/lib/Driver/ToolChains/Arch/RISCV.cpp#L145) for the code that enables it in Clang). I think it would make sense to enable by default, at least for all hosted targets since the `gp` register should be automatically set up by the runtime. For bare-metal targets, `gp` must be set up manually, so it is probably best to leave off by default to avoid breaking existing applications that do not set up `gp`. Leaving it disabled by default for all targets is also reasonable though.

Let me know your thoughts. Thanks!

Fixes #109426.
-rw-r--r--compiler/rustc_codegen_ssa/src/target_features.rs1
1 files changed, 1 insertions, 0 deletions
diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs
index 754b085f1a8..611dd3d1cd1 100644
--- a/compiler/rustc_codegen_ssa/src/target_features.rs
+++ b/compiler/rustc_codegen_ssa/src/target_features.rs
@@ -251,6 +251,7 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
     ("e", Some(sym::riscv_target_feature)),
     ("f", Some(sym::riscv_target_feature)),
     ("m", Some(sym::riscv_target_feature)),
+    ("relax", Some(sym::riscv_target_feature)),
     ("v", Some(sym::riscv_target_feature)),
     ("zba", Some(sym::riscv_target_feature)),
     ("zbb", Some(sym::riscv_target_feature)),