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authorAlex H <bearodark@gmail.com>2024-04-14 23:17:44 -0700
committerultrabear <bearodark@gmail.com>2024-05-04 14:51:35 -0700
commit3ef25288a4a68e4bdc03115cee9b259f33fa5b2d (patch)
tree925bb677516567c2021f69860bb065c72a365fe6
parente30ad6ff2c5c83823438a9a3d872a8c5da82807e (diff)
downloadrust-3ef25288a4a68e4bdc03115cee9b259f33fa5b2d.tar.gz
rust-3ef25288a4a68e4bdc03115cee9b259f33fa5b2d.zip
Make f16 and f128 docs clearer on platform support
Co-authored-by: Jubilee <46493976+workingjubilee@users.noreply.github.com>

Update library/core/src/primitive_docs.rs

Rewrite f16 and f128 hw support comments to match PR feedback

I wrote RISC-V allcaps in all cases, and wrote amd64 lowercase in all
cases, im not sure if either is the more correct way for either
platform, thats just how I normally write them, if theres a precedent
elsewhere it should probably be changed to match though.

Update library/core/src/primitive_docs.rs

Co-authored-by: Jubilee <46493976+workingjubilee@users.noreply.github.com>

Update library/core/src/primitive_docs.rs

Co-authored-by: Jubilee <46493976+workingjubilee@users.noreply.github.com>

Update library/core/src/primitive_docs.rs
-rw-r--r--library/core/src/primitive_docs.rs15
1 files changed, 11 insertions, 4 deletions
diff --git a/library/core/src/primitive_docs.rs b/library/core/src/primitive_docs.rs
index b1bc3ba1112..7fa119b5006 100644
--- a/library/core/src/primitive_docs.rs
+++ b/library/core/src/primitive_docs.rs
@@ -1082,8 +1082,12 @@ impl<T> (T,) {}
 /// bits. Please see [the documentation for [`prim@f32`] or [Wikipedia on
 /// half-precision values][wikipedia] for more information.
 ///
-/// Note that most major platforms will provide `f16` math support by converting to and from
-/// an `f32`, which is usually fairly performant but will not be as fast as using `f32` directly.
+/// Note that most common platforms will not support `f16` in hardware without enabling extra target
+/// features, with the notable exception of Apple Silicon (also known as M1, M2, etc.) processors.
+/// Hardware support on x86-64 requires the avx512fp16 feature, while RISC-V requires Zhf.
+/// Usually the fallback implementation will be to use `f32` hardware if it exists, and convert
+/// between `f16` and `f32` when performing math.
+///
 /// *[See also the `std::f16::consts` module](crate::f16::consts).*
 ///
 /// [wikipedia]: https://en.wikipedia.org/wiki/Half-precision_floating-point_format
@@ -1183,12 +1187,15 @@ mod prim_f64 {}
 /// as many bits as `f64`. Please see [the documentation for [`prim@f32`] or [Wikipedia on
 /// quad-precision values][wikipedia] for more information.
 ///
-/// Note that most major platforms do not have hardware support for `f128`, in which case a
-/// software implementation will be used. This can be significantly slower than using `f64`.
+/// Note that no platforms have hardware support for `f128` without enabling target specific features
+/// (and [only some consumer level hardware has support][wikipedia-support], for example RISC-V has support, but
+/// neither amd64 nor aarch64 has support), in which case a software implementation will be used. This can be
+/// significantly slower than using `f64`.
 ///
 /// *[See also the `std::f128::consts` module](crate::f128::consts).*
 ///
 /// [wikipedia]: https://en.wikipedia.org/wiki/Quadruple-precision_floating-point_format
+/// [wikipedia-support]: https://en.wikipedia.org/wiki/Quadruple-precision_floating-point_format#Hardware_support
 #[unstable(feature = "f128", issue = "116909")]
 mod prim_f128 {}