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| author | Matthias Krüger <matthias.krueger@famsik.de> | 2021-11-10 23:04:26 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-10 23:04:26 +0100 |
| commit | 90bb5fc08e34c3c4a709bdf277c868228f20a030 (patch) | |
| tree | b979a7204a83e910936e33d339942ceea98b1229 | |
| parent | a09115f3b4e24916bba27012d0f0299df21ef6a8 (diff) | |
| parent | a306d3557065570d3162c0d0be3ffeee4ebfeb9a (diff) | |
| download | rust-90bb5fc08e34c3c4a709bdf277c868228f20a030.tar.gz rust-90bb5fc08e34c3c4a709bdf277c868228f20a030.zip | |
Rollup merge of #90736 - Lokathor:inline-asm-docs-updates, r=Amanieu
adjust documented inline-asm register constraints This change more clearly specifies how `reg` and `reg_thumb` work with ARM, Thumb2, and Thumb1 code. Based upon the [llvm documentation](https://llvm.org/docs/LangRef.html#supported-constraint-code-list) for register constraint codes. To be clear, this just updates the docs to match what already happens with rustc/llvm. No change in the compiler is required to make it match this new documentation.
| -rw-r--r-- | src/doc/unstable-book/src/library-features/asm.md | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md index 84fc6dcc339..c4e8c6e5eb8 100644 --- a/src/doc/unstable-book/src/library-features/asm.md +++ b/src/doc/unstable-book/src/library-features/asm.md @@ -562,9 +562,12 @@ Here is the list of currently supported register classes: | AArch64 | `vreg` | `v[0-31]` | `w` | | AArch64 | `vreg_low16` | `v[0-15]` | `x` | | AArch64 | `preg` | `p[0-15]`, `ffr` | Only clobbers | -| ARM | `reg` | `r[0-12]`, `r14` | `r` | -| ARM (Thumb) | `reg_thumb` | `r[0-r7]` | `l` | +| ARM (ARM) | `reg` | `r[0-12]`, `r14` | `r` | +| ARM (Thumb2) | `reg` | `r[0-12]`, `r14` | `r` | +| ARM (Thumb1) | `reg` | `r[0-7]` | `r` | | ARM (ARM) | `reg_thumb` | `r[0-r12]`, `r14` | `l` | +| ARM (Thumb2) | `reg_thumb` | `r[0-7]` | `l` | +| ARM (Thumb1) | `reg_thumb` | `r[0-7]` | `l` | | ARM | `sreg` | `s[0-31]` | `t` | | ARM | `sreg_low16` | `s[0-15]` | `x` | | ARM | `dreg` | `d[0-31]` | `w` | |