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authortux3 <barrdetwix@gmail.com>2022-08-14 12:09:44 +0200
committertux3 <barrdetwix@gmail.com>2022-08-14 12:09:44 +0200
commitbe8fd0e59186f82318acac9381d304f21f4c715d (patch)
tree2ec8714cf5704f91bee72bbc1bc44a87883815a2
parent2fbc08e2ce64dee45a29cb6133da6b32366268aa (diff)
downloadrust-be8fd0e59186f82318acac9381d304f21f4c715d.tar.gz
rust-be8fd0e59186f82318acac9381d304f21f4c715d.zip
feat: Target features for 1st group of RISC-V Bitmanip extensions
These use the same names as LLVM and is_riscv_feature_detected!:
- zba (address generation instructions)
- zbb (basic bit manipulation)
- zbc (carry-less multiplication)
- zbs (single-bit manipulation)
-rw-r--r--compiler/rustc_codegen_ssa/src/target_features.rs4
1 files changed, 4 insertions, 0 deletions
diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs
index ecad0518533..9062a83b8be 100644
--- a/compiler/rustc_codegen_ssa/src/target_features.rs
+++ b/compiler/rustc_codegen_ssa/src/target_features.rs
@@ -227,6 +227,10 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
     ("zhinxmin", Some(sym::riscv_target_feature)),
     ("zfh", Some(sym::riscv_target_feature)),
     ("zfhmin", Some(sym::riscv_target_feature)),
+    ("zba", Some(sym::riscv_target_feature)),
+    ("zbb", Some(sym::riscv_target_feature)),
+    ("zbc", Some(sym::riscv_target_feature)),
+    ("zbs", Some(sym::riscv_target_feature)),
     ("zbkb", Some(sym::riscv_target_feature)),
     ("zbkc", Some(sym::riscv_target_feature)),
     ("zbkx", Some(sym::riscv_target_feature)),