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| author | bors <bors@rust-lang.org> | 2023-11-01 16:39:22 +0000 |
|---|---|---|
| committer | bors <bors@rust-lang.org> | 2023-11-01 16:39:22 +0000 |
| commit | f3457dbf84cd86d284454d12705861398ece76c3 (patch) | |
| tree | 38468c2c51db37538b01764fa4b6f22965670f93 | |
| parent | 146dafa26277c873172f555017b970ef006d302a (diff) | |
| parent | ecefd4eb3f3bbd14d715586f8b6c5caae6779a6c (diff) | |
| download | rust-f3457dbf84cd86d284454d12705861398ece76c3.tar.gz rust-f3457dbf84cd86d284454d12705861398ece76c3.zip | |
Auto merge of #117307 - taiki-e:espidf-atomic-64, r=Amanieu
Set max_atomic_width for riscv32*-esp-espidf to 32 Fixes #117305 > Since riscv32 does not have 64-bit atomic instructions, I do not believe there is any way to fix this problem other than setting max_atomic_width of these targets to 32. This is a breaking change because Atomic\*64 will become unavailable, but all affected targets are tier 3, and the current Atomic*64 violates the standard library's API contract and can cause problems with code that rely on the standard library's atomic types being lock-free. r? `@Amanieu` cc `@ivmarkov` `@MabezDev`
| -rw-r--r-- | compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs | 2 | ||||
| -rw-r--r-- | compiler/rustc_target/src/spec/riscv32imc_esp_espidf.rs | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs b/compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs index 0795065409a..25f5c3bc2a6 100644 --- a/compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs +++ b/compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs @@ -17,7 +17,7 @@ pub fn target() -> Target { // As RiscV32IMAC architecture does natively support atomics, // automatically enable the support for the Rust STD library. - max_atomic_width: Some(64), + max_atomic_width: Some(32), atomic_cas: true, features: "+m,+a,+c".into(), diff --git a/compiler/rustc_target/src/spec/riscv32imc_esp_espidf.rs b/compiler/rustc_target/src/spec/riscv32imc_esp_espidf.rs index 25638a092b5..3aa9923ee4d 100644 --- a/compiler/rustc_target/src/spec/riscv32imc_esp_espidf.rs +++ b/compiler/rustc_target/src/spec/riscv32imc_esp_espidf.rs @@ -16,11 +16,11 @@ pub fn target() -> Target { cpu: "generic-rv32".into(), // While the RiscV32IMC architecture does not natively support atomics, ESP-IDF does support - // the __atomic* and __sync* GCC builtins, so setting `max_atomic_width` to `Some(64)` + // the __atomic* and __sync* GCC builtins, so setting `max_atomic_width` to `Some(32)` // and `atomic_cas` to `true` will cause the compiler to emit libcalls to these builtins. // // Support for atomics is necessary for the Rust STD library, which is supported by the ESP-IDF framework. - max_atomic_width: Some(64), + max_atomic_width: Some(32), atomic_cas: true, features: "+m,+c".into(), |