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| author | Guillaume Gomez <guillaume1.gomez@gmail.com> | 2025-06-18 15:11:44 +0200 |
|---|---|---|
| committer | Guillaume Gomez <guillaume1.gomez@gmail.com> | 2025-06-18 15:11:44 +0200 |
| commit | c48d8d4d800df8a59d412c5c4299c8fadcd039e9 (patch) | |
| tree | cba780e8e9940952265aa1587419e557994e3423 /compiler/rustc_codegen_gcc | |
| parent | 6f935a044d1ddeb6160494a6320d008d7c311aef (diff) | |
| parent | fda0bb9588912a3e0606e880ca9f6e913cf8a5a4 (diff) | |
| download | rust-c48d8d4d800df8a59d412c5c4299c8fadcd039e9.tar.gz rust-c48d8d4d800df8a59d412c5c4299c8fadcd039e9.zip | |
Merge commit 'fda0bb9588912a3e0606e880ca9f6e913cf8a5a4' into subtree-update_cg_gcc_2025-06-18
Diffstat (limited to 'compiler/rustc_codegen_gcc')
54 files changed, 11917 insertions, 10357 deletions
diff --git a/compiler/rustc_codegen_gcc/.cspell.json b/compiler/rustc_codegen_gcc/.cspell.json new file mode 100644 index 00000000000..388ccce2b09 --- /dev/null +++ b/compiler/rustc_codegen_gcc/.cspell.json @@ -0,0 +1,27 @@ +{ + "allowCompoundWords": true, + "dictionaries": ["cpp", "rust-extra", "rustc_codegen_gcc"], + "dictionaryDefinitions": [ + { + "name": "rust-extra", + "path": "tools/cspell_dicts/rust.txt", + "addWords": true + }, + { + "name": "rustc_codegen_gcc", + "path": "tools/cspell_dicts/rustc_codegen_gcc.txt", + "addWords": true + } + ], + "files": [ + "src/**/*.rs" + ], + "ignorePaths": [ + "src/intrinsic/archs.rs", + "src/intrinsic/llvm.rs" + ], + "ignoreRegExpList": [ + "/(FIXME|NOTE|TODO)\\([^)]+\\)/", + "__builtin_\\w*" + ] +} diff --git a/compiler/rustc_codegen_gcc/.github/workflows/ci.yml b/compiler/rustc_codegen_gcc/.github/workflows/ci.yml index ef024258ffc..5c8e7d62816 100644 --- a/compiler/rustc_codegen_gcc/.github/workflows/ci.yml +++ b/compiler/rustc_codegen_gcc/.github/workflows/ci.yml @@ -12,6 +12,8 @@ permissions: env: # Enable backtraces for easier debugging RUST_BACKTRACE: 1 + # For the run-make tests. + LLVM_BIN_DIR: /usr/bin jobs: build: @@ -48,7 +50,7 @@ jobs: - name: Install packages # `llvm-14-tools` is needed to install the `FileCheck` binary which is used for asm tests. - run: sudo apt-get install ninja-build ripgrep llvm-14-tools + run: sudo apt-get install ninja-build ripgrep llvm-14-tools llvm - name: Install rustfmt & clippy run: rustup component add rustfmt clippy @@ -61,11 +63,15 @@ jobs: sudo dpkg --force-overwrite -i ${{ matrix.libgccjit_version.gcc }} echo 'gcc-path = "/usr/lib/"' > config.toml + # Some run-make tests fail if we use our forked GCC because it doesn't + # bundle libstdc++, so we switch to gcc-14 to have a GCC that has + # libstdc++. + - name: Set default GCC to gcc-14 + run: sudo update-alternatives --install /usr/bin/cc cc /usr/bin/gcc-14 30 + - name: Set env run: | echo "workspace="$GITHUB_WORKSPACE >> $GITHUB_ENV - echo "LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV - echo "LD_LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV #- name: Cache rust repository ## We only clone the rust repository for rustc tests @@ -76,12 +82,22 @@ jobs: #path: rust #key: ${{ runner.os }}-packages-${{ hashFiles('rust/.git/HEAD') }} + - name: Prepare + run: ./y.sh prepare --only-libcore + + - name: Check formatting + run: ./y.sh fmt --check + + - name: clippy + run: | + cargo clippy --all-targets -- -D warnings + cargo clippy --all-targets --no-default-features -- -D warnings + cargo clippy --manifest-path build_system/Cargo.toml --all-targets -- -D warnings + - name: Build run: | - ./y.sh prepare --only-libcore ./y.sh build --sysroot - ./y.sh test --mini-tests - cargo test + ./y.sh test --cargo-tests - name: Run y.sh cargo build run: | @@ -101,20 +117,19 @@ jobs: run: | ./y.sh test --release --clean --build-sysroot ${{ matrix.commands }} - - name: Check formatting - run: ./y.sh fmt --check - - - name: clippy - run: | - cargo clippy --all-targets -- -D warnings - cargo clippy --all-targets --features master -- -D warnings - duplicates: runs-on: ubuntu-24.04 steps: - uses: actions/checkout@v4 - run: python tools/check_intrinsics_duplicates.py + spell_check: + runs-on: ubuntu-24.04 + steps: + - uses: actions/checkout@v4 + - uses: crate-ci/typos@v1.32.0 + - uses: streetsidesoftware/cspell-action@v7 + build_system: runs-on: ubuntu-24.04 steps: diff --git a/compiler/rustc_codegen_gcc/.github/workflows/failures.yml b/compiler/rustc_codegen_gcc/.github/workflows/failures.yml index bc42eb1468e..67b7fbe4478 100644 --- a/compiler/rustc_codegen_gcc/.github/workflows/failures.yml +++ b/compiler/rustc_codegen_gcc/.github/workflows/failures.yml @@ -66,8 +66,8 @@ jobs: run: | sudo dpkg --force-overwrite -i gcc-15.deb echo 'gcc-path = "/usr/lib"' > config.toml - echo "LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV - echo "LD_LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV + + - name: Set env run: | diff --git a/compiler/rustc_codegen_gcc/.github/workflows/m68k.yml b/compiler/rustc_codegen_gcc/.github/workflows/m68k.yml index 21731f7087e..245bee7f2a3 100644 --- a/compiler/rustc_codegen_gcc/.github/workflows/m68k.yml +++ b/compiler/rustc_codegen_gcc/.github/workflows/m68k.yml @@ -65,8 +65,8 @@ jobs: - name: Set env run: | echo "workspace="$GITHUB_WORKSPACE >> $GITHUB_ENV - echo "LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV - echo "LD_LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV + + #- name: Cache rust repository ## We only clone the rust repository for rustc tests @@ -95,7 +95,7 @@ jobs: ./y.sh prepare --only-libcore --cross ./y.sh build --sysroot --features compiler_builtins/no-f16-f128 --target-triple m68k-unknown-linux-gnu ./y.sh test --mini-tests - CG_GCC_TEST_TARGET=m68k-unknown-linux-gnu cargo test + CG_GCC_TEST_TARGET=m68k-unknown-linux-gnu ./y.sh test --cargo-tests ./y.sh clean all - name: Prepare dependencies diff --git a/compiler/rustc_codegen_gcc/.github/workflows/release.yml b/compiler/rustc_codegen_gcc/.github/workflows/release.yml index 47a40286554..1d8eaf9a141 100644 --- a/compiler/rustc_codegen_gcc/.github/workflows/release.yml +++ b/compiler/rustc_codegen_gcc/.github/workflows/release.yml @@ -12,6 +12,8 @@ permissions: env: # Enable backtraces for easier debugging RUST_BACKTRACE: 1 + # For the run-make tests. + LLVM_BIN_DIR: /usr/bin jobs: build: @@ -36,7 +38,8 @@ jobs: uses: Swatinem/rust-cache@v2 - name: Install packages - run: sudo apt-get install ninja-build ripgrep + # `llvm-14-tools` is needed to install the `FileCheck` binary which is used for run-make tests. + run: sudo apt-get install ninja-build ripgrep llvm-14-tools llvm - name: Download artifact run: curl -LO https://github.com/rust-lang/gcc/releases/latest/download/gcc-15.deb @@ -46,18 +49,21 @@ jobs: sudo dpkg --force-overwrite -i gcc-15.deb echo 'gcc-path = "/usr/lib/"' > config.toml + # Some run-make tests fail if we use our forked GCC because it doesn't + # bundle libstdc++, so we switch to gcc-14 to have a GCC that has + # libstdc++. + - name: Set default GCC to gcc-14 + run: sudo update-alternatives --install /usr/bin/cc cc /usr/bin/gcc-14 30 + - name: Set env run: | echo "workspace="$GITHUB_WORKSPACE >> $GITHUB_ENV - echo "LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV - echo "LD_LIBRARY_PATH=/usr/lib" >> $GITHUB_ENV - name: Build run: | ./y.sh prepare --only-libcore EMBED_LTO_BITCODE=1 ./y.sh build --sysroot --release --release-sysroot - ./y.sh test --mini-tests - cargo test + ./y.sh test --cargo-tests ./y.sh clean all - name: Prepare dependencies diff --git a/compiler/rustc_codegen_gcc/.github/workflows/stdarch.yml b/compiler/rustc_codegen_gcc/.github/workflows/stdarch.yml index f26ac3b755f..20d009f08a7 100644 --- a/compiler/rustc_codegen_gcc/.github/workflows/stdarch.yml +++ b/compiler/rustc_codegen_gcc/.github/workflows/stdarch.yml @@ -90,7 +90,7 @@ jobs: if: ${{ !matrix.cargo_runner }} run: | ./y.sh test --release --clean --release-sysroot --build-sysroot --mini-tests --std-tests --test-libcore - cargo test + ./y.sh test --cargo-tests - name: Run stdarch tests if: ${{ !matrix.cargo_runner }} diff --git a/compiler/rustc_codegen_gcc/.gitignore b/compiler/rustc_codegen_gcc/.gitignore index c1e6631a281..8f73d3eb972 100644 --- a/compiler/rustc_codegen_gcc/.gitignore +++ b/compiler/rustc_codegen_gcc/.gitignore @@ -19,4 +19,5 @@ tools/llvmint-2 llvm build_system/target config.toml -build \ No newline at end of file +build +rustlantis \ No newline at end of file diff --git a/compiler/rustc_codegen_gcc/CONTRIBUTING.md b/compiler/rustc_codegen_gcc/CONTRIBUTING.md index 8e313ab08b5..54cba0e6de3 100644 --- a/compiler/rustc_codegen_gcc/CONTRIBUTING.md +++ b/compiler/rustc_codegen_gcc/CONTRIBUTING.md @@ -33,7 +33,7 @@ To run specific tests, use appropriate flags such as: - `./y.sh test --test-libcore` - `./y.sh test --std-tests` -- `cargo test -- <name of test>` +- `./y.sh test --cargo-tests -- <name of test>` Additionally, you can run the tests of `libgccjit`: diff --git a/compiler/rustc_codegen_gcc/Cargo.lock b/compiler/rustc_codegen_gcc/Cargo.lock index 967a51a1cc6..b20c181a8cb 100644 --- a/compiler/rustc_codegen_gcc/Cargo.lock +++ b/compiler/rustc_codegen_gcc/Cargo.lock @@ -82,6 +82,18 @@ dependencies = [ ] [[package]] +name = "getrandom" +version = "0.3.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "26145e563e54f2cadc477553f1ec5ee650b00862f0a58bcd12cbdc5f0ea2d2f4" +dependencies = [ + "cfg-if", + "libc", + "r-efi", + "wasi", +] + +[[package]] name = "hermit-abi" version = "0.3.1" source = "registry+https://github.com/rust-lang/crates.io-index" @@ -111,9 +123,9 @@ checksum = "5aaeb2981e0606ca11d79718f8bb01164f1d6ed75080182d3abf017e6d244b6d" [[package]] name = "linux-raw-sys" -version = "0.4.14" +version = "0.9.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89" +checksum = "cd945864f07fe9f5371a27ad7b52a172b4b499999f1d97574c9fa68373937e12" [[package]] name = "memchr" @@ -138,6 +150,12 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "1261fe7e33c73b354eab43b1273a57c8f967d0391e80353e51f764ac02cf6775" [[package]] +name = "r-efi" +version = "5.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "74765f6d916ee2faa39bc8e68e4f3ed8949b48cccdac59983d287a7cb71ce9c5" + +[[package]] name = "regex" version = "1.8.4" source = "registry+https://github.com/rust-lang/crates.io-index" @@ -166,9 +184,9 @@ dependencies = [ [[package]] name = "rustix" -version = "0.38.42" +version = "1.0.7" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f93dc38ecbab2eb790ff964bb77fa94faf256fd3e73285fd7ba0903b76bedb85" +checksum = "c71e83d6afe7ff64890ec6b71d6a69bb8a610ab78ce364b3352876bb4c801266" dependencies = [ "bitflags", "errno", @@ -188,12 +206,12 @@ dependencies = [ [[package]] name = "tempfile" -version = "3.14.0" +version = "3.20.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "28cce251fcbc87fac86a866eeb0d6c2d536fc16d06f184bb61aeae11aa4cee0c" +checksum = "e8a64e3985349f2441a1a9ef0b853f869006c3855f2cda6862a94d26ebb9d6a1" dependencies = [ - "cfg-if", "fastrand", + "getrandom", "once_cell", "rustix", "windows-sys", @@ -243,6 +261,15 @@ dependencies = [ ] [[package]] +name = "wasi" +version = "0.14.2+wasi-0.2.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9683f9a5a998d873c0d21fcbe3c083009670149a8fab228644b8bd36b2c48cb3" +dependencies = [ + "wit-bindgen-rt", +] + +[[package]] name = "winapi" version = "0.3.9" source = "registry+https://github.com/rust-lang/crates.io-index" @@ -345,3 +372,12 @@ name = "windows_x86_64_msvc" version = "0.52.6" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec" + +[[package]] +name = "wit-bindgen-rt" +version = "0.39.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "6f42320e61fe2cfd34354ecb597f86f413484a798ba44a8ca1165c58d42da6c1" +dependencies = [ + "bitflags", +] diff --git a/compiler/rustc_codegen_gcc/Cargo.toml b/compiler/rustc_codegen_gcc/Cargo.toml index c692a90f0a4..c284e3f060b 100644 --- a/compiler/rustc_codegen_gcc/Cargo.toml +++ b/compiler/rustc_codegen_gcc/Cargo.toml @@ -31,7 +31,7 @@ gccjit = "2.7" [dev-dependencies] boml = "0.3.1" lang_tester = "0.8.0" -tempfile = "3.7.1" +tempfile = "3.20" [profile.dev] # By compiling dependencies with optimizations, performing tests gets much faster. diff --git a/compiler/rustc_codegen_gcc/_typos.toml b/compiler/rustc_codegen_gcc/_typos.toml new file mode 100644 index 00000000000..4a6a506a981 --- /dev/null +++ b/compiler/rustc_codegen_gcc/_typos.toml @@ -0,0 +1,9 @@ +[default.extend-words] +ba = "ba" +hsa = "hsa" +olt = "olt" +seh = "seh" +typ = "typ" + +[files] +extend-exclude = ["src/intrinsic/archs.rs"] diff --git a/compiler/rustc_codegen_gcc/build_system/build_sysroot/Cargo.lock b/compiler/rustc_codegen_gcc/build_system/build_sysroot/Cargo.lock index 51bec5aa9e3..0c75977ee79 100644 --- a/compiler/rustc_codegen_gcc/build_system/build_sysroot/Cargo.lock +++ b/compiler/rustc_codegen_gcc/build_system/build_sysroot/Cargo.lock @@ -1,24 +1,24 @@ # This file is automatically @generated by Cargo. # It is not intended for manual editing. -version = 3 +version = 4 [[package]] name = "addr2line" -version = "0.22.0" +version = "0.24.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6e4503c46a5c0c7844e948c9a4d6acd9f50cccb4de1c48eb9e291ea17470c678" +checksum = "dfbe277e56a376000877090da837660b4427aad530e3028d44e0bffe4f89a1c1" dependencies = [ "compiler_builtins", - "gimli 0.29.0", + "gimli", "rustc-std-workspace-alloc", "rustc-std-workspace-core", ] [[package]] -name = "adler" -version = "1.0.2" +name = "adler2" +version = "2.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f26201604c87b1e01bd3d98f8d5d9a8fcbb815e8cedb41ffccbeb4bf593a35fe" +checksum = "512761e0bb2578dd7380c6baaa0f4ce03e84f95e960231d1dec8bf4d7d6e2627" dependencies = [ "compiler_builtins", "rustc-std-workspace-core", @@ -33,10 +33,21 @@ dependencies = [ ] [[package]] -name = "allocator-api2" -version = "0.2.18" +name = "alloctests" +version = "0.0.0" +dependencies = [ + "rand", + "rand_xorshift", +] + +[[package]] +name = "cc" +version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5c6cb57a04249c6480766f7f7cef5467412af1490f8d1e243141daddada3264f" +checksum = "1aeb932158bd710538c73702db6945cb68a8fb08c519e6e12706b94263b36db8" +dependencies = [ + "shlex", +] [[package]] name = "cfg-if" @@ -50,10 +61,11 @@ dependencies = [ [[package]] name = "compiler_builtins" -version = "0.1.118" +version = "0.1.160" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "92afe7344b64cccf3662ca26d5d1c0828ab826f04206b97d856e3625e390e4b5" +checksum = "6376049cfa92c0aa8b9ac95fae22184b981c658208d4ed8a1dc553cd83612895" dependencies = [ + "cc", "rustc-std-workspace-core", ] @@ -62,10 +74,18 @@ name = "core" version = "0.0.0" [[package]] +name = "coretests" +version = "0.0.0" +dependencies = [ + "rand", + "rand_xorshift", +] + +[[package]] name = "dlmalloc" -version = "0.2.6" +version = "0.2.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3264b043b8e977326c1ee9e723da2c1f8d09a99df52cacf00b4dbce5ac54414d" +checksum = "8cff88b751e7a276c4ab0e222c3f355190adc6dde9ce39c851db39da34990df7" dependencies = [ "cfg-if", "compiler_builtins", @@ -97,20 +117,9 @@ dependencies = [ [[package]] name = "gimli" -version = "0.29.0" +version = "0.31.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "40ecd4077b5ae9fd2e9e169b102c6c330d0605168eb0e8bf79952b256dbefffd" -dependencies = [ - "compiler_builtins", - "rustc-std-workspace-alloc", - "rustc-std-workspace-core", -] - -[[package]] -name = "gimli" -version = "0.30.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e2e1d97fbe9722ba9bbd0c97051c2956e726562b61f86a25a4360398a40edfc9" +checksum = "07e28edb80900c19c28f1072f2e8aeca7fa06b23cd4169cefe1af5aa3260783f" dependencies = [ "compiler_builtins", "rustc-std-workspace-alloc", @@ -119,11 +128,10 @@ dependencies = [ [[package]] name = "hashbrown" -version = "0.14.5" +version = "0.15.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e5274423e17b7c9fc20b6e7e208532f9b19825d82dfd615708b70edd83df41f1" +checksum = "84b26c544d002229e640969970a2e74021aadf6e2f96372b9c58eff97de08eb3" dependencies = [ - "allocator-api2", "compiler_builtins", "rustc-std-workspace-alloc", "rustc-std-workspace-core", @@ -131,9 +139,9 @@ dependencies = [ [[package]] name = "hermit-abi" -version = "0.4.0" +version = "0.5.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fbf6a919d6cf397374f7dfeeea91d974c7c0a7221d0d0f4f20d859d329e53fcc" +checksum = "f154ce46856750ed433c8649605bf7ed2de3bc35fd9d2a9f30cddd873c80cb08" dependencies = [ "compiler_builtins", "rustc-std-workspace-alloc", @@ -142,9 +150,9 @@ dependencies = [ [[package]] name = "libc" -version = "0.2.155" +version = "0.2.172" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "97b3888a4aecf77e811145cadf6eef5901f4782c53886191b2f693f24761847c" +checksum = "d750af042f7ef4f724306de029d18836c26c1765a54a6a3f094cbd23a7267ffa" dependencies = [ "rustc-std-workspace-core", ] @@ -161,11 +169,11 @@ dependencies = [ [[package]] name = "miniz_oxide" -version = "0.7.4" +version = "0.8.8" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b8a240ddb74feaf34a79a7add65a741f3167852fba007066dcac1ca548d89c08" +checksum = "3be647b768db090acb35d5ec5db2b0e1f1de11133ca123b9eacf5137868f892a" dependencies = [ - "adler", + "adler2", "compiler_builtins", "rustc-std-workspace-alloc", "rustc-std-workspace-core", @@ -173,9 +181,9 @@ dependencies = [ [[package]] name = "object" -version = "0.36.3" +version = "0.36.7" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "27b64972346851a39438c60b341ebc01bba47464ae329e55cf343eb93964efd9" +checksum = "62948e14d923ea95ea2c7c86c71013138b66525b86bdc08d2dcc262bdb497b87" dependencies = [ "compiler_builtins", "memchr", @@ -188,7 +196,6 @@ name = "panic_abort" version = "0.0.0" dependencies = [ "alloc", - "cfg-if", "compiler_builtins", "core", "libc", @@ -211,14 +218,22 @@ name = "proc_macro" version = "0.0.0" dependencies = [ "core", + "rustc-literal-escaper", "std", ] [[package]] +name = "profiler_builtins" +version = "0.0.0" +dependencies = [ + "cc", +] + +[[package]] name = "r-efi" -version = "4.5.0" +version = "5.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e9e935efc5854715dfc0a4c9ef18dc69dee0ec3bf9cc3ab740db831c0fdd86a3" +checksum = "74765f6d916ee2faa39bc8e68e4f3ed8949b48cccdac59983d287a7cb71ce9c5" dependencies = [ "compiler_builtins", "rustc-std-workspace-core", @@ -226,9 +241,9 @@ dependencies = [ [[package]] name = "r-efi-alloc" -version = "1.0.0" +version = "2.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "31d6f09fe2b6ad044bc3d2c34ce4979796581afd2f1ebc185837e02421e02fd7" +checksum = "e43c53ff1a01d423d1cb762fd991de07d32965ff0ca2e4f80444ac7804198203" dependencies = [ "compiler_builtins", "r-efi", @@ -236,6 +251,30 @@ dependencies = [ ] [[package]] +name = "rand" +version = "0.9.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9fbfd9d094a40bf3ae768db9361049ace4c0e04a4fd6b359518bd7b73a73dd97" +dependencies = [ + "rand_core", +] + +[[package]] +name = "rand_core" +version = "0.9.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "99d9a13982dcf210057a8a78572b2217b667c3beacbf3a0d8b454f6f82837d38" + +[[package]] +name = "rand_xorshift" +version = "0.4.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "513962919efc330f829edb2535844d1b912b0fbe2ca165d613e4e8788bb05a5a" +dependencies = [ + "rand_core", +] + +[[package]] name = "rustc-demangle" version = "0.1.24" source = "registry+https://github.com/rust-lang/crates.io-index" @@ -246,6 +285,15 @@ dependencies = [ ] [[package]] +name = "rustc-literal-escaper" +version = "0.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0041b6238913c41fe704213a4a9329e2f685a156d1781998128b4149c230ad04" +dependencies = [ + "rustc-std-workspace-std", +] + +[[package]] name = "rustc-std-workspace-alloc" version = "1.99.0" dependencies = [ @@ -267,6 +315,12 @@ dependencies = [ ] [[package]] +name = "shlex" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64" + +[[package]] name = "std" version = "0.0.0" dependencies = [ @@ -286,10 +340,13 @@ dependencies = [ "panic_unwind", "r-efi", "r-efi-alloc", + "rand", + "rand_xorshift", "rustc-demangle", "std_detect", "unwind", "wasi", + "windows-targets 0.0.0", ] [[package]] @@ -298,6 +355,7 @@ version = "0.1.5" dependencies = [ "cfg-if", "compiler_builtins", + "libc", "rustc-std-workspace-alloc", "rustc-std-workspace-core", ] @@ -306,10 +364,8 @@ dependencies = [ name = "sysroot" version = "0.0.0" dependencies = [ - "alloc", - "compiler_builtins", - "core", "proc_macro", + "profiler_builtins", "std", "test", ] @@ -326,9 +382,9 @@ dependencies = [ [[package]] name = "unicode-width" -version = "0.1.13" +version = "0.1.14" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0336d538f7abc86d282a4189614dfaa90810dfc2c6f6427eaf88e16311dd225d" +checksum = "7dd6e30e90baa6f72411720665d41d89b9a3d039dc45b8faea1ddd07f617f6af" dependencies = [ "compiler_builtins", "rustc-std-workspace-core", @@ -348,12 +404,12 @@ dependencies = [ [[package]] name = "unwinding" -version = "0.2.2" +version = "0.2.6" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "dc55842d0db6329a669d55a623c674b02d677b16bfb2d24857d4089d41eba882" +checksum = "8393f2782b6060a807337ff353780c1ca15206f9ba2424df18cb6e733bd7b345" dependencies = [ "compiler_builtins", - "gimli 0.30.0", + "gimli", "rustc-std-workspace-core", ] @@ -370,15 +426,19 @@ dependencies = [ [[package]] name = "windows-sys" -version = "0.52.0" +version = "0.59.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d" +checksum = "1e38bc4d79ed67fd075bcc251a1c39b32a1776bbe92e5bef1f0bf1f8c531853b" dependencies = [ - "windows-targets", + "windows-targets 0.52.6", ] [[package]] name = "windows-targets" +version = "0.0.0" + +[[package]] +name = "windows-targets" version = "0.52.6" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973" diff --git a/compiler/rustc_codegen_gcc/build_system/src/build.rs b/compiler/rustc_codegen_gcc/build_system/src/build.rs index e98377f15a9..ecc4c1b2fe2 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/build.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/build.rs @@ -33,7 +33,7 @@ impl BuildArg { } arg => { if !build_arg.config_info.parse_argument(arg, &mut args)? { - return Err(format!("Unknown argument `{}`", arg)); + return Err(format!("Unknown argument `{arg}`")); } } } @@ -105,14 +105,14 @@ pub fn create_build_sysroot_content(start_dir: &Path) -> Result<(), String> { if !start_dir.is_dir() { create_dir(start_dir)?; } - copy_file("build_system/build_sysroot/Cargo.toml", &start_dir.join("Cargo.toml"))?; - copy_file("build_system/build_sysroot/Cargo.lock", &start_dir.join("Cargo.lock"))?; + copy_file("build_system/build_sysroot/Cargo.toml", start_dir.join("Cargo.toml"))?; + copy_file("build_system/build_sysroot/Cargo.lock", start_dir.join("Cargo.lock"))?; let src_dir = start_dir.join("src"); if !src_dir.is_dir() { create_dir(&src_dir)?; } - copy_file("build_system/build_sysroot/lib.rs", &start_dir.join("src/lib.rs")) + copy_file("build_system/build_sysroot/lib.rs", start_dir.join("src/lib.rs")) } pub fn build_sysroot(env: &HashMap<String, String>, config: &ConfigInfo) -> Result<(), String> { @@ -169,7 +169,7 @@ pub fn build_sysroot(env: &HashMap<String, String>, config: &ConfigInfo) -> Resu run_command(&[&"cp", &"-r", &dir_to_copy, &sysroot_path], None).map(|_| ()) }; walk_dir( - start_dir.join(&format!("target/{}/{}/deps", config.target_triple, channel)), + start_dir.join(format!("target/{}/{}/deps", config.target_triple, channel)), &mut copier.clone(), &mut copier, false, diff --git a/compiler/rustc_codegen_gcc/build_system/src/clean.rs b/compiler/rustc_codegen_gcc/build_system/src/clean.rs index 768a78e789e..a441ed613f9 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/clean.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/clean.rs @@ -17,12 +17,12 @@ enum CleanArg { impl CleanArg { fn new() -> Result<Self, String> { // We skip the binary and the "clean" option. - for arg in std::env::args().skip(2) { + if let Some(arg) = std::env::args().nth(2) { return match arg.as_str() { "all" => Ok(Self::All), "ui-tests" => Ok(Self::UiTests), "--help" => Ok(Self::Help), - a => Err(format!("Unknown argument `{}`", a)), + a => Err(format!("Unknown argument `{a}`")), }; } Ok(Self::default()) diff --git a/compiler/rustc_codegen_gcc/build_system/src/clone_gcc.rs b/compiler/rustc_codegen_gcc/build_system/src/clone_gcc.rs index b49dd47f352..ee683df419c 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/clone_gcc.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/clone_gcc.rs @@ -43,7 +43,7 @@ impl Args { } arg => { if !command_args.config_info.parse_argument(arg, &mut args)? { - return Err(format!("Unknown option {}", arg)); + return Err(format!("Unknown option {arg}")); } } } @@ -52,7 +52,7 @@ impl Args { Some(p) => p.into(), None => PathBuf::from("./gcc"), }; - return Ok(Some(command_args)); + Ok(Some(command_args)) } } @@ -64,7 +64,7 @@ pub fn run() -> Result<(), String> { let result = git_clone("https://github.com/rust-lang/gcc", Some(&args.out_path), false)?; if result.ran_clone { let gcc_commit = args.config_info.get_gcc_commit()?; - println!("Checking out GCC commit `{}`...", gcc_commit); + println!("Checking out GCC commit `{gcc_commit}`..."); run_command_with_output( &[&"git", &"checkout", &gcc_commit], Some(Path::new(&result.repo_dir)), diff --git a/compiler/rustc_codegen_gcc/build_system/src/config.rs b/compiler/rustc_codegen_gcc/build_system/src/config.rs index 4f9fcc97151..650c030ca53 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/config.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/config.rs @@ -66,7 +66,7 @@ impl ConfigFile { "Expected a boolean for `download-gccjit`", ); } - _ => return failed_config_parsing(config_file, &format!("Unknown key `{}`", key)), + _ => return failed_config_parsing(config_file, &format!("Unknown key `{key}`")), } } match (config.gcc_path.as_mut(), config.download_gccjit) { @@ -86,9 +86,7 @@ impl ConfigFile { let path = Path::new(gcc_path); *gcc_path = path .canonicalize() - .map_err(|err| { - format!("Failed to get absolute path of `{}`: {:?}", gcc_path, err) - })? + .map_err(|err| format!("Failed to get absolute path of `{gcc_path}`: {err:?}"))? .display() .to_string(); } @@ -175,7 +173,7 @@ impl ConfigInfo { "--sysroot-panic-abort" => self.sysroot_panic_abort = true, "--gcc-path" => match args.next() { Some(arg) if !arg.is_empty() => { - self.gcc_path = Some(arg.into()); + self.gcc_path = Some(arg); } _ => { return Err("Expected a value after `--gcc-path`, found nothing".to_string()); @@ -244,7 +242,7 @@ impl ConfigInfo { let libgccjit_so = output_dir.join(libgccjit_so_name); if !libgccjit_so.is_file() && !self.no_download { // Download time! - let tempfile_name = format!("{}.download", libgccjit_so_name); + let tempfile_name = format!("{libgccjit_so_name}.download"); let tempfile = output_dir.join(&tempfile_name); let is_in_ci = std::env::var("GITHUB_ACTIONS").is_ok(); @@ -262,14 +260,14 @@ impl ConfigInfo { ) })?; - println!("Downloaded libgccjit.so version {} successfully!", commit); + println!("Downloaded libgccjit.so version {commit} successfully!"); // We need to create a link named `libgccjit.so.0` because that's what the linker is // looking for. - create_symlink(&libgccjit_so, output_dir.join(&format!("{}.0", libgccjit_so_name)))?; + create_symlink(&libgccjit_so, output_dir.join(format!("{libgccjit_so_name}.0")))?; } let gcc_path = output_dir.display().to_string(); - println!("Using `{}` as path for libgccjit", gcc_path); + println!("Using `{gcc_path}` as path for libgccjit"); self.gcc_path = Some(gcc_path); Ok(()) } @@ -286,8 +284,7 @@ impl ConfigInfo { // since we already have everything we need. if let Some(gcc_path) = &self.gcc_path { println!( - "`--gcc-path` was provided, ignoring config file. Using `{}` as path for libgccjit", - gcc_path + "`--gcc-path` was provided, ignoring config file. Using `{gcc_path}` as path for libgccjit" ); return Ok(()); } @@ -343,7 +340,7 @@ impl ConfigInfo { self.dylib_ext = match os_name.as_str() { "Linux" => "so", "Darwin" => "dylib", - os => return Err(format!("unsupported OS `{}`", os)), + os => return Err(format!("unsupported OS `{os}`")), } .to_string(); let rustc = match env.get("RUSTC") { @@ -355,10 +352,10 @@ impl ConfigInfo { None => return Err("no host found".to_string()), }; - if self.target_triple.is_empty() { - if let Some(overwrite) = env.get("OVERWRITE_TARGET_TRIPLE") { - self.target_triple = overwrite.clone(); - } + if self.target_triple.is_empty() + && let Some(overwrite) = env.get("OVERWRITE_TARGET_TRIPLE") + { + self.target_triple = overwrite.clone(); } if self.target_triple.is_empty() { self.target_triple = self.host_triple.clone(); @@ -378,7 +375,7 @@ impl ConfigInfo { } let current_dir = - std_env::current_dir().map_err(|error| format!("`current_dir` failed: {:?}", error))?; + std_env::current_dir().map_err(|error| format!("`current_dir` failed: {error:?}"))?; let channel = if self.channel == Channel::Release { "release" } else if let Some(channel) = env.get("CHANNEL") { @@ -391,15 +388,15 @@ impl ConfigInfo { self.cg_backend_path = current_dir .join("target") .join(channel) - .join(&format!("librustc_codegen_gcc.{}", self.dylib_ext)) + .join(format!("librustc_codegen_gcc.{}", self.dylib_ext)) .display() .to_string(); self.sysroot_path = - current_dir.join(&get_sysroot_dir()).join("sysroot").display().to_string(); + current_dir.join(get_sysroot_dir()).join("sysroot").display().to_string(); if let Some(backend) = &self.backend { // This option is only used in the rust compiler testsuite. The sysroot is handled // by its build system directly so no need to set it ourselves. - rustflags.push(format!("-Zcodegen-backend={}", backend)); + rustflags.push(format!("-Zcodegen-backend={backend}")); } else { rustflags.extend_from_slice(&[ "--sysroot".to_string(), @@ -412,10 +409,10 @@ impl ConfigInfo { // We have a different environment variable than RUSTFLAGS to make sure those flags are // only sent to rustc_codegen_gcc and not the LLVM backend. if let Some(cg_rustflags) = env.get("CG_RUSTFLAGS") { - rustflags.extend_from_slice(&split_args(&cg_rustflags)?); + rustflags.extend_from_slice(&split_args(cg_rustflags)?); } if let Some(test_flags) = env.get("TEST_FLAGS") { - rustflags.extend_from_slice(&split_args(&test_flags)?); + rustflags.extend_from_slice(&split_args(test_flags)?); } if let Some(linker) = linker { @@ -438,8 +435,8 @@ impl ConfigInfo { env.insert("RUSTC_LOG".to_string(), "warn".to_string()); let sysroot = current_dir - .join(&get_sysroot_dir()) - .join(&format!("sysroot/lib/rustlib/{}/lib", self.target_triple)); + .join(get_sysroot_dir()) + .join(format!("sysroot/lib/rustlib/{}/lib", self.target_triple)); let ld_library_path = format!( "{target}:{sysroot}:{gcc_path}", target = self.cargo_target_dir, @@ -505,7 +502,7 @@ fn download_gccjit( with_progress_bar: bool, ) -> Result<(), String> { let url = if std::env::consts::OS == "linux" && std::env::consts::ARCH == "x86_64" { - format!("https://github.com/rust-lang/gcc/releases/download/master-{}/libgccjit.so", commit) + format!("https://github.com/rust-lang/gcc/releases/download/master-{commit}/libgccjit.so") } else { eprintln!( "\ @@ -518,7 +515,7 @@ to `download-gccjit = false` and set `gcc-path` to the appropriate directory." )); }; - println!("Downloading `{}`...", url); + println!("Downloading `{url}`..."); // Try curl. If that fails and we are on windows, fallback to PowerShell. let mut ret = run_command_with_output( @@ -538,7 +535,7 @@ to `download-gccjit = false` and set `gcc-path` to the appropriate directory." if with_progress_bar { &"--progress-bar" } else { &"-s" }, &url.as_str(), ], - Some(&output_dir), + Some(output_dir), ); if ret.is_err() && cfg!(windows) { eprintln!("Fallback to PowerShell"); @@ -549,12 +546,11 @@ to `download-gccjit = false` and set `gcc-path` to the appropriate directory." &"-Command", &"[Net.ServicePointManager]::SecurityProtocol = [Net.SecurityProtocolType]::Tls12;", &format!( - "(New-Object System.Net.WebClient).DownloadFile('{}', '{}')", - url, tempfile_name, + "(New-Object System.Net.WebClient).DownloadFile('{url}', '{tempfile_name}')", ) .as_str(), ], - Some(&output_dir), + Some(output_dir), ); } ret diff --git a/compiler/rustc_codegen_gcc/build_system/src/fmt.rs b/compiler/rustc_codegen_gcc/build_system/src/fmt.rs index de310a6a30f..7e6594f50f9 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/fmt.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/fmt.rs @@ -16,21 +16,21 @@ fn show_usage() { pub fn run() -> Result<(), String> { let mut check = false; // We skip binary name and the `info` command. - let mut args = std::env::args().skip(2); - while let Some(arg) = args.next() { + let args = std::env::args().skip(2); + for arg in args { match arg.as_str() { "--help" => { show_usage(); return Ok(()); } "--check" => check = true, - _ => return Err(format!("Unknown option {}", arg)), + _ => return Err(format!("Unknown option {arg}")), } } let cmd: &[&dyn AsRef<OsStr>] = if check { &[&"cargo", &"fmt", &"--check"] } else { &[&"cargo", &"fmt"] }; - run_command_with_output(cmd, Some(&Path::new(".")))?; - run_command_with_output(cmd, Some(&Path::new("build_system"))) + run_command_with_output(cmd, Some(Path::new(".")))?; + run_command_with_output(cmd, Some(Path::new("build_system"))) } diff --git a/compiler/rustc_codegen_gcc/build_system/src/fuzz.rs b/compiler/rustc_codegen_gcc/build_system/src/fuzz.rs new file mode 100644 index 00000000000..453211366b3 --- /dev/null +++ b/compiler/rustc_codegen_gcc/build_system/src/fuzz.rs @@ -0,0 +1,289 @@ +use std::ffi::OsStr; +use std::path::Path; + +mod reduce; + +use crate::utils::run_command_with_output; + +fn show_usage() { + println!( + r#" +`fuzz` command help: + --reduce : Reduces a file generated by rustlantis + --help : Show this help + --start : Start of the fuzzed range + --count : The number of cases to fuzz + -j --jobs : The number of threads to use during fuzzing"# + ); +} + +pub fn run() -> Result<(), String> { + // We skip binary name and the `fuzz` command. + let mut args = std::env::args().skip(2); + let mut start = 0; + let mut count = 100; + let mut threads = + std::thread::available_parallelism().map(|threads| threads.get()).unwrap_or(1); + while let Some(arg) = args.next() { + match arg.as_str() { + "--reduce" => { + let Some(path) = args.next() else { + return Err("--reduce must be provided with a path".into()); + }; + if !std::fs::exists(&path).unwrap_or(false) { + return Err("--reduce must be provided with a valid path".into()); + } + reduce::reduce(&path); + return Ok(()); + } + "--help" => { + show_usage(); + return Ok(()); + } + "--start" => { + start = + str::parse(&args.next().ok_or_else(|| "Fuzz start not provided!".to_string())?) + .map_err(|err| (format!("Fuzz start not a number {err:?}!")))?; + } + "--count" => { + count = + str::parse(&args.next().ok_or_else(|| "Fuzz count not provided!".to_string())?) + .map_err(|err| (format!("Fuzz count not a number {err:?}!")))?; + } + "-j" | "--jobs" => { + threads = str::parse( + &args.next().ok_or_else(|| "Fuzz thread count not provided!".to_string())?, + ) + .map_err(|err| (format!("Fuzz thread count not a number {err:?}!")))?; + } + _ => return Err(format!("Unknown option {arg}")), + } + } + + // Ensure that we have a cloned version of rustlantis on hand. + crate::utils::git_clone( + "https://github.com/cbeuw/rustlantis.git", + Some("clones/rustlantis".as_ref()), + true, + ) + .map_err(|err| (format!("Git clone failed with message: {err:?}!")))?; + + // Ensure that we are on the newest rustlantis commit. + let cmd: &[&dyn AsRef<OsStr>] = &[&"git", &"pull", &"origin"]; + run_command_with_output(cmd, Some(Path::new("clones/rustlantis")))?; + + // Build the release version of rustlantis + let cmd: &[&dyn AsRef<OsStr>] = &[&"cargo", &"build", &"--release"]; + run_command_with_output(cmd, Some(Path::new("clones/rustlantis")))?; + // Fuzz a given range + fuzz_range(start, start + count, threads); + Ok(()) +} + +/// Fuzzes a range `start..end` with `threads`. +fn fuzz_range(start: u64, end: u64, threads: usize) { + use std::sync::Arc; + use std::sync::atomic::{AtomicU64, Ordering}; + use std::time::{Duration, Instant}; + // Total amount of files to fuzz + let total = end - start; + // Currently fuzzed element + let start = Arc::new(AtomicU64::new(start)); + // Count time during fuzzing + let start_time = Instant::now(); + let mut workers = Vec::with_capacity(threads); + // Spawn `threads`.. + for _ in 0..threads { + let start = start.clone(); + // .. which each will .. + workers.push(std::thread::spawn(move || { + // ... grab the next fuzz seed ... + while start.load(Ordering::Relaxed) < end { + let next = start.fetch_add(1, Ordering::Relaxed); + // .. test that seed . + match test(next, false) { + Err(err) => { + // If the test failed at compile-time... + println!("test({next}) failed because {err:?}"); + // ... copy that file to the directory `target/fuzz/compiletime_error`... + let mut out_path: std::path::PathBuf = + "target/fuzz/compiletime_error".into(); + std::fs::create_dir_all(&out_path).unwrap(); + // .. into a file named `fuzz{seed}.rs`. + out_path.push(format!("fuzz{next}.rs")); + std::fs::copy(err, out_path).unwrap(); + } + Ok(Err(err)) => { + // If the test failed at run-time... + println!("The LLVM and GCC results don't match for {err:?}"); + // ... generate a new file, which prints temporaries(instead of hashing them)... + let mut out_path: std::path::PathBuf = "target/fuzz/runtime_error".into(); + std::fs::create_dir_all(&out_path).unwrap(); + let Ok(Err(tmp_print_err)) = test(next, true) else { + // ... if that file does not reproduce the issue... + // ... save the original sample in a file named `fuzz{seed}.rs`... + out_path.push(format!("fuzz{next}.rs")); + std::fs::copy(err, &out_path).unwrap(); + continue; + }; + // ... if that new file still produces the issue, copy it to `fuzz{seed}.rs`.. + out_path.push(format!("fuzz{next}.rs")); + std::fs::copy(tmp_print_err, &out_path).unwrap(); + // ... and start reducing it, using some properties of `rustlantis` to speed up the process. + reduce::reduce(&out_path); + } + // If the test passed, do nothing + Ok(Ok(())) => (), + } + } + })); + } + // The "manager" thread loop. + while start.load(Ordering::Relaxed) < end || !workers.iter().all(|t| t.is_finished()) { + // Every 500 ms... + let five_hundred_millis = Duration::from_millis(500); + std::thread::sleep(five_hundred_millis); + // ... calculate the remaining fuzz iters ... + let remaining = end - start.load(Ordering::Relaxed); + // ... fix the count(the start counter counts the cases that + // begun fuzzing, and not only the ones that are done)... + let fuzzed = (total - remaining).saturating_sub(threads as u64); + // ... and the fuzz speed ... + let iter_per_sec = fuzzed as f64 / start_time.elapsed().as_secs_f64(); + // .. and use them to display fuzzing stats. + println!( + "fuzzed {fuzzed} cases({}%), at rate {iter_per_sec} iter/s, remaining ~{}s", + (100 * fuzzed) as f64 / total as f64, + (remaining as f64) / iter_per_sec + ) + } + drop(workers); +} + +/// Builds & runs a file with LLVM. +fn debug_llvm(path: &std::path::Path) -> Result<Vec<u8>, String> { + // Build a file named `llvm_elf`... + let exe_path = path.with_extension("llvm_elf"); + // ... using the LLVM backend ... + let output = std::process::Command::new("rustc") + .arg(path) + .arg("-o") + .arg(&exe_path) + .output() + .map_err(|err| format!("{err:?}"))?; + // ... check that the compilation succeeded ... + if !output.status.success() { + return Err(format!("LLVM compilation failed:{output:?}")); + } + // ... run the resulting executable ... + let output = + std::process::Command::new(&exe_path).output().map_err(|err| format!("{err:?}"))?; + // ... check it run normally ... + if !output.status.success() { + return Err(format!( + "The program at {path:?}, compiled with LLVM, exited unsuccessfully:{output:?}" + )); + } + // ... cleanup that executable ... + std::fs::remove_file(exe_path).map_err(|err| format!("{err:?}"))?; + // ... and return the output(stdout + stderr - this allows UB checks to fire). + let mut res = output.stdout; + res.extend(output.stderr); + Ok(res) +} + +/// Builds & runs a file with GCC. +fn release_gcc(path: &std::path::Path) -> Result<Vec<u8>, String> { + // Build a file named `gcc_elf`... + let exe_path = path.with_extension("gcc_elf"); + // ... using the GCC backend ... + let output = std::process::Command::new("./y.sh") + .arg("rustc") + .arg(path) + .arg("-O") + .arg("-o") + .arg(&exe_path) + .output() + .map_err(|err| format!("{err:?}"))?; + // ... check that the compilation succeeded ... + if !output.status.success() { + return Err(format!("GCC compilation failed:{output:?}")); + } + // ... run the resulting executable .. + let output = + std::process::Command::new(&exe_path).output().map_err(|err| format!("{err:?}"))?; + // ... check it run normally ... + if !output.status.success() { + return Err(format!( + "The program at {path:?}, compiled with GCC, exited unsuccessfully:{output:?}" + )); + } + // ... cleanup that executable ... + std::fs::remove_file(exe_path).map_err(|err| format!("{err:?}"))?; + // ... and return the output(stdout + stderr - this allows UB checks to fire). + let mut res = output.stdout; + res.extend(output.stderr); + Ok(res) +} +type ResultCache = Option<(Vec<u8>, Vec<u8>)>; +/// Generates a new rustlantis file, & compares the result of running it with GCC and LLVM. +fn test(seed: u64, print_tmp_vars: bool) -> Result<Result<(), std::path::PathBuf>, String> { + // Generate a Rust source... + let source_file = generate(seed, print_tmp_vars)?; + test_file(&source_file, true) +} +/// Tests a file with a cached LLVM result. Used for reduction, when it is known +/// that a given transformation should not change the execution result. +fn test_cached( + source_file: &Path, + remove_tmps: bool, + cache: &mut ResultCache, +) -> Result<Result<(), std::path::PathBuf>, String> { + // Test `source_file` with release GCC ... + let gcc_res = release_gcc(source_file)?; + if cache.is_none() { + // ...test `source_file` with debug LLVM ... + *cache = Some((debug_llvm(source_file)?, gcc_res.clone())); + } + let (llvm_res, old_gcc) = cache.as_ref().unwrap(); + // ... compare the results ... + if *llvm_res != gcc_res && gcc_res == *old_gcc { + // .. if they don't match, report an error. + Ok(Err(source_file.to_path_buf())) + } else { + if remove_tmps { + std::fs::remove_file(source_file).map_err(|err| format!("{err:?}"))?; + } + Ok(Ok(())) + } +} +fn test_file( + source_file: &Path, + remove_tmps: bool, +) -> Result<Result<(), std::path::PathBuf>, String> { + let mut uncached = None; + test_cached(source_file, remove_tmps, &mut uncached) +} + +/// Generates a new rustlantis file for us to run tests on. +fn generate(seed: u64, print_tmp_vars: bool) -> Result<std::path::PathBuf, String> { + use std::io::Write; + let mut out_path = std::env::temp_dir(); + out_path.push(format!("fuzz{seed}.rs")); + // We need to get the command output here. + let mut generate = std::process::Command::new("cargo"); + generate + .args(["run", "--release", "--bin", "generate"]) + .arg(format!("{seed}")) + .current_dir("clones/rustlantis"); + if print_tmp_vars { + generate.arg("--debug"); + } + let out = generate.output().map_err(|err| format!("{err:?}"))?; + // Stuff the rustlantis output in a source file. + std::fs::File::create(&out_path) + .map_err(|err| format!("{err:?}"))? + .write_all(&out.stdout) + .map_err(|err| format!("{err:?}"))?; + Ok(out_path) +} diff --git a/compiler/rustc_codegen_gcc/build_system/src/fuzz/reduce.rs b/compiler/rustc_codegen_gcc/build_system/src/fuzz/reduce.rs new file mode 100644 index 00000000000..20715ab0e7c --- /dev/null +++ b/compiler/rustc_codegen_gcc/build_system/src/fuzz/reduce.rs @@ -0,0 +1,432 @@ +use std::io::Write; +use std::path::{Path, PathBuf}; + +use super::ResultCache; + +/// Saves a reduced file for a given `stage` +fn save_reduction(lines: &[String], path: &Path, stage: &str) { + let mut path = path.to_path_buf(); + path.set_extension(format!("rs.{stage}")); + let mut file = std::fs::File::create(&path).expect("Could not create the reduced example file"); + for line in lines { + file.write_all(line.as_bytes()).expect("Could not save the reduced example"); + } +} + +/// Checks if a given reduction is valid. +fn test_reduction(lines: &[String], path: &Path, cache: &mut ResultCache) -> bool { + let mut path = path.to_path_buf(); + path.set_extension("rs_reduced"); + let mut file = std::fs::File::create(&path).expect("Could not create the reduced example file"); + for line in lines { + file.write_all(line.as_bytes()).expect("Could not save the reduced example"); + } + let res = super::test_cached(&path, false, cache); + let Ok(Err(_)) = res else { + return false; + }; + true +} + +/// Removes duplicate assignments in bulk. +/// If a line A = B is followed directly by A = C, +/// then removing the first line ought to be fully sound, +/// and not change the behaviour of the program at all. Detect & remove such lines. +fn remove_dup_assign( + file: &mut Vec<String>, + path: &PathBuf, + starts: usize, + ends: usize, + cache: &mut ResultCache, +) { + let mut file_copy = file.clone(); + let mut reduction_count = 0; + // Not worth it. + if ends - starts < 8 { + return; + } + for index in starts..ends { + let Some((prefix, _)) = file_copy[index].split_once('=') else { + continue; + }; + let Some((prefix2, postifx2)) = file_copy[index + 1].split_once('=') else { + continue; + }; + let prefix = prefix.trim(); + let prefix2 = prefix2.trim(); + // FIXME: Right now, remove_dup_assign cares about assignments to the exact same place. + // However, given an assigemnt like this: + // ``` + // A.0 = 1_u32; + // A = (2_u32, 3.0); + // ``` + // The first assignment could be safely omitted. + // Additionally, we try to check if the second assignment could depend on the first one. + // In such cases, the result is likely to change, so we bail. + if prefix == prefix2 && !postifx2.contains(prefix) { + file_copy[index] = "".into(); + reduction_count += 1; + } + } + // We have removed no lines - no point in testing. + if reduction_count == 0 { + return; + } + // Check if the removed lines affected the execution result in any way, shape or form. + if test_reduction(&file_copy, path, cache) { + println!("Reduced {path:?} by {reduction_count} lines `remove_dup_assign`"); + *file = file_copy; + } else { + // The execution result changed. + // This can occur if the second assignment depended on the first one. + // Eg. + // ``` + // a = b + c; + // a = a + d; + // ``` + remove_dup_assign(file, path, starts, (starts + ends) / 2, cache); + remove_dup_assign(file, path, (starts + ends) / 2, ends, cache); + } + save_reduction(file, path, "remove_dup_assign"); +} + +/// Removes all the unneeded calls to `dump_var`. This is not something tools like `cvise` can do, +/// but it greately speeds up MIR interpretation + native execution. +fn remove_dump_var(file: &mut Vec<String>, path: &PathBuf) { + let mut curr = 0; + // ... try disabling `dump_vars` one by one, until only the necessary ones are left. + while curr < file.len() { + let Some(line) = file[curr..].iter().position(|line| line.contains("dump_var")) else { + // No more `dump_var`s to remove - exit early. + break; + }; + // Make the line absolute again. + let line = line + curr; + let mut file_copy = file.clone(); + // Try removing 3 consecutive lines(the call, block end and block beginning). This effectively removes a `dump_var`. + file_copy.remove(line); + file_copy.remove(line); + file_copy.remove(line); + // Not cached - the execution result can change. + let mut uncached = None; + // Check if this reduction is valid. + if test_reduction(&file_copy, path, &mut uncached) { + println!("Reduced {path:?} by 3 lines `remove_dump_var`"); + *file = file_copy; + curr = line; + } else { + curr = line + 1; + } + } + save_reduction(file, path, "remove_dump_var"); +} + +/// Replaces matches with gotos where possible. +/// This exploits some properties of rustlantis(match arm order), +/// and is only soundly applicable to MIR generated by it. +/// Still, it is not something `cvise` can do, but it simplifies the code a ton. +fn match_to_goto(file: &mut Vec<String>, path: &PathBuf, cache: &mut ResultCache) { + let mut curr = 0; + + while curr < file.len() { + let Some(match_starts) = file[curr..].iter().position(|line| line.contains("match")) else { + // No more `match`es to remove - exit early. + break; + }; + let match_starts = match_starts + curr; + // Find the end of the match + let Some(match_ends) = file[match_starts..].iter().position(|line| line.contains('}')) + else { + // Can't find match end - exit early. + break; + }; + let match_ends = match_ends + match_starts; + let match_body = &file[match_starts..match_ends]; + + // Find where this match should normally jump to. + // This *should* be the second-last arm of the match, as per the paper(the remaining blocks are decoys). + // If this ever changes, this reduction may not always be sound. + // This is not a problem, however: we NEED to use MIRI for reduction anwyway, + // and it will catch this issue. + let jumps_to = &match_body[match_body.len() - 2].trim(); + let Some((_, bb_ident)) = jumps_to.split_once("bb") else { + break; + }; + // We now have the number of the block we jump to at runtime. + let bb_ident = bb_ident.trim_matches(','); + // Try replacing this match with an unconditional jump. + let mut file_copy = file.clone(); + for _ in match_starts..(match_ends + 1) { + file_copy.remove(match_starts); + } + file_copy.insert(match_starts, format!("Goto(bb{bb_ident})\n")); + if test_reduction(&file_copy, path, cache) { + println!("Reduced {path:?} by {} lines `match_to_goto`", match_ends - match_starts); + *file = file_copy; + curr = match_starts; + } else { + curr = match_ends; + } + } + save_reduction(file, path, "match_to_goto"); +} + +/// At this point, we can try "killing" blocks, by replacing their bodies with calls to `abort`. +/// This is always sound(the program aborts, so no UB can occur after the block), +/// and allows us to safely remove *a lot* of unneeded blocks. +fn block_abort(file: &mut Vec<String>, path: &PathBuf, cache: &mut ResultCache) { + let mut curr = 0; + while curr < file.len() { + let Some(block_starts) = file[curr..] + .iter() + .position(|line| line.starts_with("bb") && line.trim_end().ends_with(" = {")) + else { + // No more `block`s to kill - exit early. + break; + }; + let block_starts = block_starts + curr; + // Find the beginning of the next block to find the end of this block. + let Some(block_ends) = file[(block_starts + 1)..] + .iter() + .position(|line| line.starts_with("bb") && line.trim_end().ends_with(" = {")) + else { + // No more `block`s to kill - exit early. + break; + }; + let block_ends = block_starts + block_ends; + let block_starts = block_starts + 1; + let mut file_copy = file.clone(); + // Remove the block body... + for _ in block_starts..(block_ends) { + file_copy.remove(block_starts); + } + // ..and insert an unconditional call to abort. + file_copy.insert( + block_starts, + "Call(tmp = core::intrinsics::abort(), ReturnTo(bb1), UnwindUnreachable())\n" + .to_string(), + ); + file_copy.insert(block_starts, "let tmp = ();\n".to_string()); + + if test_reduction(&file_copy, path, cache) { + println!("Reduced {path:?} by {} lines `block_abort`", block_ends - block_starts - 2); + *file = file_copy; + curr = block_starts; + } else { + curr = block_ends; + } + } + save_reduction(file, path, "block_abort"); +} + +/// Removes unreachable basic blocks +fn remove_block(file: &mut Vec<String>, path: &PathBuf, cache: &mut ResultCache) { + let mut curr = 0; + + // Next, we try to outright remove blocks. + while curr < file.len() { + let Some(block_starts) = file[curr..] + .iter() + .position(|line| line.starts_with("bb") && line.trim_end().ends_with(" = {")) + else { + // No more `block`s to remove - exit early. + break; + }; + let block_starts = block_starts + curr; + // Find the beginning of the next block to find the end of this block. + let Some(block_ends) = file[(block_starts + 1)..] + .iter() + .position(|line| line.starts_with("bb") && line.trim_end().ends_with(" = {")) + else { + // No more `block`s to remove - exit early. + break; + }; + let block_ends = block_starts + block_ends + 1; + // Large blocks are likely to be necessary. + if block_ends - block_starts > 6 { + curr = block_starts + 1; + continue; + } + let mut file_copy = file.clone(); + file_copy.drain(block_starts..block_ends); + if test_reduction(&file_copy, path, cache) { + println!("Reduced {path:?} by {} lines `remove_blocks`", block_ends - block_starts); + *file = file_copy; + curr = block_starts; + } else { + curr = block_starts + 1; + } + } + save_reduction(file, path, "remove_block"); +} + +/// Merges blocks ending with unconditional jumps. +fn linearize_cf(file: &mut Vec<String>, path: &PathBuf, cache: &mut ResultCache) { + let mut curr = 0; + + // Next, we try to linearize the control flow. What the does that mean? + // Given a sequence like this: + // Goto(bb22) + // } + // bb22 = { + // We remove those 3 lines, merging the blocks together. This is not something `cvise` can do, + // and it makes other transformations easier. + while curr < file.len() { + let Some(block_starts) = file[curr..] + .iter() + .position(|line| line.starts_with("bb") && line.trim_end().ends_with(" = {")) + else { + // No more `block`s to remove - exit early. + break; + }; + let block_starts = block_starts + curr; + // Extract the block id. + let Some((block, _)) = file[block_starts].split_once('=') else { + curr = block_starts + 1; + continue; + }; + let block = block.trim(); + if file[block_starts - 2].trim() != format!("Goto({block})") { + curr = block_starts + 1; + continue; + } + let mut file_copy = file.clone(); + // Try removing 3 consecutive lines(the goto, block end and block beginning). This effectively removes a `Goto(next)`. + file_copy.remove(block_starts - 2); + file_copy.remove(block_starts - 2); + file_copy.remove(block_starts - 2); + // Check if this reduction is valid. + if test_reduction(&file_copy, path, cache) { + println!("Reduced {path:?} by 3 lines `linearize_cf`"); + *file = file_copy; + curr = block_starts; + } else { + curr = block_starts + 1; + } + } + save_reduction(file, path, "linearize_cf"); +} + +/// Replaces a call to a given function with a 0 assignment to the destination place, and a Goto. +/// This is always sound, because: +/// 1. All the functions arguments are always initialized +/// 2. and point to initialized memory(the operand of &raw must be an initialized place in rustlantis). +fn remove_fn_calls(file: &mut Vec<String>, path: &PathBuf, cache: &mut ResultCache) { + let mut curr = 0; + + while curr < file.len() { + let Some(fn_call) = + file[curr..].iter().position(|line| line.contains("Call(") && line.contains(" = fn")) + else { + // No more calls to remove - exit early. + break; + }; + let fn_call = fn_call + curr; + let line = file[fn_call].trim(); + // Skip the Call( + let line = &line["Call(".len()..]; + // Extract the destination place + let Some((place, line)) = line.split_once('=') else { + curr = fn_call + 1; + continue; + }; + // Skip till the return block id. + let Some((_, line)) = line.split_once("ReturnTo(") else { + curr = fn_call + 1; + continue; + }; + // Extract the full return block + let Some((block, _)) = line.split_once(')') else { + curr = fn_call + 1; + continue; + }; + let mut file_copy = file.clone(); + // Remove the call. + file_copy.remove(fn_call); + file_copy.insert(fn_call, format!("Goto({block})\n")); + file_copy.insert(fn_call, format!("{place} = 0;\n")); + // Check if this reduction is valid. + if test_reduction(&file_copy, path, cache) { + println!("Reduced {path:?} using `remove_fn_calls` {cache:?}"); + *file = file_copy; + curr = fn_call; + } else { + curr = fn_call + 1; + } + } + save_reduction(file, path, "remove_fn_calls"); +} + +/// Fully removes unreachable functions. +fn remove_fns(file: &mut Vec<String>, path: &PathBuf, cache: &mut ResultCache) { + let mut curr = 0; + + while curr < file.len() { + // Find a function start + let Some(fn_start) = file[curr..].iter().position(|line| { + line.contains("#[custom_mir(dialect = \"runtime\", phase = \"initial\")]") + }) else { + // No more functions to remove - exit early. + break; + }; + // Find the next function(and use that to find the end of this one). + // FIXME: this check is flawed: it will never remove the very last function(the one before main). + // The other checks will turn that function into a single call to abort, but it is still annoying that it is kept. + let fn_start = fn_start + curr; + let Some(fn_end) = file[(fn_start + 3)..].iter().position(|line| line.contains("fn fn")) + else { + // No more functions to remove - exit early. + break; + }; + let fn_end = fn_start + 2 + fn_end; + let mut file_copy = file.clone(); + // Remove the function.\\ + file_copy.drain(fn_start..fn_end); + // Check if this reduction is valid. + if test_reduction(&file_copy, path, cache) { + println!("Reduced {path:?} by {} lines `remove_fns`", fn_end - fn_start); + *file = file_copy; + } else { + curr = fn_start + 1; + } + } + save_reduction(file, path, "remove_fns"); +} + +pub(super) fn reduce(path: impl AsRef<Path>) { + let path = path.as_ref().to_owned(); + // ... read the file to a buffer .. + let file = std::fs::read_to_string(&path).expect("Could not open the file to reduce"); + let mut file: Vec<_> = file.split_inclusive('\n').map(|s| s.to_string()).collect(); + + // ... and run reduction passes. + println!("running `remove_dump_var` on {path:?}."); + remove_dump_var(&mut file, &path); + // After `dump_var`, the execution results ought not to change. Cache them. + let mut cache = None; + // Fill the cache + assert!( + test_reduction(&file, &path, &mut cache), + "Reduction error: check that the input file is a valid reproducer." + ); + println!("cache:{cache:?}"); + println!("running `remove_fn_calls` on {path:?}."); + remove_fn_calls(&mut file, &path, &mut cache); + println!("running `remove_fns` on {path:?}."); + remove_fns(&mut file, &path, &mut cache); + let len = file.len(); + println!("running `remove_dup_assign` on {path:?}."); + remove_dup_assign(&mut file, &path, 0, len, &mut cache); + file.retain(|line| !line.is_empty()); + println!("running `match_to_goto` on {path:?}."); + match_to_goto(&mut file, &path, &mut cache); + println!("running `block_abort` on {path:?}."); + block_abort(&mut file, &path, &mut cache); + println!("running `remove_block` on {path:?}."); + remove_block(&mut file, &path, &mut cache); + println!("running `linearize_cf` on {path:?}."); + linearize_cf(&mut file, &path, &mut cache); + let mut out = std::fs::File::create(&path).expect("Could not save the reduction result."); + let file = file.into_iter().collect::<String>(); + out.write_all(file.as_bytes()).expect("failed to write into file"); +} diff --git a/compiler/rustc_codegen_gcc/build_system/src/info.rs b/compiler/rustc_codegen_gcc/build_system/src/info.rs index bd891de2eb4..66fdcf88cbb 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/info.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/info.rs @@ -15,7 +15,7 @@ pub fn run() -> Result<(), String> { config.no_download = true; config.setup_gcc_path()?; if let Some(gcc_path) = config.gcc_path { - println!("{}", gcc_path); + println!("{gcc_path}"); } Ok(()) } diff --git a/compiler/rustc_codegen_gcc/build_system/src/main.rs b/compiler/rustc_codegen_gcc/build_system/src/main.rs index c70b00e09ae..078a4726ba8 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/main.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/main.rs @@ -5,6 +5,7 @@ mod clean; mod clone_gcc; mod config; mod fmt; +mod fuzz; mod info; mod prepare; mod rust_tools; @@ -42,7 +43,8 @@ Commands: test : Runs tests for the project. info : Displays information about the build environment and project configuration. clone-gcc : Clones the GCC compiler from a specified source. - fmt : Runs rustfmt" + fmt : Runs rustfmt + fuzz : Fuzzes `cg_gcc` using rustlantis" ); } @@ -56,6 +58,7 @@ pub enum Command { Test, Info, Fmt, + Fuzz, } fn main() { @@ -75,6 +78,7 @@ fn main() { Some("info") => Command::Info, Some("clone-gcc") => Command::CloneGcc, Some("fmt") => Command::Fmt, + Some("fuzz") => Command::Fuzz, Some("--help") => { usage(); process::exit(0); @@ -97,6 +101,7 @@ fn main() { Command::Info => info::run(), Command::CloneGcc => clone_gcc::run(), Command::Fmt => fmt::run(), + Command::Fuzz => fuzz::run(), } { eprintln!("Command failed to run: {e}"); process::exit(1); diff --git a/compiler/rustc_codegen_gcc/build_system/src/prepare.rs b/compiler/rustc_codegen_gcc/build_system/src/prepare.rs index d14639afee5..35a6e20fb86 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/prepare.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/prepare.rs @@ -18,9 +18,9 @@ fn prepare_libcore( if let Some(path) = sysroot_source { rustlib_dir = Path::new(&path) .canonicalize() - .map_err(|error| format!("Failed to canonicalize path: {:?}", error))?; + .map_err(|error| format!("Failed to canonicalize path: {error:?}"))?; if !rustlib_dir.is_dir() { - return Err(format!("Custom sysroot path {:?} not found", rustlib_dir)); + return Err(format!("Custom sysroot path {rustlib_dir:?} not found")); } } else { let rustc_path = match get_rustc_path() { @@ -36,17 +36,17 @@ fn prepare_libcore( rustlib_dir = parent .join("../lib/rustlib/src/rust") .canonicalize() - .map_err(|error| format!("Failed to canonicalize path: {:?}", error))?; + .map_err(|error| format!("Failed to canonicalize path: {error:?}"))?; if !rustlib_dir.is_dir() { return Err("Please install `rust-src` component".to_string()); } } let sysroot_dir = sysroot_path.join("sysroot_src"); - if sysroot_dir.is_dir() { - if let Err(error) = fs::remove_dir_all(&sysroot_dir) { - return Err(format!("Failed to remove `{}`: {:?}", sysroot_dir.display(), error,)); - } + if sysroot_dir.is_dir() + && let Err(error) = fs::remove_dir_all(&sysroot_dir) + { + return Err(format!("Failed to remove `{}`: {:?}", sysroot_dir.display(), error,)); } let sysroot_library_dir = sysroot_dir.join("library"); @@ -122,7 +122,7 @@ fn prepare_rand() -> Result<(), String> { // Apply patch for the rand crate. let file_path = "patches/crates/0001-Remove-deny-warnings.patch"; let rand_dir = Path::new("build/rand"); - println!("[GIT] apply `{}`", file_path); + println!("[GIT] apply `{file_path}`"); let path = Path::new("../..").join(file_path); run_command_with_output(&[&"git", &"apply", &path], Some(rand_dir))?; run_command_with_output(&[&"git", &"add", &"-A"], Some(rand_dir))?; @@ -149,7 +149,7 @@ fn clone_and_setup<F>(repo_url: &str, checkout_commit: &str, extra: Option<F>) - where F: Fn(&Path) -> Result<(), String>, { - let clone_result = git_clone_root_dir(repo_url, &Path::new(crate::BUILD_DIR), false)?; + let clone_result = git_clone_root_dir(repo_url, Path::new(crate::BUILD_DIR), false)?; if !clone_result.ran_clone { println!("`{}` has already been cloned", clone_result.repo_name); } diff --git a/compiler/rustc_codegen_gcc/build_system/src/rust_tools.rs b/compiler/rustc_codegen_gcc/build_system/src/rust_tools.rs index 105f5eebe24..b1faa27acc4 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/rust_tools.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/rust_tools.rs @@ -1,24 +1,22 @@ use std::collections::HashMap; use std::ffi::OsStr; +#[cfg(unix)] +use std::os::unix::process::CommandExt; use std::path::PathBuf; use crate::config::ConfigInfo; -use crate::utils::{ - get_toolchain, run_command_with_output_and_env_no_err, rustc_toolchain_version_info, - rustc_version_info, -}; +use crate::utils::{get_toolchain, rustc_toolchain_version_info, rustc_version_info}; fn args(command: &str) -> Result<Option<Vec<String>>, String> { // We skip the binary and the "cargo"/"rustc" option. - if let Some("--help") = std::env::args().skip(2).next().as_deref() { + if let Some("--help") = std::env::args().nth(2).as_deref() { usage(command); return Ok(None); } let args = std::env::args().skip(2).collect::<Vec<_>>(); if args.is_empty() { return Err(format!( - "Expected at least one argument for `{}` subcommand, found none", - command + "Expected at least one argument for `{command}` subcommand, found none" )); } Ok(Some(args)) @@ -27,12 +25,11 @@ fn args(command: &str) -> Result<Option<Vec<String>>, String> { fn usage(command: &str) { println!( r#" -`{}` command help: +`{command}` command help: [args] : Arguments to be passed to the cargo command --help : Show this help "#, - command, ) } @@ -51,10 +48,10 @@ impl RustcTools { // expected. let current_dir = std::env::current_dir() .and_then(|path| path.canonicalize()) - .map_err(|error| format!("Failed to get current directory path: {:?}", error))?; + .map_err(|error| format!("Failed to get current directory path: {error:?}"))?; let current_exe = std::env::current_exe() .and_then(|path| path.canonicalize()) - .map_err(|error| format!("Failed to get current exe path: {:?}", error))?; + .map_err(|error| format!("Failed to get current exe path: {error:?}"))?; let mut parent_dir = current_exe.components().map(|comp| comp.as_os_str()).collect::<Vec<_>>(); // We run this script from "build_system/target/release/y", so we need to remove these elements. @@ -68,7 +65,7 @@ impl RustcTools { )); } } - let parent_dir = PathBuf::from(parent_dir.join(&OsStr::new("/"))); + let parent_dir = PathBuf::from(parent_dir.join(OsStr::new("/"))); std::env::set_current_dir(&parent_dir).map_err(|error| { format!("Failed to go to `{}` folder: {:?}", parent_dir.display(), error) })?; @@ -92,11 +89,31 @@ impl RustcTools { std::env::set_current_dir(¤t_dir).map_err(|error| { format!("Failed to go back to `{}` folder: {:?}", current_dir.display(), error) })?; - let toolchain = format!("+{}", toolchain); + let toolchain = format!("+{toolchain}"); Ok(Some(Self { toolchain, args, env, config })) } } +fn exec(input: &[&dyn AsRef<OsStr>], env: &HashMap<String, String>) -> Result<(), String> { + #[cfg(unix)] + { + // We use `exec` to call the `execvp` syscall instead of creating a new process where the + // command will be executed because very few signals can actually kill a current process, + // so if segmentation fault (SIGSEGV signal) happens and we raise to the current process, + // it will simply do nothing and we won't have the nice error message for the shell. + let error = crate::utils::get_command_inner(input, None, Some(env)).exec(); + eprintln!("execvp syscall failed: {error:?}"); + std::process::exit(1); + } + #[cfg(not(unix))] + { + if crate::utils::run_command_with_output_and_env_no_err(input, None, Some(env)).is_err() { + std::process::exit(1); + } + Ok(()) + } +} + pub fn run_cargo() -> Result<(), String> { let Some(mut tools) = RustcTools::new("cargo")? else { return Ok(()) }; let rustflags = tools.env.get("RUSTFLAGS").cloned().unwrap_or_default(); @@ -105,11 +122,7 @@ pub fn run_cargo() -> Result<(), String> { for arg in &tools.args { command.push(arg); } - if run_command_with_output_and_env_no_err(&command, None, Some(&tools.env)).is_err() { - std::process::exit(1); - } - - Ok(()) + exec(&command, &tools.env) } pub fn run_rustc() -> Result<(), String> { @@ -118,8 +131,5 @@ pub fn run_rustc() -> Result<(), String> { for arg in &tools.args { command.push(arg); } - if run_command_with_output_and_env_no_err(&command, None, Some(&tools.env)).is_err() { - std::process::exit(1); - } - Ok(()) + exec(&command, &tools.env) } diff --git a/compiler/rustc_codegen_gcc/build_system/src/test.rs b/compiler/rustc_codegen_gcc/build_system/src/test.rs index df4ac85233b..bcaab0fb526 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/test.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/test.rs @@ -9,8 +9,8 @@ use crate::build; use crate::config::{Channel, ConfigInfo}; use crate::utils::{ create_dir, get_sysroot_dir, get_toolchain, git_clone, git_clone_root_dir, remove_file, - run_command, run_command_with_env, run_command_with_output_and_env, rustc_version_info, - split_args, walk_dir, + run_command, run_command_with_env, run_command_with_output, run_command_with_output_and_env, + rustc_version_info, split_args, walk_dir, }; type Env = HashMap<String, String>; @@ -42,7 +42,7 @@ fn get_runners() -> Runners { ); runners.insert("--extended-regex-tests", ("Run extended regex tests", extended_regex_tests)); runners.insert("--mini-tests", ("Run mini tests", mini_tests)); - + runners.insert("--cargo-tests", ("Run cargo tests", cargo_tests)); runners } @@ -53,9 +53,9 @@ fn get_number_after_arg( match args.next() { Some(nb) if !nb.is_empty() => match usize::from_str(&nb) { Ok(nb) => Ok(nb), - Err(_) => Err(format!("Expected a number after `{}`, found `{}`", option, nb)), + Err(_) => Err(format!("Expected a number after `{option}`, found `{nb}`")), }, - _ => Err(format!("Expected a number after `{}`, found nothing", option)), + _ => Err(format!("Expected a number after `{option}`, found nothing")), } } @@ -76,8 +76,8 @@ fn show_usage() { for (option, (doc, _)) in get_runners() { // FIXME: Instead of using the hard-coded `23` value, better to compute it instead. let needed_spaces = 23_usize.saturating_sub(option.len()); - let spaces: String = std::iter::repeat(' ').take(needed_spaces).collect(); - println!(" {}{}: {}", option, spaces, doc); + let spaces: String = std::iter::repeat_n(' ', needed_spaces).collect(); + println!(" {option}{spaces}: {doc}"); } println!(" --help : Show this help"); } @@ -88,6 +88,8 @@ struct TestArg { use_system_gcc: bool, runners: Vec<String>, flags: Vec<String>, + /// Additional arguments, to be passed to commands like `cargo test`. + test_args: Vec<String>, nb_parts: Option<usize>, current_part: Option<usize>, sysroot_panic_abort: bool, @@ -137,13 +139,14 @@ impl TestArg { test_arg.sysroot_features.push(feature); } _ => { - return Err(format!("Expected an argument after `{}`, found nothing", arg)); + return Err(format!("Expected an argument after `{arg}`, found nothing")); } }, "--help" => { show_usage(); return Ok(None); } + "--" => test_arg.test_args.extend(&mut args), x if runners.contains_key(x) && !test_arg.runners.iter().any(|runner| runner == x) => { @@ -151,7 +154,7 @@ impl TestArg { } arg => { if !test_arg.config_info.parse_argument(arg, &mut args)? { - return Err(format!("Unknown option {}", arg)); + return Err(format!("Unknown option {arg}")); } } } @@ -189,7 +192,7 @@ fn build_if_no_backend(env: &Env, args: &TestArg) -> Result<(), String> { command.push(&"--release"); &tmp_env } else { - &env + env }; for flag in args.flags.iter() { command.push(flag); @@ -203,6 +206,33 @@ fn clean(_env: &Env, args: &TestArg) -> Result<(), String> { create_dir(&path) } +fn cargo_tests(test_env: &Env, test_args: &TestArg) -> Result<(), String> { + // First, we call `mini_tests` to build minicore for us. This ensures we are testing with a working `minicore`, + // and that any changes we have made affect `minicore`(since it would get rebuilt). + mini_tests(test_env, test_args)?; + // Then, we copy some of the env vars from `test_env` + // We don't want to pass things like `RUSTFLAGS`, since they contain the -Zcodegen-backend flag. + // That would force `cg_gcc` to *rebuild itself* and only then run tests, which is undesirable. + let mut env = HashMap::new(); + env.insert( + "LD_LIBRARY_PATH".into(), + test_env.get("LD_LIBRARY_PATH").expect("LD_LIBRARY_PATH missing!").to_string(), + ); + env.insert( + "LIBRARY_PATH".into(), + test_env.get("LIBRARY_PATH").expect("LIBRARY_PATH missing!").to_string(), + ); + env.insert( + "CG_RUSTFLAGS".into(), + test_env.get("CG_RUSTFLAGS").map(|s| s.as_str()).unwrap_or("").to_string(), + ); + // Pass all the default args + the user-specified ones. + let mut args: Vec<&dyn AsRef<OsStr>> = vec![&"cargo", &"test"]; + args.extend(test_args.test_args.iter().map(|s| s as &dyn AsRef<OsStr>)); + run_command_with_output_and_env(&args, None, Some(&env))?; + Ok(()) +} + fn mini_tests(env: &Env, args: &TestArg) -> Result<(), String> { // FIXME: create a function "display_if_not_quiet" or something along the line. println!("[BUILD] mini_core"); @@ -222,7 +252,7 @@ fn mini_tests(env: &Env, args: &TestArg) -> Result<(), String> { &"--target", &args.config_info.target_triple, ]); - run_command_with_output_and_env(&command, None, Some(&env))?; + run_command_with_output_and_env(&command, None, Some(env))?; // FIXME: create a function "display_if_not_quiet" or something along the line. println!("[BUILD] example"); @@ -234,7 +264,7 @@ fn mini_tests(env: &Env, args: &TestArg) -> Result<(), String> { &"--target", &args.config_info.target_triple, ]); - run_command_with_output_and_env(&command, None, Some(&env))?; + run_command_with_output_and_env(&command, None, Some(env))?; // FIXME: create a function "display_if_not_quiet" or something along the line. println!("[AOT] mini_core_hello_world"); @@ -249,14 +279,14 @@ fn mini_tests(env: &Env, args: &TestArg) -> Result<(), String> { &"--target", &args.config_info.target_triple, ]); - run_command_with_output_and_env(&command, None, Some(&env))?; + run_command_with_output_and_env(&command, None, Some(env))?; let command: &[&dyn AsRef<OsStr>] = &[ &Path::new(&args.config_info.cargo_target_dir).join("mini_core_hello_world"), &"abc", &"bcd", ]; - maybe_run_command_in_vm(&command, env, args)?; + maybe_run_command_in_vm(command, env, args)?; Ok(()) } @@ -454,22 +484,47 @@ fn setup_rustc(env: &mut Env, args: &TestArg) -> Result<PathBuf, String> { } else { run_command_with_output_and_env(&[&"git", &"checkout"], rust_dir, Some(env))?; } + + let mut patches = Vec::new(); + walk_dir( + "patches/tests", + &mut |_| Ok(()), + &mut |file_path: &Path| { + patches.push(file_path.to_path_buf()); + Ok(()) + }, + false, + )?; + patches.sort(); + // TODO: remove duplication with prepare.rs by creating a apply_patch function in the utils + // module. + for file_path in patches { + println!("[GIT] apply `{}`", file_path.display()); + let path = Path::new("../..").join(file_path); + run_command_with_output(&[&"git", &"apply", &path], rust_dir)?; + run_command_with_output(&[&"git", &"add", &"-A"], rust_dir)?; + run_command_with_output( + &[&"git", &"commit", &"--no-gpg-sign", &"-m", &format!("Patch {}", path.display())], + rust_dir, + )?; + } + let cargo = String::from_utf8( run_command_with_env(&[&"rustup", &"which", &"cargo"], rust_dir, Some(env))?.stdout, ) - .map_err(|error| format!("Failed to retrieve cargo path: {:?}", error)) + .map_err(|error| format!("Failed to retrieve cargo path: {error:?}")) .and_then(|cargo| { let cargo = cargo.trim().to_owned(); - if cargo.is_empty() { Err(format!("`cargo` path is empty")) } else { Ok(cargo) } + if cargo.is_empty() { Err("`cargo` path is empty".to_string()) } else { Ok(cargo) } })?; let rustc = String::from_utf8( run_command_with_env(&[&"rustup", &toolchain, &"which", &"rustc"], rust_dir, Some(env))? .stdout, ) - .map_err(|error| format!("Failed to retrieve rustc path: {:?}", error)) + .map_err(|error| format!("Failed to retrieve rustc path: {error:?}")) .and_then(|rustc| { let rustc = rustc.trim().to_owned(); - if rustc.is_empty() { Err(format!("`rustc` path is empty")) } else { Ok(rustc) } + if rustc.is_empty() { Err("`rustc` path is empty".to_string()) } else { Ok(rustc) } })?; let llvm_filecheck = match run_command_with_env( &[ @@ -479,7 +534,8 @@ fn setup_rustc(env: &mut Env, args: &TestArg) -> Result<PathBuf, String> { which FileCheck-11 || \ which FileCheck-12 || \ which FileCheck-13 || \ - which FileCheck-14", + which FileCheck-14 || \ + which FileCheck", ], rust_dir, Some(env), @@ -487,13 +543,15 @@ fn setup_rustc(env: &mut Env, args: &TestArg) -> Result<PathBuf, String> { Ok(cmd) => String::from_utf8_lossy(&cmd.stdout).to_string(), Err(_) => { eprintln!("Failed to retrieve LLVM FileCheck, ignoring..."); + // FIXME: the test tests/run-make/no-builtins-attribute will fail if we cannot find + // FileCheck. String::new() } }; let file_path = rust_dir_path.join("config.toml"); std::fs::write( &file_path, - &format!( + format!( r#"change-id = 115898 [rust] @@ -532,7 +590,7 @@ fn asm_tests(env: &Env, args: &TestArg) -> Result<(), String> { let codegen_backend_path = format!( "{pwd}/target/{channel}/librustc_codegen_gcc.{dylib_ext}", pwd = std::env::current_dir() - .map_err(|error| format!("`current_dir` failed: {:?}", error))? + .map_err(|error| format!("`current_dir` failed: {error:?}"))? .display(), channel = args.config_info.channel.as_str(), dylib_ext = args.config_info.dylib_ext, @@ -587,11 +645,11 @@ where F: Fn(&[&dyn AsRef<OsStr>], Option<&Path>, &Env) -> Result<(), String>, { let toolchain = get_toolchain()?; - let toolchain_arg = format!("+{}", toolchain); + let toolchain_arg = format!("+{toolchain}"); let rustc_version = String::from_utf8( run_command_with_env(&[&args.config_info.rustc_command[0], &"-V"], cwd, Some(env))?.stdout, ) - .map_err(|error| format!("Failed to retrieve rustc version: {:?}", error))?; + .map_err(|error| format!("Failed to retrieve rustc version: {error:?}"))?; let rustc_toolchain_version = String::from_utf8( run_command_with_env( &[&args.config_info.rustc_command[0], &toolchain_arg, &"-V"], @@ -600,20 +658,19 @@ where )? .stdout, ) - .map_err(|error| format!("Failed to retrieve rustc +toolchain version: {:?}", error))?; + .map_err(|error| format!("Failed to retrieve rustc +toolchain version: {error:?}"))?; if rustc_version != rustc_toolchain_version { eprintln!( - "rustc_codegen_gcc is built for `{}` but the default rustc version is `{}`.", - rustc_toolchain_version, rustc_version, + "rustc_codegen_gcc is built for `{rustc_toolchain_version}` but the default rustc version is `{rustc_version}`.", ); - eprintln!("Using `{}`.", rustc_toolchain_version); + eprintln!("Using `{rustc_toolchain_version}`."); } let mut env = env.clone(); let rustflags = env.get("RUSTFLAGS").cloned().unwrap_or_default(); env.insert("RUSTDOCFLAGS".to_string(), rustflags); let mut cargo_command: Vec<&dyn AsRef<OsStr>> = vec![&"cargo", &toolchain_arg]; - cargo_command.extend_from_slice(&command); + cargo_command.extend_from_slice(command); callback(&cargo_command, cwd, &env) } @@ -680,7 +737,15 @@ fn test_libcore(env: &Env, args: &TestArg) -> Result<(), String> { println!("[TEST] libcore"); let path = get_sysroot_dir().join("sysroot_src/library/coretests"); let _ = remove_dir_all(path.join("target")); - run_cargo_command(&[&"test"], Some(&path), env, args)?; + // TODO(antoyo): run in release mode when we fix the failures. + // TODO(antoyo): remove the --skip f16::test_total_cmp when this issue is fixed: + // https://github.com/rust-lang/rust/issues/141503 + run_cargo_command( + &[&"test", &"--", &"--skip", &"f16::test_total_cmp"], + Some(&path), + env, + args, + )?; Ok(()) } @@ -818,7 +883,7 @@ fn contains_ui_error_patterns(file_path: &Path, keep_lto_tests: bool) -> Result< // Tests generating errors. let file = File::open(file_path) .map_err(|error| format!("Failed to read `{}`: {:?}", file_path.display(), error))?; - for line in BufReader::new(file).lines().filter_map(|line| line.ok()) { + for line in BufReader::new(file).lines().map_while(Result::ok) { let line = line.trim(); if line.is_empty() { continue; @@ -887,7 +952,7 @@ where if !prepare_files_callback(&rust_path)? { // FIXME: create a function "display_if_not_quiet" or something along the line. - println!("Keeping all {} tests", test_type); + println!("Keeping all {test_type} tests"); } if test_type == "ui" { @@ -919,8 +984,7 @@ where "borrowck", "test-attrs", ] - .iter() - .any(|name| *name == dir_name) + .contains(&dir_name) { remove_dir_all(dir).map_err(|error| { format!("Failed to remove folder `{}`: {:?}", dir.display(), error) @@ -975,10 +1039,7 @@ where if nb_parts > 0 { let current_part = args.current_part.unwrap(); // FIXME: create a function "display_if_not_quiet" or something along the line. - println!( - "Splitting ui_test into {} parts (and running part {})", - nb_parts, current_part - ); + println!("Splitting ui_test into {nb_parts} parts (and running part {current_part})"); let out = String::from_utf8( run_command( &[ @@ -996,7 +1057,7 @@ where )? .stdout, ) - .map_err(|error| format!("Failed to retrieve output of find command: {:?}", error))?; + .map_err(|error| format!("Failed to retrieve output of find command: {error:?}"))?; let mut files = out .split('\n') .map(|line| line.trim()) @@ -1016,7 +1077,7 @@ where } // FIXME: create a function "display_if_not_quiet" or something along the line. - println!("[TEST] rustc {} test suite", test_type); + println!("[TEST] rustc {test_type} test suite"); env.insert("COMPILETEST_FORCE_STAGE0".to_string(), "1".to_string()); let extra = @@ -1040,7 +1101,7 @@ where &"always", &"--stage", &"0", - &format!("tests/{}", test_type), + &format!("tests/{test_type}"), &"--compiletest-rustc-args", &rustc_args, ], @@ -1051,19 +1112,18 @@ where } fn test_rustc(env: &Env, args: &TestArg) -> Result<(), String> { - //test_rustc_inner(env, args, |_| Ok(false), false, "run-make")?; + test_rustc_inner(env, args, |_| Ok(false), false, "run-make")?; test_rustc_inner(env, args, |_| Ok(false), false, "ui") } fn test_failing_rustc(env: &Env, args: &TestArg) -> Result<(), String> { - let result1 = Ok(()); - /*test_rustc_inner( + let result1 = test_rustc_inner( env, args, retain_files_callback("tests/failing-run-make-tests.txt", "run-make"), false, "run-make", - )*/ + ); let result2 = test_rustc_inner( env, @@ -1084,14 +1144,13 @@ fn test_successful_rustc(env: &Env, args: &TestArg) -> Result<(), String> { false, "ui", )?; - Ok(()) - /*test_rustc_inner( + test_rustc_inner( env, args, remove_files_callback("tests/failing-run-make-tests.txt", "run-make"), false, "run-make", - )*/ + ) } fn test_failing_ui_pattern_tests(env: &Env, args: &TestArg) -> Result<(), String> { @@ -1118,7 +1177,7 @@ fn retain_files_callback<'a>( run_command( &[ &"find", - &format!("tests/{}", test_type), + &format!("tests/{test_type}"), &"-mindepth", &"1", &"-type", @@ -1137,7 +1196,7 @@ fn retain_files_callback<'a>( run_command( &[ &"find", - &format!("tests/{}", test_type), + &format!("tests/{test_type}"), &"-type", &"f", &"-name", @@ -1152,15 +1211,12 @@ fn retain_files_callback<'a>( } // Putting back only the failing ones. - if let Ok(files) = std::fs::read_to_string(&file_path) { + if let Ok(files) = std::fs::read_to_string(file_path) { for file in files.split('\n').map(|line| line.trim()).filter(|line| !line.is_empty()) { - run_command(&[&"git", &"checkout", &"--", &file], Some(&rust_path))?; + run_command(&[&"git", &"checkout", &"--", &file], Some(rust_path))?; } } else { - println!( - "Failed to read `{}`, not putting back failing {} tests", - file_path, test_type - ); + println!("Failed to read `{file_path}`, not putting back failing {test_type} tests"); } Ok(true) @@ -1188,8 +1244,7 @@ fn remove_files_callback<'a>( } } else { println!( - "Failed to read `{}`, not putting back failing {} tests", - file_path, test_type + "Failed to read `{file_path}`, not putting back failing {test_type} tests" ); } } else { @@ -1202,7 +1257,7 @@ fn remove_files_callback<'a>( remove_file(&path)?; } } else { - println!("Failed to read `{}`, not putting back failing ui tests", file_path); + println!("Failed to read `{file_path}`, not putting back failing ui tests"); } } Ok(true) @@ -1217,7 +1272,9 @@ fn run_all(env: &Env, args: &TestArg) -> Result<(), String> { // asm_tests(env, args)?; test_libcore(env, args)?; extended_sysroot_tests(env, args)?; + cargo_tests(env, args)?; test_rustc(env, args)?; + Ok(()) } diff --git a/compiler/rustc_codegen_gcc/build_system/src/utils.rs b/compiler/rustc_codegen_gcc/build_system/src/utils.rs index ca177a5feb8..d77707d5f17 100644 --- a/compiler/rustc_codegen_gcc/build_system/src/utils.rs +++ b/compiler/rustc_codegen_gcc/build_system/src/utils.rs @@ -1,7 +1,5 @@ use std::collections::HashMap; use std::ffi::OsStr; -#[cfg(unix)] -use std::ffi::c_int; use std::fmt::Debug; use std::fs; #[cfg(unix)] @@ -9,11 +7,6 @@ use std::os::unix::process::ExitStatusExt; use std::path::{Path, PathBuf}; use std::process::{Command, ExitStatus, Output}; -#[cfg(unix)] -unsafe extern "C" { - fn raise(signal: c_int) -> c_int; -} - fn exec_command( input: &[&dyn AsRef<OsStr>], cwd: Option<&Path>, @@ -27,17 +20,14 @@ fn exec_command( #[cfg(unix)] { if let Some(signal) = status.signal() { - unsafe { - raise(signal as _); - } // In case the signal didn't kill the current process. - return Err(command_error(input, &cwd, format!("Process received signal {}", signal))); + return Err(command_error(input, &cwd, format!("Process received signal {signal}"))); } } Ok(status) } -fn get_command_inner( +pub(crate) fn get_command_inner( input: &[&dyn AsRef<OsStr>], cwd: Option<&Path>, env: Option<&HashMap<String, String>>, @@ -75,18 +65,18 @@ fn check_exit_status( ); let input = input.iter().map(|i| i.as_ref()).collect::<Vec<&OsStr>>(); if show_err { - eprintln!("Command `{:?}` failed", input); + eprintln!("Command `{input:?}` failed"); } if let Some(output) = output { let stdout = String::from_utf8_lossy(&output.stdout); if !stdout.is_empty() { error.push_str("\n==== STDOUT ====\n"); - error.push_str(&*stdout); + error.push_str(&stdout); } let stderr = String::from_utf8_lossy(&output.stderr); if !stderr.is_empty() { error.push_str("\n==== STDERR ====\n"); - error.push_str(&*stderr); + error.push_str(&stderr); } } Err(error) @@ -136,6 +126,7 @@ pub fn run_command_with_output_and_env( Ok(()) } +#[cfg(not(unix))] pub fn run_command_with_output_and_env_no_err( input: &[&dyn AsRef<OsStr>], cwd: Option<&Path>, @@ -242,7 +233,7 @@ pub fn get_toolchain() -> Result<String, String> { if !line.starts_with("channel") { return None; } - line.split('"').skip(1).next() + line.split('"').nth(1) }) .next() { @@ -281,7 +272,7 @@ fn git_clone_inner( } fn get_repo_name(url: &str) -> String { - let repo_name = url.split('/').last().unwrap(); + let repo_name = url.split('/').next_back().unwrap(); match repo_name.strip_suffix(".git") { Some(n) => n.to_string(), None => repo_name.to_string(), diff --git a/compiler/rustc_codegen_gcc/example/std_example.rs b/compiler/rustc_codegen_gcc/example/std_example.rs index 5fa1e0afb06..7587b4827ca 100644 --- a/compiler/rustc_codegen_gcc/example/std_example.rs +++ b/compiler/rustc_codegen_gcc/example/std_example.rs @@ -77,18 +77,18 @@ fn main() { assert_eq!(tmp as i128, -0x1234_5678_9ABC_DEF0i128); // Check that all u/i128 <-> float casts work correctly. - let houndred_u128 = 100u128; - let houndred_i128 = 100i128; - let houndred_f32 = 100.0f32; - let houndred_f64 = 100.0f64; - assert_eq!(houndred_u128 as f32, 100.0); - assert_eq!(houndred_u128 as f64, 100.0); - assert_eq!(houndred_f32 as u128, 100); - assert_eq!(houndred_f64 as u128, 100); - assert_eq!(houndred_i128 as f32, 100.0); - assert_eq!(houndred_i128 as f64, 100.0); - assert_eq!(houndred_f32 as i128, 100); - assert_eq!(houndred_f64 as i128, 100); + let hundred_u128 = 100u128; + let hundred_i128 = 100i128; + let hundred_f32 = 100.0f32; + let hundred_f64 = 100.0f64; + assert_eq!(hundred_u128 as f32, 100.0); + assert_eq!(hundred_u128 as f64, 100.0); + assert_eq!(hundred_f32 as u128, 100); + assert_eq!(hundred_f64 as u128, 100); + assert_eq!(hundred_i128 as f32, 100.0); + assert_eq!(hundred_i128 as f64, 100.0); + assert_eq!(hundred_f32 as i128, 100); + assert_eq!(hundred_f64 as i128, 100); let _a = 1u32 << 2u8; diff --git a/compiler/rustc_codegen_gcc/patches/0001-Pin-compiler_builtins-to-0.1.160.patch b/compiler/rustc_codegen_gcc/patches/0001-Pin-compiler_builtins-to-0.1.160.patch new file mode 100644 index 00000000000..39266e081ed --- /dev/null +++ b/compiler/rustc_codegen_gcc/patches/0001-Pin-compiler_builtins-to-0.1.160.patch @@ -0,0 +1,39 @@ +From cdb3d407740e4f15c3746051f8ba89b8e74e99d3 Mon Sep 17 00:00:00 2001 +From: None <none@example.com> +Date: Fri, 30 May 2025 13:46:22 -0400 +Subject: [PATCH] Pin compiler_builtins to 0.1.160 + +--- + library/alloc/Cargo.toml | 2 +- + library/std/Cargo.toml | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/library/alloc/Cargo.toml b/library/alloc/Cargo.toml +index 9d0d957..365c9dc 100644 +--- a/library/alloc/Cargo.toml ++++ b/library/alloc/Cargo.toml +@@ -16,7 +16,7 @@ bench = false + + [dependencies] + core = { path = "../core", public = true } +-compiler_builtins = { version = "=0.1.159", features = ['rustc-dep-of-std'] } ++compiler_builtins = { version = "=0.1.160", features = ['rustc-dep-of-std'] } + + [features] + compiler-builtins-mem = ['compiler_builtins/mem'] +diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml +index 4ff4895..31371f0 100644 +--- a/library/std/Cargo.toml ++++ b/library/std/Cargo.toml +@@ -18,7 +18,7 @@ cfg-if = { version = "1.0", features = ['rustc-dep-of-std'] } + panic_unwind = { path = "../panic_unwind", optional = true } + panic_abort = { path = "../panic_abort" } + core = { path = "../core", public = true } +-compiler_builtins = { version = "=0.1.159" } ++compiler_builtins = { version = "=0.1.160" } + unwind = { path = "../unwind" } + hashbrown = { version = "0.15", default-features = false, features = [ + 'rustc-dep-of-std', +-- +2.49.0 + diff --git a/compiler/rustc_codegen_gcc/patches/tests/0001-Workaround-to-make-a-run-make-test-pass.patch b/compiler/rustc_codegen_gcc/patches/tests/0001-Workaround-to-make-a-run-make-test-pass.patch new file mode 100644 index 00000000000..a329d09a95e --- /dev/null +++ b/compiler/rustc_codegen_gcc/patches/tests/0001-Workaround-to-make-a-run-make-test-pass.patch @@ -0,0 +1,25 @@ +From a131c69e54b5c02fe3b517e8f3ad23d4f784ffc8 Mon Sep 17 00:00:00 2001 +From: Antoni Boucher <bouanto@zoho.com> +Date: Fri, 13 Jun 2025 20:25:33 -0400 +Subject: [PATCH] Workaround to make a run-make test pass + +--- + tests/run-make/linker-warning/rmake.rs | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tests/run-make/linker-warning/rmake.rs b/tests/run-make/linker-warning/rmake.rs +index bc21739fefc..0946a7e2a48 100644 +--- a/tests/run-make/linker-warning/rmake.rs ++++ b/tests/run-make/linker-warning/rmake.rs +@@ -55,7 +55,7 @@ fn main() { + diff() + .expected_file("short-error.txt") + .actual_text("(linker error)", out.stderr()) +- .normalize(r#"/rustc[^/]*/"#, "/rustc/") ++ .normalize(r#"/tmp/rustc[^/]*/"#, "/tmp/rustc/") + .normalize( + regex::escape(run_make_support::build_root().to_str().unwrap()), + "/build-root", +-- +2.49.0 + diff --git a/compiler/rustc_codegen_gcc/rust-toolchain b/compiler/rustc_codegen_gcc/rust-toolchain index a8cda28688c..bafe497a2a2 100644 --- a/compiler/rustc_codegen_gcc/rust-toolchain +++ b/compiler/rustc_codegen_gcc/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2025-05-12" +channel = "nightly-2025-05-21" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] diff --git a/compiler/rustc_codegen_gcc/src/allocator.rs b/compiler/rustc_codegen_gcc/src/allocator.rs index cf8aa500c77..9e54ba05a9b 100644 --- a/compiler/rustc_codegen_gcc/src/allocator.rs +++ b/compiler/rustc_codegen_gcc/src/allocator.rs @@ -158,6 +158,7 @@ fn create_wrapper_function( } } else { assert!(output.is_none()); + block.add_eval(None, ret); block.end_with_void_return(None); } diff --git a/compiler/rustc_codegen_gcc/src/asm.rs b/compiler/rustc_codegen_gcc/src/asm.rs index c35337ae7ce..17e2e028b16 100644 --- a/compiler/rustc_codegen_gcc/src/asm.rs +++ b/compiler/rustc_codegen_gcc/src/asm.rs @@ -1,3 +1,5 @@ +// cSpell:ignoreRegExp [afkspqvwy]reg + use std::borrow::Cow; use gccjit::{LValue, RValue, ToRValue, Type}; @@ -138,7 +140,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // `outputs.len() + inputs.len()`. let mut labels = vec![]; - // Clobbers collected from `out("explicit register") _` and `inout("expl_reg") var => _` + // Clobbers collected from `out("explicit register") _` and `inout("explicit_reg") var => _` let mut clobbers = vec![]; // We're trying to preallocate space for the template @@ -203,7 +205,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { // is also used as an in register, do not add it to the clobbers list. // it will be treated as a lateout register with `out_place: None` if !late { - bug!("input registers can only be used as lateout regisers"); + bug!("input registers can only be used as lateout registers"); } ("r", dummy_output_type(self.cx, reg.reg_class())) } else { @@ -641,7 +643,8 @@ fn explicit_reg_to_gcc(reg: InlineAsmReg) -> &'static str { }, } } - + InlineAsmReg::Arm(reg) => reg.name(), + InlineAsmReg::AArch64(reg) => reg.name(), _ => unimplemented!(), } } diff --git a/compiler/rustc_codegen_gcc/src/attributes.rs b/compiler/rustc_codegen_gcc/src/attributes.rs index c853c88a6ea..bf0927dc590 100644 --- a/compiler/rustc_codegen_gcc/src/attributes.rs +++ b/compiler/rustc_codegen_gcc/src/attributes.rs @@ -16,7 +16,7 @@ use crate::gcc_util::to_gcc_features; /// Checks if the function `instance` is recursively inline. /// Returns `false` if a functions is guaranteed to be non-recursive, and `true` if it *might* be recursive. #[cfg(feature = "master")] -fn resursively_inline<'gcc, 'tcx>( +fn recursively_inline<'gcc, 'tcx>( cx: &CodegenCx<'gcc, 'tcx>, instance: ty::Instance<'tcx>, ) -> bool { @@ -61,7 +61,7 @@ fn inline_attr<'gcc, 'tcx>( // // That prevents issues steming from recursive `#[inline(always)]` at a *relatively* small cost. // We *only* need to check all the terminators of a function marked with this attribute. - if resursively_inline(cx, instance) { + if recursively_inline(cx, instance) { Some(FnAttribute::Inline) } else { Some(FnAttribute::AlwaysInline) diff --git a/compiler/rustc_codegen_gcc/src/back/lto.rs b/compiler/rustc_codegen_gcc/src/back/lto.rs index e9c87f35779..10fce860b77 100644 --- a/compiler/rustc_codegen_gcc/src/back/lto.rs +++ b/compiler/rustc_codegen_gcc/src/back/lto.rs @@ -11,11 +11,12 @@ // does not remove it? // // TODO(antoyo): for performance, check which optimizations the C++ frontend enables. -// +// cSpell:disable // Fix these warnings: // /usr/bin/ld: warning: type of symbol `_RNvNvNvNtCs5JWOrf9uCus_5rayon11thread_pool19WORKER_THREAD_STATE7___getit5___KEY' changed from 1 to 6 in /tmp/ccKeUSiR.ltrans0.ltrans.o // /usr/bin/ld: warning: type of symbol `_RNvNvNvNvNtNtNtCsAj5i4SGTR7_3std4sync4mpmc5waker17current_thread_id5DUMMY7___getit5___KEY' changed from 1 to 6 in /tmp/ccKeUSiR.ltrans0.ltrans.o // /usr/bin/ld: warning: incremental linking of LTO and non-LTO objects; using -flinker-output=nolto-rel which will bypass whole program optimization +// cSpell:enable use std::ffi::{CStr, CString}; use std::fs::{self, File}; use std::path::{Path, PathBuf}; diff --git a/compiler/rustc_codegen_gcc/src/back/write.rs b/compiler/rustc_codegen_gcc/src/back/write.rs index 09e955acf39..d03d063bdac 100644 --- a/compiler/rustc_codegen_gcc/src/back/write.rs +++ b/compiler/rustc_codegen_gcc/src/back/write.rs @@ -186,6 +186,7 @@ pub(crate) fn codegen( if fat_lto { let lto_path = format!("{}.lto", path); + // cSpell:disable // FIXME(antoyo): The LTO frontend generates the following warning: // ../build_sysroot/sysroot_src/library/core/src/num/dec2flt/lemire.rs:150:15: warning: type of ‘_ZN4core3num7dec2flt5table17POWER_OF_FIVE_12817ha449a68fb31379e4E’ does not match original declaration [-Wlto-type-mismatch] // 150 | let (lo5, hi5) = POWER_OF_FIVE_128[index]; @@ -193,6 +194,7 @@ pub(crate) fn codegen( // lto1: note: ‘_ZN4core3num7dec2flt5table17POWER_OF_FIVE_12817ha449a68fb31379e4E’ was previously declared here // // This option is to mute it to make the UI tests pass with LTO enabled. + // cSpell:enable context.add_driver_option("-Wno-lto-type-mismatch"); // NOTE: this doesn't actually generate an executable. With the above // flags, it combines the .o files together in another .o. diff --git a/compiler/rustc_codegen_gcc/src/builder.rs b/compiler/rustc_codegen_gcc/src/builder.rs index 68c6156fa4b..a2e34d1f8fb 100644 --- a/compiler/rustc_codegen_gcc/src/builder.rs +++ b/compiler/rustc_codegen_gcc/src/builder.rs @@ -765,7 +765,15 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { #[cfg(feature = "master")] match self.cx.type_kind(a_type) { - TypeKind::Half | TypeKind::Float => { + TypeKind::Half => { + let fmodf = self.context.get_builtin_function("fmodf"); + let f32_type = self.type_f32(); + let a = self.context.new_cast(self.location, a, f32_type); + let b = self.context.new_cast(self.location, b, f32_type); + let result = self.context.new_call(self.location, fmodf, &[a, b]); + return self.context.new_cast(self.location, result, a_type); + } + TypeKind::Float => { let fmodf = self.context.get_builtin_function("fmodf"); return self.context.new_call(self.location, fmodf, &[a, b]); } @@ -774,8 +782,19 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { return self.context.new_call(self.location, fmod, &[a, b]); } TypeKind::FP128 => { - let fmodl = self.context.get_builtin_function("fmodl"); - return self.context.new_call(self.location, fmodl, &[a, b]); + let f128_type = self.type_f128(); + let fmodf128 = self.context.new_function( + None, + gccjit::FunctionType::Extern, + f128_type, + &[ + self.context.new_parameter(None, f128_type, "a"), + self.context.new_parameter(None, f128_type, "b"), + ], + "fmodf128", + false, + ); + return self.context.new_call(self.location, fmodf128, &[a, b]); } _ => (), } @@ -924,7 +943,12 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { // dereference after a drop, for instance. // FIXME(antoyo): this check that we don't call get_aligned() a second time on a type. // Ideally, we shouldn't need to do this check. - let aligned_type = if pointee_ty == self.cx.u128_type || pointee_ty == self.cx.i128_type { + // FractalFir: the `align == self.int128_align` check ensures we *do* call `get_aligned` if + // the alignment of a `u128`/`i128` is not the one mandated by the ABI. This ensures we handle + // under-aligned loads correctly. + let aligned_type = if (pointee_ty == self.cx.u128_type || pointee_ty == self.cx.i128_type) + && align == self.int128_align + { pointee_ty } else { pointee_ty.get_aligned(align.bytes()) @@ -1010,13 +1034,13 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> { let b_offset = a.size(self).align_to(b.align(self).abi); let mut load = |i, scalar: &abi::Scalar, align| { - let llptr = if i == 0 { + let ptr = if i == 0 { place.val.llval } else { self.inbounds_ptradd(place.val.llval, self.const_usize(b_offset.bytes())) }; let llty = place.layout.scalar_pair_element_gcc_type(self, i); - let load = self.load(llty, llptr, align); + let load = self.load(llty, ptr, align); scalar_load_metadata(self, load, scalar); if scalar.is_bool() { self.trunc(load, self.type_i1()) } else { load } }; diff --git a/compiler/rustc_codegen_gcc/src/callee.rs b/compiler/rustc_codegen_gcc/src/callee.rs index c8130b7c010..189ac7cd779 100644 --- a/compiler/rustc_codegen_gcc/src/callee.rs +++ b/compiler/rustc_codegen_gcc/src/callee.rs @@ -34,7 +34,7 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) unreachable!(); /* // Create a fn pointer with the new signature. - let ptrty = fn_abi.ptr_to_gcc_type(cx); + let ptrtype = fn_abi.ptr_to_gcc_type(cx); // This is subtle and surprising, but sometimes we have to bitcast // the resulting fn pointer. The reason has to do with external @@ -59,7 +59,7 @@ pub fn get_fn<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, instance: Instance<'tcx>) // This can occur on either a crate-local or crate-external // reference. It also occurs when testing libcore and in some // other weird situations. Annoying. - if cx.val_ty(func) != ptrty { + if cx.val_ty(func) != ptrtype { // TODO(antoyo): cast the pointer. func } diff --git a/compiler/rustc_codegen_gcc/src/common.rs b/compiler/rustc_codegen_gcc/src/common.rs index 918195364ff..58ff2f1f8f0 100644 --- a/compiler/rustc_codegen_gcc/src/common.rs +++ b/compiler/rustc_codegen_gcc/src/common.rs @@ -9,7 +9,6 @@ use rustc_middle::mir::Mutability; use rustc_middle::mir::interpret::{ConstAllocation, GlobalAlloc, Scalar}; use rustc_middle::ty::layout::LayoutOf; -use crate::consts::const_alloc_to_gcc; use crate::context::CodegenCx; use crate::type_of::LayoutGccExt; @@ -46,12 +45,65 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) -> RValue<'gcc> { - let context = &cx.context; - let byte_type = context.new_type::<u8>(); - let typ = context.new_array_type(None, byte_type, bytes.len() as u64); - let elements: Vec<_> = - bytes.iter().map(|&byte| context.new_rvalue_from_int(byte_type, byte as i32)).collect(); - context.new_array_constructor(None, typ, &elements) + // Instead of always using an array of bytes, use an array of larger integers of target endianness + // if possible. This reduces the amount of `rvalues` we use, which reduces memory usage significantly. + // + // FIXME(FractalFir): Consider using `global_set_initializer` instead. Before this is done, we need to confirm that + // `global_set_initializer` is more memory efficient than the current solution. + // `global_set_initializer` calls `global_set_initializer_rvalue` under the hood - does it generate an array of rvalues, + // or is it using a more efficient representation? + match bytes.len() % 8 { + 0 => { + let context = &cx.context; + let byte_type = context.new_type::<u64>(); + let typ = context.new_array_type(None, byte_type, bytes.len() as u64 / 8); + let elements: Vec<_> = bytes + .chunks_exact(8) + .map(|arr| { + let arr: [u8; 8] = arr.try_into().unwrap(); + context.new_rvalue_from_long( + byte_type, + // Since we are representing arbitrary byte runs as integers, we need to follow the target + // endianness. + match cx.sess().target.options.endian { + rustc_abi::Endian::Little => u64::from_le_bytes(arr) as i64, + rustc_abi::Endian::Big => u64::from_be_bytes(arr) as i64, + }, + ) + }) + .collect(); + context.new_array_constructor(None, typ, &elements) + } + 4 => { + let context = &cx.context; + let byte_type = context.new_type::<u32>(); + let typ = context.new_array_type(None, byte_type, bytes.len() as u64 / 4); + let elements: Vec<_> = bytes + .chunks_exact(4) + .map(|arr| { + let arr: [u8; 4] = arr.try_into().unwrap(); + context.new_rvalue_from_int( + byte_type, + match cx.sess().target.options.endian { + rustc_abi::Endian::Little => u32::from_le_bytes(arr) as i32, + rustc_abi::Endian::Big => u32::from_be_bytes(arr) as i32, + }, + ) + }) + .collect(); + context.new_array_constructor(None, typ, &elements) + } + _ => { + let context = cx.context; + let byte_type = context.new_type::<u8>(); + let typ = context.new_array_type(None, byte_type, bytes.len() as u64); + let elements: Vec<_> = bytes + .iter() + .map(|&byte| context.new_rvalue_from_int(byte_type, byte as i32)) + .collect(); + context.new_array_constructor(None, typ, &elements) + } + } } pub fn type_is_pointer(typ: Type<'_>) -> bool { @@ -185,14 +237,15 @@ impl<'gcc, 'tcx> ConstCodegenMethods for CodegenCx<'gcc, 'tcx> { // FIXME(antoyo): there's some issues with using the u128 code that follows, so hard-code // the paths for floating-point values. - if ty == self.float_type { + // TODO: Remove this code? + /*if ty == self.float_type { return self .context .new_rvalue_from_double(ty, f32::from_bits(data as u32) as f64); } if ty == self.double_type { return self.context.new_rvalue_from_double(ty, f64::from_bits(data as u64)); - } + }*/ let value = self.const_uint_big(self.type_ix(bitsize), data); let bytesize = layout.size(self).bytes(); @@ -212,7 +265,20 @@ impl<'gcc, 'tcx> ConstCodegenMethods for CodegenCx<'gcc, 'tcx> { let alloc_id = prov.alloc_id(); let base_addr = match self.tcx.global_alloc(alloc_id) { GlobalAlloc::Memory(alloc) => { - let init = const_alloc_to_gcc(self, alloc); + // For ZSTs directly codegen an aligned pointer. + // This avoids generating a zero-sized constant value and actually needing a + // real address at runtime. + if alloc.inner().len() == 0 { + assert_eq!(offset.bytes(), 0); + let val = self.const_usize(alloc.inner().align.bytes()); + return if matches!(layout.primitive(), Pointer(_)) { + self.context.new_cast(None, val, ty) + } else { + self.const_bitcast(val, ty) + }; + } + + let init = self.const_data_from_alloc(alloc); let alloc = alloc.inner(); let value = match alloc.mutability { Mutability::Mut => self.static_addr_of_mut(init, alloc.align, None), @@ -234,7 +300,7 @@ impl<'gcc, 'tcx> ConstCodegenMethods for CodegenCx<'gcc, 'tcx> { }), ))) .unwrap_memory(); - let init = const_alloc_to_gcc(self, alloc); + let init = self.const_data_from_alloc(alloc); self.static_addr_of(init, alloc.inner().align, None) } GlobalAlloc::Static(def_id) => { @@ -257,7 +323,19 @@ impl<'gcc, 'tcx> ConstCodegenMethods for CodegenCx<'gcc, 'tcx> { } fn const_data_from_alloc(&self, alloc: ConstAllocation<'_>) -> Self::Value { - const_alloc_to_gcc(self, alloc) + // We ignore the alignment for the purpose of deduping RValues + // The alignment is not handled / used in any way by `const_alloc_to_gcc`, + // so it is OK to overwrite it here. + let mut mock_alloc = alloc.inner().clone(); + mock_alloc.align = rustc_abi::Align::MAX; + // Check if the rvalue is already in the cache - if so, just return it directly. + if let Some(res) = self.const_cache.borrow().get(&mock_alloc) { + return *res; + } + // Rvalue not in the cache - convert and add it. + let res = crate::consts::const_alloc_to_gcc_uncached(self, alloc); + self.const_cache.borrow_mut().insert(mock_alloc, res); + res } fn const_ptr_byte_offset(&self, base_addr: Self::Value, offset: abi::Size) -> Self::Value { diff --git a/compiler/rustc_codegen_gcc/src/consts.rs b/compiler/rustc_codegen_gcc/src/consts.rs index 1690641a5bc..b43f9b24c6a 100644 --- a/compiler/rustc_codegen_gcc/src/consts.rs +++ b/compiler/rustc_codegen_gcc/src/consts.rs @@ -36,18 +36,14 @@ fn set_global_alignment<'gcc, 'tcx>( impl<'gcc, 'tcx> StaticCodegenMethods for CodegenCx<'gcc, 'tcx> { fn static_addr_of(&self, cv: RValue<'gcc>, align: Align, kind: Option<&str>) -> RValue<'gcc> { - // TODO(antoyo): implement a proper rvalue comparison in libgccjit instead of doing the - // following: - for (value, variable) in &*self.const_globals.borrow() { - if format!("{:?}", value) == format!("{:?}", cv) { - if let Some(global_variable) = self.global_lvalues.borrow().get(variable) { - let alignment = align.bits() as i32; - if alignment > global_variable.get_alignment() { - global_variable.set_alignment(alignment); - } + if let Some(variable) = self.const_globals.borrow().get(&cv) { + if let Some(global_variable) = self.global_lvalues.borrow().get(variable) { + let alignment = align.bits() as i32; + if alignment > global_variable.get_alignment() { + global_variable.set_alignment(alignment); } - return *variable; } + return *variable; } let global_value = self.static_addr_of_mut(cv, align, kind); #[cfg(feature = "master")] @@ -288,8 +284,10 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { global } } - -pub fn const_alloc_to_gcc<'gcc>( +/// Converts a given const alloc to a gcc Rvalue, without any caching or deduplication. +/// YOU SHOULD NOT call this function directly - that may break the semantics of Rust. +/// Use `const_data_from_alloc` instead. +pub(crate) fn const_alloc_to_gcc_uncached<'gcc>( cx: &CodegenCx<'gcc, '_>, alloc: ConstAllocation<'_>, ) -> RValue<'gcc> { @@ -321,7 +319,7 @@ pub fn const_alloc_to_gcc<'gcc>( // and we properly interpret the provenance as a relocation pointer offset. alloc.inspect_with_uninit_and_ptr_outside_interpreter(offset..(offset + pointer_size)), ) - .expect("const_alloc_to_llvm: could not read relocation pointer") + .expect("const_alloc_to_gcc_uncached: could not read relocation pointer") as u64; let address_space = cx.tcx.global_alloc(alloc_id).address_space(cx); @@ -360,7 +358,7 @@ fn codegen_static_initializer<'gcc, 'tcx>( def_id: DefId, ) -> Result<(RValue<'gcc>, ConstAllocation<'tcx>), ErrorHandled> { let alloc = cx.tcx.eval_static_initializer(def_id)?; - Ok((const_alloc_to_gcc(cx, alloc), alloc)) + Ok((cx.const_data_from_alloc(alloc), alloc)) } fn check_and_apply_linkage<'gcc, 'tcx>( diff --git a/compiler/rustc_codegen_gcc/src/context.rs b/compiler/rustc_codegen_gcc/src/context.rs index 4955e039e7b..ff141ad365b 100644 --- a/compiler/rustc_codegen_gcc/src/context.rs +++ b/compiler/rustc_codegen_gcc/src/context.rs @@ -1,14 +1,16 @@ use std::cell::{Cell, RefCell}; +use std::collections::HashMap; use gccjit::{ Block, CType, Context, Function, FunctionPtrType, FunctionType, LValue, Location, RValue, Type, }; -use rustc_abi::{HasDataLayout, PointeeInfo, Size, TargetDataLayout, VariantIdx}; +use rustc_abi::{Align, HasDataLayout, PointeeInfo, Size, TargetDataLayout, VariantIdx}; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::errors as ssa_errors; use rustc_codegen_ssa::traits::{BackendTypes, BaseTypeCodegenMethods, MiscCodegenMethods}; use rustc_data_structures::base_n::{ALPHANUMERIC_ONLY, ToBaseN}; use rustc_data_structures::fx::{FxHashMap, FxHashSet}; +use rustc_middle::mir::interpret::Allocation; use rustc_middle::mir::mono::CodegenUnit; use rustc_middle::span_bug; use rustc_middle::ty::layout::{ @@ -28,6 +30,8 @@ use crate::common::SignType; #[cfg_attr(not(feature = "master"), allow(dead_code))] pub struct CodegenCx<'gcc, 'tcx> { + /// A cache of converted ConstAllocs + pub const_cache: RefCell<HashMap<Allocation, RValue<'gcc>>>, pub codegen_unit: &'tcx CodegenUnit<'tcx>, pub context: &'gcc Context<'gcc>, @@ -129,6 +133,9 @@ pub struct CodegenCx<'gcc, 'tcx> { #[cfg(feature = "master")] pub cleanup_blocks: RefCell<FxHashSet<Block<'gcc>>>, + /// The alignment of a u128/i128 type. + // We cache this, since it is needed for alignment checks during loads. + pub int128_align: Align, } impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { @@ -220,6 +227,12 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { } let mut cx = Self { + int128_align: tcx + .layout_of(ty::TypingEnv::fully_monomorphized().as_query_input(tcx.types.i128)) + .expect("Can't get the layout of `i128`") + .align + .abi, + const_cache: Default::default(), codegen_unit, context, current_func: RefCell::new(None), @@ -428,8 +441,8 @@ impl<'gcc, 'tcx> MiscCodegenMethods<'tcx> for CodegenCx<'gcc, 'tcx> { // `rust_eh_personality` function, but rather we wired it up to the // CRT's custom personality function, which forces LLVM to consider // landing pads as "landing pads for SEH". - if let Some(llpersonality) = self.eh_personality.get() { - return llpersonality; + if let Some(personality_func) = self.eh_personality.get() { + return personality_func; } let tcx = self.tcx; let func = match tcx.lang_items().eh_personality() { diff --git a/compiler/rustc_codegen_gcc/src/gcc_util.rs b/compiler/rustc_codegen_gcc/src/gcc_util.rs index d90e66aea31..2e00d5fcb61 100644 --- a/compiler/rustc_codegen_gcc/src/gcc_util.rs +++ b/compiler/rustc_codegen_gcc/src/gcc_util.rs @@ -143,6 +143,7 @@ pub(crate) fn global_gcc_features(sess: &Session, diagnostics: bool) -> Vec<Stri // To find a list of GCC's names, check https://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html pub fn to_gcc_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]> { let arch = if sess.target.arch == "x86_64" { "x86" } else { &*sess.target.arch }; + // cSpell:disable match (arch, s) { // FIXME: seems like x87 does not exist? ("x86", "x87") => smallvec![], @@ -181,6 +182,7 @@ pub fn to_gcc_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]> ("aarch64", "sve2-bitperm") => smallvec!["sve2-bitperm", "neon"], (_, s) => smallvec![s], } + // cSpell:enable } fn arch_to_gcc(name: &str) -> &str { diff --git a/compiler/rustc_codegen_gcc/src/int.rs b/compiler/rustc_codegen_gcc/src/int.rs index eb4acd8ade9..6f21ce9352b 100644 --- a/compiler/rustc_codegen_gcc/src/int.rs +++ b/compiler/rustc_codegen_gcc/src/int.rs @@ -2,6 +2,8 @@ //! This module exists because some integer types are not supported on some gcc platforms, e.g. //! 128-bit integers on 32-bit platforms and thus require to be handled manually. +// cSpell:words cmpti divti modti mulodi muloti udivti umodti + use gccjit::{BinaryOp, ComparisonOp, FunctionType, Location, RValue, ToRValue, Type, UnaryOp}; use rustc_abi::{CanonAbi, Endian, ExternAbi}; use rustc_codegen_ssa::common::{IntPredicate, TypeKind}; @@ -913,9 +915,11 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { debug_assert!(value_type.dyncast_array().is_some()); let name_suffix = match self.type_kind(dest_typ) { + // cSpell:disable TypeKind::Float => "tisf", TypeKind::Double => "tidf", - TypeKind::FP128 => "tixf", + TypeKind::FP128 => "titf", + // cSpell:enable kind => panic!("cannot cast a non-native integer to type {:?}", kind), }; let sign = if signed { "" } else { "un" }; @@ -957,8 +961,10 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> { debug_assert!(dest_typ.dyncast_array().is_some()); let name_suffix = match self.type_kind(value_type) { + // cSpell:disable TypeKind::Float => "sfti", TypeKind::Double => "dfti", + // cSpell:enable kind => panic!("cannot cast a {:?} to non-native integer", kind), }; let sign = if signed { "" } else { "uns" }; diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/archs.rs b/compiler/rustc_codegen_gcc/src/intrinsic/archs.rs index 5ada535aa41..f0352c5e6e5 100644 --- a/compiler/rustc_codegen_gcc/src/intrinsic/archs.rs +++ b/compiler/rustc_codegen_gcc/src/intrinsic/archs.rs @@ -1,9978 +1,10178 @@ // File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py` // DO NOT EDIT IT! -match name { - // AMDGPU - "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", - "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", - "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", - "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", - "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", - "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", - "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", - "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", - // aarch64 - "llvm.aarch64.chkfeat" => "__builtin_arm_chkfeat", - "llvm.aarch64.dmb" => "__builtin_arm_dmb", - "llvm.aarch64.dsb" => "__builtin_arm_dsb", - "llvm.aarch64.gcspopm" => "__builtin_arm_gcspopm", - "llvm.aarch64.gcsss" => "__builtin_arm_gcsss", - "llvm.aarch64.isb" => "__builtin_arm_isb", - "llvm.aarch64.prefetch" => "__builtin_arm_prefetch", - "llvm.aarch64.sme.in.streaming.mode" => "__builtin_arm_in_streaming_mode", - "llvm.aarch64.sve.aesd" => "__builtin_sve_svaesd_u8", - "llvm.aarch64.sve.aese" => "__builtin_sve_svaese_u8", - "llvm.aarch64.sve.aesimc" => "__builtin_sve_svaesimc_u8", - "llvm.aarch64.sve.aesmc" => "__builtin_sve_svaesmc_u8", - "llvm.aarch64.sve.rax1" => "__builtin_sve_svrax1_u64", - "llvm.aarch64.sve.rdffr" => "__builtin_sve_svrdffr", - "llvm.aarch64.sve.rdffr.z" => "__builtin_sve_svrdffr_z", - "llvm.aarch64.sve.setffr" => "__builtin_sve_svsetffr", - "llvm.aarch64.sve.sm4e" => "__builtin_sve_svsm4e_u32", - "llvm.aarch64.sve.sm4ekey" => "__builtin_sve_svsm4ekey_u32", - "llvm.aarch64.sve.wrffr" => "__builtin_sve_svwrffr", - "llvm.aarch64.tcancel" => "__builtin_arm_tcancel", - "llvm.aarch64.tcommit" => "__builtin_arm_tcommit", - "llvm.aarch64.tstart" => "__builtin_arm_tstart", - "llvm.aarch64.ttest" => "__builtin_arm_ttest", - // amdgcn - "llvm.amdgcn.alignbyte" => "__builtin_amdgcn_alignbyte", - "llvm.amdgcn.ashr.pk.i8.i32" => "__builtin_amdgcn_ashr_pk_i8_i32", - "llvm.amdgcn.ashr.pk.u8.i32" => "__builtin_amdgcn_ashr_pk_u8_i32", - "llvm.amdgcn.buffer.wbinvl1" => "__builtin_amdgcn_buffer_wbinvl1", - "llvm.amdgcn.buffer.wbinvl1.sc" => "__builtin_amdgcn_buffer_wbinvl1_sc", - "llvm.amdgcn.buffer.wbinvl1.vol" => "__builtin_amdgcn_buffer_wbinvl1_vol", - "llvm.amdgcn.cubeid" => "__builtin_amdgcn_cubeid", - "llvm.amdgcn.cubema" => "__builtin_amdgcn_cubema", - "llvm.amdgcn.cubesc" => "__builtin_amdgcn_cubesc", - "llvm.amdgcn.cubetc" => "__builtin_amdgcn_cubetc", - "llvm.amdgcn.cvt.f32.bf8" => "__builtin_amdgcn_cvt_f32_bf8", - "llvm.amdgcn.cvt.f32.fp8" => "__builtin_amdgcn_cvt_f32_fp8", - "llvm.amdgcn.cvt.off.f32.i4" => "__builtin_amdgcn_cvt_off_f32_i4", - "llvm.amdgcn.cvt.pk.bf8.f32" => "__builtin_amdgcn_cvt_pk_bf8_f32", - "llvm.amdgcn.cvt.pk.f32.bf8" => "__builtin_amdgcn_cvt_pk_f32_bf8", - "llvm.amdgcn.cvt.pk.f32.fp8" => "__builtin_amdgcn_cvt_pk_f32_fp8", - "llvm.amdgcn.cvt.pk.fp8.f32" => "__builtin_amdgcn_cvt_pk_fp8_f32", - "llvm.amdgcn.cvt.pk.i16" => "__builtin_amdgcn_cvt_pk_i16", - "llvm.amdgcn.cvt.pk.u16" => "__builtin_amdgcn_cvt_pk_u16", - "llvm.amdgcn.cvt.pk.u8.f32" => "__builtin_amdgcn_cvt_pk_u8_f32", - "llvm.amdgcn.cvt.pknorm.i16" => "__builtin_amdgcn_cvt_pknorm_i16", - "llvm.amdgcn.cvt.pknorm.u16" => "__builtin_amdgcn_cvt_pknorm_u16", - "llvm.amdgcn.cvt.pkrtz" => "__builtin_amdgcn_cvt_pkrtz", - "llvm.amdgcn.cvt.scalef32.2xpk16.bf6.f32" => "__builtin_amdgcn_cvt_scalef32_2xpk16_bf6_f32", - "llvm.amdgcn.cvt.scalef32.2xpk16.fp6.f32" => "__builtin_amdgcn_cvt_scalef32_2xpk16_fp6_f32", - "llvm.amdgcn.cvt.scalef32.f16.bf8" => "__builtin_amdgcn_cvt_scalef32_f16_bf8", - "llvm.amdgcn.cvt.scalef32.f16.fp8" => "__builtin_amdgcn_cvt_scalef32_f16_fp8", - "llvm.amdgcn.cvt.scalef32.f32.bf8" => "__builtin_amdgcn_cvt_scalef32_f32_bf8", - "llvm.amdgcn.cvt.scalef32.f32.fp8" => "__builtin_amdgcn_cvt_scalef32_f32_fp8", - "llvm.amdgcn.cvt.scalef32.pk.bf16.bf8" => "__builtin_amdgcn_cvt_scalef32_pk_bf16_bf8", - "llvm.amdgcn.cvt.scalef32.pk.bf16.fp4" => "__builtin_amdgcn_cvt_scalef32_pk_bf16_fp4", - "llvm.amdgcn.cvt.scalef32.pk.bf16.fp8" => "__builtin_amdgcn_cvt_scalef32_pk_bf16_fp8", - "llvm.amdgcn.cvt.scalef32.pk.bf8.bf16" => "__builtin_amdgcn_cvt_scalef32_pk_bf8_bf16", - "llvm.amdgcn.cvt.scalef32.pk.bf8.f16" => "__builtin_amdgcn_cvt_scalef32_pk_bf8_f16", - "llvm.amdgcn.cvt.scalef32.pk.bf8.f32" => "__builtin_amdgcn_cvt_scalef32_pk_bf8_f32", - "llvm.amdgcn.cvt.scalef32.pk.f16.bf8" => "__builtin_amdgcn_cvt_scalef32_pk_f16_bf8", - "llvm.amdgcn.cvt.scalef32.pk.f16.fp4" => "__builtin_amdgcn_cvt_scalef32_pk_f16_fp4", - "llvm.amdgcn.cvt.scalef32.pk.f16.fp8" => "__builtin_amdgcn_cvt_scalef32_pk_f16_fp8", - "llvm.amdgcn.cvt.scalef32.pk.f32.bf8" => "__builtin_amdgcn_cvt_scalef32_pk_f32_bf8", - "llvm.amdgcn.cvt.scalef32.pk.f32.fp4" => "__builtin_amdgcn_cvt_scalef32_pk_f32_fp4", - "llvm.amdgcn.cvt.scalef32.pk.f32.fp8" => "__builtin_amdgcn_cvt_scalef32_pk_f32_fp8", - "llvm.amdgcn.cvt.scalef32.pk.fp4.bf16" => "__builtin_amdgcn_cvt_scalef32_pk_fp4_bf16", - "llvm.amdgcn.cvt.scalef32.pk.fp4.f16" => "__builtin_amdgcn_cvt_scalef32_pk_fp4_f16", - "llvm.amdgcn.cvt.scalef32.pk.fp4.f32" => "__builtin_amdgcn_cvt_scalef32_pk_fp4_f32", - "llvm.amdgcn.cvt.scalef32.pk.fp8.bf16" => "__builtin_amdgcn_cvt_scalef32_pk_fp8_bf16", - "llvm.amdgcn.cvt.scalef32.pk.fp8.f16" => "__builtin_amdgcn_cvt_scalef32_pk_fp8_f16", - "llvm.amdgcn.cvt.scalef32.pk.fp8.f32" => "__builtin_amdgcn_cvt_scalef32_pk_fp8_f32", - "llvm.amdgcn.cvt.scalef32.pk32.bf16.bf6" => "__builtin_amdgcn_cvt_scalef32_pk32_bf16_bf6", - "llvm.amdgcn.cvt.scalef32.pk32.bf16.fp6" => "__builtin_amdgcn_cvt_scalef32_pk32_bf16_fp6", - "llvm.amdgcn.cvt.scalef32.pk32.bf6.bf16" => "__builtin_amdgcn_cvt_scalef32_pk32_bf6_bf16", - "llvm.amdgcn.cvt.scalef32.pk32.bf6.f16" => "__builtin_amdgcn_cvt_scalef32_pk32_bf6_f16", - "llvm.amdgcn.cvt.scalef32.pk32.f16.bf6" => "__builtin_amdgcn_cvt_scalef32_pk32_f16_bf6", - "llvm.amdgcn.cvt.scalef32.pk32.f16.fp6" => "__builtin_amdgcn_cvt_scalef32_pk32_f16_fp6", - "llvm.amdgcn.cvt.scalef32.pk32.f32.bf6" => "__builtin_amdgcn_cvt_scalef32_pk32_f32_bf6", - "llvm.amdgcn.cvt.scalef32.pk32.f32.fp6" => "__builtin_amdgcn_cvt_scalef32_pk32_f32_fp6", - "llvm.amdgcn.cvt.scalef32.pk32.fp6.bf16" => "__builtin_amdgcn_cvt_scalef32_pk32_fp6_bf16", - "llvm.amdgcn.cvt.scalef32.pk32.fp6.f16" => "__builtin_amdgcn_cvt_scalef32_pk32_fp6_f16", - "llvm.amdgcn.cvt.scalef32.sr.bf8.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_bf8_bf16", - "llvm.amdgcn.cvt.scalef32.sr.bf8.f16" => "__builtin_amdgcn_cvt_scalef32_sr_bf8_f16", - "llvm.amdgcn.cvt.scalef32.sr.bf8.f32" => "__builtin_amdgcn_cvt_scalef32_sr_bf8_f32", - "llvm.amdgcn.cvt.scalef32.sr.fp8.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_fp8_bf16", - "llvm.amdgcn.cvt.scalef32.sr.fp8.f16" => "__builtin_amdgcn_cvt_scalef32_sr_fp8_f16", - "llvm.amdgcn.cvt.scalef32.sr.fp8.f32" => "__builtin_amdgcn_cvt_scalef32_sr_fp8_f32", - "llvm.amdgcn.cvt.scalef32.sr.pk.fp4.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_pk_fp4_bf16", - "llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16" => "__builtin_amdgcn_cvt_scalef32_sr_pk_fp4_f16", - "llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f32" => "__builtin_amdgcn_cvt_scalef32_sr_pk_fp4_f32", - "llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_pk32_bf6_bf16", - "llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16" => "__builtin_amdgcn_cvt_scalef32_sr_pk32_bf6_f16", - "llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32" => "__builtin_amdgcn_cvt_scalef32_sr_pk32_bf6_f32", - "llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_pk32_fp6_bf16", - "llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16" => "__builtin_amdgcn_cvt_scalef32_sr_pk32_fp6_f16", - "llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32" => "__builtin_amdgcn_cvt_scalef32_sr_pk32_fp6_f32", - "llvm.amdgcn.cvt.sr.bf16.f32" => "__builtin_amdgcn_cvt_sr_bf16_f32", - "llvm.amdgcn.cvt.sr.bf8.f32" => "__builtin_amdgcn_cvt_sr_bf8_f32", - "llvm.amdgcn.cvt.sr.f16.f32" => "__builtin_amdgcn_cvt_sr_f16_f32", - "llvm.amdgcn.cvt.sr.fp8.f32" => "__builtin_amdgcn_cvt_sr_fp8_f32", - "llvm.amdgcn.dispatch.id" => "__builtin_amdgcn_dispatch_id", - "llvm.amdgcn.dot4.f32.bf8.bf8" => "__builtin_amdgcn_dot4_f32_bf8_bf8", - "llvm.amdgcn.dot4.f32.bf8.fp8" => "__builtin_amdgcn_dot4_f32_bf8_fp8", - "llvm.amdgcn.dot4.f32.fp8.bf8" => "__builtin_amdgcn_dot4_f32_fp8_bf8", - "llvm.amdgcn.dot4.f32.fp8.fp8" => "__builtin_amdgcn_dot4_f32_fp8_fp8", - "llvm.amdgcn.ds.add.gs.reg.rtn" => "__builtin_amdgcn_ds_add_gs_reg_rtn", - "llvm.amdgcn.ds.bpermute" => "__builtin_amdgcn_ds_bpermute", - "llvm.amdgcn.ds.bpermute.fi.b32" => "__builtin_amdgcn_ds_bpermute_fi_b32", - "llvm.amdgcn.ds.gws.barrier" => "__builtin_amdgcn_ds_gws_barrier", - "llvm.amdgcn.ds.gws.init" => "__builtin_amdgcn_ds_gws_init", - "llvm.amdgcn.ds.gws.sema.br" => "__builtin_amdgcn_ds_gws_sema_br", - "llvm.amdgcn.ds.gws.sema.p" => "__builtin_amdgcn_ds_gws_sema_p", - "llvm.amdgcn.ds.gws.sema.release.all" => "__builtin_amdgcn_ds_gws_sema_release_all", - "llvm.amdgcn.ds.gws.sema.v" => "__builtin_amdgcn_ds_gws_sema_v", - "llvm.amdgcn.ds.permute" => "__builtin_amdgcn_ds_permute", - "llvm.amdgcn.ds.sub.gs.reg.rtn" => "__builtin_amdgcn_ds_sub_gs_reg_rtn", - "llvm.amdgcn.ds.swizzle" => "__builtin_amdgcn_ds_swizzle", - "llvm.amdgcn.endpgm" => "__builtin_amdgcn_endpgm", - "llvm.amdgcn.fdot2" => "__builtin_amdgcn_fdot2", - "llvm.amdgcn.fdot2.bf16.bf16" => "__builtin_amdgcn_fdot2_bf16_bf16", - "llvm.amdgcn.fdot2.f16.f16" => "__builtin_amdgcn_fdot2_f16_f16", - "llvm.amdgcn.fdot2.f32.bf16" => "__builtin_amdgcn_fdot2_f32_bf16", - "llvm.amdgcn.fdot2c.f32.bf16" => "__builtin_amdgcn_fdot2c_f32_bf16", - "llvm.amdgcn.fmul.legacy" => "__builtin_amdgcn_fmul_legacy", - "llvm.amdgcn.global.load.lds" => "__builtin_amdgcn_global_load_lds", - "llvm.amdgcn.groupstaticsize" => "__builtin_amdgcn_groupstaticsize", - "llvm.amdgcn.iglp.opt" => "__builtin_amdgcn_iglp_opt", - "llvm.amdgcn.implicit.buffer.ptr" => "__builtin_amdgcn_implicit_buffer_ptr", - "llvm.amdgcn.implicitarg.ptr" => "__builtin_amdgcn_implicitarg_ptr", - "llvm.amdgcn.interp.mov" => "__builtin_amdgcn_interp_mov", - "llvm.amdgcn.interp.p1" => "__builtin_amdgcn_interp_p1", - "llvm.amdgcn.interp.p1.f16" => "__builtin_amdgcn_interp_p1_f16", - "llvm.amdgcn.interp.p2" => "__builtin_amdgcn_interp_p2", - "llvm.amdgcn.interp.p2.f16" => "__builtin_amdgcn_interp_p2_f16", - "llvm.amdgcn.is.private" => "__builtin_amdgcn_is_private", - "llvm.amdgcn.is.shared" => "__builtin_amdgcn_is_shared", - "llvm.amdgcn.kernarg.segment.ptr" => "__builtin_amdgcn_kernarg_segment_ptr", - "llvm.amdgcn.lerp" => "__builtin_amdgcn_lerp", - "llvm.amdgcn.mbcnt.hi" => "__builtin_amdgcn_mbcnt_hi", - "llvm.amdgcn.mbcnt.lo" => "__builtin_amdgcn_mbcnt_lo", - "llvm.amdgcn.mfma.f32.16x16x16bf16.1k" => "__builtin_amdgcn_mfma_f32_16x16x16bf16_1k", - "llvm.amdgcn.mfma.f32.16x16x16f16" => "__builtin_amdgcn_mfma_f32_16x16x16f16", - "llvm.amdgcn.mfma.f32.16x16x1f32" => "__builtin_amdgcn_mfma_f32_16x16x1f32", - "llvm.amdgcn.mfma.f32.16x16x2bf16" => "__builtin_amdgcn_mfma_f32_16x16x2bf16", - "llvm.amdgcn.mfma.f32.16x16x32.bf16" => "__builtin_amdgcn_mfma_f32_16x16x32_bf16", - "llvm.amdgcn.mfma.f32.16x16x32.bf8.bf8" => "__builtin_amdgcn_mfma_f32_16x16x32_bf8_bf8", - "llvm.amdgcn.mfma.f32.16x16x32.bf8.fp8" => "__builtin_amdgcn_mfma_f32_16x16x32_bf8_fp8", - "llvm.amdgcn.mfma.f32.16x16x32.f16" => "__builtin_amdgcn_mfma_f32_16x16x32_f16", - "llvm.amdgcn.mfma.f32.16x16x32.fp8.bf8" => "__builtin_amdgcn_mfma_f32_16x16x32_fp8_bf8", - "llvm.amdgcn.mfma.f32.16x16x32.fp8.fp8" => "__builtin_amdgcn_mfma_f32_16x16x32_fp8_fp8", - "llvm.amdgcn.mfma.f32.16x16x4bf16.1k" => "__builtin_amdgcn_mfma_f32_16x16x4bf16_1k", - "llvm.amdgcn.mfma.f32.16x16x4f16" => "__builtin_amdgcn_mfma_f32_16x16x4f16", - "llvm.amdgcn.mfma.f32.16x16x4f32" => "__builtin_amdgcn_mfma_f32_16x16x4f32", - "llvm.amdgcn.mfma.f32.16x16x8.xf32" => "__builtin_amdgcn_mfma_f32_16x16x8_xf32", - "llvm.amdgcn.mfma.f32.16x16x8bf16" => "__builtin_amdgcn_mfma_f32_16x16x8bf16", - "llvm.amdgcn.mfma.f32.32x32x16.bf16" => "__builtin_amdgcn_mfma_f32_32x32x16_bf16", - "llvm.amdgcn.mfma.f32.32x32x16.bf8.bf8" => "__builtin_amdgcn_mfma_f32_32x32x16_bf8_bf8", - "llvm.amdgcn.mfma.f32.32x32x16.bf8.fp8" => "__builtin_amdgcn_mfma_f32_32x32x16_bf8_fp8", - "llvm.amdgcn.mfma.f32.32x32x16.f16" => "__builtin_amdgcn_mfma_f32_32x32x16_f16", - "llvm.amdgcn.mfma.f32.32x32x16.fp8.bf8" => "__builtin_amdgcn_mfma_f32_32x32x16_fp8_bf8", - "llvm.amdgcn.mfma.f32.32x32x16.fp8.fp8" => "__builtin_amdgcn_mfma_f32_32x32x16_fp8_fp8", - "llvm.amdgcn.mfma.f32.32x32x1f32" => "__builtin_amdgcn_mfma_f32_32x32x1f32", - "llvm.amdgcn.mfma.f32.32x32x2bf16" => "__builtin_amdgcn_mfma_f32_32x32x2bf16", - "llvm.amdgcn.mfma.f32.32x32x2f32" => "__builtin_amdgcn_mfma_f32_32x32x2f32", - "llvm.amdgcn.mfma.f32.32x32x4.xf32" => "__builtin_amdgcn_mfma_f32_32x32x4_xf32", - "llvm.amdgcn.mfma.f32.32x32x4bf16" => "__builtin_amdgcn_mfma_f32_32x32x4bf16", - "llvm.amdgcn.mfma.f32.32x32x4bf16.1k" => "__builtin_amdgcn_mfma_f32_32x32x4bf16_1k", - "llvm.amdgcn.mfma.f32.32x32x4f16" => "__builtin_amdgcn_mfma_f32_32x32x4f16", - "llvm.amdgcn.mfma.f32.32x32x8bf16.1k" => "__builtin_amdgcn_mfma_f32_32x32x8bf16_1k", - "llvm.amdgcn.mfma.f32.32x32x8f16" => "__builtin_amdgcn_mfma_f32_32x32x8f16", - "llvm.amdgcn.mfma.f32.4x4x1f32" => "__builtin_amdgcn_mfma_f32_4x4x1f32", - "llvm.amdgcn.mfma.f32.4x4x2bf16" => "__builtin_amdgcn_mfma_f32_4x4x2bf16", - "llvm.amdgcn.mfma.f32.4x4x4bf16.1k" => "__builtin_amdgcn_mfma_f32_4x4x4bf16_1k", - "llvm.amdgcn.mfma.f32.4x4x4f16" => "__builtin_amdgcn_mfma_f32_4x4x4f16", - "llvm.amdgcn.mfma.f64.16x16x4f64" => "__builtin_amdgcn_mfma_f64_16x16x4f64", - "llvm.amdgcn.mfma.f64.4x4x4f64" => "__builtin_amdgcn_mfma_f64_4x4x4f64", - "llvm.amdgcn.mfma.i32.16x16x16i8" => "__builtin_amdgcn_mfma_i32_16x16x16i8", - "llvm.amdgcn.mfma.i32.16x16x32.i8" => "__builtin_amdgcn_mfma_i32_16x16x32_i8", - "llvm.amdgcn.mfma.i32.16x16x4i8" => "__builtin_amdgcn_mfma_i32_16x16x4i8", - "llvm.amdgcn.mfma.i32.16x16x64.i8" => "__builtin_amdgcn_mfma_i32_16x16x64_i8", - "llvm.amdgcn.mfma.i32.32x32x16.i8" => "__builtin_amdgcn_mfma_i32_32x32x16_i8", - "llvm.amdgcn.mfma.i32.32x32x32.i8" => "__builtin_amdgcn_mfma_i32_32x32x32_i8", - "llvm.amdgcn.mfma.i32.32x32x4i8" => "__builtin_amdgcn_mfma_i32_32x32x4i8", - "llvm.amdgcn.mfma.i32.32x32x8i8" => "__builtin_amdgcn_mfma_i32_32x32x8i8", - "llvm.amdgcn.mfma.i32.4x4x4i8" => "__builtin_amdgcn_mfma_i32_4x4x4i8", - "llvm.amdgcn.mqsad.pk.u16.u8" => "__builtin_amdgcn_mqsad_pk_u16_u8", - "llvm.amdgcn.mqsad.u32.u8" => "__builtin_amdgcn_mqsad_u32_u8", - "llvm.amdgcn.msad.u8" => "__builtin_amdgcn_msad_u8", - "llvm.amdgcn.perm" => "__builtin_amdgcn_perm", - "llvm.amdgcn.permlane16.var" => "__builtin_amdgcn_permlane16_var", - "llvm.amdgcn.permlanex16.var" => "__builtin_amdgcn_permlanex16_var", - "llvm.amdgcn.prng.b32" => "__builtin_amdgcn_prng_b32", - "llvm.amdgcn.qsad.pk.u16.u8" => "__builtin_amdgcn_qsad_pk_u16_u8", - "llvm.amdgcn.queue.ptr" => "__builtin_amdgcn_queue_ptr", - "llvm.amdgcn.raw.ptr.buffer.load.lds" => "__builtin_amdgcn_raw_ptr_buffer_load_lds", - "llvm.amdgcn.rcp.legacy" => "__builtin_amdgcn_rcp_legacy", - "llvm.amdgcn.rsq.legacy" => "__builtin_amdgcn_rsq_legacy", - "llvm.amdgcn.s.barrier" => "__builtin_amdgcn_s_barrier", - "llvm.amdgcn.s.barrier.signal" => "__builtin_amdgcn_s_barrier_signal", - "llvm.amdgcn.s.barrier.signal.isfirst" => "__builtin_amdgcn_s_barrier_signal_isfirst", - "llvm.amdgcn.s.barrier.signal.var" => "__builtin_amdgcn_s_barrier_signal_var", - "llvm.amdgcn.s.barrier.wait" => "__builtin_amdgcn_s_barrier_wait", - "llvm.amdgcn.s.buffer.prefetch.data" => "__builtin_amdgcn_s_buffer_prefetch_data", - "llvm.amdgcn.s.dcache.inv" => "__builtin_amdgcn_s_dcache_inv", - "llvm.amdgcn.s.dcache.inv.vol" => "__builtin_amdgcn_s_dcache_inv_vol", - "llvm.amdgcn.s.dcache.wb" => "__builtin_amdgcn_s_dcache_wb", - "llvm.amdgcn.s.dcache.wb.vol" => "__builtin_amdgcn_s_dcache_wb_vol", - "llvm.amdgcn.s.decperflevel" => "__builtin_amdgcn_s_decperflevel", - "llvm.amdgcn.s.get.barrier.state" => "__builtin_amdgcn_s_get_barrier_state", - "llvm.amdgcn.s.get.named.barrier.state" => "__builtin_amdgcn_s_get_named_barrier_state", - "llvm.amdgcn.s.get.waveid.in.workgroup" => "__builtin_amdgcn_s_get_waveid_in_workgroup", - "llvm.amdgcn.s.getpc" => "__builtin_amdgcn_s_getpc", - "llvm.amdgcn.s.getreg" => "__builtin_amdgcn_s_getreg", - "llvm.amdgcn.s.incperflevel" => "__builtin_amdgcn_s_incperflevel", - "llvm.amdgcn.s.memrealtime" => "__builtin_amdgcn_s_memrealtime", - "llvm.amdgcn.s.memtime" => "__builtin_amdgcn_s_memtime", - "llvm.amdgcn.s.sendmsg" => "__builtin_amdgcn_s_sendmsg", - "llvm.amdgcn.s.sendmsghalt" => "__builtin_amdgcn_s_sendmsghalt", - "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio", - "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg", - "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", - "llvm.amdgcn.s.sleep.var" => "__builtin_amdgcn_s_sleep_var", - "llvm.amdgcn.s.ttracedata" => "__builtin_amdgcn_s_ttracedata", - "llvm.amdgcn.s.ttracedata.imm" => "__builtin_amdgcn_s_ttracedata_imm", - "llvm.amdgcn.s.wait.event.export.ready" => "__builtin_amdgcn_s_wait_event_export_ready", - "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt", - "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", - "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", - "llvm.amdgcn.sad.u8" => "__builtin_amdgcn_sad_u8", - "llvm.amdgcn.sched.barrier" => "__builtin_amdgcn_sched_barrier", - "llvm.amdgcn.sched.group.barrier" => "__builtin_amdgcn_sched_group_barrier", - "llvm.amdgcn.sdot2" => "__builtin_amdgcn_sdot2", - "llvm.amdgcn.sdot4" => "__builtin_amdgcn_sdot4", - "llvm.amdgcn.sdot8" => "__builtin_amdgcn_sdot8", - "llvm.amdgcn.smfmac.f32.16x16x128.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x128_bf8_bf8", - "llvm.amdgcn.smfmac.f32.16x16x128.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x128_bf8_fp8", - "llvm.amdgcn.smfmac.f32.16x16x128.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x128_fp8_bf8", - "llvm.amdgcn.smfmac.f32.16x16x128.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x128_fp8_fp8", - "llvm.amdgcn.smfmac.f32.16x16x32.bf16" => "__builtin_amdgcn_smfmac_f32_16x16x32_bf16", - "llvm.amdgcn.smfmac.f32.16x16x32.f16" => "__builtin_amdgcn_smfmac_f32_16x16x32_f16", - "llvm.amdgcn.smfmac.f32.16x16x64.bf16" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf16", - "llvm.amdgcn.smfmac.f32.16x16x64.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf8_bf8", - "llvm.amdgcn.smfmac.f32.16x16x64.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf8_fp8", - "llvm.amdgcn.smfmac.f32.16x16x64.f16" => "__builtin_amdgcn_smfmac_f32_16x16x64_f16", - "llvm.amdgcn.smfmac.f32.16x16x64.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x64_fp8_bf8", - "llvm.amdgcn.smfmac.f32.16x16x64.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x64_fp8_fp8", - "llvm.amdgcn.smfmac.f32.32x32x16.bf16" => "__builtin_amdgcn_smfmac_f32_32x32x16_bf16", - "llvm.amdgcn.smfmac.f32.32x32x16.f16" => "__builtin_amdgcn_smfmac_f32_32x32x16_f16", - "llvm.amdgcn.smfmac.f32.32x32x32.bf16" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf16", - "llvm.amdgcn.smfmac.f32.32x32x32.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf8_bf8", - "llvm.amdgcn.smfmac.f32.32x32x32.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf8_fp8", - "llvm.amdgcn.smfmac.f32.32x32x32.f16" => "__builtin_amdgcn_smfmac_f32_32x32x32_f16", - "llvm.amdgcn.smfmac.f32.32x32x32.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x32_fp8_bf8", - "llvm.amdgcn.smfmac.f32.32x32x32.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x32_fp8_fp8", - "llvm.amdgcn.smfmac.f32.32x32x64.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x64_bf8_bf8", - "llvm.amdgcn.smfmac.f32.32x32x64.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x64_bf8_fp8", - "llvm.amdgcn.smfmac.f32.32x32x64.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x64_fp8_bf8", - "llvm.amdgcn.smfmac.f32.32x32x64.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x64_fp8_fp8", - "llvm.amdgcn.smfmac.i32.16x16x128.i8" => "__builtin_amdgcn_smfmac_i32_16x16x128_i8", - "llvm.amdgcn.smfmac.i32.16x16x64.i8" => "__builtin_amdgcn_smfmac_i32_16x16x64_i8", - "llvm.amdgcn.smfmac.i32.32x32x32.i8" => "__builtin_amdgcn_smfmac_i32_32x32x32_i8", - "llvm.amdgcn.smfmac.i32.32x32x64.i8" => "__builtin_amdgcn_smfmac_i32_32x32x64_i8", - "llvm.amdgcn.sudot4" => "__builtin_amdgcn_sudot4", - "llvm.amdgcn.sudot8" => "__builtin_amdgcn_sudot8", - "llvm.amdgcn.udot2" => "__builtin_amdgcn_udot2", - "llvm.amdgcn.udot4" => "__builtin_amdgcn_udot4", - "llvm.amdgcn.udot8" => "__builtin_amdgcn_udot8", - "llvm.amdgcn.wave.barrier" => "__builtin_amdgcn_wave_barrier", - "llvm.amdgcn.wavefrontsize" => "__builtin_amdgcn_wavefrontsize", - "llvm.amdgcn.workgroup.id.x" => "__builtin_amdgcn_workgroup_id_x", - "llvm.amdgcn.workgroup.id.y" => "__builtin_amdgcn_workgroup_id_y", - "llvm.amdgcn.workgroup.id.z" => "__builtin_amdgcn_workgroup_id_z", - "llvm.amdgcn.workitem.id.x" => "__builtin_amdgcn_workitem_id_x", - "llvm.amdgcn.workitem.id.y" => "__builtin_amdgcn_workitem_id_y", - "llvm.amdgcn.workitem.id.z" => "__builtin_amdgcn_workitem_id_z", - // arm - "llvm.arm.cdp" => "__builtin_arm_cdp", - "llvm.arm.cdp2" => "__builtin_arm_cdp2", - "llvm.arm.cmse.tt" => "__builtin_arm_cmse_TT", - "llvm.arm.cmse.tta" => "__builtin_arm_cmse_TTA", - "llvm.arm.cmse.ttat" => "__builtin_arm_cmse_TTAT", - "llvm.arm.cmse.ttt" => "__builtin_arm_cmse_TTT", - "llvm.arm.dmb" => "__builtin_arm_dmb", - "llvm.arm.dsb" => "__builtin_arm_dsb", - "llvm.arm.get.fpscr" => "__builtin_arm_get_fpscr", - "llvm.arm.isb" => "__builtin_arm_isb", - "llvm.arm.ldc" => "__builtin_arm_ldc", - "llvm.arm.ldc2" => "__builtin_arm_ldc2", - "llvm.arm.ldc2l" => "__builtin_arm_ldc2l", - "llvm.arm.ldcl" => "__builtin_arm_ldcl", - "llvm.arm.mcr" => "__builtin_arm_mcr", - "llvm.arm.mcr2" => "__builtin_arm_mcr2", - "llvm.arm.mcrr" => "__builtin_arm_mcrr", - "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", - "llvm.arm.mrc" => "__builtin_arm_mrc", - "llvm.arm.mrc2" => "__builtin_arm_mrc2", - "llvm.arm.qadd" => "__builtin_arm_qadd", - "llvm.arm.qadd16" => "__builtin_arm_qadd16", - "llvm.arm.qadd8" => "__builtin_arm_qadd8", - "llvm.arm.qasx" => "__builtin_arm_qasx", - "llvm.arm.qsax" => "__builtin_arm_qsax", - "llvm.arm.qsub" => "__builtin_arm_qsub", - "llvm.arm.qsub16" => "__builtin_arm_qsub16", - "llvm.arm.qsub8" => "__builtin_arm_qsub8", - "llvm.arm.sadd16" => "__builtin_arm_sadd16", - "llvm.arm.sadd8" => "__builtin_arm_sadd8", - "llvm.arm.sasx" => "__builtin_arm_sasx", - "llvm.arm.sel" => "__builtin_arm_sel", - "llvm.arm.set.fpscr" => "__builtin_arm_set_fpscr", - "llvm.arm.shadd16" => "__builtin_arm_shadd16", - "llvm.arm.shadd8" => "__builtin_arm_shadd8", - "llvm.arm.shasx" => "__builtin_arm_shasx", - "llvm.arm.shsax" => "__builtin_arm_shsax", - "llvm.arm.shsub16" => "__builtin_arm_shsub16", - "llvm.arm.shsub8" => "__builtin_arm_shsub8", - "llvm.arm.smlabb" => "__builtin_arm_smlabb", - "llvm.arm.smlabt" => "__builtin_arm_smlabt", - "llvm.arm.smlad" => "__builtin_arm_smlad", - "llvm.arm.smladx" => "__builtin_arm_smladx", - "llvm.arm.smlald" => "__builtin_arm_smlald", - "llvm.arm.smlaldx" => "__builtin_arm_smlaldx", - "llvm.arm.smlatb" => "__builtin_arm_smlatb", - "llvm.arm.smlatt" => "__builtin_arm_smlatt", - "llvm.arm.smlawb" => "__builtin_arm_smlawb", - "llvm.arm.smlawt" => "__builtin_arm_smlawt", - "llvm.arm.smlsd" => "__builtin_arm_smlsd", - "llvm.arm.smlsdx" => "__builtin_arm_smlsdx", - "llvm.arm.smlsld" => "__builtin_arm_smlsld", - "llvm.arm.smlsldx" => "__builtin_arm_smlsldx", - "llvm.arm.smuad" => "__builtin_arm_smuad", - "llvm.arm.smuadx" => "__builtin_arm_smuadx", - "llvm.arm.smulbb" => "__builtin_arm_smulbb", - "llvm.arm.smulbt" => "__builtin_arm_smulbt", - "llvm.arm.smultb" => "__builtin_arm_smultb", - "llvm.arm.smultt" => "__builtin_arm_smultt", - "llvm.arm.smulwb" => "__builtin_arm_smulwb", - "llvm.arm.smulwt" => "__builtin_arm_smulwt", - "llvm.arm.smusd" => "__builtin_arm_smusd", - "llvm.arm.smusdx" => "__builtin_arm_smusdx", - "llvm.arm.ssat" => "__builtin_arm_ssat", - "llvm.arm.ssat16" => "__builtin_arm_ssat16", - "llvm.arm.ssax" => "__builtin_arm_ssax", - "llvm.arm.ssub16" => "__builtin_arm_ssub16", - "llvm.arm.ssub8" => "__builtin_arm_ssub8", - "llvm.arm.stc" => "__builtin_arm_stc", - "llvm.arm.stc2" => "__builtin_arm_stc2", - "llvm.arm.stc2l" => "__builtin_arm_stc2l", - "llvm.arm.stcl" => "__builtin_arm_stcl", - "llvm.arm.sxtab16" => "__builtin_arm_sxtab16", - "llvm.arm.sxtb16" => "__builtin_arm_sxtb16", - "llvm.arm.thread.pointer" => "__builtin_thread_pointer", - "llvm.arm.uadd16" => "__builtin_arm_uadd16", - "llvm.arm.uadd8" => "__builtin_arm_uadd8", - "llvm.arm.uasx" => "__builtin_arm_uasx", - "llvm.arm.uhadd16" => "__builtin_arm_uhadd16", - "llvm.arm.uhadd8" => "__builtin_arm_uhadd8", - "llvm.arm.uhasx" => "__builtin_arm_uhasx", - "llvm.arm.uhsax" => "__builtin_arm_uhsax", - "llvm.arm.uhsub16" => "__builtin_arm_uhsub16", - "llvm.arm.uhsub8" => "__builtin_arm_uhsub8", - "llvm.arm.uqadd16" => "__builtin_arm_uqadd16", - "llvm.arm.uqadd8" => "__builtin_arm_uqadd8", - "llvm.arm.uqasx" => "__builtin_arm_uqasx", - "llvm.arm.uqsax" => "__builtin_arm_uqsax", - "llvm.arm.uqsub16" => "__builtin_arm_uqsub16", - "llvm.arm.uqsub8" => "__builtin_arm_uqsub8", - "llvm.arm.usad8" => "__builtin_arm_usad8", - "llvm.arm.usada8" => "__builtin_arm_usada8", - "llvm.arm.usat" => "__builtin_arm_usat", - "llvm.arm.usat16" => "__builtin_arm_usat16", - "llvm.arm.usax" => "__builtin_arm_usax", - "llvm.arm.usub16" => "__builtin_arm_usub16", - "llvm.arm.usub8" => "__builtin_arm_usub8", - "llvm.arm.uxtab16" => "__builtin_arm_uxtab16", - "llvm.arm.uxtb16" => "__builtin_arm_uxtb16", - // bpf - "llvm.bpf.btf.type.id" => "__builtin_bpf_btf_type_id", - "llvm.bpf.compare" => "__builtin_bpf_compare", - "llvm.bpf.getelementptr.and.load" => "__builtin_bpf_getelementptr_and_load", - "llvm.bpf.getelementptr.and.store" => "__builtin_bpf_getelementptr_and_store", - "llvm.bpf.load.byte" => "__builtin_bpf_load_byte", - "llvm.bpf.load.half" => "__builtin_bpf_load_half", - "llvm.bpf.load.word" => "__builtin_bpf_load_word", - "llvm.bpf.passthrough" => "__builtin_bpf_passthrough", - "llvm.bpf.preserve.enum.value" => "__builtin_bpf_preserve_enum_value", - "llvm.bpf.preserve.field.info" => "__builtin_bpf_preserve_field_info", - "llvm.bpf.preserve.type.info" => "__builtin_bpf_preserve_type_info", - "llvm.bpf.pseudo" => "__builtin_bpf_pseudo", - // cuda - "llvm.cuda.syncthreads" => "__syncthreads", - // hexagon - "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs", - "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp", - "llvm.hexagon.A2.abssat" => "__builtin_HEXAGON_A2_abssat", - "llvm.hexagon.A2.add" => "__builtin_HEXAGON_A2_add", - "llvm.hexagon.A2.addh.h16.hh" => "__builtin_HEXAGON_A2_addh_h16_hh", - "llvm.hexagon.A2.addh.h16.hl" => "__builtin_HEXAGON_A2_addh_h16_hl", - "llvm.hexagon.A2.addh.h16.lh" => "__builtin_HEXAGON_A2_addh_h16_lh", - "llvm.hexagon.A2.addh.h16.ll" => "__builtin_HEXAGON_A2_addh_h16_ll", - "llvm.hexagon.A2.addh.h16.sat.hh" => "__builtin_HEXAGON_A2_addh_h16_sat_hh", - "llvm.hexagon.A2.addh.h16.sat.hl" => "__builtin_HEXAGON_A2_addh_h16_sat_hl", - "llvm.hexagon.A2.addh.h16.sat.lh" => "__builtin_HEXAGON_A2_addh_h16_sat_lh", - "llvm.hexagon.A2.addh.h16.sat.ll" => "__builtin_HEXAGON_A2_addh_h16_sat_ll", - "llvm.hexagon.A2.addh.l16.hl" => "__builtin_HEXAGON_A2_addh_l16_hl", - "llvm.hexagon.A2.addh.l16.ll" => "__builtin_HEXAGON_A2_addh_l16_ll", - "llvm.hexagon.A2.addh.l16.sat.hl" => "__builtin_HEXAGON_A2_addh_l16_sat_hl", - "llvm.hexagon.A2.addh.l16.sat.ll" => "__builtin_HEXAGON_A2_addh_l16_sat_ll", - "llvm.hexagon.A2.addi" => "__builtin_HEXAGON_A2_addi", - "llvm.hexagon.A2.addp" => "__builtin_HEXAGON_A2_addp", - "llvm.hexagon.A2.addpsat" => "__builtin_HEXAGON_A2_addpsat", - "llvm.hexagon.A2.addsat" => "__builtin_HEXAGON_A2_addsat", - "llvm.hexagon.A2.addsp" => "__builtin_HEXAGON_A2_addsp", - "llvm.hexagon.A2.and" => "__builtin_HEXAGON_A2_and", - "llvm.hexagon.A2.andir" => "__builtin_HEXAGON_A2_andir", - "llvm.hexagon.A2.andp" => "__builtin_HEXAGON_A2_andp", - "llvm.hexagon.A2.aslh" => "__builtin_HEXAGON_A2_aslh", - "llvm.hexagon.A2.asrh" => "__builtin_HEXAGON_A2_asrh", - "llvm.hexagon.A2.combine.hh" => "__builtin_HEXAGON_A2_combine_hh", - "llvm.hexagon.A2.combine.hl" => "__builtin_HEXAGON_A2_combine_hl", - "llvm.hexagon.A2.combine.lh" => "__builtin_HEXAGON_A2_combine_lh", - "llvm.hexagon.A2.combine.ll" => "__builtin_HEXAGON_A2_combine_ll", - "llvm.hexagon.A2.combineii" => "__builtin_HEXAGON_A2_combineii", - "llvm.hexagon.A2.combinew" => "__builtin_HEXAGON_A2_combinew", - "llvm.hexagon.A2.max" => "__builtin_HEXAGON_A2_max", - "llvm.hexagon.A2.maxp" => "__builtin_HEXAGON_A2_maxp", - "llvm.hexagon.A2.maxu" => "__builtin_HEXAGON_A2_maxu", - "llvm.hexagon.A2.maxup" => "__builtin_HEXAGON_A2_maxup", - "llvm.hexagon.A2.min" => "__builtin_HEXAGON_A2_min", - "llvm.hexagon.A2.minp" => "__builtin_HEXAGON_A2_minp", - "llvm.hexagon.A2.minu" => "__builtin_HEXAGON_A2_minu", - "llvm.hexagon.A2.minup" => "__builtin_HEXAGON_A2_minup", - "llvm.hexagon.A2.neg" => "__builtin_HEXAGON_A2_neg", - "llvm.hexagon.A2.negp" => "__builtin_HEXAGON_A2_negp", - "llvm.hexagon.A2.negsat" => "__builtin_HEXAGON_A2_negsat", - "llvm.hexagon.A2.not" => "__builtin_HEXAGON_A2_not", - "llvm.hexagon.A2.notp" => "__builtin_HEXAGON_A2_notp", - "llvm.hexagon.A2.or" => "__builtin_HEXAGON_A2_or", - "llvm.hexagon.A2.orir" => "__builtin_HEXAGON_A2_orir", - "llvm.hexagon.A2.orp" => "__builtin_HEXAGON_A2_orp", - "llvm.hexagon.A2.roundsat" => "__builtin_HEXAGON_A2_roundsat", - "llvm.hexagon.A2.sat" => "__builtin_HEXAGON_A2_sat", - "llvm.hexagon.A2.satb" => "__builtin_HEXAGON_A2_satb", - "llvm.hexagon.A2.sath" => "__builtin_HEXAGON_A2_sath", - "llvm.hexagon.A2.satub" => "__builtin_HEXAGON_A2_satub", - "llvm.hexagon.A2.satuh" => "__builtin_HEXAGON_A2_satuh", - "llvm.hexagon.A2.sub" => "__builtin_HEXAGON_A2_sub", - "llvm.hexagon.A2.subh.h16.hh" => "__builtin_HEXAGON_A2_subh_h16_hh", - "llvm.hexagon.A2.subh.h16.hl" => "__builtin_HEXAGON_A2_subh_h16_hl", - "llvm.hexagon.A2.subh.h16.lh" => "__builtin_HEXAGON_A2_subh_h16_lh", - "llvm.hexagon.A2.subh.h16.ll" => "__builtin_HEXAGON_A2_subh_h16_ll", - "llvm.hexagon.A2.subh.h16.sat.hh" => "__builtin_HEXAGON_A2_subh_h16_sat_hh", - "llvm.hexagon.A2.subh.h16.sat.hl" => "__builtin_HEXAGON_A2_subh_h16_sat_hl", - "llvm.hexagon.A2.subh.h16.sat.lh" => "__builtin_HEXAGON_A2_subh_h16_sat_lh", - "llvm.hexagon.A2.subh.h16.sat.ll" => "__builtin_HEXAGON_A2_subh_h16_sat_ll", - "llvm.hexagon.A2.subh.l16.hl" => "__builtin_HEXAGON_A2_subh_l16_hl", - "llvm.hexagon.A2.subh.l16.ll" => "__builtin_HEXAGON_A2_subh_l16_ll", - "llvm.hexagon.A2.subh.l16.sat.hl" => "__builtin_HEXAGON_A2_subh_l16_sat_hl", - "llvm.hexagon.A2.subh.l16.sat.ll" => "__builtin_HEXAGON_A2_subh_l16_sat_ll", - "llvm.hexagon.A2.subp" => "__builtin_HEXAGON_A2_subp", - "llvm.hexagon.A2.subri" => "__builtin_HEXAGON_A2_subri", - "llvm.hexagon.A2.subsat" => "__builtin_HEXAGON_A2_subsat", - "llvm.hexagon.A2.svaddh" => "__builtin_HEXAGON_A2_svaddh", - "llvm.hexagon.A2.svaddhs" => "__builtin_HEXAGON_A2_svaddhs", - "llvm.hexagon.A2.svadduhs" => "__builtin_HEXAGON_A2_svadduhs", - "llvm.hexagon.A2.svavgh" => "__builtin_HEXAGON_A2_svavgh", - "llvm.hexagon.A2.svavghs" => "__builtin_HEXAGON_A2_svavghs", - "llvm.hexagon.A2.svnavgh" => "__builtin_HEXAGON_A2_svnavgh", - "llvm.hexagon.A2.svsubh" => "__builtin_HEXAGON_A2_svsubh", - "llvm.hexagon.A2.svsubhs" => "__builtin_HEXAGON_A2_svsubhs", - "llvm.hexagon.A2.svsubuhs" => "__builtin_HEXAGON_A2_svsubuhs", - "llvm.hexagon.A2.swiz" => "__builtin_HEXAGON_A2_swiz", - "llvm.hexagon.A2.sxtb" => "__builtin_HEXAGON_A2_sxtb", - "llvm.hexagon.A2.sxth" => "__builtin_HEXAGON_A2_sxth", - "llvm.hexagon.A2.sxtw" => "__builtin_HEXAGON_A2_sxtw", - "llvm.hexagon.A2.tfr" => "__builtin_HEXAGON_A2_tfr", - "llvm.hexagon.A2.tfrih" => "__builtin_HEXAGON_A2_tfrih", - "llvm.hexagon.A2.tfril" => "__builtin_HEXAGON_A2_tfril", - "llvm.hexagon.A2.tfrp" => "__builtin_HEXAGON_A2_tfrp", - "llvm.hexagon.A2.tfrpi" => "__builtin_HEXAGON_A2_tfrpi", - "llvm.hexagon.A2.tfrsi" => "__builtin_HEXAGON_A2_tfrsi", - "llvm.hexagon.A2.vabsh" => "__builtin_HEXAGON_A2_vabsh", - "llvm.hexagon.A2.vabshsat" => "__builtin_HEXAGON_A2_vabshsat", - "llvm.hexagon.A2.vabsw" => "__builtin_HEXAGON_A2_vabsw", - "llvm.hexagon.A2.vabswsat" => "__builtin_HEXAGON_A2_vabswsat", - "llvm.hexagon.A2.vaddb.map" => "__builtin_HEXAGON_A2_vaddb_map", - "llvm.hexagon.A2.vaddh" => "__builtin_HEXAGON_A2_vaddh", - "llvm.hexagon.A2.vaddhs" => "__builtin_HEXAGON_A2_vaddhs", - "llvm.hexagon.A2.vaddub" => "__builtin_HEXAGON_A2_vaddub", - "llvm.hexagon.A2.vaddubs" => "__builtin_HEXAGON_A2_vaddubs", - "llvm.hexagon.A2.vadduhs" => "__builtin_HEXAGON_A2_vadduhs", - "llvm.hexagon.A2.vaddw" => "__builtin_HEXAGON_A2_vaddw", - "llvm.hexagon.A2.vaddws" => "__builtin_HEXAGON_A2_vaddws", - "llvm.hexagon.A2.vavgh" => "__builtin_HEXAGON_A2_vavgh", - "llvm.hexagon.A2.vavghcr" => "__builtin_HEXAGON_A2_vavghcr", - "llvm.hexagon.A2.vavghr" => "__builtin_HEXAGON_A2_vavghr", - "llvm.hexagon.A2.vavgub" => "__builtin_HEXAGON_A2_vavgub", - "llvm.hexagon.A2.vavgubr" => "__builtin_HEXAGON_A2_vavgubr", - "llvm.hexagon.A2.vavguh" => "__builtin_HEXAGON_A2_vavguh", - "llvm.hexagon.A2.vavguhr" => "__builtin_HEXAGON_A2_vavguhr", - "llvm.hexagon.A2.vavguw" => "__builtin_HEXAGON_A2_vavguw", - "llvm.hexagon.A2.vavguwr" => "__builtin_HEXAGON_A2_vavguwr", - "llvm.hexagon.A2.vavgw" => "__builtin_HEXAGON_A2_vavgw", - "llvm.hexagon.A2.vavgwcr" => "__builtin_HEXAGON_A2_vavgwcr", - "llvm.hexagon.A2.vavgwr" => "__builtin_HEXAGON_A2_vavgwr", - "llvm.hexagon.A2.vcmpbeq" => "__builtin_HEXAGON_A2_vcmpbeq", - "llvm.hexagon.A2.vcmpbgtu" => "__builtin_HEXAGON_A2_vcmpbgtu", - "llvm.hexagon.A2.vcmpheq" => "__builtin_HEXAGON_A2_vcmpheq", - "llvm.hexagon.A2.vcmphgt" => "__builtin_HEXAGON_A2_vcmphgt", - "llvm.hexagon.A2.vcmphgtu" => "__builtin_HEXAGON_A2_vcmphgtu", - "llvm.hexagon.A2.vcmpweq" => "__builtin_HEXAGON_A2_vcmpweq", - "llvm.hexagon.A2.vcmpwgt" => "__builtin_HEXAGON_A2_vcmpwgt", - "llvm.hexagon.A2.vcmpwgtu" => "__builtin_HEXAGON_A2_vcmpwgtu", - "llvm.hexagon.A2.vconj" => "__builtin_HEXAGON_A2_vconj", - "llvm.hexagon.A2.vmaxb" => "__builtin_HEXAGON_A2_vmaxb", - "llvm.hexagon.A2.vmaxh" => "__builtin_HEXAGON_A2_vmaxh", - "llvm.hexagon.A2.vmaxub" => "__builtin_HEXAGON_A2_vmaxub", - "llvm.hexagon.A2.vmaxuh" => "__builtin_HEXAGON_A2_vmaxuh", - "llvm.hexagon.A2.vmaxuw" => "__builtin_HEXAGON_A2_vmaxuw", - "llvm.hexagon.A2.vmaxw" => "__builtin_HEXAGON_A2_vmaxw", - "llvm.hexagon.A2.vminb" => "__builtin_HEXAGON_A2_vminb", - "llvm.hexagon.A2.vminh" => "__builtin_HEXAGON_A2_vminh", - "llvm.hexagon.A2.vminub" => "__builtin_HEXAGON_A2_vminub", - "llvm.hexagon.A2.vminuh" => "__builtin_HEXAGON_A2_vminuh", - "llvm.hexagon.A2.vminuw" => "__builtin_HEXAGON_A2_vminuw", - "llvm.hexagon.A2.vminw" => "__builtin_HEXAGON_A2_vminw", - "llvm.hexagon.A2.vnavgh" => "__builtin_HEXAGON_A2_vnavgh", - "llvm.hexagon.A2.vnavghcr" => "__builtin_HEXAGON_A2_vnavghcr", - "llvm.hexagon.A2.vnavghr" => "__builtin_HEXAGON_A2_vnavghr", - "llvm.hexagon.A2.vnavgw" => "__builtin_HEXAGON_A2_vnavgw", - "llvm.hexagon.A2.vnavgwcr" => "__builtin_HEXAGON_A2_vnavgwcr", - "llvm.hexagon.A2.vnavgwr" => "__builtin_HEXAGON_A2_vnavgwr", - "llvm.hexagon.A2.vraddub" => "__builtin_HEXAGON_A2_vraddub", - "llvm.hexagon.A2.vraddub.acc" => "__builtin_HEXAGON_A2_vraddub_acc", - "llvm.hexagon.A2.vrsadub" => "__builtin_HEXAGON_A2_vrsadub", - "llvm.hexagon.A2.vrsadub.acc" => "__builtin_HEXAGON_A2_vrsadub_acc", - "llvm.hexagon.A2.vsubb.map" => "__builtin_HEXAGON_A2_vsubb_map", - "llvm.hexagon.A2.vsubh" => "__builtin_HEXAGON_A2_vsubh", - "llvm.hexagon.A2.vsubhs" => "__builtin_HEXAGON_A2_vsubhs", - "llvm.hexagon.A2.vsubub" => "__builtin_HEXAGON_A2_vsubub", - "llvm.hexagon.A2.vsububs" => "__builtin_HEXAGON_A2_vsububs", - "llvm.hexagon.A2.vsubuhs" => "__builtin_HEXAGON_A2_vsubuhs", - "llvm.hexagon.A2.vsubw" => "__builtin_HEXAGON_A2_vsubw", - "llvm.hexagon.A2.vsubws" => "__builtin_HEXAGON_A2_vsubws", - "llvm.hexagon.A2.xor" => "__builtin_HEXAGON_A2_xor", - "llvm.hexagon.A2.xorp" => "__builtin_HEXAGON_A2_xorp", - "llvm.hexagon.A2.zxtb" => "__builtin_HEXAGON_A2_zxtb", - "llvm.hexagon.A2.zxth" => "__builtin_HEXAGON_A2_zxth", - "llvm.hexagon.A4.andn" => "__builtin_HEXAGON_A4_andn", - "llvm.hexagon.A4.andnp" => "__builtin_HEXAGON_A4_andnp", - "llvm.hexagon.A4.bitsplit" => "__builtin_HEXAGON_A4_bitsplit", - "llvm.hexagon.A4.bitspliti" => "__builtin_HEXAGON_A4_bitspliti", - "llvm.hexagon.A4.boundscheck" => "__builtin_HEXAGON_A4_boundscheck", - "llvm.hexagon.A4.cmpbeq" => "__builtin_HEXAGON_A4_cmpbeq", - "llvm.hexagon.A4.cmpbeqi" => "__builtin_HEXAGON_A4_cmpbeqi", - "llvm.hexagon.A4.cmpbgt" => "__builtin_HEXAGON_A4_cmpbgt", - "llvm.hexagon.A4.cmpbgti" => "__builtin_HEXAGON_A4_cmpbgti", - "llvm.hexagon.A4.cmpbgtu" => "__builtin_HEXAGON_A4_cmpbgtu", - "llvm.hexagon.A4.cmpbgtui" => "__builtin_HEXAGON_A4_cmpbgtui", - "llvm.hexagon.A4.cmpheq" => "__builtin_HEXAGON_A4_cmpheq", - "llvm.hexagon.A4.cmpheqi" => "__builtin_HEXAGON_A4_cmpheqi", - "llvm.hexagon.A4.cmphgt" => "__builtin_HEXAGON_A4_cmphgt", - "llvm.hexagon.A4.cmphgti" => "__builtin_HEXAGON_A4_cmphgti", - "llvm.hexagon.A4.cmphgtu" => "__builtin_HEXAGON_A4_cmphgtu", - "llvm.hexagon.A4.cmphgtui" => "__builtin_HEXAGON_A4_cmphgtui", - "llvm.hexagon.A4.combineir" => "__builtin_HEXAGON_A4_combineir", - "llvm.hexagon.A4.combineri" => "__builtin_HEXAGON_A4_combineri", - "llvm.hexagon.A4.cround.ri" => "__builtin_HEXAGON_A4_cround_ri", - "llvm.hexagon.A4.cround.rr" => "__builtin_HEXAGON_A4_cround_rr", - "llvm.hexagon.A4.modwrapu" => "__builtin_HEXAGON_A4_modwrapu", - "llvm.hexagon.A4.orn" => "__builtin_HEXAGON_A4_orn", - "llvm.hexagon.A4.ornp" => "__builtin_HEXAGON_A4_ornp", - "llvm.hexagon.A4.rcmpeq" => "__builtin_HEXAGON_A4_rcmpeq", - "llvm.hexagon.A4.rcmpeqi" => "__builtin_HEXAGON_A4_rcmpeqi", - "llvm.hexagon.A4.rcmpneq" => "__builtin_HEXAGON_A4_rcmpneq", - "llvm.hexagon.A4.rcmpneqi" => "__builtin_HEXAGON_A4_rcmpneqi", - "llvm.hexagon.A4.round.ri" => "__builtin_HEXAGON_A4_round_ri", - "llvm.hexagon.A4.round.ri.sat" => "__builtin_HEXAGON_A4_round_ri_sat", - "llvm.hexagon.A4.round.rr" => "__builtin_HEXAGON_A4_round_rr", - "llvm.hexagon.A4.round.rr.sat" => "__builtin_HEXAGON_A4_round_rr_sat", - "llvm.hexagon.A4.tlbmatch" => "__builtin_HEXAGON_A4_tlbmatch", - "llvm.hexagon.A4.vcmpbeq.any" => "__builtin_HEXAGON_A4_vcmpbeq_any", - "llvm.hexagon.A4.vcmpbeqi" => "__builtin_HEXAGON_A4_vcmpbeqi", - "llvm.hexagon.A4.vcmpbgt" => "__builtin_HEXAGON_A4_vcmpbgt", - "llvm.hexagon.A4.vcmpbgti" => "__builtin_HEXAGON_A4_vcmpbgti", - "llvm.hexagon.A4.vcmpbgtui" => "__builtin_HEXAGON_A4_vcmpbgtui", - "llvm.hexagon.A4.vcmpheqi" => "__builtin_HEXAGON_A4_vcmpheqi", - "llvm.hexagon.A4.vcmphgti" => "__builtin_HEXAGON_A4_vcmphgti", - "llvm.hexagon.A4.vcmphgtui" => "__builtin_HEXAGON_A4_vcmphgtui", - "llvm.hexagon.A4.vcmpweqi" => "__builtin_HEXAGON_A4_vcmpweqi", - "llvm.hexagon.A4.vcmpwgti" => "__builtin_HEXAGON_A4_vcmpwgti", - "llvm.hexagon.A4.vcmpwgtui" => "__builtin_HEXAGON_A4_vcmpwgtui", - "llvm.hexagon.A4.vrmaxh" => "__builtin_HEXAGON_A4_vrmaxh", - "llvm.hexagon.A4.vrmaxuh" => "__builtin_HEXAGON_A4_vrmaxuh", - "llvm.hexagon.A4.vrmaxuw" => "__builtin_HEXAGON_A4_vrmaxuw", - "llvm.hexagon.A4.vrmaxw" => "__builtin_HEXAGON_A4_vrmaxw", - "llvm.hexagon.A4.vrminh" => "__builtin_HEXAGON_A4_vrminh", - "llvm.hexagon.A4.vrminuh" => "__builtin_HEXAGON_A4_vrminuh", - "llvm.hexagon.A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw", - "llvm.hexagon.A4.vrminw" => "__builtin_HEXAGON_A4_vrminw", - "llvm.hexagon.A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs", - "llvm.hexagon.A6.vcmpbeq.notany" => "__builtin_HEXAGON_A6_vcmpbeq_notany", - "llvm.hexagon.A7.clip" => "__builtin_HEXAGON_A7_clip", - "llvm.hexagon.A7.croundd.ri" => "__builtin_HEXAGON_A7_croundd_ri", - "llvm.hexagon.A7.croundd.rr" => "__builtin_HEXAGON_A7_croundd_rr", - "llvm.hexagon.A7.vclip" => "__builtin_HEXAGON_A7_vclip", - "llvm.hexagon.C2.all8" => "__builtin_HEXAGON_C2_all8", - "llvm.hexagon.C2.and" => "__builtin_HEXAGON_C2_and", - "llvm.hexagon.C2.andn" => "__builtin_HEXAGON_C2_andn", - "llvm.hexagon.C2.any8" => "__builtin_HEXAGON_C2_any8", - "llvm.hexagon.C2.bitsclr" => "__builtin_HEXAGON_C2_bitsclr", - "llvm.hexagon.C2.bitsclri" => "__builtin_HEXAGON_C2_bitsclri", - "llvm.hexagon.C2.bitsset" => "__builtin_HEXAGON_C2_bitsset", - "llvm.hexagon.C2.cmpeq" => "__builtin_HEXAGON_C2_cmpeq", - "llvm.hexagon.C2.cmpeqi" => "__builtin_HEXAGON_C2_cmpeqi", - "llvm.hexagon.C2.cmpeqp" => "__builtin_HEXAGON_C2_cmpeqp", - "llvm.hexagon.C2.cmpgei" => "__builtin_HEXAGON_C2_cmpgei", - "llvm.hexagon.C2.cmpgeui" => "__builtin_HEXAGON_C2_cmpgeui", - "llvm.hexagon.C2.cmpgt" => "__builtin_HEXAGON_C2_cmpgt", - "llvm.hexagon.C2.cmpgti" => "__builtin_HEXAGON_C2_cmpgti", - "llvm.hexagon.C2.cmpgtp" => "__builtin_HEXAGON_C2_cmpgtp", - "llvm.hexagon.C2.cmpgtu" => "__builtin_HEXAGON_C2_cmpgtu", - "llvm.hexagon.C2.cmpgtui" => "__builtin_HEXAGON_C2_cmpgtui", - "llvm.hexagon.C2.cmpgtup" => "__builtin_HEXAGON_C2_cmpgtup", - "llvm.hexagon.C2.cmplt" => "__builtin_HEXAGON_C2_cmplt", - "llvm.hexagon.C2.cmpltu" => "__builtin_HEXAGON_C2_cmpltu", - "llvm.hexagon.C2.mask" => "__builtin_HEXAGON_C2_mask", - "llvm.hexagon.C2.mux" => "__builtin_HEXAGON_C2_mux", - "llvm.hexagon.C2.muxii" => "__builtin_HEXAGON_C2_muxii", - "llvm.hexagon.C2.muxir" => "__builtin_HEXAGON_C2_muxir", - "llvm.hexagon.C2.muxri" => "__builtin_HEXAGON_C2_muxri", - "llvm.hexagon.C2.not" => "__builtin_HEXAGON_C2_not", - "llvm.hexagon.C2.or" => "__builtin_HEXAGON_C2_or", - "llvm.hexagon.C2.orn" => "__builtin_HEXAGON_C2_orn", - "llvm.hexagon.C2.pxfer.map" => "__builtin_HEXAGON_C2_pxfer_map", - "llvm.hexagon.C2.tfrpr" => "__builtin_HEXAGON_C2_tfrpr", - "llvm.hexagon.C2.tfrrp" => "__builtin_HEXAGON_C2_tfrrp", - "llvm.hexagon.C2.vitpack" => "__builtin_HEXAGON_C2_vitpack", - "llvm.hexagon.C2.vmux" => "__builtin_HEXAGON_C2_vmux", - "llvm.hexagon.C2.xor" => "__builtin_HEXAGON_C2_xor", - "llvm.hexagon.C4.and.and" => "__builtin_HEXAGON_C4_and_and", - "llvm.hexagon.C4.and.andn" => "__builtin_HEXAGON_C4_and_andn", - "llvm.hexagon.C4.and.or" => "__builtin_HEXAGON_C4_and_or", - "llvm.hexagon.C4.and.orn" => "__builtin_HEXAGON_C4_and_orn", - "llvm.hexagon.C4.cmplte" => "__builtin_HEXAGON_C4_cmplte", - "llvm.hexagon.C4.cmpltei" => "__builtin_HEXAGON_C4_cmpltei", - "llvm.hexagon.C4.cmplteu" => "__builtin_HEXAGON_C4_cmplteu", - "llvm.hexagon.C4.cmplteui" => "__builtin_HEXAGON_C4_cmplteui", - "llvm.hexagon.C4.cmpneq" => "__builtin_HEXAGON_C4_cmpneq", - "llvm.hexagon.C4.cmpneqi" => "__builtin_HEXAGON_C4_cmpneqi", - "llvm.hexagon.C4.fastcorner9" => "__builtin_HEXAGON_C4_fastcorner9", - "llvm.hexagon.C4.fastcorner9.not" => "__builtin_HEXAGON_C4_fastcorner9_not", - "llvm.hexagon.C4.nbitsclr" => "__builtin_HEXAGON_C4_nbitsclr", - "llvm.hexagon.C4.nbitsclri" => "__builtin_HEXAGON_C4_nbitsclri", - "llvm.hexagon.C4.nbitsset" => "__builtin_HEXAGON_C4_nbitsset", - "llvm.hexagon.C4.or.and" => "__builtin_HEXAGON_C4_or_and", - "llvm.hexagon.C4.or.andn" => "__builtin_HEXAGON_C4_or_andn", - "llvm.hexagon.C4.or.or" => "__builtin_HEXAGON_C4_or_or", - "llvm.hexagon.C4.or.orn" => "__builtin_HEXAGON_C4_or_orn", - "llvm.hexagon.F2.conv.d2df" => "__builtin_HEXAGON_F2_conv_d2df", - "llvm.hexagon.F2.conv.d2sf" => "__builtin_HEXAGON_F2_conv_d2sf", - "llvm.hexagon.F2.conv.df2d" => "__builtin_HEXAGON_F2_conv_df2d", - "llvm.hexagon.F2.conv.df2d.chop" => "__builtin_HEXAGON_F2_conv_df2d_chop", - "llvm.hexagon.F2.conv.df2sf" => "__builtin_HEXAGON_F2_conv_df2sf", - "llvm.hexagon.F2.conv.df2ud" => "__builtin_HEXAGON_F2_conv_df2ud", - "llvm.hexagon.F2.conv.df2ud.chop" => "__builtin_HEXAGON_F2_conv_df2ud_chop", - "llvm.hexagon.F2.conv.df2uw" => "__builtin_HEXAGON_F2_conv_df2uw", - "llvm.hexagon.F2.conv.df2uw.chop" => "__builtin_HEXAGON_F2_conv_df2uw_chop", - "llvm.hexagon.F2.conv.df2w" => "__builtin_HEXAGON_F2_conv_df2w", - "llvm.hexagon.F2.conv.df2w.chop" => "__builtin_HEXAGON_F2_conv_df2w_chop", - "llvm.hexagon.F2.conv.sf2d" => "__builtin_HEXAGON_F2_conv_sf2d", - "llvm.hexagon.F2.conv.sf2d.chop" => "__builtin_HEXAGON_F2_conv_sf2d_chop", - "llvm.hexagon.F2.conv.sf2df" => "__builtin_HEXAGON_F2_conv_sf2df", - "llvm.hexagon.F2.conv.sf2ud" => "__builtin_HEXAGON_F2_conv_sf2ud", - "llvm.hexagon.F2.conv.sf2ud.chop" => "__builtin_HEXAGON_F2_conv_sf2ud_chop", - "llvm.hexagon.F2.conv.sf2uw" => "__builtin_HEXAGON_F2_conv_sf2uw", - "llvm.hexagon.F2.conv.sf2uw.chop" => "__builtin_HEXAGON_F2_conv_sf2uw_chop", - "llvm.hexagon.F2.conv.sf2w" => "__builtin_HEXAGON_F2_conv_sf2w", - "llvm.hexagon.F2.conv.sf2w.chop" => "__builtin_HEXAGON_F2_conv_sf2w_chop", - "llvm.hexagon.F2.conv.ud2df" => "__builtin_HEXAGON_F2_conv_ud2df", - "llvm.hexagon.F2.conv.ud2sf" => "__builtin_HEXAGON_F2_conv_ud2sf", - "llvm.hexagon.F2.conv.uw2df" => "__builtin_HEXAGON_F2_conv_uw2df", - "llvm.hexagon.F2.conv.uw2sf" => "__builtin_HEXAGON_F2_conv_uw2sf", - "llvm.hexagon.F2.conv.w2df" => "__builtin_HEXAGON_F2_conv_w2df", - "llvm.hexagon.F2.conv.w2sf" => "__builtin_HEXAGON_F2_conv_w2sf", - "llvm.hexagon.F2.dfadd" => "__builtin_HEXAGON_F2_dfadd", - "llvm.hexagon.F2.dfclass" => "__builtin_HEXAGON_F2_dfclass", - "llvm.hexagon.F2.dfcmpeq" => "__builtin_HEXAGON_F2_dfcmpeq", - "llvm.hexagon.F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge", - "llvm.hexagon.F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt", - "llvm.hexagon.F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo", - "llvm.hexagon.F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd", - "llvm.hexagon.F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn", - "llvm.hexagon.F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr", - "llvm.hexagon.F2.dffma" => "__builtin_HEXAGON_F2_dffma", - "llvm.hexagon.F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib", - "llvm.hexagon.F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc", - "llvm.hexagon.F2.dffms" => "__builtin_HEXAGON_F2_dffms", - "llvm.hexagon.F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib", - "llvm.hexagon.F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n", - "llvm.hexagon.F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p", - "llvm.hexagon.F2.dfmax" => "__builtin_HEXAGON_F2_dfmax", - "llvm.hexagon.F2.dfmin" => "__builtin_HEXAGON_F2_dfmin", - "llvm.hexagon.F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy", - "llvm.hexagon.F2.dfmpyfix" => "__builtin_HEXAGON_F2_dfmpyfix", - "llvm.hexagon.F2.dfmpyhh" => "__builtin_HEXAGON_F2_dfmpyhh", - "llvm.hexagon.F2.dfmpylh" => "__builtin_HEXAGON_F2_dfmpylh", - "llvm.hexagon.F2.dfmpyll" => "__builtin_HEXAGON_F2_dfmpyll", - "llvm.hexagon.F2.dfsub" => "__builtin_HEXAGON_F2_dfsub", - "llvm.hexagon.F2.sfadd" => "__builtin_HEXAGON_F2_sfadd", - "llvm.hexagon.F2.sfclass" => "__builtin_HEXAGON_F2_sfclass", - "llvm.hexagon.F2.sfcmpeq" => "__builtin_HEXAGON_F2_sfcmpeq", - "llvm.hexagon.F2.sfcmpge" => "__builtin_HEXAGON_F2_sfcmpge", - "llvm.hexagon.F2.sfcmpgt" => "__builtin_HEXAGON_F2_sfcmpgt", - "llvm.hexagon.F2.sfcmpuo" => "__builtin_HEXAGON_F2_sfcmpuo", - "llvm.hexagon.F2.sffixupd" => "__builtin_HEXAGON_F2_sffixupd", - "llvm.hexagon.F2.sffixupn" => "__builtin_HEXAGON_F2_sffixupn", - "llvm.hexagon.F2.sffixupr" => "__builtin_HEXAGON_F2_sffixupr", - "llvm.hexagon.F2.sffma" => "__builtin_HEXAGON_F2_sffma", - "llvm.hexagon.F2.sffma.lib" => "__builtin_HEXAGON_F2_sffma_lib", - "llvm.hexagon.F2.sffma.sc" => "__builtin_HEXAGON_F2_sffma_sc", - "llvm.hexagon.F2.sffms" => "__builtin_HEXAGON_F2_sffms", - "llvm.hexagon.F2.sffms.lib" => "__builtin_HEXAGON_F2_sffms_lib", - "llvm.hexagon.F2.sfimm.n" => "__builtin_HEXAGON_F2_sfimm_n", - "llvm.hexagon.F2.sfimm.p" => "__builtin_HEXAGON_F2_sfimm_p", - "llvm.hexagon.F2.sfmax" => "__builtin_HEXAGON_F2_sfmax", - "llvm.hexagon.F2.sfmin" => "__builtin_HEXAGON_F2_sfmin", - "llvm.hexagon.F2.sfmpy" => "__builtin_HEXAGON_F2_sfmpy", - "llvm.hexagon.F2.sfsub" => "__builtin_HEXAGON_F2_sfsub", - "llvm.hexagon.L2.loadw.locked" => "__builtin_HEXAGON_L2_loadw_locked", - "llvm.hexagon.L4.loadd.locked" => "__builtin__HEXAGON_L4_loadd_locked", - "llvm.hexagon.M2.acci" => "__builtin_HEXAGON_M2_acci", - "llvm.hexagon.M2.accii" => "__builtin_HEXAGON_M2_accii", - "llvm.hexagon.M2.cmaci.s0" => "__builtin_HEXAGON_M2_cmaci_s0", - "llvm.hexagon.M2.cmacr.s0" => "__builtin_HEXAGON_M2_cmacr_s0", - "llvm.hexagon.M2.cmacs.s0" => "__builtin_HEXAGON_M2_cmacs_s0", - "llvm.hexagon.M2.cmacs.s1" => "__builtin_HEXAGON_M2_cmacs_s1", - "llvm.hexagon.M2.cmacsc.s0" => "__builtin_HEXAGON_M2_cmacsc_s0", - "llvm.hexagon.M2.cmacsc.s1" => "__builtin_HEXAGON_M2_cmacsc_s1", - "llvm.hexagon.M2.cmpyi.s0" => "__builtin_HEXAGON_M2_cmpyi_s0", - "llvm.hexagon.M2.cmpyr.s0" => "__builtin_HEXAGON_M2_cmpyr_s0", - "llvm.hexagon.M2.cmpyrs.s0" => "__builtin_HEXAGON_M2_cmpyrs_s0", - "llvm.hexagon.M2.cmpyrs.s1" => "__builtin_HEXAGON_M2_cmpyrs_s1", - "llvm.hexagon.M2.cmpyrsc.s0" => "__builtin_HEXAGON_M2_cmpyrsc_s0", - "llvm.hexagon.M2.cmpyrsc.s1" => "__builtin_HEXAGON_M2_cmpyrsc_s1", - "llvm.hexagon.M2.cmpys.s0" => "__builtin_HEXAGON_M2_cmpys_s0", - "llvm.hexagon.M2.cmpys.s1" => "__builtin_HEXAGON_M2_cmpys_s1", - "llvm.hexagon.M2.cmpysc.s0" => "__builtin_HEXAGON_M2_cmpysc_s0", - "llvm.hexagon.M2.cmpysc.s1" => "__builtin_HEXAGON_M2_cmpysc_s1", - "llvm.hexagon.M2.cnacs.s0" => "__builtin_HEXAGON_M2_cnacs_s0", - "llvm.hexagon.M2.cnacs.s1" => "__builtin_HEXAGON_M2_cnacs_s1", - "llvm.hexagon.M2.cnacsc.s0" => "__builtin_HEXAGON_M2_cnacsc_s0", - "llvm.hexagon.M2.cnacsc.s1" => "__builtin_HEXAGON_M2_cnacsc_s1", - "llvm.hexagon.M2.dpmpyss.acc.s0" => "__builtin_HEXAGON_M2_dpmpyss_acc_s0", - "llvm.hexagon.M2.dpmpyss.nac.s0" => "__builtin_HEXAGON_M2_dpmpyss_nac_s0", - "llvm.hexagon.M2.dpmpyss.rnd.s0" => "__builtin_HEXAGON_M2_dpmpyss_rnd_s0", - "llvm.hexagon.M2.dpmpyss.s0" => "__builtin_HEXAGON_M2_dpmpyss_s0", - "llvm.hexagon.M2.dpmpyuu.acc.s0" => "__builtin_HEXAGON_M2_dpmpyuu_acc_s0", - "llvm.hexagon.M2.dpmpyuu.nac.s0" => "__builtin_HEXAGON_M2_dpmpyuu_nac_s0", - "llvm.hexagon.M2.dpmpyuu.s0" => "__builtin_HEXAGON_M2_dpmpyuu_s0", - "llvm.hexagon.M2.hmmpyh.rs1" => "__builtin_HEXAGON_M2_hmmpyh_rs1", - "llvm.hexagon.M2.hmmpyh.s1" => "__builtin_HEXAGON_M2_hmmpyh_s1", - "llvm.hexagon.M2.hmmpyl.rs1" => "__builtin_HEXAGON_M2_hmmpyl_rs1", - "llvm.hexagon.M2.hmmpyl.s1" => "__builtin_HEXAGON_M2_hmmpyl_s1", - "llvm.hexagon.M2.maci" => "__builtin_HEXAGON_M2_maci", - "llvm.hexagon.M2.macsin" => "__builtin_HEXAGON_M2_macsin", - "llvm.hexagon.M2.macsip" => "__builtin_HEXAGON_M2_macsip", - "llvm.hexagon.M2.mmachs.rs0" => "__builtin_HEXAGON_M2_mmachs_rs0", - "llvm.hexagon.M2.mmachs.rs1" => "__builtin_HEXAGON_M2_mmachs_rs1", - "llvm.hexagon.M2.mmachs.s0" => "__builtin_HEXAGON_M2_mmachs_s0", - "llvm.hexagon.M2.mmachs.s1" => "__builtin_HEXAGON_M2_mmachs_s1", - "llvm.hexagon.M2.mmacls.rs0" => "__builtin_HEXAGON_M2_mmacls_rs0", - "llvm.hexagon.M2.mmacls.rs1" => "__builtin_HEXAGON_M2_mmacls_rs1", - "llvm.hexagon.M2.mmacls.s0" => "__builtin_HEXAGON_M2_mmacls_s0", - "llvm.hexagon.M2.mmacls.s1" => "__builtin_HEXAGON_M2_mmacls_s1", - "llvm.hexagon.M2.mmacuhs.rs0" => "__builtin_HEXAGON_M2_mmacuhs_rs0", - "llvm.hexagon.M2.mmacuhs.rs1" => "__builtin_HEXAGON_M2_mmacuhs_rs1", - "llvm.hexagon.M2.mmacuhs.s0" => "__builtin_HEXAGON_M2_mmacuhs_s0", - "llvm.hexagon.M2.mmacuhs.s1" => "__builtin_HEXAGON_M2_mmacuhs_s1", - "llvm.hexagon.M2.mmaculs.rs0" => "__builtin_HEXAGON_M2_mmaculs_rs0", - "llvm.hexagon.M2.mmaculs.rs1" => "__builtin_HEXAGON_M2_mmaculs_rs1", - "llvm.hexagon.M2.mmaculs.s0" => "__builtin_HEXAGON_M2_mmaculs_s0", - "llvm.hexagon.M2.mmaculs.s1" => "__builtin_HEXAGON_M2_mmaculs_s1", - "llvm.hexagon.M2.mmpyh.rs0" => "__builtin_HEXAGON_M2_mmpyh_rs0", - "llvm.hexagon.M2.mmpyh.rs1" => "__builtin_HEXAGON_M2_mmpyh_rs1", - "llvm.hexagon.M2.mmpyh.s0" => "__builtin_HEXAGON_M2_mmpyh_s0", - "llvm.hexagon.M2.mmpyh.s1" => "__builtin_HEXAGON_M2_mmpyh_s1", - "llvm.hexagon.M2.mmpyl.rs0" => "__builtin_HEXAGON_M2_mmpyl_rs0", - "llvm.hexagon.M2.mmpyl.rs1" => "__builtin_HEXAGON_M2_mmpyl_rs1", - "llvm.hexagon.M2.mmpyl.s0" => "__builtin_HEXAGON_M2_mmpyl_s0", - "llvm.hexagon.M2.mmpyl.s1" => "__builtin_HEXAGON_M2_mmpyl_s1", - "llvm.hexagon.M2.mmpyuh.rs0" => "__builtin_HEXAGON_M2_mmpyuh_rs0", - "llvm.hexagon.M2.mmpyuh.rs1" => "__builtin_HEXAGON_M2_mmpyuh_rs1", - "llvm.hexagon.M2.mmpyuh.s0" => "__builtin_HEXAGON_M2_mmpyuh_s0", - "llvm.hexagon.M2.mmpyuh.s1" => "__builtin_HEXAGON_M2_mmpyuh_s1", - "llvm.hexagon.M2.mmpyul.rs0" => "__builtin_HEXAGON_M2_mmpyul_rs0", - "llvm.hexagon.M2.mmpyul.rs1" => "__builtin_HEXAGON_M2_mmpyul_rs1", - "llvm.hexagon.M2.mmpyul.s0" => "__builtin_HEXAGON_M2_mmpyul_s0", - "llvm.hexagon.M2.mmpyul.s1" => "__builtin_HEXAGON_M2_mmpyul_s1", - "llvm.hexagon.M2.mnaci" => "__builtin_HEXAGON_M2_mnaci", - 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"__builtin_HEXAGON_M2_vraddh", - "llvm.hexagon.M2.vradduh" => "__builtin_HEXAGON_M2_vradduh", - "llvm.hexagon.M2.vrcmaci.s0" => "__builtin_HEXAGON_M2_vrcmaci_s0", - "llvm.hexagon.M2.vrcmaci.s0c" => "__builtin_HEXAGON_M2_vrcmaci_s0c", - "llvm.hexagon.M2.vrcmacr.s0" => "__builtin_HEXAGON_M2_vrcmacr_s0", - "llvm.hexagon.M2.vrcmacr.s0c" => "__builtin_HEXAGON_M2_vrcmacr_s0c", - "llvm.hexagon.M2.vrcmpyi.s0" => "__builtin_HEXAGON_M2_vrcmpyi_s0", - "llvm.hexagon.M2.vrcmpyi.s0c" => "__builtin_HEXAGON_M2_vrcmpyi_s0c", - "llvm.hexagon.M2.vrcmpyr.s0" => "__builtin_HEXAGON_M2_vrcmpyr_s0", - "llvm.hexagon.M2.vrcmpyr.s0c" => "__builtin_HEXAGON_M2_vrcmpyr_s0c", - "llvm.hexagon.M2.vrcmpys.acc.s1" => "__builtin_HEXAGON_M2_vrcmpys_acc_s1", - "llvm.hexagon.M2.vrcmpys.s1" => "__builtin_HEXAGON_M2_vrcmpys_s1", - "llvm.hexagon.M2.vrcmpys.s1rp" => "__builtin_HEXAGON_M2_vrcmpys_s1rp", - "llvm.hexagon.M2.vrmac.s0" => "__builtin_HEXAGON_M2_vrmac_s0", - "llvm.hexagon.M2.vrmpy.s0" => "__builtin_HEXAGON_M2_vrmpy_s0", - "llvm.hexagon.M2.xor.xacc" => "__builtin_HEXAGON_M2_xor_xacc", - "llvm.hexagon.M4.and.and" => "__builtin_HEXAGON_M4_and_and", - "llvm.hexagon.M4.and.andn" => "__builtin_HEXAGON_M4_and_andn", - "llvm.hexagon.M4.and.or" => "__builtin_HEXAGON_M4_and_or", - "llvm.hexagon.M4.and.xor" => "__builtin_HEXAGON_M4_and_xor", - "llvm.hexagon.M4.cmpyi.wh" => "__builtin_HEXAGON_M4_cmpyi_wh", - "llvm.hexagon.M4.cmpyi.whc" => "__builtin_HEXAGON_M4_cmpyi_whc", - "llvm.hexagon.M4.cmpyr.wh" => "__builtin_HEXAGON_M4_cmpyr_wh", - "llvm.hexagon.M4.cmpyr.whc" => "__builtin_HEXAGON_M4_cmpyr_whc", - "llvm.hexagon.M4.mac.up.s1.sat" => "__builtin_HEXAGON_M4_mac_up_s1_sat", - "llvm.hexagon.M4.mpyri.addi" => "__builtin_HEXAGON_M4_mpyri_addi", - "llvm.hexagon.M4.mpyri.addr" => "__builtin_HEXAGON_M4_mpyri_addr", - "llvm.hexagon.M4.mpyri.addr.u2" => "__builtin_HEXAGON_M4_mpyri_addr_u2", - "llvm.hexagon.M4.mpyrr.addi" => "__builtin_HEXAGON_M4_mpyrr_addi", - "llvm.hexagon.M4.mpyrr.addr" => "__builtin_HEXAGON_M4_mpyrr_addr", - "llvm.hexagon.M4.nac.up.s1.sat" => "__builtin_HEXAGON_M4_nac_up_s1_sat", - "llvm.hexagon.M4.or.and" => "__builtin_HEXAGON_M4_or_and", - "llvm.hexagon.M4.or.andn" => "__builtin_HEXAGON_M4_or_andn", - "llvm.hexagon.M4.or.or" => "__builtin_HEXAGON_M4_or_or", - "llvm.hexagon.M4.or.xor" => "__builtin_HEXAGON_M4_or_xor", - "llvm.hexagon.M4.pmpyw" => "__builtin_HEXAGON_M4_pmpyw", - "llvm.hexagon.M4.pmpyw.acc" => "__builtin_HEXAGON_M4_pmpyw_acc", - "llvm.hexagon.M4.vpmpyh" => "__builtin_HEXAGON_M4_vpmpyh", - "llvm.hexagon.M4.vpmpyh.acc" => "__builtin_HEXAGON_M4_vpmpyh_acc", - "llvm.hexagon.M4.vrmpyeh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s0", - "llvm.hexagon.M4.vrmpyeh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s1", - "llvm.hexagon.M4.vrmpyeh.s0" => "__builtin_HEXAGON_M4_vrmpyeh_s0", - "llvm.hexagon.M4.vrmpyeh.s1" => "__builtin_HEXAGON_M4_vrmpyeh_s1", - "llvm.hexagon.M4.vrmpyoh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s0", - "llvm.hexagon.M4.vrmpyoh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s1", - "llvm.hexagon.M4.vrmpyoh.s0" => "__builtin_HEXAGON_M4_vrmpyoh_s0", - "llvm.hexagon.M4.vrmpyoh.s1" => "__builtin_HEXAGON_M4_vrmpyoh_s1", - "llvm.hexagon.M4.xor.and" => "__builtin_HEXAGON_M4_xor_and", - "llvm.hexagon.M4.xor.andn" => "__builtin_HEXAGON_M4_xor_andn", - "llvm.hexagon.M4.xor.or" => "__builtin_HEXAGON_M4_xor_or", - "llvm.hexagon.M4.xor.xacc" => "__builtin_HEXAGON_M4_xor_xacc", - "llvm.hexagon.M5.vdmacbsu" => "__builtin_HEXAGON_M5_vdmacbsu", - "llvm.hexagon.M5.vdmpybsu" => "__builtin_HEXAGON_M5_vdmpybsu", - "llvm.hexagon.M5.vmacbsu" => "__builtin_HEXAGON_M5_vmacbsu", - "llvm.hexagon.M5.vmacbuu" => "__builtin_HEXAGON_M5_vmacbuu", - "llvm.hexagon.M5.vmpybsu" => "__builtin_HEXAGON_M5_vmpybsu", - "llvm.hexagon.M5.vmpybuu" => "__builtin_HEXAGON_M5_vmpybuu", - "llvm.hexagon.M5.vrmacbsu" => "__builtin_HEXAGON_M5_vrmacbsu", - "llvm.hexagon.M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu", - "llvm.hexagon.M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu", - "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", - "llvm.hexagon.M6.vabsdiffb" => "__builtin_HEXAGON_M6_vabsdiffb", - "llvm.hexagon.M6.vabsdiffub" => "__builtin_HEXAGON_M6_vabsdiffub", - "llvm.hexagon.M7.dcmpyiw" => "__builtin_HEXAGON_M7_dcmpyiw", - "llvm.hexagon.M7.dcmpyiw.acc" => "__builtin_HEXAGON_M7_dcmpyiw_acc", - "llvm.hexagon.M7.dcmpyiwc" => "__builtin_HEXAGON_M7_dcmpyiwc", - "llvm.hexagon.M7.dcmpyiwc.acc" => "__builtin_HEXAGON_M7_dcmpyiwc_acc", - "llvm.hexagon.M7.dcmpyrw" => "__builtin_HEXAGON_M7_dcmpyrw", - "llvm.hexagon.M7.dcmpyrw.acc" => "__builtin_HEXAGON_M7_dcmpyrw_acc", - "llvm.hexagon.M7.dcmpyrwc" => "__builtin_HEXAGON_M7_dcmpyrwc", - "llvm.hexagon.M7.dcmpyrwc.acc" => "__builtin_HEXAGON_M7_dcmpyrwc_acc", - "llvm.hexagon.M7.vdmpy" => "__builtin_HEXAGON_M7_vdmpy", - "llvm.hexagon.M7.vdmpy.acc" => "__builtin_HEXAGON_M7_vdmpy_acc", - "llvm.hexagon.M7.wcmpyiw" => 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- "llvm.hexagon.S2.asl.r.p.xor" => "__builtin_HEXAGON_S2_asl_r_p_xor", - "llvm.hexagon.S2.asl.r.r" => "__builtin_HEXAGON_S2_asl_r_r", - "llvm.hexagon.S2.asl.r.r.acc" => "__builtin_HEXAGON_S2_asl_r_r_acc", - "llvm.hexagon.S2.asl.r.r.and" => "__builtin_HEXAGON_S2_asl_r_r_and", - "llvm.hexagon.S2.asl.r.r.nac" => "__builtin_HEXAGON_S2_asl_r_r_nac", - "llvm.hexagon.S2.asl.r.r.or" => "__builtin_HEXAGON_S2_asl_r_r_or", - "llvm.hexagon.S2.asl.r.r.sat" => "__builtin_HEXAGON_S2_asl_r_r_sat", - "llvm.hexagon.S2.asl.r.vh" => "__builtin_HEXAGON_S2_asl_r_vh", - "llvm.hexagon.S2.asl.r.vw" => "__builtin_HEXAGON_S2_asl_r_vw", - "llvm.hexagon.S2.asr.i.p" => "__builtin_HEXAGON_S2_asr_i_p", - "llvm.hexagon.S2.asr.i.p.acc" => "__builtin_HEXAGON_S2_asr_i_p_acc", - "llvm.hexagon.S2.asr.i.p.and" => "__builtin_HEXAGON_S2_asr_i_p_and", - "llvm.hexagon.S2.asr.i.p.nac" => "__builtin_HEXAGON_S2_asr_i_p_nac", - "llvm.hexagon.S2.asr.i.p.or" => "__builtin_HEXAGON_S2_asr_i_p_or", - "llvm.hexagon.S2.asr.i.p.rnd" => "__builtin_HEXAGON_S2_asr_i_p_rnd", - "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax", - "llvm.hexagon.S2.asr.i.r" => "__builtin_HEXAGON_S2_asr_i_r", - "llvm.hexagon.S2.asr.i.r.acc" => "__builtin_HEXAGON_S2_asr_i_r_acc", - "llvm.hexagon.S2.asr.i.r.and" => "__builtin_HEXAGON_S2_asr_i_r_and", - "llvm.hexagon.S2.asr.i.r.nac" => "__builtin_HEXAGON_S2_asr_i_r_nac", - "llvm.hexagon.S2.asr.i.r.or" => "__builtin_HEXAGON_S2_asr_i_r_or", - "llvm.hexagon.S2.asr.i.r.rnd" => "__builtin_HEXAGON_S2_asr_i_r_rnd", - "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax", - "llvm.hexagon.S2.asr.i.svw.trun" => "__builtin_HEXAGON_S2_asr_i_svw_trun", - "llvm.hexagon.S2.asr.i.vh" => "__builtin_HEXAGON_S2_asr_i_vh", - "llvm.hexagon.S2.asr.i.vw" => "__builtin_HEXAGON_S2_asr_i_vw", - "llvm.hexagon.S2.asr.r.p" => "__builtin_HEXAGON_S2_asr_r_p", - "llvm.hexagon.S2.asr.r.p.acc" => "__builtin_HEXAGON_S2_asr_r_p_acc", - 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=> "__builtin_HEXAGON_V6_vasrhbrndsat_128B", - "llvm.hexagon.V6.vasrhbsat" => "__builtin_HEXAGON_V6_vasrhbsat", - "llvm.hexagon.V6.vasrhbsat.128B" => "__builtin_HEXAGON_V6_vasrhbsat_128B", - "llvm.hexagon.V6.vasrhubrndsat" => "__builtin_HEXAGON_V6_vasrhubrndsat", - "llvm.hexagon.V6.vasrhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrhubrndsat_128B", - "llvm.hexagon.V6.vasrhubsat" => "__builtin_HEXAGON_V6_vasrhubsat", - "llvm.hexagon.V6.vasrhubsat.128B" => "__builtin_HEXAGON_V6_vasrhubsat_128B", - "llvm.hexagon.V6.vasrhv" => "__builtin_HEXAGON_V6_vasrhv", - "llvm.hexagon.V6.vasrhv.128B" => "__builtin_HEXAGON_V6_vasrhv_128B", - "llvm.hexagon.V6.vasruhubrndsat" => "__builtin_HEXAGON_V6_vasruhubrndsat", - "llvm.hexagon.V6.vasruhubrndsat.128B" => "__builtin_HEXAGON_V6_vasruhubrndsat_128B", - "llvm.hexagon.V6.vasruhubsat" => "__builtin_HEXAGON_V6_vasruhubsat", - "llvm.hexagon.V6.vasruhubsat.128B" => "__builtin_HEXAGON_V6_vasruhubsat_128B", - "llvm.hexagon.V6.vasruwuhrndsat" => "__builtin_HEXAGON_V6_vasruwuhrndsat", - "llvm.hexagon.V6.vasruwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasruwuhrndsat_128B", - "llvm.hexagon.V6.vasruwuhsat" => "__builtin_HEXAGON_V6_vasruwuhsat", - "llvm.hexagon.V6.vasruwuhsat.128B" => "__builtin_HEXAGON_V6_vasruwuhsat_128B", - "llvm.hexagon.V6.vasrvuhubrndsat" => "__builtin_HEXAGON_V6_vasrvuhubrndsat", - "llvm.hexagon.V6.vasrvuhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrvuhubrndsat_128B", - "llvm.hexagon.V6.vasrvuhubsat" => "__builtin_HEXAGON_V6_vasrvuhubsat", - "llvm.hexagon.V6.vasrvuhubsat.128B" => "__builtin_HEXAGON_V6_vasrvuhubsat_128B", - "llvm.hexagon.V6.vasrvwuhrndsat" => "__builtin_HEXAGON_V6_vasrvwuhrndsat", - "llvm.hexagon.V6.vasrvwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasrvwuhrndsat_128B", - "llvm.hexagon.V6.vasrvwuhsat" => "__builtin_HEXAGON_V6_vasrvwuhsat", - "llvm.hexagon.V6.vasrvwuhsat.128B" => "__builtin_HEXAGON_V6_vasrvwuhsat_128B", - "llvm.hexagon.V6.vasrw" => "__builtin_HEXAGON_V6_vasrw", - "llvm.hexagon.V6.vasrw.128B" => "__builtin_HEXAGON_V6_vasrw_128B", - "llvm.hexagon.V6.vasrw.acc" => "__builtin_HEXAGON_V6_vasrw_acc", - "llvm.hexagon.V6.vasrw.acc.128B" => "__builtin_HEXAGON_V6_vasrw_acc_128B", - "llvm.hexagon.V6.vasrwh" => "__builtin_HEXAGON_V6_vasrwh", - "llvm.hexagon.V6.vasrwh.128B" => "__builtin_HEXAGON_V6_vasrwh_128B", - "llvm.hexagon.V6.vasrwhrndsat" => "__builtin_HEXAGON_V6_vasrwhrndsat", - "llvm.hexagon.V6.vasrwhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwhrndsat_128B", - "llvm.hexagon.V6.vasrwhsat" => "__builtin_HEXAGON_V6_vasrwhsat", - "llvm.hexagon.V6.vasrwhsat.128B" => "__builtin_HEXAGON_V6_vasrwhsat_128B", - "llvm.hexagon.V6.vasrwuhrndsat" => "__builtin_HEXAGON_V6_vasrwuhrndsat", - "llvm.hexagon.V6.vasrwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwuhrndsat_128B", - "llvm.hexagon.V6.vasrwuhsat" => "__builtin_HEXAGON_V6_vasrwuhsat", - "llvm.hexagon.V6.vasrwuhsat.128B" => "__builtin_HEXAGON_V6_vasrwuhsat_128B", - "llvm.hexagon.V6.vasrwv" => "__builtin_HEXAGON_V6_vasrwv", - "llvm.hexagon.V6.vasrwv.128B" => "__builtin_HEXAGON_V6_vasrwv_128B", - "llvm.hexagon.V6.vassign" => "__builtin_HEXAGON_V6_vassign", - "llvm.hexagon.V6.vassign.128B" => "__builtin_HEXAGON_V6_vassign_128B", - "llvm.hexagon.V6.vassign.fp" => "__builtin_HEXAGON_V6_vassign_fp", - "llvm.hexagon.V6.vassign.fp.128B" => "__builtin_HEXAGON_V6_vassign_fp_128B", - "llvm.hexagon.V6.vassignp" => "__builtin_HEXAGON_V6_vassignp", - "llvm.hexagon.V6.vassignp.128B" => "__builtin_HEXAGON_V6_vassignp_128B", - "llvm.hexagon.V6.vavgb" => "__builtin_HEXAGON_V6_vavgb", - "llvm.hexagon.V6.vavgb.128B" => "__builtin_HEXAGON_V6_vavgb_128B", - "llvm.hexagon.V6.vavgbrnd" => "__builtin_HEXAGON_V6_vavgbrnd", - "llvm.hexagon.V6.vavgbrnd.128B" => "__builtin_HEXAGON_V6_vavgbrnd_128B", - "llvm.hexagon.V6.vavgh" => "__builtin_HEXAGON_V6_vavgh", - "llvm.hexagon.V6.vavgh.128B" => "__builtin_HEXAGON_V6_vavgh_128B", - "llvm.hexagon.V6.vavghrnd" => "__builtin_HEXAGON_V6_vavghrnd", - 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"__builtin_HEXAGON_V6_vavgw_128B", - "llvm.hexagon.V6.vavgwrnd" => "__builtin_HEXAGON_V6_vavgwrnd", - "llvm.hexagon.V6.vavgwrnd.128B" => "__builtin_HEXAGON_V6_vavgwrnd_128B", - "llvm.hexagon.V6.vcl0h" => "__builtin_HEXAGON_V6_vcl0h", - "llvm.hexagon.V6.vcl0h.128B" => "__builtin_HEXAGON_V6_vcl0h_128B", - "llvm.hexagon.V6.vcl0w" => "__builtin_HEXAGON_V6_vcl0w", - "llvm.hexagon.V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B", - "llvm.hexagon.V6.vcombine" => "__builtin_HEXAGON_V6_vcombine", - "llvm.hexagon.V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B", - "llvm.hexagon.V6.vconv.h.hf" => "__builtin_HEXAGON_V6_vconv_h_hf", - "llvm.hexagon.V6.vconv.h.hf.128B" => "__builtin_HEXAGON_V6_vconv_h_hf_128B", - "llvm.hexagon.V6.vconv.hf.h" => "__builtin_HEXAGON_V6_vconv_hf_h", - "llvm.hexagon.V6.vconv.hf.h.128B" => "__builtin_HEXAGON_V6_vconv_hf_h_128B", - "llvm.hexagon.V6.vconv.hf.qf16" => "__builtin_HEXAGON_V6_vconv_hf_qf16", - "llvm.hexagon.V6.vconv.hf.qf16.128B" => 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"llvm.hexagon.V6.vdelta" => "__builtin_HEXAGON_V6_vdelta", - "llvm.hexagon.V6.vdelta.128B" => "__builtin_HEXAGON_V6_vdelta_128B", - "llvm.hexagon.V6.vdmpy.sf.hf" => "__builtin_HEXAGON_V6_vdmpy_sf_hf", - "llvm.hexagon.V6.vdmpy.sf.hf.128B" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_128B", - "llvm.hexagon.V6.vdmpy.sf.hf.acc" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_acc", - "llvm.hexagon.V6.vdmpy.sf.hf.acc.128B" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_acc_128B", - "llvm.hexagon.V6.vdmpybus" => "__builtin_HEXAGON_V6_vdmpybus", - "llvm.hexagon.V6.vdmpybus.128B" => "__builtin_HEXAGON_V6_vdmpybus_128B", - "llvm.hexagon.V6.vdmpybus.acc" => "__builtin_HEXAGON_V6_vdmpybus_acc", - "llvm.hexagon.V6.vdmpybus.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_acc_128B", - "llvm.hexagon.V6.vdmpybus.dv" => "__builtin_HEXAGON_V6_vdmpybus_dv", - "llvm.hexagon.V6.vdmpybus.dv.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_128B", - "llvm.hexagon.V6.vdmpybus.dv.acc" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc", - "llvm.hexagon.V6.vdmpybus.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc_128B", - "llvm.hexagon.V6.vdmpyhb" => "__builtin_HEXAGON_V6_vdmpyhb", - "llvm.hexagon.V6.vdmpyhb.128B" => "__builtin_HEXAGON_V6_vdmpyhb_128B", - "llvm.hexagon.V6.vdmpyhb.acc" => "__builtin_HEXAGON_V6_vdmpyhb_acc", - "llvm.hexagon.V6.vdmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_acc_128B", - "llvm.hexagon.V6.vdmpyhb.dv" => "__builtin_HEXAGON_V6_vdmpyhb_dv", - "llvm.hexagon.V6.vdmpyhb.dv.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_128B", - "llvm.hexagon.V6.vdmpyhb.dv.acc" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc", - "llvm.hexagon.V6.vdmpyhb.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc_128B", - "llvm.hexagon.V6.vdmpyhisat" => "__builtin_HEXAGON_V6_vdmpyhisat", - "llvm.hexagon.V6.vdmpyhisat.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_128B", - "llvm.hexagon.V6.vdmpyhisat.acc" => "__builtin_HEXAGON_V6_vdmpyhisat_acc", - "llvm.hexagon.V6.vdmpyhisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_acc_128B", - "llvm.hexagon.V6.vdmpyhsat" => "__builtin_HEXAGON_V6_vdmpyhsat", - "llvm.hexagon.V6.vdmpyhsat.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_128B", - "llvm.hexagon.V6.vdmpyhsat.acc" => "__builtin_HEXAGON_V6_vdmpyhsat_acc", - "llvm.hexagon.V6.vdmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_acc_128B", - "llvm.hexagon.V6.vdmpyhsuisat" => "__builtin_HEXAGON_V6_vdmpyhsuisat", - "llvm.hexagon.V6.vdmpyhsuisat.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_128B", - "llvm.hexagon.V6.vdmpyhsuisat.acc" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc", - "llvm.hexagon.V6.vdmpyhsuisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc_128B", - "llvm.hexagon.V6.vdmpyhsusat" => "__builtin_HEXAGON_V6_vdmpyhsusat", - "llvm.hexagon.V6.vdmpyhsusat.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_128B", - "llvm.hexagon.V6.vdmpyhsusat.acc" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc", - "llvm.hexagon.V6.vdmpyhsusat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc_128B", - "llvm.hexagon.V6.vdmpyhvsat" => "__builtin_HEXAGON_V6_vdmpyhvsat", - "llvm.hexagon.V6.vdmpyhvsat.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_128B", - "llvm.hexagon.V6.vdmpyhvsat.acc" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc", - "llvm.hexagon.V6.vdmpyhvsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc_128B", - "llvm.hexagon.V6.vdsaduh" => "__builtin_HEXAGON_V6_vdsaduh", - "llvm.hexagon.V6.vdsaduh.128B" => "__builtin_HEXAGON_V6_vdsaduh_128B", - "llvm.hexagon.V6.vdsaduh.acc" => "__builtin_HEXAGON_V6_vdsaduh_acc", - "llvm.hexagon.V6.vdsaduh.acc.128B" => "__builtin_HEXAGON_V6_vdsaduh_acc_128B", - "llvm.hexagon.V6.veqb" => "__builtin_HEXAGON_V6_veqb", - "llvm.hexagon.V6.veqb.128B" => "__builtin_HEXAGON_V6_veqb_128B", - "llvm.hexagon.V6.veqb.and" => "__builtin_HEXAGON_V6_veqb_and", - "llvm.hexagon.V6.veqb.and.128B" => "__builtin_HEXAGON_V6_veqb_and_128B", - "llvm.hexagon.V6.veqb.or" => "__builtin_HEXAGON_V6_veqb_or", - "llvm.hexagon.V6.veqb.or.128B" => "__builtin_HEXAGON_V6_veqb_or_128B", - "llvm.hexagon.V6.veqb.xor" => "__builtin_HEXAGON_V6_veqb_xor", - "llvm.hexagon.V6.veqb.xor.128B" => "__builtin_HEXAGON_V6_veqb_xor_128B", - "llvm.hexagon.V6.veqh" => "__builtin_HEXAGON_V6_veqh", - "llvm.hexagon.V6.veqh.128B" => "__builtin_HEXAGON_V6_veqh_128B", - "llvm.hexagon.V6.veqh.and" => "__builtin_HEXAGON_V6_veqh_and", - "llvm.hexagon.V6.veqh.and.128B" => "__builtin_HEXAGON_V6_veqh_and_128B", - "llvm.hexagon.V6.veqh.or" => "__builtin_HEXAGON_V6_veqh_or", - "llvm.hexagon.V6.veqh.or.128B" => "__builtin_HEXAGON_V6_veqh_or_128B", - "llvm.hexagon.V6.veqh.xor" => "__builtin_HEXAGON_V6_veqh_xor", - "llvm.hexagon.V6.veqh.xor.128B" => "__builtin_HEXAGON_V6_veqh_xor_128B", - "llvm.hexagon.V6.veqw" => "__builtin_HEXAGON_V6_veqw", - "llvm.hexagon.V6.veqw.128B" => "__builtin_HEXAGON_V6_veqw_128B", - "llvm.hexagon.V6.veqw.and" => "__builtin_HEXAGON_V6_veqw_and", - "llvm.hexagon.V6.veqw.and.128B" => "__builtin_HEXAGON_V6_veqw_and_128B", - "llvm.hexagon.V6.veqw.or" => "__builtin_HEXAGON_V6_veqw_or", - "llvm.hexagon.V6.veqw.or.128B" => "__builtin_HEXAGON_V6_veqw_or_128B", - "llvm.hexagon.V6.veqw.xor" => "__builtin_HEXAGON_V6_veqw_xor", - "llvm.hexagon.V6.veqw.xor.128B" => "__builtin_HEXAGON_V6_veqw_xor_128B", - "llvm.hexagon.V6.vfmax.f8" => "__builtin_HEXAGON_V6_vfmax_f8", - "llvm.hexagon.V6.vfmax.f8.128B" => "__builtin_HEXAGON_V6_vfmax_f8_128B", - "llvm.hexagon.V6.vfmax.hf" => "__builtin_HEXAGON_V6_vfmax_hf", - "llvm.hexagon.V6.vfmax.hf.128B" => "__builtin_HEXAGON_V6_vfmax_hf_128B", - "llvm.hexagon.V6.vfmax.sf" => "__builtin_HEXAGON_V6_vfmax_sf", - "llvm.hexagon.V6.vfmax.sf.128B" => "__builtin_HEXAGON_V6_vfmax_sf_128B", - "llvm.hexagon.V6.vfmin.f8" => "__builtin_HEXAGON_V6_vfmin_f8", - "llvm.hexagon.V6.vfmin.f8.128B" => "__builtin_HEXAGON_V6_vfmin_f8_128B", - "llvm.hexagon.V6.vfmin.hf" => "__builtin_HEXAGON_V6_vfmin_hf", - "llvm.hexagon.V6.vfmin.hf.128B" => "__builtin_HEXAGON_V6_vfmin_hf_128B", - "llvm.hexagon.V6.vfmin.sf" => "__builtin_HEXAGON_V6_vfmin_sf", - "llvm.hexagon.V6.vfmin.sf.128B" => "__builtin_HEXAGON_V6_vfmin_sf_128B", - "llvm.hexagon.V6.vfneg.f8" => "__builtin_HEXAGON_V6_vfneg_f8", - "llvm.hexagon.V6.vfneg.f8.128B" => "__builtin_HEXAGON_V6_vfneg_f8_128B", - "llvm.hexagon.V6.vfneg.hf" => "__builtin_HEXAGON_V6_vfneg_hf", - "llvm.hexagon.V6.vfneg.hf.128B" => "__builtin_HEXAGON_V6_vfneg_hf_128B", - "llvm.hexagon.V6.vfneg.sf" => "__builtin_HEXAGON_V6_vfneg_sf", - "llvm.hexagon.V6.vfneg.sf.128B" => "__builtin_HEXAGON_V6_vfneg_sf_128B", - "llvm.hexagon.V6.vgathermh" => "__builtin_HEXAGON_V6_vgathermh", - "llvm.hexagon.V6.vgathermh.128B" => "__builtin_HEXAGON_V6_vgathermh_128B", - "llvm.hexagon.V6.vgathermhq" => "__builtin_HEXAGON_V6_vgathermhq", - "llvm.hexagon.V6.vgathermhq.128B" => "__builtin_HEXAGON_V6_vgathermhq_128B", - "llvm.hexagon.V6.vgathermhw" => "__builtin_HEXAGON_V6_vgathermhw", - "llvm.hexagon.V6.vgathermhw.128B" => "__builtin_HEXAGON_V6_vgathermhw_128B", - "llvm.hexagon.V6.vgathermhwq" => "__builtin_HEXAGON_V6_vgathermhwq", - "llvm.hexagon.V6.vgathermhwq.128B" => "__builtin_HEXAGON_V6_vgathermhwq_128B", - "llvm.hexagon.V6.vgathermw" => "__builtin_HEXAGON_V6_vgathermw", - "llvm.hexagon.V6.vgathermw.128B" => "__builtin_HEXAGON_V6_vgathermw_128B", - "llvm.hexagon.V6.vgathermwq" => "__builtin_HEXAGON_V6_vgathermwq", - "llvm.hexagon.V6.vgathermwq.128B" => "__builtin_HEXAGON_V6_vgathermwq_128B", - "llvm.hexagon.V6.vgtb" => "__builtin_HEXAGON_V6_vgtb", - "llvm.hexagon.V6.vgtb.128B" => "__builtin_HEXAGON_V6_vgtb_128B", - "llvm.hexagon.V6.vgtb.and" => "__builtin_HEXAGON_V6_vgtb_and", - "llvm.hexagon.V6.vgtb.and.128B" => "__builtin_HEXAGON_V6_vgtb_and_128B", - "llvm.hexagon.V6.vgtb.or" => "__builtin_HEXAGON_V6_vgtb_or", - "llvm.hexagon.V6.vgtb.or.128B" => "__builtin_HEXAGON_V6_vgtb_or_128B", - "llvm.hexagon.V6.vgtb.xor" => "__builtin_HEXAGON_V6_vgtb_xor", - "llvm.hexagon.V6.vgtb.xor.128B" => "__builtin_HEXAGON_V6_vgtb_xor_128B", - "llvm.hexagon.V6.vgtbf" => "__builtin_HEXAGON_V6_vgtbf", - "llvm.hexagon.V6.vgtbf.128B" => "__builtin_HEXAGON_V6_vgtbf_128B", - "llvm.hexagon.V6.vgtbf.and" => "__builtin_HEXAGON_V6_vgtbf_and", - "llvm.hexagon.V6.vgtbf.and.128B" => "__builtin_HEXAGON_V6_vgtbf_and_128B", - "llvm.hexagon.V6.vgtbf.or" => "__builtin_HEXAGON_V6_vgtbf_or", - "llvm.hexagon.V6.vgtbf.or.128B" => "__builtin_HEXAGON_V6_vgtbf_or_128B", - "llvm.hexagon.V6.vgtbf.xor" => "__builtin_HEXAGON_V6_vgtbf_xor", - "llvm.hexagon.V6.vgtbf.xor.128B" => "__builtin_HEXAGON_V6_vgtbf_xor_128B", - "llvm.hexagon.V6.vgth" => "__builtin_HEXAGON_V6_vgth", - "llvm.hexagon.V6.vgth.128B" => "__builtin_HEXAGON_V6_vgth_128B", - "llvm.hexagon.V6.vgth.and" => "__builtin_HEXAGON_V6_vgth_and", - "llvm.hexagon.V6.vgth.and.128B" => "__builtin_HEXAGON_V6_vgth_and_128B", - "llvm.hexagon.V6.vgth.or" => "__builtin_HEXAGON_V6_vgth_or", - "llvm.hexagon.V6.vgth.or.128B" => "__builtin_HEXAGON_V6_vgth_or_128B", - "llvm.hexagon.V6.vgth.xor" => "__builtin_HEXAGON_V6_vgth_xor", - "llvm.hexagon.V6.vgth.xor.128B" => "__builtin_HEXAGON_V6_vgth_xor_128B", - "llvm.hexagon.V6.vgthf" => "__builtin_HEXAGON_V6_vgthf", - "llvm.hexagon.V6.vgthf.128B" => "__builtin_HEXAGON_V6_vgthf_128B", - "llvm.hexagon.V6.vgthf.and" => "__builtin_HEXAGON_V6_vgthf_and", - "llvm.hexagon.V6.vgthf.and.128B" => "__builtin_HEXAGON_V6_vgthf_and_128B", - "llvm.hexagon.V6.vgthf.or" => "__builtin_HEXAGON_V6_vgthf_or", - "llvm.hexagon.V6.vgthf.or.128B" => "__builtin_HEXAGON_V6_vgthf_or_128B", - "llvm.hexagon.V6.vgthf.xor" => "__builtin_HEXAGON_V6_vgthf_xor", - "llvm.hexagon.V6.vgthf.xor.128B" => "__builtin_HEXAGON_V6_vgthf_xor_128B", - "llvm.hexagon.V6.vgtsf" => "__builtin_HEXAGON_V6_vgtsf", - "llvm.hexagon.V6.vgtsf.128B" => "__builtin_HEXAGON_V6_vgtsf_128B", - "llvm.hexagon.V6.vgtsf.and" => "__builtin_HEXAGON_V6_vgtsf_and", - "llvm.hexagon.V6.vgtsf.and.128B" => "__builtin_HEXAGON_V6_vgtsf_and_128B", - "llvm.hexagon.V6.vgtsf.or" => "__builtin_HEXAGON_V6_vgtsf_or", - "llvm.hexagon.V6.vgtsf.or.128B" => "__builtin_HEXAGON_V6_vgtsf_or_128B", - "llvm.hexagon.V6.vgtsf.xor" => "__builtin_HEXAGON_V6_vgtsf_xor", - "llvm.hexagon.V6.vgtsf.xor.128B" => "__builtin_HEXAGON_V6_vgtsf_xor_128B", - "llvm.hexagon.V6.vgtub" => "__builtin_HEXAGON_V6_vgtub", - "llvm.hexagon.V6.vgtub.128B" => "__builtin_HEXAGON_V6_vgtub_128B", - "llvm.hexagon.V6.vgtub.and" => "__builtin_HEXAGON_V6_vgtub_and", - "llvm.hexagon.V6.vgtub.and.128B" => "__builtin_HEXAGON_V6_vgtub_and_128B", - "llvm.hexagon.V6.vgtub.or" => "__builtin_HEXAGON_V6_vgtub_or", - "llvm.hexagon.V6.vgtub.or.128B" => "__builtin_HEXAGON_V6_vgtub_or_128B", - "llvm.hexagon.V6.vgtub.xor" => "__builtin_HEXAGON_V6_vgtub_xor", - "llvm.hexagon.V6.vgtub.xor.128B" => "__builtin_HEXAGON_V6_vgtub_xor_128B", - "llvm.hexagon.V6.vgtuh" => "__builtin_HEXAGON_V6_vgtuh", - "llvm.hexagon.V6.vgtuh.128B" => "__builtin_HEXAGON_V6_vgtuh_128B", - "llvm.hexagon.V6.vgtuh.and" => "__builtin_HEXAGON_V6_vgtuh_and", - "llvm.hexagon.V6.vgtuh.and.128B" => "__builtin_HEXAGON_V6_vgtuh_and_128B", - "llvm.hexagon.V6.vgtuh.or" => "__builtin_HEXAGON_V6_vgtuh_or", - "llvm.hexagon.V6.vgtuh.or.128B" => "__builtin_HEXAGON_V6_vgtuh_or_128B", - "llvm.hexagon.V6.vgtuh.xor" => "__builtin_HEXAGON_V6_vgtuh_xor", - "llvm.hexagon.V6.vgtuh.xor.128B" => "__builtin_HEXAGON_V6_vgtuh_xor_128B", - "llvm.hexagon.V6.vgtuw" => "__builtin_HEXAGON_V6_vgtuw", - "llvm.hexagon.V6.vgtuw.128B" => "__builtin_HEXAGON_V6_vgtuw_128B", - "llvm.hexagon.V6.vgtuw.and" => "__builtin_HEXAGON_V6_vgtuw_and", - "llvm.hexagon.V6.vgtuw.and.128B" => "__builtin_HEXAGON_V6_vgtuw_and_128B", - "llvm.hexagon.V6.vgtuw.or" => "__builtin_HEXAGON_V6_vgtuw_or", - "llvm.hexagon.V6.vgtuw.or.128B" => "__builtin_HEXAGON_V6_vgtuw_or_128B", - "llvm.hexagon.V6.vgtuw.xor" => "__builtin_HEXAGON_V6_vgtuw_xor", - "llvm.hexagon.V6.vgtuw.xor.128B" => "__builtin_HEXAGON_V6_vgtuw_xor_128B", - "llvm.hexagon.V6.vgtw" => "__builtin_HEXAGON_V6_vgtw", - "llvm.hexagon.V6.vgtw.128B" => "__builtin_HEXAGON_V6_vgtw_128B", - "llvm.hexagon.V6.vgtw.and" => "__builtin_HEXAGON_V6_vgtw_and", - "llvm.hexagon.V6.vgtw.and.128B" => "__builtin_HEXAGON_V6_vgtw_and_128B", - "llvm.hexagon.V6.vgtw.or" => "__builtin_HEXAGON_V6_vgtw_or", - "llvm.hexagon.V6.vgtw.or.128B" => "__builtin_HEXAGON_V6_vgtw_or_128B", - "llvm.hexagon.V6.vgtw.xor" => "__builtin_HEXAGON_V6_vgtw_xor", - "llvm.hexagon.V6.vgtw.xor.128B" => "__builtin_HEXAGON_V6_vgtw_xor_128B", - "llvm.hexagon.V6.vinsertwr" => "__builtin_HEXAGON_V6_vinsertwr", - "llvm.hexagon.V6.vinsertwr.128B" => "__builtin_HEXAGON_V6_vinsertwr_128B", - "llvm.hexagon.V6.vlalignb" => "__builtin_HEXAGON_V6_vlalignb", - "llvm.hexagon.V6.vlalignb.128B" => "__builtin_HEXAGON_V6_vlalignb_128B", - "llvm.hexagon.V6.vlalignbi" => "__builtin_HEXAGON_V6_vlalignbi", - "llvm.hexagon.V6.vlalignbi.128B" => "__builtin_HEXAGON_V6_vlalignbi_128B", - "llvm.hexagon.V6.vlsrb" => "__builtin_HEXAGON_V6_vlsrb", - "llvm.hexagon.V6.vlsrb.128B" => "__builtin_HEXAGON_V6_vlsrb_128B", - "llvm.hexagon.V6.vlsrh" => "__builtin_HEXAGON_V6_vlsrh", - "llvm.hexagon.V6.vlsrh.128B" => "__builtin_HEXAGON_V6_vlsrh_128B", - "llvm.hexagon.V6.vlsrhv" => "__builtin_HEXAGON_V6_vlsrhv", - "llvm.hexagon.V6.vlsrhv.128B" => "__builtin_HEXAGON_V6_vlsrhv_128B", - "llvm.hexagon.V6.vlsrw" => "__builtin_HEXAGON_V6_vlsrw", - "llvm.hexagon.V6.vlsrw.128B" => "__builtin_HEXAGON_V6_vlsrw_128B", - "llvm.hexagon.V6.vlsrwv" => "__builtin_HEXAGON_V6_vlsrwv", - "llvm.hexagon.V6.vlsrwv.128B" => "__builtin_HEXAGON_V6_vlsrwv_128B", - "llvm.hexagon.V6.vlut4" => "__builtin_HEXAGON_V6_vlut4", - "llvm.hexagon.V6.vlut4.128B" => "__builtin_HEXAGON_V6_vlut4_128B", - "llvm.hexagon.V6.vlutb" => "__builtin_HEXAGON_V6_vlutb", - "llvm.hexagon.V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B", - "llvm.hexagon.V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc", - "llvm.hexagon.V6.vlutb.acc.128B" => "__builtin_HEXAGON_V6_vlutb_acc_128B", - "llvm.hexagon.V6.vlutb.dv" => "__builtin_HEXAGON_V6_vlutb_dv", - "llvm.hexagon.V6.vlutb.dv.128B" => "__builtin_HEXAGON_V6_vlutb_dv_128B", - "llvm.hexagon.V6.vlutb.dv.acc" => "__builtin_HEXAGON_V6_vlutb_dv_acc", - "llvm.hexagon.V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B", - "llvm.hexagon.V6.vlutvvb" => "__builtin_HEXAGON_V6_vlutvvb", - "llvm.hexagon.V6.vlutvvb.128B" => "__builtin_HEXAGON_V6_vlutvvb_128B", - "llvm.hexagon.V6.vlutvvb.nm" => "__builtin_HEXAGON_V6_vlutvvb_nm", - "llvm.hexagon.V6.vlutvvb.nm.128B" => "__builtin_HEXAGON_V6_vlutvvb_nm_128B", - "llvm.hexagon.V6.vlutvvb.oracc" => "__builtin_HEXAGON_V6_vlutvvb_oracc", - "llvm.hexagon.V6.vlutvvb.oracc.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracc_128B", - "llvm.hexagon.V6.vlutvvb.oracci" => "__builtin_HEXAGON_V6_vlutvvb_oracci", - "llvm.hexagon.V6.vlutvvb.oracci.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracci_128B", - "llvm.hexagon.V6.vlutvvbi" => "__builtin_HEXAGON_V6_vlutvvbi", - "llvm.hexagon.V6.vlutvvbi.128B" => "__builtin_HEXAGON_V6_vlutvvbi_128B", - "llvm.hexagon.V6.vlutvwh" => "__builtin_HEXAGON_V6_vlutvwh", - "llvm.hexagon.V6.vlutvwh.128B" => "__builtin_HEXAGON_V6_vlutvwh_128B", - "llvm.hexagon.V6.vlutvwh.nm" => "__builtin_HEXAGON_V6_vlutvwh_nm", - "llvm.hexagon.V6.vlutvwh.nm.128B" => "__builtin_HEXAGON_V6_vlutvwh_nm_128B", - "llvm.hexagon.V6.vlutvwh.oracc" => "__builtin_HEXAGON_V6_vlutvwh_oracc", - "llvm.hexagon.V6.vlutvwh.oracc.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracc_128B", - "llvm.hexagon.V6.vlutvwh.oracci" => "__builtin_HEXAGON_V6_vlutvwh_oracci", - "llvm.hexagon.V6.vlutvwh.oracci.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracci_128B", - "llvm.hexagon.V6.vlutvwhi" => "__builtin_HEXAGON_V6_vlutvwhi", - "llvm.hexagon.V6.vlutvwhi.128B" => "__builtin_HEXAGON_V6_vlutvwhi_128B", - "llvm.hexagon.V6.vmax.bf" => "__builtin_HEXAGON_V6_vmax_bf", - "llvm.hexagon.V6.vmax.bf.128B" => "__builtin_HEXAGON_V6_vmax_bf_128B", - "llvm.hexagon.V6.vmax.hf" => "__builtin_HEXAGON_V6_vmax_hf", - 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"llvm.hexagon.V6.vminw.128B" => "__builtin_HEXAGON_V6_vminw_128B", - "llvm.hexagon.V6.vmpabus" => "__builtin_HEXAGON_V6_vmpabus", - "llvm.hexagon.V6.vmpabus.128B" => "__builtin_HEXAGON_V6_vmpabus_128B", - "llvm.hexagon.V6.vmpabus.acc" => "__builtin_HEXAGON_V6_vmpabus_acc", - "llvm.hexagon.V6.vmpabus.acc.128B" => "__builtin_HEXAGON_V6_vmpabus_acc_128B", - "llvm.hexagon.V6.vmpabusv" => "__builtin_HEXAGON_V6_vmpabusv", - "llvm.hexagon.V6.vmpabusv.128B" => "__builtin_HEXAGON_V6_vmpabusv_128B", - "llvm.hexagon.V6.vmpabuu" => "__builtin_HEXAGON_V6_vmpabuu", - "llvm.hexagon.V6.vmpabuu.128B" => "__builtin_HEXAGON_V6_vmpabuu_128B", - "llvm.hexagon.V6.vmpabuu.acc" => "__builtin_HEXAGON_V6_vmpabuu_acc", - "llvm.hexagon.V6.vmpabuu.acc.128B" => "__builtin_HEXAGON_V6_vmpabuu_acc_128B", - "llvm.hexagon.V6.vmpabuuv" => "__builtin_HEXAGON_V6_vmpabuuv", - "llvm.hexagon.V6.vmpabuuv.128B" => "__builtin_HEXAGON_V6_vmpabuuv_128B", - "llvm.hexagon.V6.vmpahb" => "__builtin_HEXAGON_V6_vmpahb", - "llvm.hexagon.V6.vmpahb.128B" => "__builtin_HEXAGON_V6_vmpahb_128B", - "llvm.hexagon.V6.vmpahb.acc" => "__builtin_HEXAGON_V6_vmpahb_acc", - "llvm.hexagon.V6.vmpahb.acc.128B" => "__builtin_HEXAGON_V6_vmpahb_acc_128B", - "llvm.hexagon.V6.vmpahhsat" => "__builtin_HEXAGON_V6_vmpahhsat", - "llvm.hexagon.V6.vmpahhsat.128B" => "__builtin_HEXAGON_V6_vmpahhsat_128B", - "llvm.hexagon.V6.vmpauhb" => "__builtin_HEXAGON_V6_vmpauhb", - "llvm.hexagon.V6.vmpauhb.128B" => "__builtin_HEXAGON_V6_vmpauhb_128B", - "llvm.hexagon.V6.vmpauhb.acc" => "__builtin_HEXAGON_V6_vmpauhb_acc", - "llvm.hexagon.V6.vmpauhb.acc.128B" => "__builtin_HEXAGON_V6_vmpauhb_acc_128B", - "llvm.hexagon.V6.vmpauhuhsat" => "__builtin_HEXAGON_V6_vmpauhuhsat", - "llvm.hexagon.V6.vmpauhuhsat.128B" => "__builtin_HEXAGON_V6_vmpauhuhsat_128B", - "llvm.hexagon.V6.vmpsuhuhsat" => "__builtin_HEXAGON_V6_vmpsuhuhsat", - "llvm.hexagon.V6.vmpsuhuhsat.128B" => "__builtin_HEXAGON_V6_vmpsuhuhsat_128B", - "llvm.hexagon.V6.vmpy.hf.f8" => "__builtin_HEXAGON_V6_vmpy_hf_f8", - "llvm.hexagon.V6.vmpy.hf.f8.128B" => "__builtin_HEXAGON_V6_vmpy_hf_f8_128B", - "llvm.hexagon.V6.vmpy.hf.f8.acc" => "__builtin_HEXAGON_V6_vmpy_hf_f8_acc", - "llvm.hexagon.V6.vmpy.hf.f8.acc.128B" => "__builtin_HEXAGON_V6_vmpy_hf_f8_acc_128B", - "llvm.hexagon.V6.vmpy.hf.hf" => "__builtin_HEXAGON_V6_vmpy_hf_hf", - "llvm.hexagon.V6.vmpy.hf.hf.128B" => "__builtin_HEXAGON_V6_vmpy_hf_hf_128B", - "llvm.hexagon.V6.vmpy.hf.hf.acc" => "__builtin_HEXAGON_V6_vmpy_hf_hf_acc", - "llvm.hexagon.V6.vmpy.hf.hf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_hf_hf_acc_128B", - "llvm.hexagon.V6.vmpy.qf16" => "__builtin_HEXAGON_V6_vmpy_qf16", - "llvm.hexagon.V6.vmpy.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_128B", - "llvm.hexagon.V6.vmpy.qf16.hf" => "__builtin_HEXAGON_V6_vmpy_qf16_hf", - "llvm.hexagon.V6.vmpy.qf16.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_hf_128B", - "llvm.hexagon.V6.vmpy.qf16.mix.hf" => "__builtin_HEXAGON_V6_vmpy_qf16_mix_hf", - "llvm.hexagon.V6.vmpy.qf16.mix.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_mix_hf_128B", - "llvm.hexagon.V6.vmpy.qf32" => "__builtin_HEXAGON_V6_vmpy_qf32", - "llvm.hexagon.V6.vmpy.qf32.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_128B", - "llvm.hexagon.V6.vmpy.qf32.hf" => "__builtin_HEXAGON_V6_vmpy_qf32_hf", - "llvm.hexagon.V6.vmpy.qf32.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_hf_128B", - "llvm.hexagon.V6.vmpy.qf32.mix.hf" => "__builtin_HEXAGON_V6_vmpy_qf32_mix_hf", - "llvm.hexagon.V6.vmpy.qf32.mix.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_mix_hf_128B", - "llvm.hexagon.V6.vmpy.qf32.qf16" => "__builtin_HEXAGON_V6_vmpy_qf32_qf16", - "llvm.hexagon.V6.vmpy.qf32.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_qf16_128B", - "llvm.hexagon.V6.vmpy.qf32.sf" => "__builtin_HEXAGON_V6_vmpy_qf32_sf", - "llvm.hexagon.V6.vmpy.qf32.sf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_sf_128B", - "llvm.hexagon.V6.vmpy.rt.hf" => "__builtin_HEXAGON_V6_vmpy_rt_hf", - "llvm.hexagon.V6.vmpy.rt.hf.128B" => "__builtin_HEXAGON_V6_vmpy_rt_hf_128B", - "llvm.hexagon.V6.vmpy.rt.qf16" => "__builtin_HEXAGON_V6_vmpy_rt_qf16", - "llvm.hexagon.V6.vmpy.rt.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_rt_qf16_128B", - "llvm.hexagon.V6.vmpy.rt.sf" => "__builtin_HEXAGON_V6_vmpy_rt_sf", - "llvm.hexagon.V6.vmpy.rt.sf.128B" => "__builtin_HEXAGON_V6_vmpy_rt_sf_128B", - "llvm.hexagon.V6.vmpy.sf.bf" => "__builtin_HEXAGON_V6_vmpy_sf_bf", - "llvm.hexagon.V6.vmpy.sf.bf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_bf_128B", - "llvm.hexagon.V6.vmpy.sf.bf.acc" => "__builtin_HEXAGON_V6_vmpy_sf_bf_acc", - "llvm.hexagon.V6.vmpy.sf.bf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_sf_bf_acc_128B", - "llvm.hexagon.V6.vmpy.sf.hf" => "__builtin_HEXAGON_V6_vmpy_sf_hf", - "llvm.hexagon.V6.vmpy.sf.hf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_hf_128B", - "llvm.hexagon.V6.vmpy.sf.hf.acc" => "__builtin_HEXAGON_V6_vmpy_sf_hf_acc", - "llvm.hexagon.V6.vmpy.sf.hf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_sf_hf_acc_128B", - "llvm.hexagon.V6.vmpy.sf.sf" => "__builtin_HEXAGON_V6_vmpy_sf_sf", - "llvm.hexagon.V6.vmpy.sf.sf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_sf_128B", - "llvm.hexagon.V6.vmpybus" => "__builtin_HEXAGON_V6_vmpybus", - "llvm.hexagon.V6.vmpybus.128B" => "__builtin_HEXAGON_V6_vmpybus_128B", - "llvm.hexagon.V6.vmpybus.acc" => "__builtin_HEXAGON_V6_vmpybus_acc", - "llvm.hexagon.V6.vmpybus.acc.128B" => "__builtin_HEXAGON_V6_vmpybus_acc_128B", - "llvm.hexagon.V6.vmpybusv" => "__builtin_HEXAGON_V6_vmpybusv", - "llvm.hexagon.V6.vmpybusv.128B" => "__builtin_HEXAGON_V6_vmpybusv_128B", - "llvm.hexagon.V6.vmpybusv.acc" => "__builtin_HEXAGON_V6_vmpybusv_acc", - "llvm.hexagon.V6.vmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vmpybusv_acc_128B", - "llvm.hexagon.V6.vmpybv" => "__builtin_HEXAGON_V6_vmpybv", - "llvm.hexagon.V6.vmpybv.128B" => "__builtin_HEXAGON_V6_vmpybv_128B", - "llvm.hexagon.V6.vmpybv.acc" => "__builtin_HEXAGON_V6_vmpybv_acc", - "llvm.hexagon.V6.vmpybv.acc.128B" => "__builtin_HEXAGON_V6_vmpybv_acc_128B", - "llvm.hexagon.V6.vmpyewuh" => "__builtin_HEXAGON_V6_vmpyewuh", - "llvm.hexagon.V6.vmpyewuh.128B" => "__builtin_HEXAGON_V6_vmpyewuh_128B", - "llvm.hexagon.V6.vmpyewuh.64" => "__builtin_HEXAGON_V6_vmpyewuh_64", - "llvm.hexagon.V6.vmpyewuh.64.128B" => "__builtin_HEXAGON_V6_vmpyewuh_64_128B", - "llvm.hexagon.V6.vmpyh" => "__builtin_HEXAGON_V6_vmpyh", - "llvm.hexagon.V6.vmpyh.128B" => "__builtin_HEXAGON_V6_vmpyh_128B", - "llvm.hexagon.V6.vmpyh.acc" => "__builtin_HEXAGON_V6_vmpyh_acc", - "llvm.hexagon.V6.vmpyh.acc.128B" => "__builtin_HEXAGON_V6_vmpyh_acc_128B", - "llvm.hexagon.V6.vmpyhsat.acc" => "__builtin_HEXAGON_V6_vmpyhsat_acc", - "llvm.hexagon.V6.vmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vmpyhsat_acc_128B", - "llvm.hexagon.V6.vmpyhsrs" => "__builtin_HEXAGON_V6_vmpyhsrs", - "llvm.hexagon.V6.vmpyhsrs.128B" => "__builtin_HEXAGON_V6_vmpyhsrs_128B", - "llvm.hexagon.V6.vmpyhss" => "__builtin_HEXAGON_V6_vmpyhss", - "llvm.hexagon.V6.vmpyhss.128B" => "__builtin_HEXAGON_V6_vmpyhss_128B", - "llvm.hexagon.V6.vmpyhus" => "__builtin_HEXAGON_V6_vmpyhus", - "llvm.hexagon.V6.vmpyhus.128B" => "__builtin_HEXAGON_V6_vmpyhus_128B", - "llvm.hexagon.V6.vmpyhus.acc" => "__builtin_HEXAGON_V6_vmpyhus_acc", - "llvm.hexagon.V6.vmpyhus.acc.128B" => "__builtin_HEXAGON_V6_vmpyhus_acc_128B", - "llvm.hexagon.V6.vmpyhv" => "__builtin_HEXAGON_V6_vmpyhv", - "llvm.hexagon.V6.vmpyhv.128B" => "__builtin_HEXAGON_V6_vmpyhv_128B", - "llvm.hexagon.V6.vmpyhv.acc" => "__builtin_HEXAGON_V6_vmpyhv_acc", - "llvm.hexagon.V6.vmpyhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyhv_acc_128B", - "llvm.hexagon.V6.vmpyhvsrs" => "__builtin_HEXAGON_V6_vmpyhvsrs", - "llvm.hexagon.V6.vmpyhvsrs.128B" => "__builtin_HEXAGON_V6_vmpyhvsrs_128B", - "llvm.hexagon.V6.vmpyieoh" => "__builtin_HEXAGON_V6_vmpyieoh", - "llvm.hexagon.V6.vmpyieoh.128B" => "__builtin_HEXAGON_V6_vmpyieoh_128B", - "llvm.hexagon.V6.vmpyiewh.acc" => "__builtin_HEXAGON_V6_vmpyiewh_acc", - "llvm.hexagon.V6.vmpyiewh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewh_acc_128B", - "llvm.hexagon.V6.vmpyiewuh" => "__builtin_HEXAGON_V6_vmpyiewuh", - "llvm.hexagon.V6.vmpyiewuh.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_128B", - "llvm.hexagon.V6.vmpyiewuh.acc" => "__builtin_HEXAGON_V6_vmpyiewuh_acc", - "llvm.hexagon.V6.vmpyiewuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_acc_128B", - "llvm.hexagon.V6.vmpyih" => "__builtin_HEXAGON_V6_vmpyih", - "llvm.hexagon.V6.vmpyih.128B" => "__builtin_HEXAGON_V6_vmpyih_128B", - "llvm.hexagon.V6.vmpyih.acc" => "__builtin_HEXAGON_V6_vmpyih_acc", - "llvm.hexagon.V6.vmpyih.acc.128B" => "__builtin_HEXAGON_V6_vmpyih_acc_128B", - "llvm.hexagon.V6.vmpyihb" => "__builtin_HEXAGON_V6_vmpyihb", - "llvm.hexagon.V6.vmpyihb.128B" => "__builtin_HEXAGON_V6_vmpyihb_128B", - "llvm.hexagon.V6.vmpyihb.acc" => "__builtin_HEXAGON_V6_vmpyihb_acc", - "llvm.hexagon.V6.vmpyihb.acc.128B" => "__builtin_HEXAGON_V6_vmpyihb_acc_128B", - "llvm.hexagon.V6.vmpyiowh" => "__builtin_HEXAGON_V6_vmpyiowh", - "llvm.hexagon.V6.vmpyiowh.128B" => "__builtin_HEXAGON_V6_vmpyiowh_128B", - "llvm.hexagon.V6.vmpyiwb" => "__builtin_HEXAGON_V6_vmpyiwb", - "llvm.hexagon.V6.vmpyiwb.128B" => "__builtin_HEXAGON_V6_vmpyiwb_128B", - "llvm.hexagon.V6.vmpyiwb.acc" => "__builtin_HEXAGON_V6_vmpyiwb_acc", - "llvm.hexagon.V6.vmpyiwb.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwb_acc_128B", - "llvm.hexagon.V6.vmpyiwh" => "__builtin_HEXAGON_V6_vmpyiwh", - "llvm.hexagon.V6.vmpyiwh.128B" => "__builtin_HEXAGON_V6_vmpyiwh_128B", - "llvm.hexagon.V6.vmpyiwh.acc" => "__builtin_HEXAGON_V6_vmpyiwh_acc", - "llvm.hexagon.V6.vmpyiwh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwh_acc_128B", - "llvm.hexagon.V6.vmpyiwub" => "__builtin_HEXAGON_V6_vmpyiwub", - "llvm.hexagon.V6.vmpyiwub.128B" => "__builtin_HEXAGON_V6_vmpyiwub_128B", - "llvm.hexagon.V6.vmpyiwub.acc" => "__builtin_HEXAGON_V6_vmpyiwub_acc", - "llvm.hexagon.V6.vmpyiwub.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwub_acc_128B", - "llvm.hexagon.V6.vmpyowh" => "__builtin_HEXAGON_V6_vmpyowh", - "llvm.hexagon.V6.vmpyowh.128B" => "__builtin_HEXAGON_V6_vmpyowh_128B", - "llvm.hexagon.V6.vmpyowh.64.acc" => "__builtin_HEXAGON_V6_vmpyowh_64_acc", - "llvm.hexagon.V6.vmpyowh.64.acc.128B" => "__builtin_HEXAGON_V6_vmpyowh_64_acc_128B", - "llvm.hexagon.V6.vmpyowh.rnd" => "__builtin_HEXAGON_V6_vmpyowh_rnd", - "llvm.hexagon.V6.vmpyowh.rnd.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_128B", - "llvm.hexagon.V6.vmpyowh.rnd.sacc" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc", - "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc_128B", - "llvm.hexagon.V6.vmpyowh.sacc" => "__builtin_HEXAGON_V6_vmpyowh_sacc", - "llvm.hexagon.V6.vmpyowh.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_sacc_128B", - "llvm.hexagon.V6.vmpyub" => "__builtin_HEXAGON_V6_vmpyub", - "llvm.hexagon.V6.vmpyub.128B" => "__builtin_HEXAGON_V6_vmpyub_128B", - "llvm.hexagon.V6.vmpyub.acc" => "__builtin_HEXAGON_V6_vmpyub_acc", - "llvm.hexagon.V6.vmpyub.acc.128B" => "__builtin_HEXAGON_V6_vmpyub_acc_128B", - "llvm.hexagon.V6.vmpyubv" => "__builtin_HEXAGON_V6_vmpyubv", - "llvm.hexagon.V6.vmpyubv.128B" => "__builtin_HEXAGON_V6_vmpyubv_128B", - "llvm.hexagon.V6.vmpyubv.acc" => "__builtin_HEXAGON_V6_vmpyubv_acc", - "llvm.hexagon.V6.vmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vmpyubv_acc_128B", - "llvm.hexagon.V6.vmpyuh" => "__builtin_HEXAGON_V6_vmpyuh", - "llvm.hexagon.V6.vmpyuh.128B" => "__builtin_HEXAGON_V6_vmpyuh_128B", - "llvm.hexagon.V6.vmpyuh.acc" => "__builtin_HEXAGON_V6_vmpyuh_acc", - "llvm.hexagon.V6.vmpyuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyuh_acc_128B", - "llvm.hexagon.V6.vmpyuhe" => "__builtin_HEXAGON_V6_vmpyuhe", - "llvm.hexagon.V6.vmpyuhe.128B" => "__builtin_HEXAGON_V6_vmpyuhe_128B", - "llvm.hexagon.V6.vmpyuhe.acc" => "__builtin_HEXAGON_V6_vmpyuhe_acc", - "llvm.hexagon.V6.vmpyuhe.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhe_acc_128B", - "llvm.hexagon.V6.vmpyuhv" => "__builtin_HEXAGON_V6_vmpyuhv", - "llvm.hexagon.V6.vmpyuhv.128B" => "__builtin_HEXAGON_V6_vmpyuhv_128B", - "llvm.hexagon.V6.vmpyuhv.acc" => "__builtin_HEXAGON_V6_vmpyuhv_acc", - "llvm.hexagon.V6.vmpyuhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhv_acc_128B", - "llvm.hexagon.V6.vmpyuhvs" => "__builtin_HEXAGON_V6_vmpyuhvs", - "llvm.hexagon.V6.vmpyuhvs.128B" => "__builtin_HEXAGON_V6_vmpyuhvs_128B", - "llvm.hexagon.V6.vmux" => "__builtin_HEXAGON_V6_vmux", - "llvm.hexagon.V6.vmux.128B" => "__builtin_HEXAGON_V6_vmux_128B", - "llvm.hexagon.V6.vnavgb" => "__builtin_HEXAGON_V6_vnavgb", - "llvm.hexagon.V6.vnavgb.128B" => "__builtin_HEXAGON_V6_vnavgb_128B", - "llvm.hexagon.V6.vnavgh" => "__builtin_HEXAGON_V6_vnavgh", - "llvm.hexagon.V6.vnavgh.128B" => "__builtin_HEXAGON_V6_vnavgh_128B", - "llvm.hexagon.V6.vnavgub" => "__builtin_HEXAGON_V6_vnavgub", - "llvm.hexagon.V6.vnavgub.128B" => "__builtin_HEXAGON_V6_vnavgub_128B", - "llvm.hexagon.V6.vnavgw" => "__builtin_HEXAGON_V6_vnavgw", - "llvm.hexagon.V6.vnavgw.128B" => "__builtin_HEXAGON_V6_vnavgw_128B", - "llvm.hexagon.V6.vnormamth" => "__builtin_HEXAGON_V6_vnormamth", - "llvm.hexagon.V6.vnormamth.128B" => "__builtin_HEXAGON_V6_vnormamth_128B", - "llvm.hexagon.V6.vnormamtw" => "__builtin_HEXAGON_V6_vnormamtw", - "llvm.hexagon.V6.vnormamtw.128B" => "__builtin_HEXAGON_V6_vnormamtw_128B", - "llvm.hexagon.V6.vnot" => "__builtin_HEXAGON_V6_vnot", - "llvm.hexagon.V6.vnot.128B" => "__builtin_HEXAGON_V6_vnot_128B", - "llvm.hexagon.V6.vor" => "__builtin_HEXAGON_V6_vor", - "llvm.hexagon.V6.vor.128B" => "__builtin_HEXAGON_V6_vor_128B", - "llvm.hexagon.V6.vpackeb" => "__builtin_HEXAGON_V6_vpackeb", - "llvm.hexagon.V6.vpackeb.128B" => "__builtin_HEXAGON_V6_vpackeb_128B", - "llvm.hexagon.V6.vpackeh" => "__builtin_HEXAGON_V6_vpackeh", - "llvm.hexagon.V6.vpackeh.128B" => "__builtin_HEXAGON_V6_vpackeh_128B", - "llvm.hexagon.V6.vpackhb.sat" => "__builtin_HEXAGON_V6_vpackhb_sat", - "llvm.hexagon.V6.vpackhb.sat.128B" => "__builtin_HEXAGON_V6_vpackhb_sat_128B", - "llvm.hexagon.V6.vpackhub.sat" => "__builtin_HEXAGON_V6_vpackhub_sat", - "llvm.hexagon.V6.vpackhub.sat.128B" => "__builtin_HEXAGON_V6_vpackhub_sat_128B", - "llvm.hexagon.V6.vpackob" => "__builtin_HEXAGON_V6_vpackob", - "llvm.hexagon.V6.vpackob.128B" => "__builtin_HEXAGON_V6_vpackob_128B", - "llvm.hexagon.V6.vpackoh" => "__builtin_HEXAGON_V6_vpackoh", - "llvm.hexagon.V6.vpackoh.128B" => "__builtin_HEXAGON_V6_vpackoh_128B", - "llvm.hexagon.V6.vpackwh.sat" => "__builtin_HEXAGON_V6_vpackwh_sat", - "llvm.hexagon.V6.vpackwh.sat.128B" => "__builtin_HEXAGON_V6_vpackwh_sat_128B", - "llvm.hexagon.V6.vpackwuh.sat" => "__builtin_HEXAGON_V6_vpackwuh_sat", - "llvm.hexagon.V6.vpackwuh.sat.128B" => "__builtin_HEXAGON_V6_vpackwuh_sat_128B", - "llvm.hexagon.V6.vpopcounth" => "__builtin_HEXAGON_V6_vpopcounth", - "llvm.hexagon.V6.vpopcounth.128B" => "__builtin_HEXAGON_V6_vpopcounth_128B", - "llvm.hexagon.V6.vprefixqb" => "__builtin_HEXAGON_V6_vprefixqb", - "llvm.hexagon.V6.vprefixqb.128B" => "__builtin_HEXAGON_V6_vprefixqb_128B", - "llvm.hexagon.V6.vprefixqh" => "__builtin_HEXAGON_V6_vprefixqh", - "llvm.hexagon.V6.vprefixqh.128B" => "__builtin_HEXAGON_V6_vprefixqh_128B", - "llvm.hexagon.V6.vprefixqw" => "__builtin_HEXAGON_V6_vprefixqw", - "llvm.hexagon.V6.vprefixqw.128B" => "__builtin_HEXAGON_V6_vprefixqw_128B", - "llvm.hexagon.V6.vrdelta" => "__builtin_HEXAGON_V6_vrdelta", - "llvm.hexagon.V6.vrdelta.128B" => "__builtin_HEXAGON_V6_vrdelta_128B", - "llvm.hexagon.V6.vrmpybub.rtt" => "__builtin_HEXAGON_V6_vrmpybub_rtt", - "llvm.hexagon.V6.vrmpybub.rtt.128B" => "__builtin_HEXAGON_V6_vrmpybub_rtt_128B", - "llvm.hexagon.V6.vrmpybub.rtt.acc" => "__builtin_HEXAGON_V6_vrmpybub_rtt_acc", - "llvm.hexagon.V6.vrmpybub.rtt.acc.128B" => "__builtin_HEXAGON_V6_vrmpybub_rtt_acc_128B", - "llvm.hexagon.V6.vrmpybus" => "__builtin_HEXAGON_V6_vrmpybus", - "llvm.hexagon.V6.vrmpybus.128B" => "__builtin_HEXAGON_V6_vrmpybus_128B", - "llvm.hexagon.V6.vrmpybus.acc" => "__builtin_HEXAGON_V6_vrmpybus_acc", - "llvm.hexagon.V6.vrmpybus.acc.128B" => "__builtin_HEXAGON_V6_vrmpybus_acc_128B", - "llvm.hexagon.V6.vrmpybusi" => "__builtin_HEXAGON_V6_vrmpybusi", - "llvm.hexagon.V6.vrmpybusi.128B" => "__builtin_HEXAGON_V6_vrmpybusi_128B", - "llvm.hexagon.V6.vrmpybusi.acc" => "__builtin_HEXAGON_V6_vrmpybusi_acc", - "llvm.hexagon.V6.vrmpybusi.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusi_acc_128B", - "llvm.hexagon.V6.vrmpybusv" => "__builtin_HEXAGON_V6_vrmpybusv", - "llvm.hexagon.V6.vrmpybusv.128B" => "__builtin_HEXAGON_V6_vrmpybusv_128B", - "llvm.hexagon.V6.vrmpybusv.acc" => "__builtin_HEXAGON_V6_vrmpybusv_acc", - "llvm.hexagon.V6.vrmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusv_acc_128B", - "llvm.hexagon.V6.vrmpybv" => "__builtin_HEXAGON_V6_vrmpybv", - "llvm.hexagon.V6.vrmpybv.128B" => "__builtin_HEXAGON_V6_vrmpybv_128B", - "llvm.hexagon.V6.vrmpybv.acc" => "__builtin_HEXAGON_V6_vrmpybv_acc", - "llvm.hexagon.V6.vrmpybv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybv_acc_128B", - "llvm.hexagon.V6.vrmpyub" => "__builtin_HEXAGON_V6_vrmpyub", - "llvm.hexagon.V6.vrmpyub.128B" => "__builtin_HEXAGON_V6_vrmpyub_128B", - "llvm.hexagon.V6.vrmpyub.acc" => "__builtin_HEXAGON_V6_vrmpyub_acc", - "llvm.hexagon.V6.vrmpyub.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_acc_128B", - "llvm.hexagon.V6.vrmpyub.rtt" => "__builtin_HEXAGON_V6_vrmpyub_rtt", - "llvm.hexagon.V6.vrmpyub.rtt.128B" => "__builtin_HEXAGON_V6_vrmpyub_rtt_128B", - "llvm.hexagon.V6.vrmpyub.rtt.acc" => "__builtin_HEXAGON_V6_vrmpyub_rtt_acc", - "llvm.hexagon.V6.vrmpyub.rtt.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B", - "llvm.hexagon.V6.vrmpyubi" => "__builtin_HEXAGON_V6_vrmpyubi", - "llvm.hexagon.V6.vrmpyubi.128B" => "__builtin_HEXAGON_V6_vrmpyubi_128B", - "llvm.hexagon.V6.vrmpyubi.acc" => "__builtin_HEXAGON_V6_vrmpyubi_acc", - "llvm.hexagon.V6.vrmpyubi.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubi_acc_128B", - "llvm.hexagon.V6.vrmpyubv" => "__builtin_HEXAGON_V6_vrmpyubv", - "llvm.hexagon.V6.vrmpyubv.128B" => "__builtin_HEXAGON_V6_vrmpyubv_128B", - "llvm.hexagon.V6.vrmpyubv.acc" => "__builtin_HEXAGON_V6_vrmpyubv_acc", - "llvm.hexagon.V6.vrmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubv_acc_128B", - "llvm.hexagon.V6.vror" => "__builtin_HEXAGON_V6_vror", - "llvm.hexagon.V6.vror.128B" => "__builtin_HEXAGON_V6_vror_128B", - "llvm.hexagon.V6.vrotr" => "__builtin_HEXAGON_V6_vrotr", - "llvm.hexagon.V6.vrotr.128B" => "__builtin_HEXAGON_V6_vrotr_128B", - "llvm.hexagon.V6.vroundhb" => "__builtin_HEXAGON_V6_vroundhb", - "llvm.hexagon.V6.vroundhb.128B" => "__builtin_HEXAGON_V6_vroundhb_128B", - "llvm.hexagon.V6.vroundhub" => "__builtin_HEXAGON_V6_vroundhub", - "llvm.hexagon.V6.vroundhub.128B" => "__builtin_HEXAGON_V6_vroundhub_128B", - "llvm.hexagon.V6.vrounduhub" => "__builtin_HEXAGON_V6_vrounduhub", - "llvm.hexagon.V6.vrounduhub.128B" => "__builtin_HEXAGON_V6_vrounduhub_128B", - "llvm.hexagon.V6.vrounduwuh" => "__builtin_HEXAGON_V6_vrounduwuh", - "llvm.hexagon.V6.vrounduwuh.128B" => "__builtin_HEXAGON_V6_vrounduwuh_128B", - "llvm.hexagon.V6.vroundwh" => "__builtin_HEXAGON_V6_vroundwh", - "llvm.hexagon.V6.vroundwh.128B" => "__builtin_HEXAGON_V6_vroundwh_128B", - "llvm.hexagon.V6.vroundwuh" => "__builtin_HEXAGON_V6_vroundwuh", - "llvm.hexagon.V6.vroundwuh.128B" => "__builtin_HEXAGON_V6_vroundwuh_128B", - "llvm.hexagon.V6.vrsadubi" => "__builtin_HEXAGON_V6_vrsadubi", - "llvm.hexagon.V6.vrsadubi.128B" => "__builtin_HEXAGON_V6_vrsadubi_128B", - "llvm.hexagon.V6.vrsadubi.acc" => "__builtin_HEXAGON_V6_vrsadubi_acc", - "llvm.hexagon.V6.vrsadubi.acc.128B" => "__builtin_HEXAGON_V6_vrsadubi_acc_128B", - "llvm.hexagon.V6.vsatdw" => "__builtin_HEXAGON_V6_vsatdw", - "llvm.hexagon.V6.vsatdw.128B" => "__builtin_HEXAGON_V6_vsatdw_128B", - "llvm.hexagon.V6.vsathub" => "__builtin_HEXAGON_V6_vsathub", - "llvm.hexagon.V6.vsathub.128B" => "__builtin_HEXAGON_V6_vsathub_128B", - "llvm.hexagon.V6.vsatuwuh" => "__builtin_HEXAGON_V6_vsatuwuh", - "llvm.hexagon.V6.vsatuwuh.128B" => "__builtin_HEXAGON_V6_vsatuwuh_128B", - "llvm.hexagon.V6.vsatwh" => "__builtin_HEXAGON_V6_vsatwh", - "llvm.hexagon.V6.vsatwh.128B" => "__builtin_HEXAGON_V6_vsatwh_128B", - "llvm.hexagon.V6.vsb" => "__builtin_HEXAGON_V6_vsb", - "llvm.hexagon.V6.vsb.128B" => "__builtin_HEXAGON_V6_vsb_128B", - "llvm.hexagon.V6.vscattermh" => "__builtin_HEXAGON_V6_vscattermh", - "llvm.hexagon.V6.vscattermh.128B" => "__builtin_HEXAGON_V6_vscattermh_128B", - "llvm.hexagon.V6.vscattermh.add" => "__builtin_HEXAGON_V6_vscattermh_add", - "llvm.hexagon.V6.vscattermh.add.128B" => "__builtin_HEXAGON_V6_vscattermh_add_128B", - "llvm.hexagon.V6.vscattermhq" => "__builtin_HEXAGON_V6_vscattermhq", - "llvm.hexagon.V6.vscattermhq.128B" => "__builtin_HEXAGON_V6_vscattermhq_128B", - "llvm.hexagon.V6.vscattermhw" => "__builtin_HEXAGON_V6_vscattermhw", - "llvm.hexagon.V6.vscattermhw.128B" => "__builtin_HEXAGON_V6_vscattermhw_128B", - "llvm.hexagon.V6.vscattermhw.add" => "__builtin_HEXAGON_V6_vscattermhw_add", - "llvm.hexagon.V6.vscattermhw.add.128B" => "__builtin_HEXAGON_V6_vscattermhw_add_128B", - "llvm.hexagon.V6.vscattermhwq" => "__builtin_HEXAGON_V6_vscattermhwq", - "llvm.hexagon.V6.vscattermhwq.128B" => "__builtin_HEXAGON_V6_vscattermhwq_128B", - "llvm.hexagon.V6.vscattermw" => "__builtin_HEXAGON_V6_vscattermw", - "llvm.hexagon.V6.vscattermw.128B" => "__builtin_HEXAGON_V6_vscattermw_128B", - "llvm.hexagon.V6.vscattermw.add" => "__builtin_HEXAGON_V6_vscattermw_add", - "llvm.hexagon.V6.vscattermw.add.128B" => "__builtin_HEXAGON_V6_vscattermw_add_128B", - "llvm.hexagon.V6.vscattermwq" => "__builtin_HEXAGON_V6_vscattermwq", - "llvm.hexagon.V6.vscattermwq.128B" => "__builtin_HEXAGON_V6_vscattermwq_128B", - "llvm.hexagon.V6.vsh" => "__builtin_HEXAGON_V6_vsh", - "llvm.hexagon.V6.vsh.128B" => "__builtin_HEXAGON_V6_vsh_128B", - "llvm.hexagon.V6.vshufeh" => "__builtin_HEXAGON_V6_vshufeh", - "llvm.hexagon.V6.vshufeh.128B" => "__builtin_HEXAGON_V6_vshufeh_128B", - "llvm.hexagon.V6.vshuffb" => "__builtin_HEXAGON_V6_vshuffb", - "llvm.hexagon.V6.vshuffb.128B" => "__builtin_HEXAGON_V6_vshuffb_128B", - "llvm.hexagon.V6.vshuffeb" => "__builtin_HEXAGON_V6_vshuffeb", - "llvm.hexagon.V6.vshuffeb.128B" => "__builtin_HEXAGON_V6_vshuffeb_128B", - "llvm.hexagon.V6.vshuffh" => "__builtin_HEXAGON_V6_vshuffh", - "llvm.hexagon.V6.vshuffh.128B" => "__builtin_HEXAGON_V6_vshuffh_128B", - "llvm.hexagon.V6.vshuffob" => "__builtin_HEXAGON_V6_vshuffob", - "llvm.hexagon.V6.vshuffob.128B" => "__builtin_HEXAGON_V6_vshuffob_128B", - "llvm.hexagon.V6.vshuffvdd" => "__builtin_HEXAGON_V6_vshuffvdd", - "llvm.hexagon.V6.vshuffvdd.128B" => "__builtin_HEXAGON_V6_vshuffvdd_128B", - "llvm.hexagon.V6.vshufoeb" => "__builtin_HEXAGON_V6_vshufoeb", - "llvm.hexagon.V6.vshufoeb.128B" => "__builtin_HEXAGON_V6_vshufoeb_128B", - "llvm.hexagon.V6.vshufoeh" => "__builtin_HEXAGON_V6_vshufoeh", - "llvm.hexagon.V6.vshufoeh.128B" => "__builtin_HEXAGON_V6_vshufoeh_128B", - "llvm.hexagon.V6.vshufoh" => "__builtin_HEXAGON_V6_vshufoh", - "llvm.hexagon.V6.vshufoh.128B" => "__builtin_HEXAGON_V6_vshufoh_128B", - "llvm.hexagon.V6.vsub.hf" => "__builtin_HEXAGON_V6_vsub_hf", - "llvm.hexagon.V6.vsub.hf.128B" => "__builtin_HEXAGON_V6_vsub_hf_128B", - "llvm.hexagon.V6.vsub.hf.f8" => "__builtin_HEXAGON_V6_vsub_hf_f8", - "llvm.hexagon.V6.vsub.hf.f8.128B" => "__builtin_HEXAGON_V6_vsub_hf_f8_128B", - "llvm.hexagon.V6.vsub.hf.hf" => "__builtin_HEXAGON_V6_vsub_hf_hf", - "llvm.hexagon.V6.vsub.hf.hf.128B" => "__builtin_HEXAGON_V6_vsub_hf_hf_128B", - "llvm.hexagon.V6.vsub.qf16" => "__builtin_HEXAGON_V6_vsub_qf16", - "llvm.hexagon.V6.vsub.qf16.128B" => "__builtin_HEXAGON_V6_vsub_qf16_128B", - "llvm.hexagon.V6.vsub.qf16.mix" => "__builtin_HEXAGON_V6_vsub_qf16_mix", - "llvm.hexagon.V6.vsub.qf16.mix.128B" => "__builtin_HEXAGON_V6_vsub_qf16_mix_128B", - "llvm.hexagon.V6.vsub.qf32" => "__builtin_HEXAGON_V6_vsub_qf32", - "llvm.hexagon.V6.vsub.qf32.128B" => "__builtin_HEXAGON_V6_vsub_qf32_128B", - "llvm.hexagon.V6.vsub.qf32.mix" => "__builtin_HEXAGON_V6_vsub_qf32_mix", - "llvm.hexagon.V6.vsub.qf32.mix.128B" => "__builtin_HEXAGON_V6_vsub_qf32_mix_128B", - "llvm.hexagon.V6.vsub.sf" => "__builtin_HEXAGON_V6_vsub_sf", - "llvm.hexagon.V6.vsub.sf.128B" => "__builtin_HEXAGON_V6_vsub_sf_128B", - "llvm.hexagon.V6.vsub.sf.bf" => "__builtin_HEXAGON_V6_vsub_sf_bf", - "llvm.hexagon.V6.vsub.sf.bf.128B" => "__builtin_HEXAGON_V6_vsub_sf_bf_128B", - "llvm.hexagon.V6.vsub.sf.hf" => "__builtin_HEXAGON_V6_vsub_sf_hf", - "llvm.hexagon.V6.vsub.sf.hf.128B" => "__builtin_HEXAGON_V6_vsub_sf_hf_128B", - "llvm.hexagon.V6.vsub.sf.sf" => "__builtin_HEXAGON_V6_vsub_sf_sf", - "llvm.hexagon.V6.vsub.sf.sf.128B" => "__builtin_HEXAGON_V6_vsub_sf_sf_128B", - "llvm.hexagon.V6.vsubb" => "__builtin_HEXAGON_V6_vsubb", - "llvm.hexagon.V6.vsubb.128B" => "__builtin_HEXAGON_V6_vsubb_128B", - "llvm.hexagon.V6.vsubb.dv" => "__builtin_HEXAGON_V6_vsubb_dv", - "llvm.hexagon.V6.vsubb.dv.128B" => "__builtin_HEXAGON_V6_vsubb_dv_128B", - "llvm.hexagon.V6.vsubbnq" => "__builtin_HEXAGON_V6_vsubbnq", - "llvm.hexagon.V6.vsubbnq.128B" => "__builtin_HEXAGON_V6_vsubbnq_128B", - "llvm.hexagon.V6.vsubbq" => "__builtin_HEXAGON_V6_vsubbq", - "llvm.hexagon.V6.vsubbq.128B" => "__builtin_HEXAGON_V6_vsubbq_128B", - "llvm.hexagon.V6.vsubbsat" => "__builtin_HEXAGON_V6_vsubbsat", - "llvm.hexagon.V6.vsubbsat.128B" => "__builtin_HEXAGON_V6_vsubbsat_128B", - "llvm.hexagon.V6.vsubbsat.dv" => "__builtin_HEXAGON_V6_vsubbsat_dv", - "llvm.hexagon.V6.vsubbsat.dv.128B" => "__builtin_HEXAGON_V6_vsubbsat_dv_128B", - "llvm.hexagon.V6.vsubh" => "__builtin_HEXAGON_V6_vsubh", - "llvm.hexagon.V6.vsubh.128B" => "__builtin_HEXAGON_V6_vsubh_128B", - "llvm.hexagon.V6.vsubh.dv" => "__builtin_HEXAGON_V6_vsubh_dv", - "llvm.hexagon.V6.vsubh.dv.128B" => "__builtin_HEXAGON_V6_vsubh_dv_128B", - "llvm.hexagon.V6.vsubhnq" => "__builtin_HEXAGON_V6_vsubhnq", - "llvm.hexagon.V6.vsubhnq.128B" => "__builtin_HEXAGON_V6_vsubhnq_128B", - "llvm.hexagon.V6.vsubhq" => "__builtin_HEXAGON_V6_vsubhq", - "llvm.hexagon.V6.vsubhq.128B" => "__builtin_HEXAGON_V6_vsubhq_128B", - "llvm.hexagon.V6.vsubhsat" => "__builtin_HEXAGON_V6_vsubhsat", - "llvm.hexagon.V6.vsubhsat.128B" => "__builtin_HEXAGON_V6_vsubhsat_128B", - "llvm.hexagon.V6.vsubhsat.dv" => "__builtin_HEXAGON_V6_vsubhsat_dv", - "llvm.hexagon.V6.vsubhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubhsat_dv_128B", - "llvm.hexagon.V6.vsubhw" => "__builtin_HEXAGON_V6_vsubhw", - "llvm.hexagon.V6.vsubhw.128B" => "__builtin_HEXAGON_V6_vsubhw_128B", - "llvm.hexagon.V6.vsububh" => "__builtin_HEXAGON_V6_vsububh", - "llvm.hexagon.V6.vsububh.128B" => "__builtin_HEXAGON_V6_vsububh_128B", - "llvm.hexagon.V6.vsububsat" => "__builtin_HEXAGON_V6_vsububsat", - "llvm.hexagon.V6.vsububsat.128B" => "__builtin_HEXAGON_V6_vsububsat_128B", - "llvm.hexagon.V6.vsububsat.dv" => "__builtin_HEXAGON_V6_vsububsat_dv", - "llvm.hexagon.V6.vsububsat.dv.128B" => "__builtin_HEXAGON_V6_vsububsat_dv_128B", - "llvm.hexagon.V6.vsubububb.sat" => "__builtin_HEXAGON_V6_vsubububb_sat", - "llvm.hexagon.V6.vsubububb.sat.128B" => "__builtin_HEXAGON_V6_vsubububb_sat_128B", - "llvm.hexagon.V6.vsubuhsat" => "__builtin_HEXAGON_V6_vsubuhsat", - "llvm.hexagon.V6.vsubuhsat.128B" => "__builtin_HEXAGON_V6_vsubuhsat_128B", - "llvm.hexagon.V6.vsubuhsat.dv" => "__builtin_HEXAGON_V6_vsubuhsat_dv", - "llvm.hexagon.V6.vsubuhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuhsat_dv_128B", - "llvm.hexagon.V6.vsubuhw" => "__builtin_HEXAGON_V6_vsubuhw", - "llvm.hexagon.V6.vsubuhw.128B" => "__builtin_HEXAGON_V6_vsubuhw_128B", - "llvm.hexagon.V6.vsubuwsat" => "__builtin_HEXAGON_V6_vsubuwsat", - "llvm.hexagon.V6.vsubuwsat.128B" => "__builtin_HEXAGON_V6_vsubuwsat_128B", - "llvm.hexagon.V6.vsubuwsat.dv" => "__builtin_HEXAGON_V6_vsubuwsat_dv", - "llvm.hexagon.V6.vsubuwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuwsat_dv_128B", - "llvm.hexagon.V6.vsubw" => "__builtin_HEXAGON_V6_vsubw", - "llvm.hexagon.V6.vsubw.128B" => "__builtin_HEXAGON_V6_vsubw_128B", - "llvm.hexagon.V6.vsubw.dv" => "__builtin_HEXAGON_V6_vsubw_dv", - "llvm.hexagon.V6.vsubw.dv.128B" => "__builtin_HEXAGON_V6_vsubw_dv_128B", - "llvm.hexagon.V6.vsubwnq" => "__builtin_HEXAGON_V6_vsubwnq", - "llvm.hexagon.V6.vsubwnq.128B" => "__builtin_HEXAGON_V6_vsubwnq_128B", - "llvm.hexagon.V6.vsubwq" => "__builtin_HEXAGON_V6_vsubwq", - "llvm.hexagon.V6.vsubwq.128B" => "__builtin_HEXAGON_V6_vsubwq_128B", - "llvm.hexagon.V6.vsubwsat" => "__builtin_HEXAGON_V6_vsubwsat", - "llvm.hexagon.V6.vsubwsat.128B" => "__builtin_HEXAGON_V6_vsubwsat_128B", - "llvm.hexagon.V6.vsubwsat.dv" => "__builtin_HEXAGON_V6_vsubwsat_dv", - "llvm.hexagon.V6.vsubwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubwsat_dv_128B", - "llvm.hexagon.V6.vswap" => "__builtin_HEXAGON_V6_vswap", - "llvm.hexagon.V6.vswap.128B" => "__builtin_HEXAGON_V6_vswap_128B", - "llvm.hexagon.V6.vtmpyb" => "__builtin_HEXAGON_V6_vtmpyb", - "llvm.hexagon.V6.vtmpyb.128B" => "__builtin_HEXAGON_V6_vtmpyb_128B", - "llvm.hexagon.V6.vtmpyb.acc" => "__builtin_HEXAGON_V6_vtmpyb_acc", - "llvm.hexagon.V6.vtmpyb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyb_acc_128B", - "llvm.hexagon.V6.vtmpybus" => "__builtin_HEXAGON_V6_vtmpybus", - "llvm.hexagon.V6.vtmpybus.128B" => "__builtin_HEXAGON_V6_vtmpybus_128B", - "llvm.hexagon.V6.vtmpybus.acc" => "__builtin_HEXAGON_V6_vtmpybus_acc", - "llvm.hexagon.V6.vtmpybus.acc.128B" => "__builtin_HEXAGON_V6_vtmpybus_acc_128B", - "llvm.hexagon.V6.vtmpyhb" => "__builtin_HEXAGON_V6_vtmpyhb", - "llvm.hexagon.V6.vtmpyhb.128B" => "__builtin_HEXAGON_V6_vtmpyhb_128B", - "llvm.hexagon.V6.vtmpyhb.acc" => "__builtin_HEXAGON_V6_vtmpyhb_acc", - "llvm.hexagon.V6.vtmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyhb_acc_128B", - "llvm.hexagon.V6.vunpackb" => "__builtin_HEXAGON_V6_vunpackb", - "llvm.hexagon.V6.vunpackb.128B" => "__builtin_HEXAGON_V6_vunpackb_128B", - "llvm.hexagon.V6.vunpackh" => "__builtin_HEXAGON_V6_vunpackh", - "llvm.hexagon.V6.vunpackh.128B" => "__builtin_HEXAGON_V6_vunpackh_128B", - "llvm.hexagon.V6.vunpackob" => "__builtin_HEXAGON_V6_vunpackob", - "llvm.hexagon.V6.vunpackob.128B" => "__builtin_HEXAGON_V6_vunpackob_128B", - "llvm.hexagon.V6.vunpackoh" => "__builtin_HEXAGON_V6_vunpackoh", - "llvm.hexagon.V6.vunpackoh.128B" => "__builtin_HEXAGON_V6_vunpackoh_128B", - "llvm.hexagon.V6.vunpackub" => "__builtin_HEXAGON_V6_vunpackub", - "llvm.hexagon.V6.vunpackub.128B" => "__builtin_HEXAGON_V6_vunpackub_128B", - "llvm.hexagon.V6.vunpackuh" => "__builtin_HEXAGON_V6_vunpackuh", - "llvm.hexagon.V6.vunpackuh.128B" => "__builtin_HEXAGON_V6_vunpackuh_128B", - "llvm.hexagon.V6.vxor" => "__builtin_HEXAGON_V6_vxor", - "llvm.hexagon.V6.vxor.128B" => "__builtin_HEXAGON_V6_vxor_128B", - "llvm.hexagon.V6.vzb" => "__builtin_HEXAGON_V6_vzb", - "llvm.hexagon.V6.vzb.128B" => "__builtin_HEXAGON_V6_vzb_128B", - "llvm.hexagon.V6.vzh" => "__builtin_HEXAGON_V6_vzh", - "llvm.hexagon.V6.vzh.128B" => "__builtin_HEXAGON_V6_vzh_128B", - "llvm.hexagon.Y2.dccleana" => "__builtin_HEXAGON_Y2_dccleana", - "llvm.hexagon.Y2.dccleaninva" => "__builtin_HEXAGON_Y2_dccleaninva", - "llvm.hexagon.Y2.dcfetch" => "__builtin_HEXAGON_Y2_dcfetch", - "llvm.hexagon.Y2.dcinva" => "__builtin_HEXAGON_Y2_dcinva", - "llvm.hexagon.Y2.dczeroa" => "__builtin_HEXAGON_Y2_dczeroa", - "llvm.hexagon.Y4.l2fetch" => "__builtin_HEXAGON_Y4_l2fetch", - "llvm.hexagon.Y5.l2fetch" => "__builtin_HEXAGON_Y5_l2fetch", - "llvm.hexagon.Y6.dmlink" => "__builtin_HEXAGON_Y6_dmlink", - "llvm.hexagon.Y6.dmpause" => "__builtin_HEXAGON_Y6_dmpause", - "llvm.hexagon.Y6.dmpoll" => "__builtin_HEXAGON_Y6_dmpoll", - "llvm.hexagon.Y6.dmresume" => "__builtin_HEXAGON_Y6_dmresume", - "llvm.hexagon.Y6.dmstart" => "__builtin_HEXAGON_Y6_dmstart", - "llvm.hexagon.Y6.dmwait" => "__builtin_HEXAGON_Y6_dmwait", - "llvm.hexagon.brev.ldb" => "__builtin_brev_ldb", - "llvm.hexagon.brev.ldd" => "__builtin_brev_ldd", - "llvm.hexagon.brev.ldh" => "__builtin_brev_ldh", - "llvm.hexagon.brev.ldub" => "__builtin_brev_ldub", - "llvm.hexagon.brev.lduh" => "__builtin_brev_lduh", - "llvm.hexagon.brev.ldw" => "__builtin_brev_ldw", - "llvm.hexagon.brev.stb" => "__builtin_brev_stb", - "llvm.hexagon.brev.std" => "__builtin_brev_std", - "llvm.hexagon.brev.sth" => "__builtin_brev_sth", - "llvm.hexagon.brev.sthhi" => "__builtin_brev_sthhi", - "llvm.hexagon.brev.stw" => "__builtin_brev_stw", - "llvm.hexagon.circ.ldb" => "__builtin_circ_ldb", - "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", - "llvm.hexagon.circ.ldh" => "__builtin_circ_ldh", - "llvm.hexagon.circ.ldub" => "__builtin_circ_ldub", - "llvm.hexagon.circ.lduh" => "__builtin_circ_lduh", - "llvm.hexagon.circ.ldw" => "__builtin_circ_ldw", - "llvm.hexagon.circ.stb" => "__builtin_circ_stb", - "llvm.hexagon.circ.std" => "__builtin_circ_std", - "llvm.hexagon.circ.sth" => "__builtin_circ_sth", - "llvm.hexagon.circ.sthhi" => "__builtin_circ_sthhi", - "llvm.hexagon.circ.stw" => "__builtin_circ_stw", - "llvm.hexagon.mm256i.vaddw" => "__builtin__mm256i_vaddw", - "llvm.hexagon.prefetch" => "__builtin_HEXAGON_prefetch", - "llvm.hexagon.vmemcpy" => "__builtin_hexagon_vmemcpy", - "llvm.hexagon.vmemset" => "__builtin_hexagon_vmemset", - // loongarch - "llvm.loongarch.asrtgt.d" => "__builtin_loongarch_asrtgt_d", - "llvm.loongarch.asrtle.d" => "__builtin_loongarch_asrtle_d", - "llvm.loongarch.break" => "__builtin_loongarch_break", - "llvm.loongarch.cacop.d" => "__builtin_loongarch_cacop_d", - "llvm.loongarch.cacop.w" => "__builtin_loongarch_cacop_w", - "llvm.loongarch.cpucfg" => "__builtin_loongarch_cpucfg", - "llvm.loongarch.crc.w.b.w" => "__builtin_loongarch_crc_w_b_w", - "llvm.loongarch.crc.w.d.w" => "__builtin_loongarch_crc_w_d_w", - "llvm.loongarch.crc.w.h.w" => "__builtin_loongarch_crc_w_h_w", - "llvm.loongarch.crc.w.w.w" => "__builtin_loongarch_crc_w_w_w", - "llvm.loongarch.crcc.w.b.w" => "__builtin_loongarch_crcc_w_b_w", - "llvm.loongarch.crcc.w.d.w" => "__builtin_loongarch_crcc_w_d_w", - "llvm.loongarch.crcc.w.h.w" => "__builtin_loongarch_crcc_w_h_w", - "llvm.loongarch.crcc.w.w.w" => "__builtin_loongarch_crcc_w_w_w", - "llvm.loongarch.csrrd.d" => "__builtin_loongarch_csrrd_d", - "llvm.loongarch.csrrd.w" => "__builtin_loongarch_csrrd_w", - "llvm.loongarch.csrwr.d" => "__builtin_loongarch_csrwr_d", - "llvm.loongarch.csrwr.w" => "__builtin_loongarch_csrwr_w", - "llvm.loongarch.csrxchg.d" => "__builtin_loongarch_csrxchg_d", - "llvm.loongarch.csrxchg.w" => "__builtin_loongarch_csrxchg_w", - "llvm.loongarch.dbar" => "__builtin_loongarch_dbar", - "llvm.loongarch.frecipe.d" => "__builtin_loongarch_frecipe_d", - "llvm.loongarch.frecipe.s" => "__builtin_loongarch_frecipe_s", - "llvm.loongarch.frsqrte.d" => "__builtin_loongarch_frsqrte_d", - "llvm.loongarch.frsqrte.s" => "__builtin_loongarch_frsqrte_s", - "llvm.loongarch.ibar" => "__builtin_loongarch_ibar", - "llvm.loongarch.iocsrrd.b" => "__builtin_loongarch_iocsrrd_b", - "llvm.loongarch.iocsrrd.d" => "__builtin_loongarch_iocsrrd_d", - "llvm.loongarch.iocsrrd.h" => "__builtin_loongarch_iocsrrd_h", - "llvm.loongarch.iocsrrd.w" => "__builtin_loongarch_iocsrrd_w", - "llvm.loongarch.iocsrwr.b" => "__builtin_loongarch_iocsrwr_b", - "llvm.loongarch.iocsrwr.d" => "__builtin_loongarch_iocsrwr_d", - "llvm.loongarch.iocsrwr.h" => "__builtin_loongarch_iocsrwr_h", - "llvm.loongarch.iocsrwr.w" => "__builtin_loongarch_iocsrwr_w", - "llvm.loongarch.lasx.vext2xv.d.b" => "__builtin_lasx_vext2xv_d_b", - "llvm.loongarch.lasx.vext2xv.d.h" => "__builtin_lasx_vext2xv_d_h", - "llvm.loongarch.lasx.vext2xv.d.w" => "__builtin_lasx_vext2xv_d_w", - "llvm.loongarch.lasx.vext2xv.du.bu" => "__builtin_lasx_vext2xv_du_bu", - "llvm.loongarch.lasx.vext2xv.du.hu" => "__builtin_lasx_vext2xv_du_hu", - "llvm.loongarch.lasx.vext2xv.du.wu" => "__builtin_lasx_vext2xv_du_wu", - "llvm.loongarch.lasx.vext2xv.h.b" => "__builtin_lasx_vext2xv_h_b", - "llvm.loongarch.lasx.vext2xv.hu.bu" => "__builtin_lasx_vext2xv_hu_bu", - "llvm.loongarch.lasx.vext2xv.w.b" => "__builtin_lasx_vext2xv_w_b", - "llvm.loongarch.lasx.vext2xv.w.h" => "__builtin_lasx_vext2xv_w_h", - "llvm.loongarch.lasx.vext2xv.wu.bu" => "__builtin_lasx_vext2xv_wu_bu", - "llvm.loongarch.lasx.vext2xv.wu.hu" => "__builtin_lasx_vext2xv_wu_hu", - "llvm.loongarch.lasx.xbnz.b" => "__builtin_lasx_xbnz_b", - "llvm.loongarch.lasx.xbnz.d" => "__builtin_lasx_xbnz_d", - "llvm.loongarch.lasx.xbnz.h" => "__builtin_lasx_xbnz_h", - "llvm.loongarch.lasx.xbnz.v" => "__builtin_lasx_xbnz_v", - "llvm.loongarch.lasx.xbnz.w" => "__builtin_lasx_xbnz_w", - "llvm.loongarch.lasx.xbz.b" => "__builtin_lasx_xbz_b", - "llvm.loongarch.lasx.xbz.d" => "__builtin_lasx_xbz_d", - "llvm.loongarch.lasx.xbz.h" => "__builtin_lasx_xbz_h", - "llvm.loongarch.lasx.xbz.v" => "__builtin_lasx_xbz_v", - "llvm.loongarch.lasx.xbz.w" => "__builtin_lasx_xbz_w", - "llvm.loongarch.lasx.xvabsd.b" => "__builtin_lasx_xvabsd_b", - "llvm.loongarch.lasx.xvabsd.bu" => "__builtin_lasx_xvabsd_bu", - "llvm.loongarch.lasx.xvabsd.d" => "__builtin_lasx_xvabsd_d", - "llvm.loongarch.lasx.xvabsd.du" => "__builtin_lasx_xvabsd_du", - "llvm.loongarch.lasx.xvabsd.h" => "__builtin_lasx_xvabsd_h", - "llvm.loongarch.lasx.xvabsd.hu" => "__builtin_lasx_xvabsd_hu", - "llvm.loongarch.lasx.xvabsd.w" => "__builtin_lasx_xvabsd_w", - "llvm.loongarch.lasx.xvabsd.wu" => "__builtin_lasx_xvabsd_wu", - "llvm.loongarch.lasx.xvadd.b" => "__builtin_lasx_xvadd_b", - "llvm.loongarch.lasx.xvadd.d" => "__builtin_lasx_xvadd_d", - "llvm.loongarch.lasx.xvadd.h" => "__builtin_lasx_xvadd_h", - "llvm.loongarch.lasx.xvadd.q" => "__builtin_lasx_xvadd_q", - "llvm.loongarch.lasx.xvadd.w" => "__builtin_lasx_xvadd_w", - "llvm.loongarch.lasx.xvadda.b" => "__builtin_lasx_xvadda_b", - "llvm.loongarch.lasx.xvadda.d" => "__builtin_lasx_xvadda_d", - "llvm.loongarch.lasx.xvadda.h" => "__builtin_lasx_xvadda_h", - "llvm.loongarch.lasx.xvadda.w" => "__builtin_lasx_xvadda_w", - "llvm.loongarch.lasx.xvaddi.bu" => "__builtin_lasx_xvaddi_bu", - "llvm.loongarch.lasx.xvaddi.du" => "__builtin_lasx_xvaddi_du", - "llvm.loongarch.lasx.xvaddi.hu" => "__builtin_lasx_xvaddi_hu", - "llvm.loongarch.lasx.xvaddi.wu" => "__builtin_lasx_xvaddi_wu", - "llvm.loongarch.lasx.xvaddwev.d.w" => "__builtin_lasx_xvaddwev_d_w", - "llvm.loongarch.lasx.xvaddwev.d.wu" => "__builtin_lasx_xvaddwev_d_wu", - "llvm.loongarch.lasx.xvaddwev.d.wu.w" => "__builtin_lasx_xvaddwev_d_wu_w", - "llvm.loongarch.lasx.xvaddwev.h.b" => "__builtin_lasx_xvaddwev_h_b", - "llvm.loongarch.lasx.xvaddwev.h.bu" => "__builtin_lasx_xvaddwev_h_bu", - "llvm.loongarch.lasx.xvaddwev.h.bu.b" => "__builtin_lasx_xvaddwev_h_bu_b", - "llvm.loongarch.lasx.xvaddwev.q.d" => "__builtin_lasx_xvaddwev_q_d", - "llvm.loongarch.lasx.xvaddwev.q.du" => "__builtin_lasx_xvaddwev_q_du", - "llvm.loongarch.lasx.xvaddwev.q.du.d" => "__builtin_lasx_xvaddwev_q_du_d", - "llvm.loongarch.lasx.xvaddwev.w.h" => "__builtin_lasx_xvaddwev_w_h", - "llvm.loongarch.lasx.xvaddwev.w.hu" => "__builtin_lasx_xvaddwev_w_hu", - "llvm.loongarch.lasx.xvaddwev.w.hu.h" => "__builtin_lasx_xvaddwev_w_hu_h", - "llvm.loongarch.lasx.xvaddwod.d.w" => "__builtin_lasx_xvaddwod_d_w", - "llvm.loongarch.lasx.xvaddwod.d.wu" => "__builtin_lasx_xvaddwod_d_wu", - "llvm.loongarch.lasx.xvaddwod.d.wu.w" => "__builtin_lasx_xvaddwod_d_wu_w", - "llvm.loongarch.lasx.xvaddwod.h.b" => "__builtin_lasx_xvaddwod_h_b", - "llvm.loongarch.lasx.xvaddwod.h.bu" => "__builtin_lasx_xvaddwod_h_bu", - "llvm.loongarch.lasx.xvaddwod.h.bu.b" => "__builtin_lasx_xvaddwod_h_bu_b", - "llvm.loongarch.lasx.xvaddwod.q.d" => "__builtin_lasx_xvaddwod_q_d", - "llvm.loongarch.lasx.xvaddwod.q.du" => "__builtin_lasx_xvaddwod_q_du", - "llvm.loongarch.lasx.xvaddwod.q.du.d" => "__builtin_lasx_xvaddwod_q_du_d", - "llvm.loongarch.lasx.xvaddwod.w.h" => "__builtin_lasx_xvaddwod_w_h", - "llvm.loongarch.lasx.xvaddwod.w.hu" => "__builtin_lasx_xvaddwod_w_hu", - "llvm.loongarch.lasx.xvaddwod.w.hu.h" => "__builtin_lasx_xvaddwod_w_hu_h", - "llvm.loongarch.lasx.xvand.v" => "__builtin_lasx_xvand_v", - "llvm.loongarch.lasx.xvandi.b" => "__builtin_lasx_xvandi_b", - "llvm.loongarch.lasx.xvandn.v" => "__builtin_lasx_xvandn_v", - "llvm.loongarch.lasx.xvavg.b" => "__builtin_lasx_xvavg_b", - "llvm.loongarch.lasx.xvavg.bu" => "__builtin_lasx_xvavg_bu", - "llvm.loongarch.lasx.xvavg.d" => "__builtin_lasx_xvavg_d", - "llvm.loongarch.lasx.xvavg.du" => "__builtin_lasx_xvavg_du", - "llvm.loongarch.lasx.xvavg.h" => "__builtin_lasx_xvavg_h", - "llvm.loongarch.lasx.xvavg.hu" => "__builtin_lasx_xvavg_hu", - "llvm.loongarch.lasx.xvavg.w" => "__builtin_lasx_xvavg_w", - "llvm.loongarch.lasx.xvavg.wu" => "__builtin_lasx_xvavg_wu", - "llvm.loongarch.lasx.xvavgr.b" => "__builtin_lasx_xvavgr_b", - "llvm.loongarch.lasx.xvavgr.bu" => "__builtin_lasx_xvavgr_bu", - "llvm.loongarch.lasx.xvavgr.d" => "__builtin_lasx_xvavgr_d", - "llvm.loongarch.lasx.xvavgr.du" => "__builtin_lasx_xvavgr_du", - "llvm.loongarch.lasx.xvavgr.h" => "__builtin_lasx_xvavgr_h", - "llvm.loongarch.lasx.xvavgr.hu" => "__builtin_lasx_xvavgr_hu", - "llvm.loongarch.lasx.xvavgr.w" => "__builtin_lasx_xvavgr_w", - "llvm.loongarch.lasx.xvavgr.wu" => "__builtin_lasx_xvavgr_wu", - "llvm.loongarch.lasx.xvbitclr.b" => "__builtin_lasx_xvbitclr_b", - "llvm.loongarch.lasx.xvbitclr.d" => "__builtin_lasx_xvbitclr_d", - "llvm.loongarch.lasx.xvbitclr.h" => "__builtin_lasx_xvbitclr_h", - "llvm.loongarch.lasx.xvbitclr.w" => "__builtin_lasx_xvbitclr_w", - "llvm.loongarch.lasx.xvbitclri.b" => "__builtin_lasx_xvbitclri_b", - "llvm.loongarch.lasx.xvbitclri.d" => "__builtin_lasx_xvbitclri_d", - "llvm.loongarch.lasx.xvbitclri.h" => "__builtin_lasx_xvbitclri_h", - "llvm.loongarch.lasx.xvbitclri.w" => "__builtin_lasx_xvbitclri_w", - "llvm.loongarch.lasx.xvbitrev.b" => "__builtin_lasx_xvbitrev_b", - "llvm.loongarch.lasx.xvbitrev.d" => "__builtin_lasx_xvbitrev_d", - "llvm.loongarch.lasx.xvbitrev.h" => "__builtin_lasx_xvbitrev_h", - "llvm.loongarch.lasx.xvbitrev.w" => "__builtin_lasx_xvbitrev_w", - "llvm.loongarch.lasx.xvbitrevi.b" => "__builtin_lasx_xvbitrevi_b", - "llvm.loongarch.lasx.xvbitrevi.d" => "__builtin_lasx_xvbitrevi_d", - "llvm.loongarch.lasx.xvbitrevi.h" => "__builtin_lasx_xvbitrevi_h", - "llvm.loongarch.lasx.xvbitrevi.w" => "__builtin_lasx_xvbitrevi_w", - "llvm.loongarch.lasx.xvbitsel.v" => "__builtin_lasx_xvbitsel_v", - "llvm.loongarch.lasx.xvbitseli.b" => "__builtin_lasx_xvbitseli_b", - "llvm.loongarch.lasx.xvbitset.b" => "__builtin_lasx_xvbitset_b", - "llvm.loongarch.lasx.xvbitset.d" => "__builtin_lasx_xvbitset_d", - "llvm.loongarch.lasx.xvbitset.h" => "__builtin_lasx_xvbitset_h", - "llvm.loongarch.lasx.xvbitset.w" => "__builtin_lasx_xvbitset_w", - "llvm.loongarch.lasx.xvbitseti.b" => "__builtin_lasx_xvbitseti_b", - "llvm.loongarch.lasx.xvbitseti.d" => "__builtin_lasx_xvbitseti_d", - "llvm.loongarch.lasx.xvbitseti.h" => "__builtin_lasx_xvbitseti_h", - "llvm.loongarch.lasx.xvbitseti.w" => "__builtin_lasx_xvbitseti_w", - "llvm.loongarch.lasx.xvbsll.v" => "__builtin_lasx_xvbsll_v", - "llvm.loongarch.lasx.xvbsrl.v" => "__builtin_lasx_xvbsrl_v", - "llvm.loongarch.lasx.xvclo.b" => "__builtin_lasx_xvclo_b", - "llvm.loongarch.lasx.xvclo.d" => "__builtin_lasx_xvclo_d", - "llvm.loongarch.lasx.xvclo.h" => "__builtin_lasx_xvclo_h", - "llvm.loongarch.lasx.xvclo.w" => "__builtin_lasx_xvclo_w", - "llvm.loongarch.lasx.xvclz.b" => "__builtin_lasx_xvclz_b", - "llvm.loongarch.lasx.xvclz.d" => "__builtin_lasx_xvclz_d", - "llvm.loongarch.lasx.xvclz.h" => "__builtin_lasx_xvclz_h", - "llvm.loongarch.lasx.xvclz.w" => "__builtin_lasx_xvclz_w", - "llvm.loongarch.lasx.xvdiv.b" => "__builtin_lasx_xvdiv_b", - "llvm.loongarch.lasx.xvdiv.bu" => "__builtin_lasx_xvdiv_bu", - "llvm.loongarch.lasx.xvdiv.d" => "__builtin_lasx_xvdiv_d", - "llvm.loongarch.lasx.xvdiv.du" => "__builtin_lasx_xvdiv_du", - "llvm.loongarch.lasx.xvdiv.h" => "__builtin_lasx_xvdiv_h", - "llvm.loongarch.lasx.xvdiv.hu" => "__builtin_lasx_xvdiv_hu", - "llvm.loongarch.lasx.xvdiv.w" => "__builtin_lasx_xvdiv_w", - "llvm.loongarch.lasx.xvdiv.wu" => "__builtin_lasx_xvdiv_wu", - "llvm.loongarch.lasx.xvexth.d.w" => "__builtin_lasx_xvexth_d_w", - "llvm.loongarch.lasx.xvexth.du.wu" => "__builtin_lasx_xvexth_du_wu", - "llvm.loongarch.lasx.xvexth.h.b" => "__builtin_lasx_xvexth_h_b", - "llvm.loongarch.lasx.xvexth.hu.bu" => "__builtin_lasx_xvexth_hu_bu", - "llvm.loongarch.lasx.xvexth.q.d" => "__builtin_lasx_xvexth_q_d", - "llvm.loongarch.lasx.xvexth.qu.du" => "__builtin_lasx_xvexth_qu_du", - "llvm.loongarch.lasx.xvexth.w.h" => "__builtin_lasx_xvexth_w_h", - "llvm.loongarch.lasx.xvexth.wu.hu" => "__builtin_lasx_xvexth_wu_hu", - "llvm.loongarch.lasx.xvextl.q.d" => "__builtin_lasx_xvextl_q_d", - "llvm.loongarch.lasx.xvextl.qu.du" => "__builtin_lasx_xvextl_qu_du", - "llvm.loongarch.lasx.xvextrins.b" => "__builtin_lasx_xvextrins_b", - "llvm.loongarch.lasx.xvextrins.d" => "__builtin_lasx_xvextrins_d", - "llvm.loongarch.lasx.xvextrins.h" => "__builtin_lasx_xvextrins_h", - "llvm.loongarch.lasx.xvextrins.w" => "__builtin_lasx_xvextrins_w", - "llvm.loongarch.lasx.xvfadd.d" => "__builtin_lasx_xvfadd_d", - "llvm.loongarch.lasx.xvfadd.s" => "__builtin_lasx_xvfadd_s", - "llvm.loongarch.lasx.xvfclass.d" => "__builtin_lasx_xvfclass_d", - "llvm.loongarch.lasx.xvfclass.s" => "__builtin_lasx_xvfclass_s", - "llvm.loongarch.lasx.xvfcmp.caf.d" => "__builtin_lasx_xvfcmp_caf_d", - "llvm.loongarch.lasx.xvfcmp.caf.s" => "__builtin_lasx_xvfcmp_caf_s", - "llvm.loongarch.lasx.xvfcmp.ceq.d" => "__builtin_lasx_xvfcmp_ceq_d", - "llvm.loongarch.lasx.xvfcmp.ceq.s" => "__builtin_lasx_xvfcmp_ceq_s", - "llvm.loongarch.lasx.xvfcmp.cle.d" => "__builtin_lasx_xvfcmp_cle_d", - "llvm.loongarch.lasx.xvfcmp.cle.s" => "__builtin_lasx_xvfcmp_cle_s", - "llvm.loongarch.lasx.xvfcmp.clt.d" => "__builtin_lasx_xvfcmp_clt_d", - "llvm.loongarch.lasx.xvfcmp.clt.s" => "__builtin_lasx_xvfcmp_clt_s", - "llvm.loongarch.lasx.xvfcmp.cne.d" => "__builtin_lasx_xvfcmp_cne_d", - "llvm.loongarch.lasx.xvfcmp.cne.s" => "__builtin_lasx_xvfcmp_cne_s", - "llvm.loongarch.lasx.xvfcmp.cor.d" => "__builtin_lasx_xvfcmp_cor_d", - "llvm.loongarch.lasx.xvfcmp.cor.s" => "__builtin_lasx_xvfcmp_cor_s", - "llvm.loongarch.lasx.xvfcmp.cueq.d" => "__builtin_lasx_xvfcmp_cueq_d", - "llvm.loongarch.lasx.xvfcmp.cueq.s" => "__builtin_lasx_xvfcmp_cueq_s", - "llvm.loongarch.lasx.xvfcmp.cule.d" => "__builtin_lasx_xvfcmp_cule_d", - "llvm.loongarch.lasx.xvfcmp.cule.s" => "__builtin_lasx_xvfcmp_cule_s", - "llvm.loongarch.lasx.xvfcmp.cult.d" => "__builtin_lasx_xvfcmp_cult_d", - "llvm.loongarch.lasx.xvfcmp.cult.s" => "__builtin_lasx_xvfcmp_cult_s", - "llvm.loongarch.lasx.xvfcmp.cun.d" => "__builtin_lasx_xvfcmp_cun_d", - "llvm.loongarch.lasx.xvfcmp.cun.s" => "__builtin_lasx_xvfcmp_cun_s", - "llvm.loongarch.lasx.xvfcmp.cune.d" => "__builtin_lasx_xvfcmp_cune_d", - "llvm.loongarch.lasx.xvfcmp.cune.s" => "__builtin_lasx_xvfcmp_cune_s", - "llvm.loongarch.lasx.xvfcmp.saf.d" => "__builtin_lasx_xvfcmp_saf_d", - "llvm.loongarch.lasx.xvfcmp.saf.s" => "__builtin_lasx_xvfcmp_saf_s", - "llvm.loongarch.lasx.xvfcmp.seq.d" => "__builtin_lasx_xvfcmp_seq_d", - "llvm.loongarch.lasx.xvfcmp.seq.s" => "__builtin_lasx_xvfcmp_seq_s", - "llvm.loongarch.lasx.xvfcmp.sle.d" => "__builtin_lasx_xvfcmp_sle_d", - "llvm.loongarch.lasx.xvfcmp.sle.s" => "__builtin_lasx_xvfcmp_sle_s", - "llvm.loongarch.lasx.xvfcmp.slt.d" => "__builtin_lasx_xvfcmp_slt_d", - "llvm.loongarch.lasx.xvfcmp.slt.s" => "__builtin_lasx_xvfcmp_slt_s", - "llvm.loongarch.lasx.xvfcmp.sne.d" => "__builtin_lasx_xvfcmp_sne_d", - "llvm.loongarch.lasx.xvfcmp.sne.s" => "__builtin_lasx_xvfcmp_sne_s", - "llvm.loongarch.lasx.xvfcmp.sor.d" => "__builtin_lasx_xvfcmp_sor_d", - "llvm.loongarch.lasx.xvfcmp.sor.s" => "__builtin_lasx_xvfcmp_sor_s", - "llvm.loongarch.lasx.xvfcmp.sueq.d" => "__builtin_lasx_xvfcmp_sueq_d", - "llvm.loongarch.lasx.xvfcmp.sueq.s" => "__builtin_lasx_xvfcmp_sueq_s", - "llvm.loongarch.lasx.xvfcmp.sule.d" => "__builtin_lasx_xvfcmp_sule_d", - "llvm.loongarch.lasx.xvfcmp.sule.s" => "__builtin_lasx_xvfcmp_sule_s", - "llvm.loongarch.lasx.xvfcmp.sult.d" => "__builtin_lasx_xvfcmp_sult_d", - "llvm.loongarch.lasx.xvfcmp.sult.s" => "__builtin_lasx_xvfcmp_sult_s", - "llvm.loongarch.lasx.xvfcmp.sun.d" => "__builtin_lasx_xvfcmp_sun_d", - "llvm.loongarch.lasx.xvfcmp.sun.s" => "__builtin_lasx_xvfcmp_sun_s", - "llvm.loongarch.lasx.xvfcmp.sune.d" => "__builtin_lasx_xvfcmp_sune_d", - "llvm.loongarch.lasx.xvfcmp.sune.s" => "__builtin_lasx_xvfcmp_sune_s", - "llvm.loongarch.lasx.xvfcvt.h.s" => "__builtin_lasx_xvfcvt_h_s", - "llvm.loongarch.lasx.xvfcvt.s.d" => "__builtin_lasx_xvfcvt_s_d", - "llvm.loongarch.lasx.xvfcvth.d.s" => "__builtin_lasx_xvfcvth_d_s", - "llvm.loongarch.lasx.xvfcvth.s.h" => "__builtin_lasx_xvfcvth_s_h", - "llvm.loongarch.lasx.xvfcvtl.d.s" => "__builtin_lasx_xvfcvtl_d_s", - "llvm.loongarch.lasx.xvfcvtl.s.h" => "__builtin_lasx_xvfcvtl_s_h", - "llvm.loongarch.lasx.xvfdiv.d" => "__builtin_lasx_xvfdiv_d", - "llvm.loongarch.lasx.xvfdiv.s" => "__builtin_lasx_xvfdiv_s", - "llvm.loongarch.lasx.xvffint.d.l" => "__builtin_lasx_xvffint_d_l", - "llvm.loongarch.lasx.xvffint.d.lu" => "__builtin_lasx_xvffint_d_lu", - "llvm.loongarch.lasx.xvffint.s.l" => "__builtin_lasx_xvffint_s_l", - "llvm.loongarch.lasx.xvffint.s.w" => "__builtin_lasx_xvffint_s_w", - "llvm.loongarch.lasx.xvffint.s.wu" => "__builtin_lasx_xvffint_s_wu", - "llvm.loongarch.lasx.xvffinth.d.w" => "__builtin_lasx_xvffinth_d_w", - "llvm.loongarch.lasx.xvffintl.d.w" => "__builtin_lasx_xvffintl_d_w", - "llvm.loongarch.lasx.xvflogb.d" => "__builtin_lasx_xvflogb_d", - "llvm.loongarch.lasx.xvflogb.s" => "__builtin_lasx_xvflogb_s", - "llvm.loongarch.lasx.xvfmadd.d" => "__builtin_lasx_xvfmadd_d", - "llvm.loongarch.lasx.xvfmadd.s" => "__builtin_lasx_xvfmadd_s", - "llvm.loongarch.lasx.xvfmax.d" => "__builtin_lasx_xvfmax_d", - "llvm.loongarch.lasx.xvfmax.s" => "__builtin_lasx_xvfmax_s", - "llvm.loongarch.lasx.xvfmaxa.d" => "__builtin_lasx_xvfmaxa_d", - "llvm.loongarch.lasx.xvfmaxa.s" => "__builtin_lasx_xvfmaxa_s", - "llvm.loongarch.lasx.xvfmin.d" => "__builtin_lasx_xvfmin_d", - "llvm.loongarch.lasx.xvfmin.s" => "__builtin_lasx_xvfmin_s", - "llvm.loongarch.lasx.xvfmina.d" => "__builtin_lasx_xvfmina_d", - "llvm.loongarch.lasx.xvfmina.s" => "__builtin_lasx_xvfmina_s", - "llvm.loongarch.lasx.xvfmsub.d" => "__builtin_lasx_xvfmsub_d", - "llvm.loongarch.lasx.xvfmsub.s" => "__builtin_lasx_xvfmsub_s", - "llvm.loongarch.lasx.xvfmul.d" => "__builtin_lasx_xvfmul_d", - "llvm.loongarch.lasx.xvfmul.s" => "__builtin_lasx_xvfmul_s", - "llvm.loongarch.lasx.xvfnmadd.d" => "__builtin_lasx_xvfnmadd_d", - "llvm.loongarch.lasx.xvfnmadd.s" => "__builtin_lasx_xvfnmadd_s", - "llvm.loongarch.lasx.xvfnmsub.d" => "__builtin_lasx_xvfnmsub_d", - "llvm.loongarch.lasx.xvfnmsub.s" => "__builtin_lasx_xvfnmsub_s", - "llvm.loongarch.lasx.xvfrecip.d" => "__builtin_lasx_xvfrecip_d", - "llvm.loongarch.lasx.xvfrecip.s" => "__builtin_lasx_xvfrecip_s", - "llvm.loongarch.lasx.xvfrecipe.d" => "__builtin_lasx_xvfrecipe_d", - "llvm.loongarch.lasx.xvfrecipe.s" => "__builtin_lasx_xvfrecipe_s", - "llvm.loongarch.lasx.xvfrint.d" => "__builtin_lasx_xvfrint_d", - "llvm.loongarch.lasx.xvfrint.s" => "__builtin_lasx_xvfrint_s", - "llvm.loongarch.lasx.xvfrintrm.d" => "__builtin_lasx_xvfrintrm_d", - "llvm.loongarch.lasx.xvfrintrm.s" => "__builtin_lasx_xvfrintrm_s", - "llvm.loongarch.lasx.xvfrintrne.d" => "__builtin_lasx_xvfrintrne_d", - "llvm.loongarch.lasx.xvfrintrne.s" => "__builtin_lasx_xvfrintrne_s", - "llvm.loongarch.lasx.xvfrintrp.d" => "__builtin_lasx_xvfrintrp_d", - "llvm.loongarch.lasx.xvfrintrp.s" => "__builtin_lasx_xvfrintrp_s", - "llvm.loongarch.lasx.xvfrintrz.d" => "__builtin_lasx_xvfrintrz_d", - "llvm.loongarch.lasx.xvfrintrz.s" => "__builtin_lasx_xvfrintrz_s", - "llvm.loongarch.lasx.xvfrsqrt.d" => "__builtin_lasx_xvfrsqrt_d", - "llvm.loongarch.lasx.xvfrsqrt.s" => "__builtin_lasx_xvfrsqrt_s", - "llvm.loongarch.lasx.xvfrsqrte.d" => "__builtin_lasx_xvfrsqrte_d", - "llvm.loongarch.lasx.xvfrsqrte.s" => "__builtin_lasx_xvfrsqrte_s", - "llvm.loongarch.lasx.xvfrstp.b" => "__builtin_lasx_xvfrstp_b", - "llvm.loongarch.lasx.xvfrstp.h" => "__builtin_lasx_xvfrstp_h", - "llvm.loongarch.lasx.xvfrstpi.b" => "__builtin_lasx_xvfrstpi_b", - "llvm.loongarch.lasx.xvfrstpi.h" => "__builtin_lasx_xvfrstpi_h", - "llvm.loongarch.lasx.xvfsqrt.d" => "__builtin_lasx_xvfsqrt_d", - "llvm.loongarch.lasx.xvfsqrt.s" => "__builtin_lasx_xvfsqrt_s", - "llvm.loongarch.lasx.xvfsub.d" => "__builtin_lasx_xvfsub_d", - "llvm.loongarch.lasx.xvfsub.s" => "__builtin_lasx_xvfsub_s", - "llvm.loongarch.lasx.xvftint.l.d" => "__builtin_lasx_xvftint_l_d", - "llvm.loongarch.lasx.xvftint.lu.d" => "__builtin_lasx_xvftint_lu_d", - "llvm.loongarch.lasx.xvftint.w.d" => "__builtin_lasx_xvftint_w_d", - "llvm.loongarch.lasx.xvftint.w.s" => "__builtin_lasx_xvftint_w_s", - "llvm.loongarch.lasx.xvftint.wu.s" => "__builtin_lasx_xvftint_wu_s", - "llvm.loongarch.lasx.xvftinth.l.s" => "__builtin_lasx_xvftinth_l_s", - "llvm.loongarch.lasx.xvftintl.l.s" => "__builtin_lasx_xvftintl_l_s", - "llvm.loongarch.lasx.xvftintrm.l.d" => "__builtin_lasx_xvftintrm_l_d", - "llvm.loongarch.lasx.xvftintrm.w.d" => "__builtin_lasx_xvftintrm_w_d", - "llvm.loongarch.lasx.xvftintrm.w.s" => "__builtin_lasx_xvftintrm_w_s", - "llvm.loongarch.lasx.xvftintrmh.l.s" => "__builtin_lasx_xvftintrmh_l_s", - "llvm.loongarch.lasx.xvftintrml.l.s" => "__builtin_lasx_xvftintrml_l_s", - "llvm.loongarch.lasx.xvftintrne.l.d" => "__builtin_lasx_xvftintrne_l_d", - "llvm.loongarch.lasx.xvftintrne.w.d" => "__builtin_lasx_xvftintrne_w_d", - "llvm.loongarch.lasx.xvftintrne.w.s" => "__builtin_lasx_xvftintrne_w_s", - "llvm.loongarch.lasx.xvftintrneh.l.s" => "__builtin_lasx_xvftintrneh_l_s", - "llvm.loongarch.lasx.xvftintrnel.l.s" => "__builtin_lasx_xvftintrnel_l_s", - "llvm.loongarch.lasx.xvftintrp.l.d" => "__builtin_lasx_xvftintrp_l_d", - "llvm.loongarch.lasx.xvftintrp.w.d" => "__builtin_lasx_xvftintrp_w_d", - "llvm.loongarch.lasx.xvftintrp.w.s" => "__builtin_lasx_xvftintrp_w_s", - "llvm.loongarch.lasx.xvftintrph.l.s" => "__builtin_lasx_xvftintrph_l_s", - "llvm.loongarch.lasx.xvftintrpl.l.s" => "__builtin_lasx_xvftintrpl_l_s", - "llvm.loongarch.lasx.xvftintrz.l.d" => "__builtin_lasx_xvftintrz_l_d", - "llvm.loongarch.lasx.xvftintrz.lu.d" => "__builtin_lasx_xvftintrz_lu_d", - "llvm.loongarch.lasx.xvftintrz.w.d" => "__builtin_lasx_xvftintrz_w_d", - "llvm.loongarch.lasx.xvftintrz.w.s" => "__builtin_lasx_xvftintrz_w_s", - "llvm.loongarch.lasx.xvftintrz.wu.s" => "__builtin_lasx_xvftintrz_wu_s", - "llvm.loongarch.lasx.xvftintrzh.l.s" => "__builtin_lasx_xvftintrzh_l_s", - "llvm.loongarch.lasx.xvftintrzl.l.s" => "__builtin_lasx_xvftintrzl_l_s", - "llvm.loongarch.lasx.xvhaddw.d.w" => "__builtin_lasx_xvhaddw_d_w", - "llvm.loongarch.lasx.xvhaddw.du.wu" => "__builtin_lasx_xvhaddw_du_wu", - "llvm.loongarch.lasx.xvhaddw.h.b" => "__builtin_lasx_xvhaddw_h_b", - "llvm.loongarch.lasx.xvhaddw.hu.bu" => "__builtin_lasx_xvhaddw_hu_bu", - "llvm.loongarch.lasx.xvhaddw.q.d" => "__builtin_lasx_xvhaddw_q_d", - "llvm.loongarch.lasx.xvhaddw.qu.du" => "__builtin_lasx_xvhaddw_qu_du", - "llvm.loongarch.lasx.xvhaddw.w.h" => "__builtin_lasx_xvhaddw_w_h", - "llvm.loongarch.lasx.xvhaddw.wu.hu" => "__builtin_lasx_xvhaddw_wu_hu", - "llvm.loongarch.lasx.xvhsubw.d.w" => "__builtin_lasx_xvhsubw_d_w", - "llvm.loongarch.lasx.xvhsubw.du.wu" => "__builtin_lasx_xvhsubw_du_wu", - "llvm.loongarch.lasx.xvhsubw.h.b" => "__builtin_lasx_xvhsubw_h_b", - "llvm.loongarch.lasx.xvhsubw.hu.bu" => "__builtin_lasx_xvhsubw_hu_bu", - "llvm.loongarch.lasx.xvhsubw.q.d" => "__builtin_lasx_xvhsubw_q_d", - "llvm.loongarch.lasx.xvhsubw.qu.du" => "__builtin_lasx_xvhsubw_qu_du", - "llvm.loongarch.lasx.xvhsubw.w.h" => "__builtin_lasx_xvhsubw_w_h", - "llvm.loongarch.lasx.xvhsubw.wu.hu" => "__builtin_lasx_xvhsubw_wu_hu", - "llvm.loongarch.lasx.xvilvh.b" => "__builtin_lasx_xvilvh_b", - "llvm.loongarch.lasx.xvilvh.d" => "__builtin_lasx_xvilvh_d", - "llvm.loongarch.lasx.xvilvh.h" => "__builtin_lasx_xvilvh_h", - "llvm.loongarch.lasx.xvilvh.w" => "__builtin_lasx_xvilvh_w", - "llvm.loongarch.lasx.xvilvl.b" => "__builtin_lasx_xvilvl_b", - "llvm.loongarch.lasx.xvilvl.d" => "__builtin_lasx_xvilvl_d", - "llvm.loongarch.lasx.xvilvl.h" => "__builtin_lasx_xvilvl_h", - "llvm.loongarch.lasx.xvilvl.w" => "__builtin_lasx_xvilvl_w", - "llvm.loongarch.lasx.xvinsgr2vr.d" => "__builtin_lasx_xvinsgr2vr_d", - "llvm.loongarch.lasx.xvinsgr2vr.w" => "__builtin_lasx_xvinsgr2vr_w", - "llvm.loongarch.lasx.xvinsve0.d" => "__builtin_lasx_xvinsve0_d", - "llvm.loongarch.lasx.xvinsve0.w" => "__builtin_lasx_xvinsve0_w", - "llvm.loongarch.lasx.xvld" => "__builtin_lasx_xvld", - "llvm.loongarch.lasx.xvldi" => "__builtin_lasx_xvldi", - "llvm.loongarch.lasx.xvldrepl.b" => "__builtin_lasx_xvldrepl_b", - "llvm.loongarch.lasx.xvldrepl.d" => "__builtin_lasx_xvldrepl_d", - "llvm.loongarch.lasx.xvldrepl.h" => "__builtin_lasx_xvldrepl_h", - "llvm.loongarch.lasx.xvldrepl.w" => "__builtin_lasx_xvldrepl_w", - "llvm.loongarch.lasx.xvldx" => "__builtin_lasx_xvldx", - "llvm.loongarch.lasx.xvmadd.b" => "__builtin_lasx_xvmadd_b", - "llvm.loongarch.lasx.xvmadd.d" => "__builtin_lasx_xvmadd_d", - "llvm.loongarch.lasx.xvmadd.h" => "__builtin_lasx_xvmadd_h", - "llvm.loongarch.lasx.xvmadd.w" => "__builtin_lasx_xvmadd_w", - "llvm.loongarch.lasx.xvmaddwev.d.w" => "__builtin_lasx_xvmaddwev_d_w", - "llvm.loongarch.lasx.xvmaddwev.d.wu" => "__builtin_lasx_xvmaddwev_d_wu", - "llvm.loongarch.lasx.xvmaddwev.d.wu.w" => "__builtin_lasx_xvmaddwev_d_wu_w", - "llvm.loongarch.lasx.xvmaddwev.h.b" => "__builtin_lasx_xvmaddwev_h_b", - "llvm.loongarch.lasx.xvmaddwev.h.bu" => "__builtin_lasx_xvmaddwev_h_bu", - "llvm.loongarch.lasx.xvmaddwev.h.bu.b" => "__builtin_lasx_xvmaddwev_h_bu_b", - "llvm.loongarch.lasx.xvmaddwev.q.d" => "__builtin_lasx_xvmaddwev_q_d", - "llvm.loongarch.lasx.xvmaddwev.q.du" => "__builtin_lasx_xvmaddwev_q_du", - "llvm.loongarch.lasx.xvmaddwev.q.du.d" => "__builtin_lasx_xvmaddwev_q_du_d", - "llvm.loongarch.lasx.xvmaddwev.w.h" => "__builtin_lasx_xvmaddwev_w_h", - "llvm.loongarch.lasx.xvmaddwev.w.hu" => "__builtin_lasx_xvmaddwev_w_hu", - "llvm.loongarch.lasx.xvmaddwev.w.hu.h" => "__builtin_lasx_xvmaddwev_w_hu_h", - "llvm.loongarch.lasx.xvmaddwod.d.w" => "__builtin_lasx_xvmaddwod_d_w", - "llvm.loongarch.lasx.xvmaddwod.d.wu" => "__builtin_lasx_xvmaddwod_d_wu", - "llvm.loongarch.lasx.xvmaddwod.d.wu.w" => "__builtin_lasx_xvmaddwod_d_wu_w", - "llvm.loongarch.lasx.xvmaddwod.h.b" => "__builtin_lasx_xvmaddwod_h_b", - "llvm.loongarch.lasx.xvmaddwod.h.bu" => "__builtin_lasx_xvmaddwod_h_bu", - "llvm.loongarch.lasx.xvmaddwod.h.bu.b" => "__builtin_lasx_xvmaddwod_h_bu_b", - "llvm.loongarch.lasx.xvmaddwod.q.d" => "__builtin_lasx_xvmaddwod_q_d", - "llvm.loongarch.lasx.xvmaddwod.q.du" => "__builtin_lasx_xvmaddwod_q_du", - "llvm.loongarch.lasx.xvmaddwod.q.du.d" => "__builtin_lasx_xvmaddwod_q_du_d", - "llvm.loongarch.lasx.xvmaddwod.w.h" => "__builtin_lasx_xvmaddwod_w_h", - "llvm.loongarch.lasx.xvmaddwod.w.hu" => "__builtin_lasx_xvmaddwod_w_hu", - "llvm.loongarch.lasx.xvmaddwod.w.hu.h" => "__builtin_lasx_xvmaddwod_w_hu_h", - "llvm.loongarch.lasx.xvmax.b" => "__builtin_lasx_xvmax_b", - "llvm.loongarch.lasx.xvmax.bu" => "__builtin_lasx_xvmax_bu", - "llvm.loongarch.lasx.xvmax.d" => "__builtin_lasx_xvmax_d", - "llvm.loongarch.lasx.xvmax.du" => "__builtin_lasx_xvmax_du", - "llvm.loongarch.lasx.xvmax.h" => "__builtin_lasx_xvmax_h", - "llvm.loongarch.lasx.xvmax.hu" => "__builtin_lasx_xvmax_hu", - "llvm.loongarch.lasx.xvmax.w" => "__builtin_lasx_xvmax_w", - "llvm.loongarch.lasx.xvmax.wu" => "__builtin_lasx_xvmax_wu", - "llvm.loongarch.lasx.xvmaxi.b" => "__builtin_lasx_xvmaxi_b", - "llvm.loongarch.lasx.xvmaxi.bu" => "__builtin_lasx_xvmaxi_bu", - "llvm.loongarch.lasx.xvmaxi.d" => "__builtin_lasx_xvmaxi_d", - "llvm.loongarch.lasx.xvmaxi.du" => "__builtin_lasx_xvmaxi_du", - "llvm.loongarch.lasx.xvmaxi.h" => "__builtin_lasx_xvmaxi_h", - "llvm.loongarch.lasx.xvmaxi.hu" => "__builtin_lasx_xvmaxi_hu", - "llvm.loongarch.lasx.xvmaxi.w" => "__builtin_lasx_xvmaxi_w", - "llvm.loongarch.lasx.xvmaxi.wu" => "__builtin_lasx_xvmaxi_wu", - "llvm.loongarch.lasx.xvmin.b" => "__builtin_lasx_xvmin_b", - "llvm.loongarch.lasx.xvmin.bu" => "__builtin_lasx_xvmin_bu", - "llvm.loongarch.lasx.xvmin.d" => "__builtin_lasx_xvmin_d", - "llvm.loongarch.lasx.xvmin.du" => "__builtin_lasx_xvmin_du", - "llvm.loongarch.lasx.xvmin.h" => "__builtin_lasx_xvmin_h", - "llvm.loongarch.lasx.xvmin.hu" => "__builtin_lasx_xvmin_hu", - "llvm.loongarch.lasx.xvmin.w" => "__builtin_lasx_xvmin_w", - "llvm.loongarch.lasx.xvmin.wu" => "__builtin_lasx_xvmin_wu", - "llvm.loongarch.lasx.xvmini.b" => "__builtin_lasx_xvmini_b", - "llvm.loongarch.lasx.xvmini.bu" => "__builtin_lasx_xvmini_bu", - "llvm.loongarch.lasx.xvmini.d" => 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"__builtin_lsx_vfrecipe_d", - "llvm.loongarch.lsx.vfrecipe.s" => "__builtin_lsx_vfrecipe_s", - "llvm.loongarch.lsx.vfrint.d" => "__builtin_lsx_vfrint_d", - "llvm.loongarch.lsx.vfrint.s" => "__builtin_lsx_vfrint_s", - "llvm.loongarch.lsx.vfrintrm.d" => "__builtin_lsx_vfrintrm_d", - "llvm.loongarch.lsx.vfrintrm.s" => "__builtin_lsx_vfrintrm_s", - "llvm.loongarch.lsx.vfrintrne.d" => "__builtin_lsx_vfrintrne_d", - "llvm.loongarch.lsx.vfrintrne.s" => "__builtin_lsx_vfrintrne_s", - "llvm.loongarch.lsx.vfrintrp.d" => "__builtin_lsx_vfrintrp_d", - "llvm.loongarch.lsx.vfrintrp.s" => "__builtin_lsx_vfrintrp_s", - "llvm.loongarch.lsx.vfrintrz.d" => "__builtin_lsx_vfrintrz_d", - "llvm.loongarch.lsx.vfrintrz.s" => "__builtin_lsx_vfrintrz_s", - "llvm.loongarch.lsx.vfrsqrt.d" => "__builtin_lsx_vfrsqrt_d", - "llvm.loongarch.lsx.vfrsqrt.s" => "__builtin_lsx_vfrsqrt_s", - "llvm.loongarch.lsx.vfrsqrte.d" => "__builtin_lsx_vfrsqrte_d", - "llvm.loongarch.lsx.vfrsqrte.s" => "__builtin_lsx_vfrsqrte_s", - "llvm.loongarch.lsx.vfrstp.b" => "__builtin_lsx_vfrstp_b", - "llvm.loongarch.lsx.vfrstp.h" => "__builtin_lsx_vfrstp_h", - "llvm.loongarch.lsx.vfrstpi.b" => "__builtin_lsx_vfrstpi_b", - "llvm.loongarch.lsx.vfrstpi.h" => "__builtin_lsx_vfrstpi_h", - "llvm.loongarch.lsx.vfsqrt.d" => "__builtin_lsx_vfsqrt_d", - "llvm.loongarch.lsx.vfsqrt.s" => "__builtin_lsx_vfsqrt_s", - "llvm.loongarch.lsx.vfsub.d" => "__builtin_lsx_vfsub_d", - "llvm.loongarch.lsx.vfsub.s" => "__builtin_lsx_vfsub_s", - "llvm.loongarch.lsx.vftint.l.d" => "__builtin_lsx_vftint_l_d", - "llvm.loongarch.lsx.vftint.lu.d" => "__builtin_lsx_vftint_lu_d", - "llvm.loongarch.lsx.vftint.w.d" => "__builtin_lsx_vftint_w_d", - "llvm.loongarch.lsx.vftint.w.s" => "__builtin_lsx_vftint_w_s", - "llvm.loongarch.lsx.vftint.wu.s" => "__builtin_lsx_vftint_wu_s", - "llvm.loongarch.lsx.vftinth.l.s" => "__builtin_lsx_vftinth_l_s", - "llvm.loongarch.lsx.vftintl.l.s" => "__builtin_lsx_vftintl_l_s", - "llvm.loongarch.lsx.vftintrm.l.d" => "__builtin_lsx_vftintrm_l_d", - "llvm.loongarch.lsx.vftintrm.w.d" => "__builtin_lsx_vftintrm_w_d", - "llvm.loongarch.lsx.vftintrm.w.s" => "__builtin_lsx_vftintrm_w_s", - "llvm.loongarch.lsx.vftintrmh.l.s" => "__builtin_lsx_vftintrmh_l_s", - "llvm.loongarch.lsx.vftintrml.l.s" => "__builtin_lsx_vftintrml_l_s", - "llvm.loongarch.lsx.vftintrne.l.d" => "__builtin_lsx_vftintrne_l_d", - "llvm.loongarch.lsx.vftintrne.w.d" => "__builtin_lsx_vftintrne_w_d", - "llvm.loongarch.lsx.vftintrne.w.s" => "__builtin_lsx_vftintrne_w_s", - "llvm.loongarch.lsx.vftintrneh.l.s" => "__builtin_lsx_vftintrneh_l_s", - "llvm.loongarch.lsx.vftintrnel.l.s" => "__builtin_lsx_vftintrnel_l_s", - "llvm.loongarch.lsx.vftintrp.l.d" => "__builtin_lsx_vftintrp_l_d", - "llvm.loongarch.lsx.vftintrp.w.d" => "__builtin_lsx_vftintrp_w_d", - "llvm.loongarch.lsx.vftintrp.w.s" => "__builtin_lsx_vftintrp_w_s", - "llvm.loongarch.lsx.vftintrph.l.s" => "__builtin_lsx_vftintrph_l_s", - "llvm.loongarch.lsx.vftintrpl.l.s" => "__builtin_lsx_vftintrpl_l_s", - "llvm.loongarch.lsx.vftintrz.l.d" => "__builtin_lsx_vftintrz_l_d", - "llvm.loongarch.lsx.vftintrz.lu.d" => "__builtin_lsx_vftintrz_lu_d", - "llvm.loongarch.lsx.vftintrz.w.d" => "__builtin_lsx_vftintrz_w_d", - "llvm.loongarch.lsx.vftintrz.w.s" => "__builtin_lsx_vftintrz_w_s", - "llvm.loongarch.lsx.vftintrz.wu.s" => "__builtin_lsx_vftintrz_wu_s", - "llvm.loongarch.lsx.vftintrzh.l.s" => "__builtin_lsx_vftintrzh_l_s", - "llvm.loongarch.lsx.vftintrzl.l.s" => "__builtin_lsx_vftintrzl_l_s", - "llvm.loongarch.lsx.vhaddw.d.w" => "__builtin_lsx_vhaddw_d_w", - "llvm.loongarch.lsx.vhaddw.du.wu" => "__builtin_lsx_vhaddw_du_wu", - "llvm.loongarch.lsx.vhaddw.h.b" => "__builtin_lsx_vhaddw_h_b", - "llvm.loongarch.lsx.vhaddw.hu.bu" => "__builtin_lsx_vhaddw_hu_bu", - "llvm.loongarch.lsx.vhaddw.q.d" => "__builtin_lsx_vhaddw_q_d", - "llvm.loongarch.lsx.vhaddw.qu.du" => "__builtin_lsx_vhaddw_qu_du", - "llvm.loongarch.lsx.vhaddw.w.h" => "__builtin_lsx_vhaddw_w_h", - "llvm.loongarch.lsx.vhaddw.wu.hu" => "__builtin_lsx_vhaddw_wu_hu", - "llvm.loongarch.lsx.vhsubw.d.w" => "__builtin_lsx_vhsubw_d_w", - "llvm.loongarch.lsx.vhsubw.du.wu" => "__builtin_lsx_vhsubw_du_wu", - "llvm.loongarch.lsx.vhsubw.h.b" => "__builtin_lsx_vhsubw_h_b", - "llvm.loongarch.lsx.vhsubw.hu.bu" => "__builtin_lsx_vhsubw_hu_bu", - "llvm.loongarch.lsx.vhsubw.q.d" => "__builtin_lsx_vhsubw_q_d", - "llvm.loongarch.lsx.vhsubw.qu.du" => "__builtin_lsx_vhsubw_qu_du", - "llvm.loongarch.lsx.vhsubw.w.h" => "__builtin_lsx_vhsubw_w_h", - "llvm.loongarch.lsx.vhsubw.wu.hu" => "__builtin_lsx_vhsubw_wu_hu", - "llvm.loongarch.lsx.vilvh.b" => "__builtin_lsx_vilvh_b", - "llvm.loongarch.lsx.vilvh.d" => "__builtin_lsx_vilvh_d", - "llvm.loongarch.lsx.vilvh.h" => "__builtin_lsx_vilvh_h", - "llvm.loongarch.lsx.vilvh.w" => "__builtin_lsx_vilvh_w", - "llvm.loongarch.lsx.vilvl.b" => "__builtin_lsx_vilvl_b", - "llvm.loongarch.lsx.vilvl.d" => "__builtin_lsx_vilvl_d", - "llvm.loongarch.lsx.vilvl.h" => "__builtin_lsx_vilvl_h", - "llvm.loongarch.lsx.vilvl.w" => "__builtin_lsx_vilvl_w", - "llvm.loongarch.lsx.vinsgr2vr.b" => "__builtin_lsx_vinsgr2vr_b", - "llvm.loongarch.lsx.vinsgr2vr.d" => "__builtin_lsx_vinsgr2vr_d", - "llvm.loongarch.lsx.vinsgr2vr.h" => "__builtin_lsx_vinsgr2vr_h", - "llvm.loongarch.lsx.vinsgr2vr.w" => "__builtin_lsx_vinsgr2vr_w", - "llvm.loongarch.lsx.vld" => "__builtin_lsx_vld", - "llvm.loongarch.lsx.vldi" => "__builtin_lsx_vldi", - "llvm.loongarch.lsx.vldrepl.b" => "__builtin_lsx_vldrepl_b", - "llvm.loongarch.lsx.vldrepl.d" => "__builtin_lsx_vldrepl_d", - "llvm.loongarch.lsx.vldrepl.h" => "__builtin_lsx_vldrepl_h", - "llvm.loongarch.lsx.vldrepl.w" => "__builtin_lsx_vldrepl_w", - "llvm.loongarch.lsx.vldx" => "__builtin_lsx_vldx", - "llvm.loongarch.lsx.vmadd.b" => "__builtin_lsx_vmadd_b", - "llvm.loongarch.lsx.vmadd.d" => "__builtin_lsx_vmadd_d", - "llvm.loongarch.lsx.vmadd.h" => "__builtin_lsx_vmadd_h", - "llvm.loongarch.lsx.vmadd.w" => "__builtin_lsx_vmadd_w", - "llvm.loongarch.lsx.vmaddwev.d.w" => "__builtin_lsx_vmaddwev_d_w", - "llvm.loongarch.lsx.vmaddwev.d.wu" => "__builtin_lsx_vmaddwev_d_wu", - "llvm.loongarch.lsx.vmaddwev.d.wu.w" => "__builtin_lsx_vmaddwev_d_wu_w", - "llvm.loongarch.lsx.vmaddwev.h.b" => "__builtin_lsx_vmaddwev_h_b", - "llvm.loongarch.lsx.vmaddwev.h.bu" => "__builtin_lsx_vmaddwev_h_bu", - "llvm.loongarch.lsx.vmaddwev.h.bu.b" => "__builtin_lsx_vmaddwev_h_bu_b", - "llvm.loongarch.lsx.vmaddwev.q.d" => "__builtin_lsx_vmaddwev_q_d", - "llvm.loongarch.lsx.vmaddwev.q.du" => "__builtin_lsx_vmaddwev_q_du", - "llvm.loongarch.lsx.vmaddwev.q.du.d" => "__builtin_lsx_vmaddwev_q_du_d", - "llvm.loongarch.lsx.vmaddwev.w.h" => "__builtin_lsx_vmaddwev_w_h", - "llvm.loongarch.lsx.vmaddwev.w.hu" => "__builtin_lsx_vmaddwev_w_hu", - "llvm.loongarch.lsx.vmaddwev.w.hu.h" => "__builtin_lsx_vmaddwev_w_hu_h", - "llvm.loongarch.lsx.vmaddwod.d.w" => "__builtin_lsx_vmaddwod_d_w", - "llvm.loongarch.lsx.vmaddwod.d.wu" => "__builtin_lsx_vmaddwod_d_wu", - "llvm.loongarch.lsx.vmaddwod.d.wu.w" => "__builtin_lsx_vmaddwod_d_wu_w", - "llvm.loongarch.lsx.vmaddwod.h.b" => "__builtin_lsx_vmaddwod_h_b", - "llvm.loongarch.lsx.vmaddwod.h.bu" => "__builtin_lsx_vmaddwod_h_bu", - "llvm.loongarch.lsx.vmaddwod.h.bu.b" => "__builtin_lsx_vmaddwod_h_bu_b", - "llvm.loongarch.lsx.vmaddwod.q.d" => "__builtin_lsx_vmaddwod_q_d", - "llvm.loongarch.lsx.vmaddwod.q.du" => "__builtin_lsx_vmaddwod_q_du", - "llvm.loongarch.lsx.vmaddwod.q.du.d" => "__builtin_lsx_vmaddwod_q_du_d", - "llvm.loongarch.lsx.vmaddwod.w.h" => "__builtin_lsx_vmaddwod_w_h", - "llvm.loongarch.lsx.vmaddwod.w.hu" => "__builtin_lsx_vmaddwod_w_hu", - "llvm.loongarch.lsx.vmaddwod.w.hu.h" => "__builtin_lsx_vmaddwod_w_hu_h", - "llvm.loongarch.lsx.vmax.b" => "__builtin_lsx_vmax_b", - "llvm.loongarch.lsx.vmax.bu" => "__builtin_lsx_vmax_bu", - "llvm.loongarch.lsx.vmax.d" => "__builtin_lsx_vmax_d", - "llvm.loongarch.lsx.vmax.du" => "__builtin_lsx_vmax_du", - "llvm.loongarch.lsx.vmax.h" => "__builtin_lsx_vmax_h", - "llvm.loongarch.lsx.vmax.hu" => "__builtin_lsx_vmax_hu", - "llvm.loongarch.lsx.vmax.w" => "__builtin_lsx_vmax_w", - "llvm.loongarch.lsx.vmax.wu" => "__builtin_lsx_vmax_wu", - "llvm.loongarch.lsx.vmaxi.b" => "__builtin_lsx_vmaxi_b", - "llvm.loongarch.lsx.vmaxi.bu" => "__builtin_lsx_vmaxi_bu", - "llvm.loongarch.lsx.vmaxi.d" => "__builtin_lsx_vmaxi_d", - "llvm.loongarch.lsx.vmaxi.du" => "__builtin_lsx_vmaxi_du", - "llvm.loongarch.lsx.vmaxi.h" => "__builtin_lsx_vmaxi_h", - "llvm.loongarch.lsx.vmaxi.hu" => "__builtin_lsx_vmaxi_hu", - "llvm.loongarch.lsx.vmaxi.w" => "__builtin_lsx_vmaxi_w", - "llvm.loongarch.lsx.vmaxi.wu" => "__builtin_lsx_vmaxi_wu", - "llvm.loongarch.lsx.vmin.b" => "__builtin_lsx_vmin_b", - "llvm.loongarch.lsx.vmin.bu" => "__builtin_lsx_vmin_bu", - "llvm.loongarch.lsx.vmin.d" => "__builtin_lsx_vmin_d", - "llvm.loongarch.lsx.vmin.du" => "__builtin_lsx_vmin_du", - "llvm.loongarch.lsx.vmin.h" => "__builtin_lsx_vmin_h", - "llvm.loongarch.lsx.vmin.hu" => "__builtin_lsx_vmin_hu", - "llvm.loongarch.lsx.vmin.w" => "__builtin_lsx_vmin_w", - "llvm.loongarch.lsx.vmin.wu" => "__builtin_lsx_vmin_wu", - "llvm.loongarch.lsx.vmini.b" => "__builtin_lsx_vmini_b", - "llvm.loongarch.lsx.vmini.bu" => "__builtin_lsx_vmini_bu", - "llvm.loongarch.lsx.vmini.d" => "__builtin_lsx_vmini_d", - "llvm.loongarch.lsx.vmini.du" => "__builtin_lsx_vmini_du", - "llvm.loongarch.lsx.vmini.h" => "__builtin_lsx_vmini_h", - "llvm.loongarch.lsx.vmini.hu" => "__builtin_lsx_vmini_hu", - "llvm.loongarch.lsx.vmini.w" => "__builtin_lsx_vmini_w", - "llvm.loongarch.lsx.vmini.wu" => "__builtin_lsx_vmini_wu", - "llvm.loongarch.lsx.vmod.b" => "__builtin_lsx_vmod_b", - "llvm.loongarch.lsx.vmod.bu" => "__builtin_lsx_vmod_bu", - "llvm.loongarch.lsx.vmod.d" => "__builtin_lsx_vmod_d", - "llvm.loongarch.lsx.vmod.du" => "__builtin_lsx_vmod_du", - "llvm.loongarch.lsx.vmod.h" => "__builtin_lsx_vmod_h", - "llvm.loongarch.lsx.vmod.hu" => "__builtin_lsx_vmod_hu", - "llvm.loongarch.lsx.vmod.w" => "__builtin_lsx_vmod_w", - "llvm.loongarch.lsx.vmod.wu" => "__builtin_lsx_vmod_wu", - "llvm.loongarch.lsx.vmskgez.b" => "__builtin_lsx_vmskgez_b", - "llvm.loongarch.lsx.vmskltz.b" => "__builtin_lsx_vmskltz_b", - "llvm.loongarch.lsx.vmskltz.d" => "__builtin_lsx_vmskltz_d", - "llvm.loongarch.lsx.vmskltz.h" => "__builtin_lsx_vmskltz_h", - "llvm.loongarch.lsx.vmskltz.w" => "__builtin_lsx_vmskltz_w", - "llvm.loongarch.lsx.vmsknz.b" => "__builtin_lsx_vmsknz_b", - "llvm.loongarch.lsx.vmsub.b" => "__builtin_lsx_vmsub_b", - "llvm.loongarch.lsx.vmsub.d" => "__builtin_lsx_vmsub_d", - "llvm.loongarch.lsx.vmsub.h" => "__builtin_lsx_vmsub_h", - "llvm.loongarch.lsx.vmsub.w" => "__builtin_lsx_vmsub_w", - "llvm.loongarch.lsx.vmuh.b" => "__builtin_lsx_vmuh_b", - "llvm.loongarch.lsx.vmuh.bu" => "__builtin_lsx_vmuh_bu", - "llvm.loongarch.lsx.vmuh.d" => "__builtin_lsx_vmuh_d", - "llvm.loongarch.lsx.vmuh.du" => "__builtin_lsx_vmuh_du", - "llvm.loongarch.lsx.vmuh.h" => "__builtin_lsx_vmuh_h", - "llvm.loongarch.lsx.vmuh.hu" => "__builtin_lsx_vmuh_hu", - "llvm.loongarch.lsx.vmuh.w" => "__builtin_lsx_vmuh_w", - "llvm.loongarch.lsx.vmuh.wu" => "__builtin_lsx_vmuh_wu", - "llvm.loongarch.lsx.vmul.b" => "__builtin_lsx_vmul_b", - "llvm.loongarch.lsx.vmul.d" => "__builtin_lsx_vmul_d", - "llvm.loongarch.lsx.vmul.h" => "__builtin_lsx_vmul_h", - "llvm.loongarch.lsx.vmul.w" => "__builtin_lsx_vmul_w", - "llvm.loongarch.lsx.vmulwev.d.w" => "__builtin_lsx_vmulwev_d_w", - "llvm.loongarch.lsx.vmulwev.d.wu" => "__builtin_lsx_vmulwev_d_wu", - "llvm.loongarch.lsx.vmulwev.d.wu.w" => "__builtin_lsx_vmulwev_d_wu_w", - "llvm.loongarch.lsx.vmulwev.h.b" => "__builtin_lsx_vmulwev_h_b", - "llvm.loongarch.lsx.vmulwev.h.bu" => "__builtin_lsx_vmulwev_h_bu", - "llvm.loongarch.lsx.vmulwev.h.bu.b" => "__builtin_lsx_vmulwev_h_bu_b", - "llvm.loongarch.lsx.vmulwev.q.d" => "__builtin_lsx_vmulwev_q_d", - "llvm.loongarch.lsx.vmulwev.q.du" => "__builtin_lsx_vmulwev_q_du", - "llvm.loongarch.lsx.vmulwev.q.du.d" => "__builtin_lsx_vmulwev_q_du_d", - "llvm.loongarch.lsx.vmulwev.w.h" => "__builtin_lsx_vmulwev_w_h", - "llvm.loongarch.lsx.vmulwev.w.hu" => "__builtin_lsx_vmulwev_w_hu", - "llvm.loongarch.lsx.vmulwev.w.hu.h" => "__builtin_lsx_vmulwev_w_hu_h", - "llvm.loongarch.lsx.vmulwod.d.w" => "__builtin_lsx_vmulwod_d_w", - "llvm.loongarch.lsx.vmulwod.d.wu" => "__builtin_lsx_vmulwod_d_wu", - "llvm.loongarch.lsx.vmulwod.d.wu.w" => "__builtin_lsx_vmulwod_d_wu_w", - "llvm.loongarch.lsx.vmulwod.h.b" => "__builtin_lsx_vmulwod_h_b", - "llvm.loongarch.lsx.vmulwod.h.bu" => "__builtin_lsx_vmulwod_h_bu", - "llvm.loongarch.lsx.vmulwod.h.bu.b" => "__builtin_lsx_vmulwod_h_bu_b", - "llvm.loongarch.lsx.vmulwod.q.d" => "__builtin_lsx_vmulwod_q_d", - "llvm.loongarch.lsx.vmulwod.q.du" => "__builtin_lsx_vmulwod_q_du", - "llvm.loongarch.lsx.vmulwod.q.du.d" => "__builtin_lsx_vmulwod_q_du_d", - "llvm.loongarch.lsx.vmulwod.w.h" => "__builtin_lsx_vmulwod_w_h", - "llvm.loongarch.lsx.vmulwod.w.hu" => "__builtin_lsx_vmulwod_w_hu", - "llvm.loongarch.lsx.vmulwod.w.hu.h" => "__builtin_lsx_vmulwod_w_hu_h", - "llvm.loongarch.lsx.vneg.b" => "__builtin_lsx_vneg_b", - "llvm.loongarch.lsx.vneg.d" => "__builtin_lsx_vneg_d", - "llvm.loongarch.lsx.vneg.h" => "__builtin_lsx_vneg_h", - "llvm.loongarch.lsx.vneg.w" => "__builtin_lsx_vneg_w", - "llvm.loongarch.lsx.vnor.v" => "__builtin_lsx_vnor_v", - "llvm.loongarch.lsx.vnori.b" => "__builtin_lsx_vnori_b", - "llvm.loongarch.lsx.vor.v" => "__builtin_lsx_vor_v", - "llvm.loongarch.lsx.vori.b" => "__builtin_lsx_vori_b", - "llvm.loongarch.lsx.vorn.v" => "__builtin_lsx_vorn_v", - "llvm.loongarch.lsx.vpackev.b" => "__builtin_lsx_vpackev_b", - "llvm.loongarch.lsx.vpackev.d" => "__builtin_lsx_vpackev_d", - "llvm.loongarch.lsx.vpackev.h" => "__builtin_lsx_vpackev_h", - "llvm.loongarch.lsx.vpackev.w" => "__builtin_lsx_vpackev_w", - "llvm.loongarch.lsx.vpackod.b" => "__builtin_lsx_vpackod_b", - "llvm.loongarch.lsx.vpackod.d" => "__builtin_lsx_vpackod_d", - "llvm.loongarch.lsx.vpackod.h" => "__builtin_lsx_vpackod_h", - "llvm.loongarch.lsx.vpackod.w" => "__builtin_lsx_vpackod_w", - "llvm.loongarch.lsx.vpcnt.b" => "__builtin_lsx_vpcnt_b", - "llvm.loongarch.lsx.vpcnt.d" => "__builtin_lsx_vpcnt_d", - "llvm.loongarch.lsx.vpcnt.h" => "__builtin_lsx_vpcnt_h", - "llvm.loongarch.lsx.vpcnt.w" => "__builtin_lsx_vpcnt_w", - "llvm.loongarch.lsx.vpermi.w" => "__builtin_lsx_vpermi_w", - "llvm.loongarch.lsx.vpickev.b" => "__builtin_lsx_vpickev_b", - "llvm.loongarch.lsx.vpickev.d" => "__builtin_lsx_vpickev_d", - "llvm.loongarch.lsx.vpickev.h" => "__builtin_lsx_vpickev_h", - "llvm.loongarch.lsx.vpickev.w" => "__builtin_lsx_vpickev_w", - "llvm.loongarch.lsx.vpickod.b" => "__builtin_lsx_vpickod_b", - "llvm.loongarch.lsx.vpickod.d" => "__builtin_lsx_vpickod_d", - "llvm.loongarch.lsx.vpickod.h" => "__builtin_lsx_vpickod_h", - "llvm.loongarch.lsx.vpickod.w" => "__builtin_lsx_vpickod_w", - "llvm.loongarch.lsx.vpickve2gr.b" => "__builtin_lsx_vpickve2gr_b", - "llvm.loongarch.lsx.vpickve2gr.bu" => "__builtin_lsx_vpickve2gr_bu", - "llvm.loongarch.lsx.vpickve2gr.d" => "__builtin_lsx_vpickve2gr_d", - "llvm.loongarch.lsx.vpickve2gr.du" => "__builtin_lsx_vpickve2gr_du", - "llvm.loongarch.lsx.vpickve2gr.h" => "__builtin_lsx_vpickve2gr_h", - "llvm.loongarch.lsx.vpickve2gr.hu" => "__builtin_lsx_vpickve2gr_hu", - "llvm.loongarch.lsx.vpickve2gr.w" => "__builtin_lsx_vpickve2gr_w", - "llvm.loongarch.lsx.vpickve2gr.wu" => "__builtin_lsx_vpickve2gr_wu", - "llvm.loongarch.lsx.vreplgr2vr.b" => "__builtin_lsx_vreplgr2vr_b", - "llvm.loongarch.lsx.vreplgr2vr.d" => "__builtin_lsx_vreplgr2vr_d", - "llvm.loongarch.lsx.vreplgr2vr.h" => "__builtin_lsx_vreplgr2vr_h", - "llvm.loongarch.lsx.vreplgr2vr.w" => "__builtin_lsx_vreplgr2vr_w", - "llvm.loongarch.lsx.vrepli.b" => "__builtin_lsx_vrepli_b", - "llvm.loongarch.lsx.vrepli.d" => "__builtin_lsx_vrepli_d", - "llvm.loongarch.lsx.vrepli.h" => "__builtin_lsx_vrepli_h", - "llvm.loongarch.lsx.vrepli.w" => "__builtin_lsx_vrepli_w", - "llvm.loongarch.lsx.vreplve.b" => "__builtin_lsx_vreplve_b", - "llvm.loongarch.lsx.vreplve.d" => "__builtin_lsx_vreplve_d", - "llvm.loongarch.lsx.vreplve.h" => "__builtin_lsx_vreplve_h", - "llvm.loongarch.lsx.vreplve.w" => "__builtin_lsx_vreplve_w", - "llvm.loongarch.lsx.vreplvei.b" => "__builtin_lsx_vreplvei_b", - "llvm.loongarch.lsx.vreplvei.d" => "__builtin_lsx_vreplvei_d", - "llvm.loongarch.lsx.vreplvei.h" => "__builtin_lsx_vreplvei_h", - "llvm.loongarch.lsx.vreplvei.w" => "__builtin_lsx_vreplvei_w", - "llvm.loongarch.lsx.vrotr.b" => "__builtin_lsx_vrotr_b", - "llvm.loongarch.lsx.vrotr.d" => "__builtin_lsx_vrotr_d", - "llvm.loongarch.lsx.vrotr.h" => "__builtin_lsx_vrotr_h", - "llvm.loongarch.lsx.vrotr.w" => "__builtin_lsx_vrotr_w", - "llvm.loongarch.lsx.vrotri.b" => "__builtin_lsx_vrotri_b", - "llvm.loongarch.lsx.vrotri.d" => "__builtin_lsx_vrotri_d", - "llvm.loongarch.lsx.vrotri.h" => "__builtin_lsx_vrotri_h", - "llvm.loongarch.lsx.vrotri.w" => "__builtin_lsx_vrotri_w", - "llvm.loongarch.lsx.vsadd.b" => "__builtin_lsx_vsadd_b", - "llvm.loongarch.lsx.vsadd.bu" => "__builtin_lsx_vsadd_bu", - "llvm.loongarch.lsx.vsadd.d" => "__builtin_lsx_vsadd_d", - "llvm.loongarch.lsx.vsadd.du" => "__builtin_lsx_vsadd_du", - "llvm.loongarch.lsx.vsadd.h" => "__builtin_lsx_vsadd_h", - "llvm.loongarch.lsx.vsadd.hu" => "__builtin_lsx_vsadd_hu", - "llvm.loongarch.lsx.vsadd.w" => "__builtin_lsx_vsadd_w", - "llvm.loongarch.lsx.vsadd.wu" => "__builtin_lsx_vsadd_wu", - "llvm.loongarch.lsx.vsat.b" => "__builtin_lsx_vsat_b", - "llvm.loongarch.lsx.vsat.bu" => "__builtin_lsx_vsat_bu", - "llvm.loongarch.lsx.vsat.d" => "__builtin_lsx_vsat_d", - "llvm.loongarch.lsx.vsat.du" => "__builtin_lsx_vsat_du", - "llvm.loongarch.lsx.vsat.h" => "__builtin_lsx_vsat_h", - "llvm.loongarch.lsx.vsat.hu" => "__builtin_lsx_vsat_hu", - "llvm.loongarch.lsx.vsat.w" => "__builtin_lsx_vsat_w", - "llvm.loongarch.lsx.vsat.wu" => "__builtin_lsx_vsat_wu", - "llvm.loongarch.lsx.vseq.b" => "__builtin_lsx_vseq_b", - "llvm.loongarch.lsx.vseq.d" => "__builtin_lsx_vseq_d", - "llvm.loongarch.lsx.vseq.h" => "__builtin_lsx_vseq_h", - "llvm.loongarch.lsx.vseq.w" => "__builtin_lsx_vseq_w", - "llvm.loongarch.lsx.vseqi.b" => "__builtin_lsx_vseqi_b", - "llvm.loongarch.lsx.vseqi.d" => "__builtin_lsx_vseqi_d", - "llvm.loongarch.lsx.vseqi.h" => "__builtin_lsx_vseqi_h", - "llvm.loongarch.lsx.vseqi.w" => "__builtin_lsx_vseqi_w", - "llvm.loongarch.lsx.vshuf.b" => "__builtin_lsx_vshuf_b", - "llvm.loongarch.lsx.vshuf.d" => "__builtin_lsx_vshuf_d", - "llvm.loongarch.lsx.vshuf.h" => "__builtin_lsx_vshuf_h", - "llvm.loongarch.lsx.vshuf.w" => "__builtin_lsx_vshuf_w", - "llvm.loongarch.lsx.vshuf4i.b" => "__builtin_lsx_vshuf4i_b", - "llvm.loongarch.lsx.vshuf4i.d" => "__builtin_lsx_vshuf4i_d", - "llvm.loongarch.lsx.vshuf4i.h" => "__builtin_lsx_vshuf4i_h", - "llvm.loongarch.lsx.vshuf4i.w" => "__builtin_lsx_vshuf4i_w", - "llvm.loongarch.lsx.vsigncov.b" => "__builtin_lsx_vsigncov_b", - "llvm.loongarch.lsx.vsigncov.d" => "__builtin_lsx_vsigncov_d", - "llvm.loongarch.lsx.vsigncov.h" => "__builtin_lsx_vsigncov_h", - "llvm.loongarch.lsx.vsigncov.w" => "__builtin_lsx_vsigncov_w", - "llvm.loongarch.lsx.vsle.b" => "__builtin_lsx_vsle_b", - "llvm.loongarch.lsx.vsle.bu" => "__builtin_lsx_vsle_bu", - "llvm.loongarch.lsx.vsle.d" => "__builtin_lsx_vsle_d", - "llvm.loongarch.lsx.vsle.du" => "__builtin_lsx_vsle_du", - "llvm.loongarch.lsx.vsle.h" => "__builtin_lsx_vsle_h", - "llvm.loongarch.lsx.vsle.hu" => "__builtin_lsx_vsle_hu", - "llvm.loongarch.lsx.vsle.w" => "__builtin_lsx_vsle_w", - "llvm.loongarch.lsx.vsle.wu" => "__builtin_lsx_vsle_wu", - "llvm.loongarch.lsx.vslei.b" => "__builtin_lsx_vslei_b", - "llvm.loongarch.lsx.vslei.bu" => "__builtin_lsx_vslei_bu", - "llvm.loongarch.lsx.vslei.d" => "__builtin_lsx_vslei_d", - "llvm.loongarch.lsx.vslei.du" => "__builtin_lsx_vslei_du", - "llvm.loongarch.lsx.vslei.h" => "__builtin_lsx_vslei_h", - "llvm.loongarch.lsx.vslei.hu" => "__builtin_lsx_vslei_hu", - "llvm.loongarch.lsx.vslei.w" => "__builtin_lsx_vslei_w", - "llvm.loongarch.lsx.vslei.wu" => "__builtin_lsx_vslei_wu", - "llvm.loongarch.lsx.vsll.b" => "__builtin_lsx_vsll_b", - "llvm.loongarch.lsx.vsll.d" => "__builtin_lsx_vsll_d", - "llvm.loongarch.lsx.vsll.h" => "__builtin_lsx_vsll_h", - "llvm.loongarch.lsx.vsll.w" => "__builtin_lsx_vsll_w", - "llvm.loongarch.lsx.vslli.b" => "__builtin_lsx_vslli_b", - "llvm.loongarch.lsx.vslli.d" => "__builtin_lsx_vslli_d", - "llvm.loongarch.lsx.vslli.h" => "__builtin_lsx_vslli_h", - "llvm.loongarch.lsx.vslli.w" => "__builtin_lsx_vslli_w", - "llvm.loongarch.lsx.vsllwil.d.w" => "__builtin_lsx_vsllwil_d_w", - "llvm.loongarch.lsx.vsllwil.du.wu" => "__builtin_lsx_vsllwil_du_wu", - "llvm.loongarch.lsx.vsllwil.h.b" => "__builtin_lsx_vsllwil_h_b", - "llvm.loongarch.lsx.vsllwil.hu.bu" => "__builtin_lsx_vsllwil_hu_bu", - "llvm.loongarch.lsx.vsllwil.w.h" => "__builtin_lsx_vsllwil_w_h", - "llvm.loongarch.lsx.vsllwil.wu.hu" => "__builtin_lsx_vsllwil_wu_hu", - "llvm.loongarch.lsx.vslt.b" => "__builtin_lsx_vslt_b", - "llvm.loongarch.lsx.vslt.bu" => "__builtin_lsx_vslt_bu", - "llvm.loongarch.lsx.vslt.d" => "__builtin_lsx_vslt_d", - "llvm.loongarch.lsx.vslt.du" => "__builtin_lsx_vslt_du", - "llvm.loongarch.lsx.vslt.h" => "__builtin_lsx_vslt_h", - "llvm.loongarch.lsx.vslt.hu" => "__builtin_lsx_vslt_hu", - "llvm.loongarch.lsx.vslt.w" => "__builtin_lsx_vslt_w", - "llvm.loongarch.lsx.vslt.wu" => "__builtin_lsx_vslt_wu", - "llvm.loongarch.lsx.vslti.b" => "__builtin_lsx_vslti_b", - "llvm.loongarch.lsx.vslti.bu" => "__builtin_lsx_vslti_bu", - "llvm.loongarch.lsx.vslti.d" => "__builtin_lsx_vslti_d", - "llvm.loongarch.lsx.vslti.du" => "__builtin_lsx_vslti_du", - "llvm.loongarch.lsx.vslti.h" => "__builtin_lsx_vslti_h", - "llvm.loongarch.lsx.vslti.hu" => "__builtin_lsx_vslti_hu", - "llvm.loongarch.lsx.vslti.w" => "__builtin_lsx_vslti_w", - "llvm.loongarch.lsx.vslti.wu" => "__builtin_lsx_vslti_wu", - "llvm.loongarch.lsx.vsra.b" => "__builtin_lsx_vsra_b", - "llvm.loongarch.lsx.vsra.d" => "__builtin_lsx_vsra_d", - "llvm.loongarch.lsx.vsra.h" => "__builtin_lsx_vsra_h", - "llvm.loongarch.lsx.vsra.w" => "__builtin_lsx_vsra_w", - "llvm.loongarch.lsx.vsrai.b" => "__builtin_lsx_vsrai_b", - "llvm.loongarch.lsx.vsrai.d" => "__builtin_lsx_vsrai_d", - "llvm.loongarch.lsx.vsrai.h" => "__builtin_lsx_vsrai_h", - "llvm.loongarch.lsx.vsrai.w" => "__builtin_lsx_vsrai_w", - "llvm.loongarch.lsx.vsran.b.h" => "__builtin_lsx_vsran_b_h", - "llvm.loongarch.lsx.vsran.h.w" => "__builtin_lsx_vsran_h_w", - "llvm.loongarch.lsx.vsran.w.d" => "__builtin_lsx_vsran_w_d", - "llvm.loongarch.lsx.vsrani.b.h" => "__builtin_lsx_vsrani_b_h", - "llvm.loongarch.lsx.vsrani.d.q" => "__builtin_lsx_vsrani_d_q", - "llvm.loongarch.lsx.vsrani.h.w" => "__builtin_lsx_vsrani_h_w", - "llvm.loongarch.lsx.vsrani.w.d" => "__builtin_lsx_vsrani_w_d", - "llvm.loongarch.lsx.vsrar.b" => "__builtin_lsx_vsrar_b", - "llvm.loongarch.lsx.vsrar.d" => "__builtin_lsx_vsrar_d", - "llvm.loongarch.lsx.vsrar.h" => "__builtin_lsx_vsrar_h", - "llvm.loongarch.lsx.vsrar.w" => "__builtin_lsx_vsrar_w", - "llvm.loongarch.lsx.vsrari.b" => "__builtin_lsx_vsrari_b", - "llvm.loongarch.lsx.vsrari.d" => "__builtin_lsx_vsrari_d", - "llvm.loongarch.lsx.vsrari.h" => "__builtin_lsx_vsrari_h", - "llvm.loongarch.lsx.vsrari.w" => "__builtin_lsx_vsrari_w", - "llvm.loongarch.lsx.vsrarn.b.h" => "__builtin_lsx_vsrarn_b_h", - "llvm.loongarch.lsx.vsrarn.h.w" => "__builtin_lsx_vsrarn_h_w", - "llvm.loongarch.lsx.vsrarn.w.d" => "__builtin_lsx_vsrarn_w_d", - "llvm.loongarch.lsx.vsrarni.b.h" => "__builtin_lsx_vsrarni_b_h", - "llvm.loongarch.lsx.vsrarni.d.q" => "__builtin_lsx_vsrarni_d_q", - "llvm.loongarch.lsx.vsrarni.h.w" => "__builtin_lsx_vsrarni_h_w", - "llvm.loongarch.lsx.vsrarni.w.d" => "__builtin_lsx_vsrarni_w_d", - "llvm.loongarch.lsx.vsrl.b" => "__builtin_lsx_vsrl_b", - "llvm.loongarch.lsx.vsrl.d" => "__builtin_lsx_vsrl_d", - "llvm.loongarch.lsx.vsrl.h" => "__builtin_lsx_vsrl_h", - "llvm.loongarch.lsx.vsrl.w" => "__builtin_lsx_vsrl_w", - "llvm.loongarch.lsx.vsrli.b" => "__builtin_lsx_vsrli_b", - "llvm.loongarch.lsx.vsrli.d" => "__builtin_lsx_vsrli_d", - "llvm.loongarch.lsx.vsrli.h" => "__builtin_lsx_vsrli_h", - "llvm.loongarch.lsx.vsrli.w" => "__builtin_lsx_vsrli_w", - "llvm.loongarch.lsx.vsrln.b.h" => "__builtin_lsx_vsrln_b_h", - "llvm.loongarch.lsx.vsrln.h.w" => "__builtin_lsx_vsrln_h_w", - "llvm.loongarch.lsx.vsrln.w.d" => "__builtin_lsx_vsrln_w_d", - "llvm.loongarch.lsx.vsrlni.b.h" => "__builtin_lsx_vsrlni_b_h", - "llvm.loongarch.lsx.vsrlni.d.q" => "__builtin_lsx_vsrlni_d_q", - "llvm.loongarch.lsx.vsrlni.h.w" => "__builtin_lsx_vsrlni_h_w", - "llvm.loongarch.lsx.vsrlni.w.d" => "__builtin_lsx_vsrlni_w_d", - "llvm.loongarch.lsx.vsrlr.b" => "__builtin_lsx_vsrlr_b", - "llvm.loongarch.lsx.vsrlr.d" => "__builtin_lsx_vsrlr_d", - "llvm.loongarch.lsx.vsrlr.h" => "__builtin_lsx_vsrlr_h", - "llvm.loongarch.lsx.vsrlr.w" => "__builtin_lsx_vsrlr_w", - "llvm.loongarch.lsx.vsrlri.b" => "__builtin_lsx_vsrlri_b", - "llvm.loongarch.lsx.vsrlri.d" => "__builtin_lsx_vsrlri_d", - "llvm.loongarch.lsx.vsrlri.h" => "__builtin_lsx_vsrlri_h", - "llvm.loongarch.lsx.vsrlri.w" => "__builtin_lsx_vsrlri_w", - "llvm.loongarch.lsx.vsrlrn.b.h" => "__builtin_lsx_vsrlrn_b_h", - "llvm.loongarch.lsx.vsrlrn.h.w" => "__builtin_lsx_vsrlrn_h_w", - "llvm.loongarch.lsx.vsrlrn.w.d" => "__builtin_lsx_vsrlrn_w_d", - "llvm.loongarch.lsx.vsrlrni.b.h" => "__builtin_lsx_vsrlrni_b_h", - "llvm.loongarch.lsx.vsrlrni.d.q" => "__builtin_lsx_vsrlrni_d_q", - "llvm.loongarch.lsx.vsrlrni.h.w" => "__builtin_lsx_vsrlrni_h_w", - "llvm.loongarch.lsx.vsrlrni.w.d" => "__builtin_lsx_vsrlrni_w_d", - "llvm.loongarch.lsx.vssran.b.h" => "__builtin_lsx_vssran_b_h", - "llvm.loongarch.lsx.vssran.bu.h" => "__builtin_lsx_vssran_bu_h", - "llvm.loongarch.lsx.vssran.h.w" => "__builtin_lsx_vssran_h_w", - "llvm.loongarch.lsx.vssran.hu.w" => "__builtin_lsx_vssran_hu_w", - "llvm.loongarch.lsx.vssran.w.d" => "__builtin_lsx_vssran_w_d", - "llvm.loongarch.lsx.vssran.wu.d" => "__builtin_lsx_vssran_wu_d", - "llvm.loongarch.lsx.vssrani.b.h" => "__builtin_lsx_vssrani_b_h", - "llvm.loongarch.lsx.vssrani.bu.h" => "__builtin_lsx_vssrani_bu_h", - "llvm.loongarch.lsx.vssrani.d.q" => "__builtin_lsx_vssrani_d_q", - "llvm.loongarch.lsx.vssrani.du.q" => "__builtin_lsx_vssrani_du_q", - "llvm.loongarch.lsx.vssrani.h.w" => "__builtin_lsx_vssrani_h_w", - "llvm.loongarch.lsx.vssrani.hu.w" => "__builtin_lsx_vssrani_hu_w", - "llvm.loongarch.lsx.vssrani.w.d" => "__builtin_lsx_vssrani_w_d", - "llvm.loongarch.lsx.vssrani.wu.d" => "__builtin_lsx_vssrani_wu_d", - "llvm.loongarch.lsx.vssrarn.b.h" => "__builtin_lsx_vssrarn_b_h", - "llvm.loongarch.lsx.vssrarn.bu.h" => "__builtin_lsx_vssrarn_bu_h", - "llvm.loongarch.lsx.vssrarn.h.w" => "__builtin_lsx_vssrarn_h_w", - "llvm.loongarch.lsx.vssrarn.hu.w" => "__builtin_lsx_vssrarn_hu_w", - "llvm.loongarch.lsx.vssrarn.w.d" => "__builtin_lsx_vssrarn_w_d", - "llvm.loongarch.lsx.vssrarn.wu.d" => "__builtin_lsx_vssrarn_wu_d", - "llvm.loongarch.lsx.vssrarni.b.h" => "__builtin_lsx_vssrarni_b_h", - "llvm.loongarch.lsx.vssrarni.bu.h" => "__builtin_lsx_vssrarni_bu_h", - "llvm.loongarch.lsx.vssrarni.d.q" => "__builtin_lsx_vssrarni_d_q", - "llvm.loongarch.lsx.vssrarni.du.q" => "__builtin_lsx_vssrarni_du_q", - "llvm.loongarch.lsx.vssrarni.h.w" => "__builtin_lsx_vssrarni_h_w", - "llvm.loongarch.lsx.vssrarni.hu.w" => "__builtin_lsx_vssrarni_hu_w", - "llvm.loongarch.lsx.vssrarni.w.d" => "__builtin_lsx_vssrarni_w_d", - "llvm.loongarch.lsx.vssrarni.wu.d" => "__builtin_lsx_vssrarni_wu_d", - "llvm.loongarch.lsx.vssrln.b.h" => "__builtin_lsx_vssrln_b_h", - "llvm.loongarch.lsx.vssrln.bu.h" => "__builtin_lsx_vssrln_bu_h", - "llvm.loongarch.lsx.vssrln.h.w" => "__builtin_lsx_vssrln_h_w", - "llvm.loongarch.lsx.vssrln.hu.w" => "__builtin_lsx_vssrln_hu_w", - "llvm.loongarch.lsx.vssrln.w.d" => "__builtin_lsx_vssrln_w_d", - "llvm.loongarch.lsx.vssrln.wu.d" => "__builtin_lsx_vssrln_wu_d", - "llvm.loongarch.lsx.vssrlni.b.h" => "__builtin_lsx_vssrlni_b_h", - "llvm.loongarch.lsx.vssrlni.bu.h" => "__builtin_lsx_vssrlni_bu_h", - "llvm.loongarch.lsx.vssrlni.d.q" => "__builtin_lsx_vssrlni_d_q", - "llvm.loongarch.lsx.vssrlni.du.q" => "__builtin_lsx_vssrlni_du_q", - "llvm.loongarch.lsx.vssrlni.h.w" => "__builtin_lsx_vssrlni_h_w", - "llvm.loongarch.lsx.vssrlni.hu.w" => "__builtin_lsx_vssrlni_hu_w", - "llvm.loongarch.lsx.vssrlni.w.d" => "__builtin_lsx_vssrlni_w_d", - "llvm.loongarch.lsx.vssrlni.wu.d" => "__builtin_lsx_vssrlni_wu_d", - "llvm.loongarch.lsx.vssrlrn.b.h" => "__builtin_lsx_vssrlrn_b_h", - "llvm.loongarch.lsx.vssrlrn.bu.h" => "__builtin_lsx_vssrlrn_bu_h", - "llvm.loongarch.lsx.vssrlrn.h.w" => "__builtin_lsx_vssrlrn_h_w", - "llvm.loongarch.lsx.vssrlrn.hu.w" => "__builtin_lsx_vssrlrn_hu_w", - "llvm.loongarch.lsx.vssrlrn.w.d" => "__builtin_lsx_vssrlrn_w_d", - "llvm.loongarch.lsx.vssrlrn.wu.d" => "__builtin_lsx_vssrlrn_wu_d", - "llvm.loongarch.lsx.vssrlrni.b.h" => "__builtin_lsx_vssrlrni_b_h", - "llvm.loongarch.lsx.vssrlrni.bu.h" => "__builtin_lsx_vssrlrni_bu_h", - "llvm.loongarch.lsx.vssrlrni.d.q" => "__builtin_lsx_vssrlrni_d_q", - "llvm.loongarch.lsx.vssrlrni.du.q" => "__builtin_lsx_vssrlrni_du_q", - "llvm.loongarch.lsx.vssrlrni.h.w" => "__builtin_lsx_vssrlrni_h_w", - "llvm.loongarch.lsx.vssrlrni.hu.w" => "__builtin_lsx_vssrlrni_hu_w", - "llvm.loongarch.lsx.vssrlrni.w.d" => "__builtin_lsx_vssrlrni_w_d", - "llvm.loongarch.lsx.vssrlrni.wu.d" => "__builtin_lsx_vssrlrni_wu_d", - "llvm.loongarch.lsx.vssub.b" => "__builtin_lsx_vssub_b", - "llvm.loongarch.lsx.vssub.bu" => "__builtin_lsx_vssub_bu", - "llvm.loongarch.lsx.vssub.d" => "__builtin_lsx_vssub_d", - "llvm.loongarch.lsx.vssub.du" => "__builtin_lsx_vssub_du", - "llvm.loongarch.lsx.vssub.h" => "__builtin_lsx_vssub_h", - "llvm.loongarch.lsx.vssub.hu" => "__builtin_lsx_vssub_hu", - "llvm.loongarch.lsx.vssub.w" => "__builtin_lsx_vssub_w", - "llvm.loongarch.lsx.vssub.wu" => "__builtin_lsx_vssub_wu", - "llvm.loongarch.lsx.vst" => "__builtin_lsx_vst", - "llvm.loongarch.lsx.vstelm.b" => "__builtin_lsx_vstelm_b", - "llvm.loongarch.lsx.vstelm.d" => "__builtin_lsx_vstelm_d", - "llvm.loongarch.lsx.vstelm.h" => "__builtin_lsx_vstelm_h", - "llvm.loongarch.lsx.vstelm.w" => "__builtin_lsx_vstelm_w", - "llvm.loongarch.lsx.vstx" => "__builtin_lsx_vstx", - "llvm.loongarch.lsx.vsub.b" => "__builtin_lsx_vsub_b", - "llvm.loongarch.lsx.vsub.d" => "__builtin_lsx_vsub_d", - "llvm.loongarch.lsx.vsub.h" => "__builtin_lsx_vsub_h", - "llvm.loongarch.lsx.vsub.q" => "__builtin_lsx_vsub_q", - "llvm.loongarch.lsx.vsub.w" => "__builtin_lsx_vsub_w", - "llvm.loongarch.lsx.vsubi.bu" => "__builtin_lsx_vsubi_bu", - "llvm.loongarch.lsx.vsubi.du" => "__builtin_lsx_vsubi_du", - "llvm.loongarch.lsx.vsubi.hu" => "__builtin_lsx_vsubi_hu", - "llvm.loongarch.lsx.vsubi.wu" => "__builtin_lsx_vsubi_wu", - "llvm.loongarch.lsx.vsubwev.d.w" => "__builtin_lsx_vsubwev_d_w", - "llvm.loongarch.lsx.vsubwev.d.wu" => "__builtin_lsx_vsubwev_d_wu", - "llvm.loongarch.lsx.vsubwev.h.b" => "__builtin_lsx_vsubwev_h_b", - "llvm.loongarch.lsx.vsubwev.h.bu" => "__builtin_lsx_vsubwev_h_bu", - "llvm.loongarch.lsx.vsubwev.q.d" => "__builtin_lsx_vsubwev_q_d", - "llvm.loongarch.lsx.vsubwev.q.du" => "__builtin_lsx_vsubwev_q_du", - "llvm.loongarch.lsx.vsubwev.w.h" => "__builtin_lsx_vsubwev_w_h", - "llvm.loongarch.lsx.vsubwev.w.hu" => "__builtin_lsx_vsubwev_w_hu", - "llvm.loongarch.lsx.vsubwod.d.w" => "__builtin_lsx_vsubwod_d_w", - "llvm.loongarch.lsx.vsubwod.d.wu" => "__builtin_lsx_vsubwod_d_wu", - "llvm.loongarch.lsx.vsubwod.h.b" => "__builtin_lsx_vsubwod_h_b", - "llvm.loongarch.lsx.vsubwod.h.bu" => "__builtin_lsx_vsubwod_h_bu", - "llvm.loongarch.lsx.vsubwod.q.d" => "__builtin_lsx_vsubwod_q_d", - "llvm.loongarch.lsx.vsubwod.q.du" => "__builtin_lsx_vsubwod_q_du", - "llvm.loongarch.lsx.vsubwod.w.h" => "__builtin_lsx_vsubwod_w_h", - "llvm.loongarch.lsx.vsubwod.w.hu" => "__builtin_lsx_vsubwod_w_hu", - "llvm.loongarch.lsx.vxor.v" => "__builtin_lsx_vxor_v", - "llvm.loongarch.lsx.vxori.b" => "__builtin_lsx_vxori_b", - "llvm.loongarch.movfcsr2gr" => "__builtin_loongarch_movfcsr2gr", - "llvm.loongarch.movgr2fcsr" => "__builtin_loongarch_movgr2fcsr", - "llvm.loongarch.syscall" => "__builtin_loongarch_syscall", - // mips - "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph", - "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb", - "llvm.mips.absq.s.w" => "__builtin_mips_absq_s_w", - "llvm.mips.add.a.b" => "__builtin_msa_add_a_b", - "llvm.mips.add.a.d" => "__builtin_msa_add_a_d", - "llvm.mips.add.a.h" => "__builtin_msa_add_a_h", - "llvm.mips.add.a.w" => "__builtin_msa_add_a_w", - "llvm.mips.addq.ph" => "__builtin_mips_addq_ph", - "llvm.mips.addq.s.ph" => "__builtin_mips_addq_s_ph", - "llvm.mips.addq.s.w" => "__builtin_mips_addq_s_w", - "llvm.mips.addqh.ph" => "__builtin_mips_addqh_ph", - "llvm.mips.addqh.r.ph" => "__builtin_mips_addqh_r_ph", - "llvm.mips.addqh.r.w" => "__builtin_mips_addqh_r_w", - "llvm.mips.addqh.w" => "__builtin_mips_addqh_w", - "llvm.mips.adds.a.b" => "__builtin_msa_adds_a_b", - "llvm.mips.adds.a.d" => "__builtin_msa_adds_a_d", - "llvm.mips.adds.a.h" => "__builtin_msa_adds_a_h", - "llvm.mips.adds.a.w" => "__builtin_msa_adds_a_w", - "llvm.mips.adds.s.b" => "__builtin_msa_adds_s_b", - "llvm.mips.adds.s.d" => "__builtin_msa_adds_s_d", - "llvm.mips.adds.s.h" => "__builtin_msa_adds_s_h", - "llvm.mips.adds.s.w" => "__builtin_msa_adds_s_w", - "llvm.mips.adds.u.b" => "__builtin_msa_adds_u_b", - "llvm.mips.adds.u.d" => "__builtin_msa_adds_u_d", - "llvm.mips.adds.u.h" => "__builtin_msa_adds_u_h", - "llvm.mips.adds.u.w" => "__builtin_msa_adds_u_w", - "llvm.mips.addsc" => "__builtin_mips_addsc", - "llvm.mips.addu.ph" => "__builtin_mips_addu_ph", - "llvm.mips.addu.qb" => "__builtin_mips_addu_qb", - "llvm.mips.addu.s.ph" => "__builtin_mips_addu_s_ph", - "llvm.mips.addu.s.qb" => "__builtin_mips_addu_s_qb", - "llvm.mips.adduh.qb" => "__builtin_mips_adduh_qb", - "llvm.mips.adduh.r.qb" => "__builtin_mips_adduh_r_qb", - "llvm.mips.addv.b" => "__builtin_msa_addv_b", - "llvm.mips.addv.d" => "__builtin_msa_addv_d", - "llvm.mips.addv.h" => "__builtin_msa_addv_h", - "llvm.mips.addv.w" => "__builtin_msa_addv_w", - "llvm.mips.addvi.b" => "__builtin_msa_addvi_b", - "llvm.mips.addvi.d" => "__builtin_msa_addvi_d", - "llvm.mips.addvi.h" => "__builtin_msa_addvi_h", - "llvm.mips.addvi.w" => "__builtin_msa_addvi_w", - "llvm.mips.addwc" => "__builtin_mips_addwc", - "llvm.mips.and.v" => "__builtin_msa_and_v", - "llvm.mips.andi.b" => "__builtin_msa_andi_b", - "llvm.mips.append" => "__builtin_mips_append", - "llvm.mips.asub.s.b" => "__builtin_msa_asub_s_b", - "llvm.mips.asub.s.d" => "__builtin_msa_asub_s_d", - "llvm.mips.asub.s.h" => "__builtin_msa_asub_s_h", - "llvm.mips.asub.s.w" => "__builtin_msa_asub_s_w", - "llvm.mips.asub.u.b" => "__builtin_msa_asub_u_b", - "llvm.mips.asub.u.d" => "__builtin_msa_asub_u_d", - "llvm.mips.asub.u.h" => "__builtin_msa_asub_u_h", - "llvm.mips.asub.u.w" => "__builtin_msa_asub_u_w", - "llvm.mips.ave.s.b" => "__builtin_msa_ave_s_b", - "llvm.mips.ave.s.d" => "__builtin_msa_ave_s_d", - "llvm.mips.ave.s.h" => "__builtin_msa_ave_s_h", - "llvm.mips.ave.s.w" => "__builtin_msa_ave_s_w", - "llvm.mips.ave.u.b" => "__builtin_msa_ave_u_b", - "llvm.mips.ave.u.d" => "__builtin_msa_ave_u_d", - "llvm.mips.ave.u.h" => "__builtin_msa_ave_u_h", - "llvm.mips.ave.u.w" => "__builtin_msa_ave_u_w", - "llvm.mips.aver.s.b" => "__builtin_msa_aver_s_b", - "llvm.mips.aver.s.d" => "__builtin_msa_aver_s_d", - "llvm.mips.aver.s.h" => "__builtin_msa_aver_s_h", - "llvm.mips.aver.s.w" => "__builtin_msa_aver_s_w", - "llvm.mips.aver.u.b" => "__builtin_msa_aver_u_b", - "llvm.mips.aver.u.d" => "__builtin_msa_aver_u_d", - "llvm.mips.aver.u.h" => "__builtin_msa_aver_u_h", - "llvm.mips.aver.u.w" => "__builtin_msa_aver_u_w", - "llvm.mips.balign" => "__builtin_mips_balign", - "llvm.mips.bclr.b" => "__builtin_msa_bclr_b", - "llvm.mips.bclr.d" => "__builtin_msa_bclr_d", - "llvm.mips.bclr.h" => "__builtin_msa_bclr_h", - "llvm.mips.bclr.w" => "__builtin_msa_bclr_w", - "llvm.mips.bclri.b" => "__builtin_msa_bclri_b", - "llvm.mips.bclri.d" => "__builtin_msa_bclri_d", - "llvm.mips.bclri.h" => "__builtin_msa_bclri_h", - "llvm.mips.bclri.w" => "__builtin_msa_bclri_w", - "llvm.mips.binsl.b" => "__builtin_msa_binsl_b", - "llvm.mips.binsl.d" => "__builtin_msa_binsl_d", - "llvm.mips.binsl.h" => "__builtin_msa_binsl_h", - "llvm.mips.binsl.w" => "__builtin_msa_binsl_w", - "llvm.mips.binsli.b" => "__builtin_msa_binsli_b", - "llvm.mips.binsli.d" => "__builtin_msa_binsli_d", - "llvm.mips.binsli.h" => "__builtin_msa_binsli_h", - "llvm.mips.binsli.w" => "__builtin_msa_binsli_w", - "llvm.mips.binsr.b" => "__builtin_msa_binsr_b", - "llvm.mips.binsr.d" => "__builtin_msa_binsr_d", - "llvm.mips.binsr.h" => "__builtin_msa_binsr_h", - "llvm.mips.binsr.w" => "__builtin_msa_binsr_w", - "llvm.mips.binsri.b" => "__builtin_msa_binsri_b", - "llvm.mips.binsri.d" => "__builtin_msa_binsri_d", - "llvm.mips.binsri.h" => "__builtin_msa_binsri_h", - "llvm.mips.binsri.w" => "__builtin_msa_binsri_w", - "llvm.mips.bitrev" => "__builtin_mips_bitrev", - "llvm.mips.bmnz.v" => "__builtin_msa_bmnz_v", - "llvm.mips.bmnzi.b" => "__builtin_msa_bmnzi_b", - "llvm.mips.bmz.v" => "__builtin_msa_bmz_v", - "llvm.mips.bmzi.b" => "__builtin_msa_bmzi_b", - "llvm.mips.bneg.b" => "__builtin_msa_bneg_b", - "llvm.mips.bneg.d" => "__builtin_msa_bneg_d", - "llvm.mips.bneg.h" => "__builtin_msa_bneg_h", - "llvm.mips.bneg.w" => "__builtin_msa_bneg_w", - "llvm.mips.bnegi.b" => "__builtin_msa_bnegi_b", - "llvm.mips.bnegi.d" => "__builtin_msa_bnegi_d", - "llvm.mips.bnegi.h" => "__builtin_msa_bnegi_h", - "llvm.mips.bnegi.w" => "__builtin_msa_bnegi_w", - "llvm.mips.bnz.b" => "__builtin_msa_bnz_b", - "llvm.mips.bnz.d" => "__builtin_msa_bnz_d", - "llvm.mips.bnz.h" => "__builtin_msa_bnz_h", - "llvm.mips.bnz.v" => "__builtin_msa_bnz_v", - "llvm.mips.bnz.w" => "__builtin_msa_bnz_w", - "llvm.mips.bposge32" => "__builtin_mips_bposge32", - "llvm.mips.bsel.v" => "__builtin_msa_bsel_v", - "llvm.mips.bseli.b" => "__builtin_msa_bseli_b", - "llvm.mips.bset.b" => "__builtin_msa_bset_b", - "llvm.mips.bset.d" => "__builtin_msa_bset_d", - "llvm.mips.bset.h" => "__builtin_msa_bset_h", - "llvm.mips.bset.w" => "__builtin_msa_bset_w", - "llvm.mips.bseti.b" => "__builtin_msa_bseti_b", - "llvm.mips.bseti.d" => "__builtin_msa_bseti_d", - "llvm.mips.bseti.h" => "__builtin_msa_bseti_h", - "llvm.mips.bseti.w" => "__builtin_msa_bseti_w", - "llvm.mips.bz.b" => "__builtin_msa_bz_b", - "llvm.mips.bz.d" => "__builtin_msa_bz_d", - "llvm.mips.bz.h" => "__builtin_msa_bz_h", - "llvm.mips.bz.v" => "__builtin_msa_bz_v", - "llvm.mips.bz.w" => "__builtin_msa_bz_w", - "llvm.mips.ceq.b" => "__builtin_msa_ceq_b", - "llvm.mips.ceq.d" => "__builtin_msa_ceq_d", - "llvm.mips.ceq.h" => "__builtin_msa_ceq_h", - "llvm.mips.ceq.w" => "__builtin_msa_ceq_w", - "llvm.mips.ceqi.b" => "__builtin_msa_ceqi_b", - "llvm.mips.ceqi.d" => "__builtin_msa_ceqi_d", - "llvm.mips.ceqi.h" => "__builtin_msa_ceqi_h", - "llvm.mips.ceqi.w" => "__builtin_msa_ceqi_w", - "llvm.mips.cfcmsa" => "__builtin_msa_cfcmsa", - "llvm.mips.cle.s.b" => "__builtin_msa_cle_s_b", - "llvm.mips.cle.s.d" => "__builtin_msa_cle_s_d", - "llvm.mips.cle.s.h" => "__builtin_msa_cle_s_h", - "llvm.mips.cle.s.w" => "__builtin_msa_cle_s_w", - "llvm.mips.cle.u.b" => "__builtin_msa_cle_u_b", - "llvm.mips.cle.u.d" => "__builtin_msa_cle_u_d", - "llvm.mips.cle.u.h" => "__builtin_msa_cle_u_h", - "llvm.mips.cle.u.w" => "__builtin_msa_cle_u_w", - "llvm.mips.clei.s.b" => "__builtin_msa_clei_s_b", - "llvm.mips.clei.s.d" => "__builtin_msa_clei_s_d", - "llvm.mips.clei.s.h" => "__builtin_msa_clei_s_h", - "llvm.mips.clei.s.w" => "__builtin_msa_clei_s_w", - "llvm.mips.clei.u.b" => "__builtin_msa_clei_u_b", - "llvm.mips.clei.u.d" => "__builtin_msa_clei_u_d", - "llvm.mips.clei.u.h" => "__builtin_msa_clei_u_h", - "llvm.mips.clei.u.w" => "__builtin_msa_clei_u_w", - "llvm.mips.clt.s.b" => "__builtin_msa_clt_s_b", - "llvm.mips.clt.s.d" => "__builtin_msa_clt_s_d", - "llvm.mips.clt.s.h" => "__builtin_msa_clt_s_h", - "llvm.mips.clt.s.w" => "__builtin_msa_clt_s_w", - "llvm.mips.clt.u.b" => "__builtin_msa_clt_u_b", - "llvm.mips.clt.u.d" => "__builtin_msa_clt_u_d", - "llvm.mips.clt.u.h" => "__builtin_msa_clt_u_h", - "llvm.mips.clt.u.w" => "__builtin_msa_clt_u_w", - "llvm.mips.clti.s.b" => "__builtin_msa_clti_s_b", - "llvm.mips.clti.s.d" => "__builtin_msa_clti_s_d", - "llvm.mips.clti.s.h" => "__builtin_msa_clti_s_h", - "llvm.mips.clti.s.w" => "__builtin_msa_clti_s_w", - "llvm.mips.clti.u.b" => "__builtin_msa_clti_u_b", - "llvm.mips.clti.u.d" => "__builtin_msa_clti_u_d", - "llvm.mips.clti.u.h" => "__builtin_msa_clti_u_h", - "llvm.mips.clti.u.w" => "__builtin_msa_clti_u_w", - "llvm.mips.cmp.eq.ph" => "__builtin_mips_cmp_eq_ph", - "llvm.mips.cmp.le.ph" => "__builtin_mips_cmp_le_ph", - "llvm.mips.cmp.lt.ph" => "__builtin_mips_cmp_lt_ph", - "llvm.mips.cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb", - "llvm.mips.cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb", - "llvm.mips.cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb", - "llvm.mips.cmpgu.eq.qb" => "__builtin_mips_cmpgu_eq_qb", - "llvm.mips.cmpgu.le.qb" => "__builtin_mips_cmpgu_le_qb", - "llvm.mips.cmpgu.lt.qb" => "__builtin_mips_cmpgu_lt_qb", - "llvm.mips.cmpu.eq.qb" => "__builtin_mips_cmpu_eq_qb", - "llvm.mips.cmpu.le.qb" => "__builtin_mips_cmpu_le_qb", - "llvm.mips.cmpu.lt.qb" => "__builtin_mips_cmpu_lt_qb", - "llvm.mips.copy.s.b" => "__builtin_msa_copy_s_b", - "llvm.mips.copy.s.d" => "__builtin_msa_copy_s_d", - "llvm.mips.copy.s.h" => "__builtin_msa_copy_s_h", - "llvm.mips.copy.s.w" => "__builtin_msa_copy_s_w", - "llvm.mips.copy.u.b" => "__builtin_msa_copy_u_b", - "llvm.mips.copy.u.d" => "__builtin_msa_copy_u_d", - "llvm.mips.copy.u.h" => "__builtin_msa_copy_u_h", - "llvm.mips.copy.u.w" => "__builtin_msa_copy_u_w", - "llvm.mips.ctcmsa" => "__builtin_msa_ctcmsa", - "llvm.mips.div.s.b" => "__builtin_msa_div_s_b", - "llvm.mips.div.s.d" => "__builtin_msa_div_s_d", - "llvm.mips.div.s.h" => "__builtin_msa_div_s_h", - "llvm.mips.div.s.w" => "__builtin_msa_div_s_w", - "llvm.mips.div.u.b" => "__builtin_msa_div_u_b", - "llvm.mips.div.u.d" => "__builtin_msa_div_u_d", - "llvm.mips.div.u.h" => "__builtin_msa_div_u_h", - "llvm.mips.div.u.w" => "__builtin_msa_div_u_w", - "llvm.mips.dlsa" => "__builtin_mips_dlsa", - "llvm.mips.dotp.s.d" => "__builtin_msa_dotp_s_d", - "llvm.mips.dotp.s.h" => "__builtin_msa_dotp_s_h", - "llvm.mips.dotp.s.w" => "__builtin_msa_dotp_s_w", - "llvm.mips.dotp.u.d" => "__builtin_msa_dotp_u_d", - "llvm.mips.dotp.u.h" => "__builtin_msa_dotp_u_h", - "llvm.mips.dotp.u.w" => "__builtin_msa_dotp_u_w", - "llvm.mips.dpa.w.ph" => "__builtin_mips_dpa_w_ph", - "llvm.mips.dpadd.s.d" => "__builtin_msa_dpadd_s_d", - "llvm.mips.dpadd.s.h" => "__builtin_msa_dpadd_s_h", - "llvm.mips.dpadd.s.w" => "__builtin_msa_dpadd_s_w", - "llvm.mips.dpadd.u.d" => "__builtin_msa_dpadd_u_d", - "llvm.mips.dpadd.u.h" => "__builtin_msa_dpadd_u_h", - "llvm.mips.dpadd.u.w" => "__builtin_msa_dpadd_u_w", - "llvm.mips.dpaq.s.w.ph" => "__builtin_mips_dpaq_s_w_ph", - "llvm.mips.dpaq.sa.l.w" => "__builtin_mips_dpaq_sa_l_w", - "llvm.mips.dpaqx.s.w.ph" => "__builtin_mips_dpaqx_s_w_ph", - "llvm.mips.dpaqx.sa.w.ph" => "__builtin_mips_dpaqx_sa_w_ph", - "llvm.mips.dpau.h.qbl" => "__builtin_mips_dpau_h_qbl", - "llvm.mips.dpau.h.qbr" => "__builtin_mips_dpau_h_qbr", - "llvm.mips.dpax.w.ph" => "__builtin_mips_dpax_w_ph", - "llvm.mips.dps.w.ph" => "__builtin_mips_dps_w_ph", - "llvm.mips.dpsq.s.w.ph" => "__builtin_mips_dpsq_s_w_ph", - "llvm.mips.dpsq.sa.l.w" => "__builtin_mips_dpsq_sa_l_w", - "llvm.mips.dpsqx.s.w.ph" => "__builtin_mips_dpsqx_s_w_ph", - "llvm.mips.dpsqx.sa.w.ph" => "__builtin_mips_dpsqx_sa_w_ph", - "llvm.mips.dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl", - "llvm.mips.dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr", - "llvm.mips.dpsub.s.d" => "__builtin_msa_dpsub_s_d", - "llvm.mips.dpsub.s.h" => "__builtin_msa_dpsub_s_h", - "llvm.mips.dpsub.s.w" => "__builtin_msa_dpsub_s_w", - "llvm.mips.dpsub.u.d" => "__builtin_msa_dpsub_u_d", - "llvm.mips.dpsub.u.h" => "__builtin_msa_dpsub_u_h", - "llvm.mips.dpsub.u.w" => "__builtin_msa_dpsub_u_w", - "llvm.mips.dpsx.w.ph" => "__builtin_mips_dpsx_w_ph", - "llvm.mips.extp" => "__builtin_mips_extp", - "llvm.mips.extpdp" => "__builtin_mips_extpdp", - "llvm.mips.extr.r.w" => "__builtin_mips_extr_r_w", - "llvm.mips.extr.rs.w" => "__builtin_mips_extr_rs_w", - "llvm.mips.extr.s.h" => "__builtin_mips_extr_s_h", - "llvm.mips.extr.w" => "__builtin_mips_extr_w", - "llvm.mips.fadd.d" => "__builtin_msa_fadd_d", - "llvm.mips.fadd.w" => "__builtin_msa_fadd_w", - "llvm.mips.fcaf.d" => "__builtin_msa_fcaf_d", - "llvm.mips.fcaf.w" => "__builtin_msa_fcaf_w", - "llvm.mips.fceq.d" => "__builtin_msa_fceq_d", - "llvm.mips.fceq.w" => "__builtin_msa_fceq_w", - "llvm.mips.fclass.d" => "__builtin_msa_fclass_d", - "llvm.mips.fclass.w" => "__builtin_msa_fclass_w", - "llvm.mips.fcle.d" => "__builtin_msa_fcle_d", - "llvm.mips.fcle.w" => "__builtin_msa_fcle_w", - "llvm.mips.fclt.d" => "__builtin_msa_fclt_d", - "llvm.mips.fclt.w" => "__builtin_msa_fclt_w", - "llvm.mips.fcne.d" => "__builtin_msa_fcne_d", - "llvm.mips.fcne.w" => "__builtin_msa_fcne_w", - "llvm.mips.fcor.d" => "__builtin_msa_fcor_d", - "llvm.mips.fcor.w" => "__builtin_msa_fcor_w", - "llvm.mips.fcueq.d" => "__builtin_msa_fcueq_d", - "llvm.mips.fcueq.w" => "__builtin_msa_fcueq_w", - "llvm.mips.fcule.d" => "__builtin_msa_fcule_d", - "llvm.mips.fcule.w" => "__builtin_msa_fcule_w", - "llvm.mips.fcult.d" => "__builtin_msa_fcult_d", - "llvm.mips.fcult.w" => "__builtin_msa_fcult_w", - "llvm.mips.fcun.d" => "__builtin_msa_fcun_d", - "llvm.mips.fcun.w" => "__builtin_msa_fcun_w", - "llvm.mips.fcune.d" => "__builtin_msa_fcune_d", - "llvm.mips.fcune.w" => "__builtin_msa_fcune_w", - "llvm.mips.fdiv.d" => "__builtin_msa_fdiv_d", - "llvm.mips.fdiv.w" => "__builtin_msa_fdiv_w", - "llvm.mips.fexdo.h" => "__builtin_msa_fexdo_h", - "llvm.mips.fexdo.w" => "__builtin_msa_fexdo_w", - "llvm.mips.fexp2.d" => "__builtin_msa_fexp2_d", - "llvm.mips.fexp2.w" => "__builtin_msa_fexp2_w", - "llvm.mips.fexupl.d" => "__builtin_msa_fexupl_d", - "llvm.mips.fexupl.w" => "__builtin_msa_fexupl_w", - "llvm.mips.fexupr.d" => "__builtin_msa_fexupr_d", - "llvm.mips.fexupr.w" => "__builtin_msa_fexupr_w", - "llvm.mips.ffint.s.d" => "__builtin_msa_ffint_s_d", - "llvm.mips.ffint.s.w" => "__builtin_msa_ffint_s_w", - "llvm.mips.ffint.u.d" => "__builtin_msa_ffint_u_d", - "llvm.mips.ffint.u.w" => "__builtin_msa_ffint_u_w", - "llvm.mips.ffql.d" => "__builtin_msa_ffql_d", - "llvm.mips.ffql.w" => "__builtin_msa_ffql_w", - "llvm.mips.ffqr.d" => "__builtin_msa_ffqr_d", - "llvm.mips.ffqr.w" => "__builtin_msa_ffqr_w", - "llvm.mips.fill.b" => "__builtin_msa_fill_b", - "llvm.mips.fill.d" => "__builtin_msa_fill_d", - "llvm.mips.fill.h" => "__builtin_msa_fill_h", - "llvm.mips.fill.w" => "__builtin_msa_fill_w", - "llvm.mips.flog2.d" => "__builtin_msa_flog2_d", - "llvm.mips.flog2.w" => "__builtin_msa_flog2_w", - "llvm.mips.fmadd.d" => "__builtin_msa_fmadd_d", - "llvm.mips.fmadd.w" => "__builtin_msa_fmadd_w", - "llvm.mips.fmax.a.d" => "__builtin_msa_fmax_a_d", - "llvm.mips.fmax.a.w" => "__builtin_msa_fmax_a_w", - "llvm.mips.fmax.d" => "__builtin_msa_fmax_d", - "llvm.mips.fmax.w" => "__builtin_msa_fmax_w", - "llvm.mips.fmin.a.d" => "__builtin_msa_fmin_a_d", - "llvm.mips.fmin.a.w" => "__builtin_msa_fmin_a_w", - "llvm.mips.fmin.d" => "__builtin_msa_fmin_d", - "llvm.mips.fmin.w" => "__builtin_msa_fmin_w", - "llvm.mips.fmsub.d" => "__builtin_msa_fmsub_d", - "llvm.mips.fmsub.w" => "__builtin_msa_fmsub_w", - "llvm.mips.fmul.d" => "__builtin_msa_fmul_d", - "llvm.mips.fmul.w" => "__builtin_msa_fmul_w", - "llvm.mips.frcp.d" => "__builtin_msa_frcp_d", - "llvm.mips.frcp.w" => "__builtin_msa_frcp_w", - "llvm.mips.frint.d" => "__builtin_msa_frint_d", - "llvm.mips.frint.w" => "__builtin_msa_frint_w", - "llvm.mips.frsqrt.d" => "__builtin_msa_frsqrt_d", - "llvm.mips.frsqrt.w" => "__builtin_msa_frsqrt_w", - "llvm.mips.fsaf.d" => "__builtin_msa_fsaf_d", - "llvm.mips.fsaf.w" => "__builtin_msa_fsaf_w", - "llvm.mips.fseq.d" => "__builtin_msa_fseq_d", - "llvm.mips.fseq.w" => "__builtin_msa_fseq_w", - "llvm.mips.fsle.d" => "__builtin_msa_fsle_d", - "llvm.mips.fsle.w" => "__builtin_msa_fsle_w", - "llvm.mips.fslt.d" => "__builtin_msa_fslt_d", - "llvm.mips.fslt.w" => "__builtin_msa_fslt_w", - "llvm.mips.fsne.d" => "__builtin_msa_fsne_d", - "llvm.mips.fsne.w" => "__builtin_msa_fsne_w", - "llvm.mips.fsor.d" => "__builtin_msa_fsor_d", - "llvm.mips.fsor.w" => "__builtin_msa_fsor_w", - "llvm.mips.fsqrt.d" => "__builtin_msa_fsqrt_d", - "llvm.mips.fsqrt.w" => "__builtin_msa_fsqrt_w", - "llvm.mips.fsub.d" => "__builtin_msa_fsub_d", - "llvm.mips.fsub.w" => "__builtin_msa_fsub_w", - "llvm.mips.fsueq.d" => "__builtin_msa_fsueq_d", - "llvm.mips.fsueq.w" => "__builtin_msa_fsueq_w", - "llvm.mips.fsule.d" => "__builtin_msa_fsule_d", - "llvm.mips.fsule.w" => "__builtin_msa_fsule_w", - "llvm.mips.fsult.d" => "__builtin_msa_fsult_d", - "llvm.mips.fsult.w" => "__builtin_msa_fsult_w", - "llvm.mips.fsun.d" => "__builtin_msa_fsun_d", - "llvm.mips.fsun.w" => "__builtin_msa_fsun_w", - "llvm.mips.fsune.d" => "__builtin_msa_fsune_d", - "llvm.mips.fsune.w" => "__builtin_msa_fsune_w", - "llvm.mips.ftint.s.d" => "__builtin_msa_ftint_s_d", - "llvm.mips.ftint.s.w" => "__builtin_msa_ftint_s_w", - "llvm.mips.ftint.u.d" => "__builtin_msa_ftint_u_d", - "llvm.mips.ftint.u.w" => "__builtin_msa_ftint_u_w", - "llvm.mips.ftq.h" => "__builtin_msa_ftq_h", - "llvm.mips.ftq.w" => "__builtin_msa_ftq_w", - "llvm.mips.ftrunc.s.d" => "__builtin_msa_ftrunc_s_d", - "llvm.mips.ftrunc.s.w" => "__builtin_msa_ftrunc_s_w", - "llvm.mips.ftrunc.u.d" => "__builtin_msa_ftrunc_u_d", - "llvm.mips.ftrunc.u.w" => "__builtin_msa_ftrunc_u_w", - "llvm.mips.hadd.s.d" => "__builtin_msa_hadd_s_d", - "llvm.mips.hadd.s.h" => "__builtin_msa_hadd_s_h", - "llvm.mips.hadd.s.w" => "__builtin_msa_hadd_s_w", - "llvm.mips.hadd.u.d" => "__builtin_msa_hadd_u_d", - "llvm.mips.hadd.u.h" => "__builtin_msa_hadd_u_h", - "llvm.mips.hadd.u.w" => "__builtin_msa_hadd_u_w", - "llvm.mips.hsub.s.d" => "__builtin_msa_hsub_s_d", - "llvm.mips.hsub.s.h" => "__builtin_msa_hsub_s_h", - "llvm.mips.hsub.s.w" => "__builtin_msa_hsub_s_w", - "llvm.mips.hsub.u.d" => "__builtin_msa_hsub_u_d", - "llvm.mips.hsub.u.h" => "__builtin_msa_hsub_u_h", - "llvm.mips.hsub.u.w" => "__builtin_msa_hsub_u_w", - "llvm.mips.ilvev.b" => "__builtin_msa_ilvev_b", - "llvm.mips.ilvev.d" => "__builtin_msa_ilvev_d", - "llvm.mips.ilvev.h" => "__builtin_msa_ilvev_h", - "llvm.mips.ilvev.w" => "__builtin_msa_ilvev_w", - "llvm.mips.ilvl.b" => "__builtin_msa_ilvl_b", - "llvm.mips.ilvl.d" => "__builtin_msa_ilvl_d", - "llvm.mips.ilvl.h" => "__builtin_msa_ilvl_h", - "llvm.mips.ilvl.w" => "__builtin_msa_ilvl_w", - "llvm.mips.ilvod.b" => "__builtin_msa_ilvod_b", - "llvm.mips.ilvod.d" => "__builtin_msa_ilvod_d", - "llvm.mips.ilvod.h" => "__builtin_msa_ilvod_h", - "llvm.mips.ilvod.w" => "__builtin_msa_ilvod_w", - "llvm.mips.ilvr.b" => "__builtin_msa_ilvr_b", - "llvm.mips.ilvr.d" => "__builtin_msa_ilvr_d", - "llvm.mips.ilvr.h" => "__builtin_msa_ilvr_h", - "llvm.mips.ilvr.w" => "__builtin_msa_ilvr_w", - "llvm.mips.insert.b" => "__builtin_msa_insert_b", - "llvm.mips.insert.d" => "__builtin_msa_insert_d", - "llvm.mips.insert.h" => "__builtin_msa_insert_h", - "llvm.mips.insert.w" => "__builtin_msa_insert_w", - "llvm.mips.insv" => "__builtin_mips_insv", - "llvm.mips.insve.b" => "__builtin_msa_insve_b", - "llvm.mips.insve.d" => "__builtin_msa_insve_d", - "llvm.mips.insve.h" => "__builtin_msa_insve_h", - "llvm.mips.insve.w" => "__builtin_msa_insve_w", - "llvm.mips.lbux" => "__builtin_mips_lbux", - "llvm.mips.ld.b" => "__builtin_msa_ld_b", - "llvm.mips.ld.d" => "__builtin_msa_ld_d", - "llvm.mips.ld.h" => "__builtin_msa_ld_h", - "llvm.mips.ld.w" => "__builtin_msa_ld_w", - "llvm.mips.ldi.b" => "__builtin_msa_ldi_b", - "llvm.mips.ldi.d" => "__builtin_msa_ldi_d", - "llvm.mips.ldi.h" => "__builtin_msa_ldi_h", - "llvm.mips.ldi.w" => "__builtin_msa_ldi_w", - "llvm.mips.ldr.d" => "__builtin_msa_ldr_d", - "llvm.mips.ldr.w" => "__builtin_msa_ldr_w", - "llvm.mips.lhx" => "__builtin_mips_lhx", - "llvm.mips.lsa" => "__builtin_mips_lsa", - "llvm.mips.lwx" => "__builtin_mips_lwx", - "llvm.mips.madd" => "__builtin_mips_madd", - "llvm.mips.madd.q.h" => "__builtin_msa_madd_q_h", - "llvm.mips.madd.q.w" => "__builtin_msa_madd_q_w", - "llvm.mips.maddr.q.h" => "__builtin_msa_maddr_q_h", - "llvm.mips.maddr.q.w" => "__builtin_msa_maddr_q_w", - "llvm.mips.maddu" => "__builtin_mips_maddu", - "llvm.mips.maddv.b" => "__builtin_msa_maddv_b", - "llvm.mips.maddv.d" => "__builtin_msa_maddv_d", - "llvm.mips.maddv.h" => "__builtin_msa_maddv_h", - "llvm.mips.maddv.w" => "__builtin_msa_maddv_w", - "llvm.mips.maq.s.w.phl" => "__builtin_mips_maq_s_w_phl", - "llvm.mips.maq.s.w.phr" => "__builtin_mips_maq_s_w_phr", - "llvm.mips.maq.sa.w.phl" => "__builtin_mips_maq_sa_w_phl", - "llvm.mips.maq.sa.w.phr" => "__builtin_mips_maq_sa_w_phr", - "llvm.mips.max.a.b" => "__builtin_msa_max_a_b", - "llvm.mips.max.a.d" => "__builtin_msa_max_a_d", - "llvm.mips.max.a.h" => "__builtin_msa_max_a_h", - "llvm.mips.max.a.w" => "__builtin_msa_max_a_w", - "llvm.mips.max.s.b" => "__builtin_msa_max_s_b", - "llvm.mips.max.s.d" => "__builtin_msa_max_s_d", - "llvm.mips.max.s.h" => "__builtin_msa_max_s_h", - "llvm.mips.max.s.w" => "__builtin_msa_max_s_w", - "llvm.mips.max.u.b" => "__builtin_msa_max_u_b", - "llvm.mips.max.u.d" => "__builtin_msa_max_u_d", - "llvm.mips.max.u.h" => "__builtin_msa_max_u_h", - "llvm.mips.max.u.w" => "__builtin_msa_max_u_w", - "llvm.mips.maxi.s.b" => "__builtin_msa_maxi_s_b", - "llvm.mips.maxi.s.d" => "__builtin_msa_maxi_s_d", - "llvm.mips.maxi.s.h" => "__builtin_msa_maxi_s_h", - "llvm.mips.maxi.s.w" => "__builtin_msa_maxi_s_w", - "llvm.mips.maxi.u.b" => "__builtin_msa_maxi_u_b", - "llvm.mips.maxi.u.d" => "__builtin_msa_maxi_u_d", - "llvm.mips.maxi.u.h" => "__builtin_msa_maxi_u_h", - "llvm.mips.maxi.u.w" => "__builtin_msa_maxi_u_w", - "llvm.mips.min.a.b" => "__builtin_msa_min_a_b", - "llvm.mips.min.a.d" => "__builtin_msa_min_a_d", - "llvm.mips.min.a.h" => "__builtin_msa_min_a_h", - "llvm.mips.min.a.w" => "__builtin_msa_min_a_w", - "llvm.mips.min.s.b" => "__builtin_msa_min_s_b", - "llvm.mips.min.s.d" => "__builtin_msa_min_s_d", - "llvm.mips.min.s.h" => "__builtin_msa_min_s_h", - "llvm.mips.min.s.w" => "__builtin_msa_min_s_w", - "llvm.mips.min.u.b" => "__builtin_msa_min_u_b", - "llvm.mips.min.u.d" => "__builtin_msa_min_u_d", - "llvm.mips.min.u.h" => "__builtin_msa_min_u_h", - "llvm.mips.min.u.w" => "__builtin_msa_min_u_w", - "llvm.mips.mini.s.b" => "__builtin_msa_mini_s_b", - "llvm.mips.mini.s.d" => "__builtin_msa_mini_s_d", - "llvm.mips.mini.s.h" => "__builtin_msa_mini_s_h", - "llvm.mips.mini.s.w" => "__builtin_msa_mini_s_w", - "llvm.mips.mini.u.b" => "__builtin_msa_mini_u_b", - "llvm.mips.mini.u.d" => "__builtin_msa_mini_u_d", - "llvm.mips.mini.u.h" => "__builtin_msa_mini_u_h", - "llvm.mips.mini.u.w" => "__builtin_msa_mini_u_w", - "llvm.mips.mod.s.b" => "__builtin_msa_mod_s_b", - "llvm.mips.mod.s.d" => "__builtin_msa_mod_s_d", - "llvm.mips.mod.s.h" => "__builtin_msa_mod_s_h", - "llvm.mips.mod.s.w" => "__builtin_msa_mod_s_w", - "llvm.mips.mod.u.b" => "__builtin_msa_mod_u_b", - "llvm.mips.mod.u.d" => "__builtin_msa_mod_u_d", - "llvm.mips.mod.u.h" => "__builtin_msa_mod_u_h", - "llvm.mips.mod.u.w" => "__builtin_msa_mod_u_w", - "llvm.mips.modsub" => "__builtin_mips_modsub", - "llvm.mips.move.v" => "__builtin_msa_move_v", - "llvm.mips.msub" => "__builtin_mips_msub", - "llvm.mips.msub.q.h" => "__builtin_msa_msub_q_h", - "llvm.mips.msub.q.w" => "__builtin_msa_msub_q_w", - "llvm.mips.msubr.q.h" => "__builtin_msa_msubr_q_h", - "llvm.mips.msubr.q.w" => "__builtin_msa_msubr_q_w", - "llvm.mips.msubu" => "__builtin_mips_msubu", - "llvm.mips.msubv.b" => "__builtin_msa_msubv_b", - "llvm.mips.msubv.d" => "__builtin_msa_msubv_d", - "llvm.mips.msubv.h" => "__builtin_msa_msubv_h", - "llvm.mips.msubv.w" => "__builtin_msa_msubv_w", - "llvm.mips.mthlip" => "__builtin_mips_mthlip", - "llvm.mips.mul.ph" => "__builtin_mips_mul_ph", - "llvm.mips.mul.q.h" => "__builtin_msa_mul_q_h", - "llvm.mips.mul.q.w" => "__builtin_msa_mul_q_w", - "llvm.mips.mul.s.ph" => "__builtin_mips_mul_s_ph", - "llvm.mips.muleq.s.w.phl" => "__builtin_mips_muleq_s_w_phl", - "llvm.mips.muleq.s.w.phr" => "__builtin_mips_muleq_s_w_phr", - "llvm.mips.muleu.s.ph.qbl" => "__builtin_mips_muleu_s_ph_qbl", - "llvm.mips.muleu.s.ph.qbr" => "__builtin_mips_muleu_s_ph_qbr", - "llvm.mips.mulq.rs.ph" => "__builtin_mips_mulq_rs_ph", - "llvm.mips.mulq.rs.w" => "__builtin_mips_mulq_rs_w", - "llvm.mips.mulq.s.ph" => "__builtin_mips_mulq_s_ph", - "llvm.mips.mulq.s.w" => "__builtin_mips_mulq_s_w", - "llvm.mips.mulr.q.h" => "__builtin_msa_mulr_q_h", - "llvm.mips.mulr.q.w" => "__builtin_msa_mulr_q_w", - "llvm.mips.mulsa.w.ph" => "__builtin_mips_mulsa_w_ph", - "llvm.mips.mulsaq.s.w.ph" => "__builtin_mips_mulsaq_s_w_ph", - "llvm.mips.mult" => "__builtin_mips_mult", - "llvm.mips.multu" => "__builtin_mips_multu", - "llvm.mips.mulv.b" => "__builtin_msa_mulv_b", - "llvm.mips.mulv.d" => "__builtin_msa_mulv_d", - "llvm.mips.mulv.h" => "__builtin_msa_mulv_h", - "llvm.mips.mulv.w" => "__builtin_msa_mulv_w", - "llvm.mips.nloc.b" => "__builtin_msa_nloc_b", - "llvm.mips.nloc.d" => "__builtin_msa_nloc_d", - "llvm.mips.nloc.h" => "__builtin_msa_nloc_h", - "llvm.mips.nloc.w" => "__builtin_msa_nloc_w", - "llvm.mips.nlzc.b" => "__builtin_msa_nlzc_b", - "llvm.mips.nlzc.d" => "__builtin_msa_nlzc_d", - "llvm.mips.nlzc.h" => "__builtin_msa_nlzc_h", - "llvm.mips.nlzc.w" => "__builtin_msa_nlzc_w", - "llvm.mips.nor.v" => "__builtin_msa_nor_v", - "llvm.mips.nori.b" => "__builtin_msa_nori_b", - "llvm.mips.or.v" => "__builtin_msa_or_v", - "llvm.mips.ori.b" => "__builtin_msa_ori_b", - "llvm.mips.packrl.ph" => "__builtin_mips_packrl_ph", - "llvm.mips.pckev.b" => "__builtin_msa_pckev_b", - "llvm.mips.pckev.d" => "__builtin_msa_pckev_d", - "llvm.mips.pckev.h" => "__builtin_msa_pckev_h", - "llvm.mips.pckev.w" => "__builtin_msa_pckev_w", - "llvm.mips.pckod.b" => "__builtin_msa_pckod_b", - "llvm.mips.pckod.d" => "__builtin_msa_pckod_d", - "llvm.mips.pckod.h" => "__builtin_msa_pckod_h", - "llvm.mips.pckod.w" => "__builtin_msa_pckod_w", - "llvm.mips.pcnt.b" => "__builtin_msa_pcnt_b", - "llvm.mips.pcnt.d" => "__builtin_msa_pcnt_d", - "llvm.mips.pcnt.h" => "__builtin_msa_pcnt_h", - "llvm.mips.pcnt.w" => "__builtin_msa_pcnt_w", - "llvm.mips.pick.ph" => "__builtin_mips_pick_ph", - "llvm.mips.pick.qb" => "__builtin_mips_pick_qb", - "llvm.mips.preceq.w.phl" => "__builtin_mips_preceq_w_phl", - "llvm.mips.preceq.w.phr" => "__builtin_mips_preceq_w_phr", - "llvm.mips.precequ.ph.qbl" => "__builtin_mips_precequ_ph_qbl", - "llvm.mips.precequ.ph.qbla" => "__builtin_mips_precequ_ph_qbla", - "llvm.mips.precequ.ph.qbr" => "__builtin_mips_precequ_ph_qbr", - "llvm.mips.precequ.ph.qbra" => "__builtin_mips_precequ_ph_qbra", - "llvm.mips.preceu.ph.qbl" => "__builtin_mips_preceu_ph_qbl", - "llvm.mips.preceu.ph.qbla" => "__builtin_mips_preceu_ph_qbla", - "llvm.mips.preceu.ph.qbr" => "__builtin_mips_preceu_ph_qbr", - "llvm.mips.preceu.ph.qbra" => "__builtin_mips_preceu_ph_qbra", - "llvm.mips.precr.qb.ph" => "__builtin_mips_precr_qb_ph", - "llvm.mips.precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w", - "llvm.mips.precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w", - "llvm.mips.precrq.ph.w" => "__builtin_mips_precrq_ph_w", - "llvm.mips.precrq.qb.ph" => "__builtin_mips_precrq_qb_ph", - "llvm.mips.precrq.rs.ph.w" => "__builtin_mips_precrq_rs_ph_w", - "llvm.mips.precrqu.s.qb.ph" => "__builtin_mips_precrqu_s_qb_ph", - "llvm.mips.prepend" => "__builtin_mips_prepend", - "llvm.mips.raddu.w.qb" => "__builtin_mips_raddu_w_qb", - "llvm.mips.rddsp" => "__builtin_mips_rddsp", - "llvm.mips.repl.ph" => "__builtin_mips_repl_ph", - "llvm.mips.repl.qb" => "__builtin_mips_repl_qb", - "llvm.mips.sat.s.b" => "__builtin_msa_sat_s_b", - "llvm.mips.sat.s.d" => "__builtin_msa_sat_s_d", - "llvm.mips.sat.s.h" => "__builtin_msa_sat_s_h", - "llvm.mips.sat.s.w" => "__builtin_msa_sat_s_w", - "llvm.mips.sat.u.b" => "__builtin_msa_sat_u_b", - "llvm.mips.sat.u.d" => "__builtin_msa_sat_u_d", - "llvm.mips.sat.u.h" => "__builtin_msa_sat_u_h", - "llvm.mips.sat.u.w" => "__builtin_msa_sat_u_w", - "llvm.mips.shf.b" => "__builtin_msa_shf_b", - "llvm.mips.shf.h" => "__builtin_msa_shf_h", - "llvm.mips.shf.w" => "__builtin_msa_shf_w", - "llvm.mips.shilo" => "__builtin_mips_shilo", - "llvm.mips.shll.ph" => "__builtin_mips_shll_ph", - "llvm.mips.shll.qb" => "__builtin_mips_shll_qb", - "llvm.mips.shll.s.ph" => "__builtin_mips_shll_s_ph", - "llvm.mips.shll.s.w" => "__builtin_mips_shll_s_w", - "llvm.mips.shra.ph" => "__builtin_mips_shra_ph", - "llvm.mips.shra.qb" => "__builtin_mips_shra_qb", - "llvm.mips.shra.r.ph" => "__builtin_mips_shra_r_ph", - "llvm.mips.shra.r.qb" => "__builtin_mips_shra_r_qb", - "llvm.mips.shra.r.w" => "__builtin_mips_shra_r_w", - "llvm.mips.shrl.ph" => "__builtin_mips_shrl_ph", - "llvm.mips.shrl.qb" => "__builtin_mips_shrl_qb", - "llvm.mips.sld.b" => "__builtin_msa_sld_b", - "llvm.mips.sld.d" => "__builtin_msa_sld_d", - "llvm.mips.sld.h" => "__builtin_msa_sld_h", - "llvm.mips.sld.w" => "__builtin_msa_sld_w", - "llvm.mips.sldi.b" => "__builtin_msa_sldi_b", - "llvm.mips.sldi.d" => "__builtin_msa_sldi_d", - "llvm.mips.sldi.h" => "__builtin_msa_sldi_h", - "llvm.mips.sldi.w" => "__builtin_msa_sldi_w", - "llvm.mips.sll.b" => "__builtin_msa_sll_b", - "llvm.mips.sll.d" => "__builtin_msa_sll_d", - "llvm.mips.sll.h" => "__builtin_msa_sll_h", - "llvm.mips.sll.w" => "__builtin_msa_sll_w", - "llvm.mips.slli.b" => "__builtin_msa_slli_b", - "llvm.mips.slli.d" => "__builtin_msa_slli_d", - "llvm.mips.slli.h" => "__builtin_msa_slli_h", - "llvm.mips.slli.w" => "__builtin_msa_slli_w", - "llvm.mips.splat.b" => "__builtin_msa_splat_b", - "llvm.mips.splat.d" => "__builtin_msa_splat_d", - "llvm.mips.splat.h" => "__builtin_msa_splat_h", - "llvm.mips.splat.w" => "__builtin_msa_splat_w", - "llvm.mips.splati.b" => "__builtin_msa_splati_b", - "llvm.mips.splati.d" => "__builtin_msa_splati_d", - "llvm.mips.splati.h" => "__builtin_msa_splati_h", - "llvm.mips.splati.w" => "__builtin_msa_splati_w", - "llvm.mips.sra.b" => "__builtin_msa_sra_b", - "llvm.mips.sra.d" => "__builtin_msa_sra_d", - "llvm.mips.sra.h" => "__builtin_msa_sra_h", - "llvm.mips.sra.w" => "__builtin_msa_sra_w", - "llvm.mips.srai.b" => "__builtin_msa_srai_b", - "llvm.mips.srai.d" => "__builtin_msa_srai_d", - "llvm.mips.srai.h" => "__builtin_msa_srai_h", - "llvm.mips.srai.w" => "__builtin_msa_srai_w", - "llvm.mips.srar.b" => "__builtin_msa_srar_b", - "llvm.mips.srar.d" => "__builtin_msa_srar_d", - "llvm.mips.srar.h" => "__builtin_msa_srar_h", - "llvm.mips.srar.w" => "__builtin_msa_srar_w", - "llvm.mips.srari.b" => "__builtin_msa_srari_b", - "llvm.mips.srari.d" => "__builtin_msa_srari_d", - "llvm.mips.srari.h" => "__builtin_msa_srari_h", - "llvm.mips.srari.w" => "__builtin_msa_srari_w", - "llvm.mips.srl.b" => "__builtin_msa_srl_b", - "llvm.mips.srl.d" => "__builtin_msa_srl_d", - "llvm.mips.srl.h" => "__builtin_msa_srl_h", - "llvm.mips.srl.w" => "__builtin_msa_srl_w", - "llvm.mips.srli.b" => "__builtin_msa_srli_b", - "llvm.mips.srli.d" => "__builtin_msa_srli_d", - "llvm.mips.srli.h" => "__builtin_msa_srli_h", - "llvm.mips.srli.w" => "__builtin_msa_srli_w", - "llvm.mips.srlr.b" => "__builtin_msa_srlr_b", - "llvm.mips.srlr.d" => "__builtin_msa_srlr_d", - "llvm.mips.srlr.h" => "__builtin_msa_srlr_h", - "llvm.mips.srlr.w" => "__builtin_msa_srlr_w", - "llvm.mips.srlri.b" => "__builtin_msa_srlri_b", - "llvm.mips.srlri.d" => "__builtin_msa_srlri_d", - "llvm.mips.srlri.h" => "__builtin_msa_srlri_h", - "llvm.mips.srlri.w" => "__builtin_msa_srlri_w", - "llvm.mips.st.b" => "__builtin_msa_st_b", - "llvm.mips.st.d" => "__builtin_msa_st_d", - "llvm.mips.st.h" => "__builtin_msa_st_h", - "llvm.mips.st.w" => "__builtin_msa_st_w", - "llvm.mips.str.d" => "__builtin_msa_str_d", - "llvm.mips.str.w" => "__builtin_msa_str_w", - "llvm.mips.subq.ph" => "__builtin_mips_subq_ph", - "llvm.mips.subq.s.ph" => "__builtin_mips_subq_s_ph", - "llvm.mips.subq.s.w" => "__builtin_mips_subq_s_w", - "llvm.mips.subqh.ph" => "__builtin_mips_subqh_ph", - "llvm.mips.subqh.r.ph" => "__builtin_mips_subqh_r_ph", - "llvm.mips.subqh.r.w" => "__builtin_mips_subqh_r_w", - "llvm.mips.subqh.w" => "__builtin_mips_subqh_w", - "llvm.mips.subs.s.b" => "__builtin_msa_subs_s_b", - "llvm.mips.subs.s.d" => "__builtin_msa_subs_s_d", - "llvm.mips.subs.s.h" => "__builtin_msa_subs_s_h", - "llvm.mips.subs.s.w" => "__builtin_msa_subs_s_w", - "llvm.mips.subs.u.b" => "__builtin_msa_subs_u_b", - "llvm.mips.subs.u.d" => "__builtin_msa_subs_u_d", - "llvm.mips.subs.u.h" => "__builtin_msa_subs_u_h", - "llvm.mips.subs.u.w" => "__builtin_msa_subs_u_w", - "llvm.mips.subsus.u.b" => "__builtin_msa_subsus_u_b", - "llvm.mips.subsus.u.d" => "__builtin_msa_subsus_u_d", - "llvm.mips.subsus.u.h" => "__builtin_msa_subsus_u_h", - "llvm.mips.subsus.u.w" => "__builtin_msa_subsus_u_w", - "llvm.mips.subsuu.s.b" => "__builtin_msa_subsuu_s_b", - "llvm.mips.subsuu.s.d" => "__builtin_msa_subsuu_s_d", - "llvm.mips.subsuu.s.h" => "__builtin_msa_subsuu_s_h", - "llvm.mips.subsuu.s.w" => "__builtin_msa_subsuu_s_w", - "llvm.mips.subu.ph" => "__builtin_mips_subu_ph", - "llvm.mips.subu.qb" => "__builtin_mips_subu_qb", - "llvm.mips.subu.s.ph" => "__builtin_mips_subu_s_ph", - "llvm.mips.subu.s.qb" => "__builtin_mips_subu_s_qb", - "llvm.mips.subuh.qb" => "__builtin_mips_subuh_qb", - "llvm.mips.subuh.r.qb" => "__builtin_mips_subuh_r_qb", - "llvm.mips.subv.b" => "__builtin_msa_subv_b", - "llvm.mips.subv.d" => "__builtin_msa_subv_d", - "llvm.mips.subv.h" => "__builtin_msa_subv_h", - "llvm.mips.subv.w" => "__builtin_msa_subv_w", - "llvm.mips.subvi.b" => "__builtin_msa_subvi_b", - "llvm.mips.subvi.d" => "__builtin_msa_subvi_d", - "llvm.mips.subvi.h" => "__builtin_msa_subvi_h", - "llvm.mips.subvi.w" => "__builtin_msa_subvi_w", - "llvm.mips.vshf.b" => "__builtin_msa_vshf_b", - "llvm.mips.vshf.d" => "__builtin_msa_vshf_d", - "llvm.mips.vshf.h" => "__builtin_msa_vshf_h", - "llvm.mips.vshf.w" => "__builtin_msa_vshf_w", - "llvm.mips.wrdsp" => "__builtin_mips_wrdsp", - "llvm.mips.xor.v" => "__builtin_msa_xor_v", - "llvm.mips.xori.b" => "__builtin_msa_xori_b", - // nvvm - "llvm.nvvm.abs.i" => "__nvvm_abs_i", - "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", - "llvm.nvvm.activemask" => "__nvvm_activemask", - "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d", - "llvm.nvvm.add.rm.f" => "__nvvm_add_rm_f", - "llvm.nvvm.add.rm.ftz.f" => "__nvvm_add_rm_ftz_f", - "llvm.nvvm.add.rn.d" => "__nvvm_add_rn_d", - "llvm.nvvm.add.rn.f" => "__nvvm_add_rn_f", - "llvm.nvvm.add.rn.ftz.f" => "__nvvm_add_rn_ftz_f", - "llvm.nvvm.add.rp.d" => "__nvvm_add_rp_d", - "llvm.nvvm.add.rp.f" => "__nvvm_add_rp_f", - "llvm.nvvm.add.rp.ftz.f" => "__nvvm_add_rp_ftz_f", - "llvm.nvvm.add.rz.d" => "__nvvm_add_rz_d", - "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f", - "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", - "llvm.nvvm.bar.sync" => "__nvvm_bar_sync", - "llvm.nvvm.bar.warp.sync" => "__nvvm_bar_warp_sync", - "llvm.nvvm.barrier" => "__nvvm_bar", - "llvm.nvvm.barrier.n" => "__nvvm_bar_n", - "llvm.nvvm.barrier.sync" => "__nvvm_barrier_sync", - "llvm.nvvm.barrier.sync.cnt" => "__nvvm_barrier_sync_cnt", - "llvm.nvvm.barrier0" => "__syncthreads", - // [DUPLICATE]: "llvm.nvvm.barrier0" => "__nvvm_bar0", - "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", - "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", - "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", - "llvm.nvvm.bf16x2.to.ue8m0x2.rp" => "__nvvm_bf16x2_to_ue8m0x2_rp", - "llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite" => "__nvvm_bf16x2_to_ue8m0x2_rp_satfinite", - "llvm.nvvm.bf16x2.to.ue8m0x2.rz" => "__nvvm_bf16x2_to_ue8m0x2_rz", - "llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite" => "__nvvm_bf16x2_to_ue8m0x2_rz_satfinite", - "llvm.nvvm.bf2h.rn" => "__nvvm_bf2h_rn", - "llvm.nvvm.bf2h.rn.ftz" => "__nvvm_bf2h_rn_ftz", - "llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll", - "llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i", - "llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f", - "llvm.nvvm.bitcast.ll2d" => "__nvvm_bitcast_ll2d", - "llvm.nvvm.brev32" => "__nvvm_brev32", - "llvm.nvvm.brev64" => "__nvvm_brev64", - "llvm.nvvm.ceil.d" => "__nvvm_ceil_d", - "llvm.nvvm.ceil.f" => "__nvvm_ceil_f", - "llvm.nvvm.ceil.ftz.f" => "__nvvm_ceil_ftz_f", - "llvm.nvvm.clz.i" => "__nvvm_clz_i", - "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", - "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", - "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", - "llvm.nvvm.cp.async.commit.group" => "__nvvm_cp_async_commit_group", - "llvm.nvvm.cp.async.mbarrier.arrive" => "__nvvm_cp_async_mbarrier_arrive", - "llvm.nvvm.cp.async.mbarrier.arrive.noinc" => "__nvvm_cp_async_mbarrier_arrive_noinc", - "llvm.nvvm.cp.async.mbarrier.arrive.noinc.shared" => "__nvvm_cp_async_mbarrier_arrive_noinc_shared", - "llvm.nvvm.cp.async.mbarrier.arrive.shared" => "__nvvm_cp_async_mbarrier_arrive_shared", - "llvm.nvvm.cp.async.wait.all" => "__nvvm_cp_async_wait_all", - "llvm.nvvm.cp.async.wait.group" => "__nvvm_cp_async_wait_group", - "llvm.nvvm.d2f.rm" => "__nvvm_d2f_rm", - "llvm.nvvm.d2f.rm.ftz" => "__nvvm_d2f_rm_ftz", - "llvm.nvvm.d2f.rn" => "__nvvm_d2f_rn", - "llvm.nvvm.d2f.rn.ftz" => "__nvvm_d2f_rn_ftz", - "llvm.nvvm.d2f.rp" => "__nvvm_d2f_rp", - "llvm.nvvm.d2f.rp.ftz" => "__nvvm_d2f_rp_ftz", - "llvm.nvvm.d2f.rz" => "__nvvm_d2f_rz", - "llvm.nvvm.d2f.rz.ftz" => "__nvvm_d2f_rz_ftz", - "llvm.nvvm.d2i.hi" => "__nvvm_d2i_hi", - "llvm.nvvm.d2i.lo" => "__nvvm_d2i_lo", - "llvm.nvvm.d2i.rm" => "__nvvm_d2i_rm", - "llvm.nvvm.d2i.rn" => "__nvvm_d2i_rn", - "llvm.nvvm.d2i.rp" => "__nvvm_d2i_rp", - "llvm.nvvm.d2i.rz" => "__nvvm_d2i_rz", - "llvm.nvvm.d2ll.rm" => "__nvvm_d2ll_rm", - "llvm.nvvm.d2ll.rn" => "__nvvm_d2ll_rn", - "llvm.nvvm.d2ll.rp" => "__nvvm_d2ll_rp", - "llvm.nvvm.d2ll.rz" => "__nvvm_d2ll_rz", - "llvm.nvvm.d2ui.rm" => "__nvvm_d2ui_rm", - "llvm.nvvm.d2ui.rn" => "__nvvm_d2ui_rn", - "llvm.nvvm.d2ui.rp" => "__nvvm_d2ui_rp", - "llvm.nvvm.d2ui.rz" => "__nvvm_d2ui_rz", - "llvm.nvvm.d2ull.rm" => "__nvvm_d2ull_rm", - "llvm.nvvm.d2ull.rn" => "__nvvm_d2ull_rn", - "llvm.nvvm.d2ull.rp" => "__nvvm_d2ull_rp", - "llvm.nvvm.d2ull.rz" => "__nvvm_d2ull_rz", - "llvm.nvvm.div.approx.f" => "__nvvm_div_approx_f", - "llvm.nvvm.div.approx.ftz.f" => "__nvvm_div_approx_ftz_f", - "llvm.nvvm.div.full" => "__nvvm_div_full", - "llvm.nvvm.div.full.ftz" => "__nvvm_div_full_ftz", - "llvm.nvvm.div.rm.d" => "__nvvm_div_rm_d", - "llvm.nvvm.div.rm.f" => "__nvvm_div_rm_f", - "llvm.nvvm.div.rm.ftz.f" => "__nvvm_div_rm_ftz_f", - "llvm.nvvm.div.rn.d" => "__nvvm_div_rn_d", - "llvm.nvvm.div.rn.f" => "__nvvm_div_rn_f", - "llvm.nvvm.div.rn.ftz.f" => "__nvvm_div_rn_ftz_f", - "llvm.nvvm.div.rp.d" => "__nvvm_div_rp_d", - "llvm.nvvm.div.rp.f" => "__nvvm_div_rp_f", - "llvm.nvvm.div.rp.ftz.f" => "__nvvm_div_rp_ftz_f", - "llvm.nvvm.div.rz.d" => "__nvvm_div_rz_d", - "llvm.nvvm.div.rz.f" => "__nvvm_div_rz_f", - "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", - "llvm.nvvm.e2m3x2.to.f16x2.rn" => "__nvvm_e2m3x2_to_f16x2_rn", - "llvm.nvvm.e2m3x2.to.f16x2.rn.relu" => "__nvvm_e2m3x2_to_f16x2_rn_relu", - "llvm.nvvm.e3m2x2.to.f16x2.rn" => "__nvvm_e3m2x2_to_f16x2_rn", - "llvm.nvvm.e3m2x2.to.f16x2.rn.relu" => "__nvvm_e3m2x2_to_f16x2_rn_relu", - "llvm.nvvm.e4m3x2.to.f16x2.rn" => "__nvvm_e4m3x2_to_f16x2_rn", - "llvm.nvvm.e4m3x2.to.f16x2.rn.relu" => "__nvvm_e4m3x2_to_f16x2_rn_relu", - "llvm.nvvm.e5m2x2.to.f16x2.rn" => "__nvvm_e5m2x2_to_f16x2_rn", - "llvm.nvvm.e5m2x2.to.f16x2.rn.relu" => "__nvvm_e5m2x2_to_f16x2_rn_relu", - "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", - "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", - "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", - "llvm.nvvm.exit" => "__nvvm_exit", - "llvm.nvvm.f16x2.to.e4m3x2.rn" => "__nvvm_f16x2_to_e4m3x2_rn", - "llvm.nvvm.f16x2.to.e4m3x2.rn.relu" => "__nvvm_f16x2_to_e4m3x2_rn_relu", - "llvm.nvvm.f16x2.to.e5m2x2.rn" => "__nvvm_f16x2_to_e5m2x2_rn", - "llvm.nvvm.f16x2.to.e5m2x2.rn.relu" => "__nvvm_f16x2_to_e5m2x2_rn_relu", - "llvm.nvvm.f2bf16.rn" => "__nvvm_f2bf16_rn", - "llvm.nvvm.f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu", - "llvm.nvvm.f2bf16.rz" => "__nvvm_f2bf16_rz", - "llvm.nvvm.f2bf16.rz.relu" => "__nvvm_f2bf16_rz_relu", - "llvm.nvvm.f2h.rn" => "__nvvm_f2h_rn", - "llvm.nvvm.f2h.rn.ftz" => "__nvvm_f2h_rn_ftz", - "llvm.nvvm.f2i.rm" => "__nvvm_f2i_rm", - "llvm.nvvm.f2i.rm.ftz" => "__nvvm_f2i_rm_ftz", - "llvm.nvvm.f2i.rn" => "__nvvm_f2i_rn", - "llvm.nvvm.f2i.rn.ftz" => "__nvvm_f2i_rn_ftz", - "llvm.nvvm.f2i.rp" => "__nvvm_f2i_rp", - "llvm.nvvm.f2i.rp.ftz" => "__nvvm_f2i_rp_ftz", - "llvm.nvvm.f2i.rz" => "__nvvm_f2i_rz", - "llvm.nvvm.f2i.rz.ftz" => "__nvvm_f2i_rz_ftz", - "llvm.nvvm.f2ll.rm" => "__nvvm_f2ll_rm", - "llvm.nvvm.f2ll.rm.ftz" => "__nvvm_f2ll_rm_ftz", - "llvm.nvvm.f2ll.rn" => "__nvvm_f2ll_rn", - "llvm.nvvm.f2ll.rn.ftz" => "__nvvm_f2ll_rn_ftz", - "llvm.nvvm.f2ll.rp" => "__nvvm_f2ll_rp", - "llvm.nvvm.f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz", - "llvm.nvvm.f2ll.rz" => "__nvvm_f2ll_rz", - "llvm.nvvm.f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz", - "llvm.nvvm.f2tf32.rn" => "__nvvm_f2tf32_rn", - "llvm.nvvm.f2tf32.rn.relu" => "__nvvm_f2tf32_rn_relu", - "llvm.nvvm.f2tf32.rn.relu.satfinite" => "__nvvm_f2tf32_rn_relu_satfinite", - "llvm.nvvm.f2tf32.rn.satfinite" => "__nvvm_f2tf32_rn_satfinite", - "llvm.nvvm.f2tf32.rna" => "__nvvm_f2tf32_rna", - "llvm.nvvm.f2tf32.rna.satfinite" => "__nvvm_f2tf32_rna_satfinite", - "llvm.nvvm.f2tf32.rz" => "__nvvm_f2tf32_rz", - "llvm.nvvm.f2tf32.rz.relu" => "__nvvm_f2tf32_rz_relu", - "llvm.nvvm.f2tf32.rz.relu.satfinite" => "__nvvm_f2tf32_rz_relu_satfinite", - "llvm.nvvm.f2tf32.rz.satfinite" => "__nvvm_f2tf32_rz_satfinite", - "llvm.nvvm.f2ui.rm" => "__nvvm_f2ui_rm", - "llvm.nvvm.f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz", - "llvm.nvvm.f2ui.rn" => "__nvvm_f2ui_rn", - "llvm.nvvm.f2ui.rn.ftz" => "__nvvm_f2ui_rn_ftz", - "llvm.nvvm.f2ui.rp" => "__nvvm_f2ui_rp", - "llvm.nvvm.f2ui.rp.ftz" => "__nvvm_f2ui_rp_ftz", - "llvm.nvvm.f2ui.rz" => "__nvvm_f2ui_rz", - "llvm.nvvm.f2ui.rz.ftz" => "__nvvm_f2ui_rz_ftz", - "llvm.nvvm.f2ull.rm" => "__nvvm_f2ull_rm", - "llvm.nvvm.f2ull.rm.ftz" => "__nvvm_f2ull_rm_ftz", - "llvm.nvvm.f2ull.rn" => "__nvvm_f2ull_rn", - "llvm.nvvm.f2ull.rn.ftz" => "__nvvm_f2ull_rn_ftz", - "llvm.nvvm.f2ull.rp" => "__nvvm_f2ull_rp", - "llvm.nvvm.f2ull.rp.ftz" => "__nvvm_f2ull_rp_ftz", - "llvm.nvvm.f2ull.rz" => "__nvvm_f2ull_rz", - "llvm.nvvm.f2ull.rz.ftz" => "__nvvm_f2ull_rz_ftz", - "llvm.nvvm.fabs.d" => "__nvvm_fabs_d", - "llvm.nvvm.fabs.f" => "__nvvm_fabs_f", - "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f", - "llvm.nvvm.ff.to.e2m3x2.rn.relu.satfinite" => "__nvvm_ff_to_e2m3x2_rn_relu_satfinite", - "llvm.nvvm.ff.to.e2m3x2.rn.satfinite" => "__nvvm_ff_to_e2m3x2_rn_satfinite", - "llvm.nvvm.ff.to.e3m2x2.rn.relu.satfinite" => "__nvvm_ff_to_e3m2x2_rn_relu_satfinite", - "llvm.nvvm.ff.to.e3m2x2.rn.satfinite" => "__nvvm_ff_to_e3m2x2_rn_satfinite", - "llvm.nvvm.ff.to.e4m3x2.rn" => "__nvvm_ff_to_e4m3x2_rn", - "llvm.nvvm.ff.to.e4m3x2.rn.relu" => "__nvvm_ff_to_e4m3x2_rn_relu", - "llvm.nvvm.ff.to.e5m2x2.rn" => "__nvvm_ff_to_e5m2x2_rn", - "llvm.nvvm.ff.to.e5m2x2.rn.relu" => "__nvvm_ff_to_e5m2x2_rn_relu", - "llvm.nvvm.ff.to.ue8m0x2.rp" => "__nvvm_ff_to_ue8m0x2_rp", - "llvm.nvvm.ff.to.ue8m0x2.rp.satfinite" => "__nvvm_ff_to_ue8m0x2_rp_satfinite", - "llvm.nvvm.ff.to.ue8m0x2.rz" => "__nvvm_ff_to_ue8m0x2_rz", - "llvm.nvvm.ff.to.ue8m0x2.rz.satfinite" => "__nvvm_ff_to_ue8m0x2_rz_satfinite", - "llvm.nvvm.ff2bf16x2.rn" => "__nvvm_ff2bf16x2_rn", - "llvm.nvvm.ff2bf16x2.rn.relu" => "__nvvm_ff2bf16x2_rn_relu", - "llvm.nvvm.ff2bf16x2.rz" => "__nvvm_ff2bf16x2_rz", - "llvm.nvvm.ff2bf16x2.rz.relu" => "__nvvm_ff2bf16x2_rz_relu", - "llvm.nvvm.ff2f16x2.rn" => "__nvvm_ff2f16x2_rn", - "llvm.nvvm.ff2f16x2.rn.relu" => "__nvvm_ff2f16x2_rn_relu", - "llvm.nvvm.ff2f16x2.rz" => "__nvvm_ff2f16x2_rz", - "llvm.nvvm.ff2f16x2.rz.relu" => "__nvvm_ff2f16x2_rz_relu", - "llvm.nvvm.floor.d" => "__nvvm_floor_d", - "llvm.nvvm.floor.f" => "__nvvm_floor_f", - "llvm.nvvm.floor.ftz.f" => "__nvvm_floor_ftz_f", - "llvm.nvvm.fma.rm.d" => "__nvvm_fma_rm_d", - "llvm.nvvm.fma.rm.f" => "__nvvm_fma_rm_f", - "llvm.nvvm.fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f", - "llvm.nvvm.fma.rn.bf16" => "__nvvm_fma_rn_bf16", - "llvm.nvvm.fma.rn.bf16x2" => "__nvvm_fma_rn_bf16x2", - "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d", - "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f", - "llvm.nvvm.fma.rn.ftz.bf16" => "__nvvm_fma_rn_ftz_bf16", - "llvm.nvvm.fma.rn.ftz.bf16x2" => "__nvvm_fma_rn_ftz_bf16x2", - "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", - "llvm.nvvm.fma.rn.ftz.relu.bf16" => "__nvvm_fma_rn_ftz_relu_bf16", - "llvm.nvvm.fma.rn.ftz.relu.bf16x2" => "__nvvm_fma_rn_ftz_relu_bf16x2", - "llvm.nvvm.fma.rn.ftz.sat.bf16" => "__nvvm_fma_rn_ftz_sat_bf16", - "llvm.nvvm.fma.rn.ftz.sat.bf16x2" => "__nvvm_fma_rn_ftz_sat_bf16x2", - "llvm.nvvm.fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16", - "llvm.nvvm.fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2", - "llvm.nvvm.fma.rn.sat.bf16" => "__nvvm_fma_rn_sat_bf16", - "llvm.nvvm.fma.rn.sat.bf16x2" => "__nvvm_fma_rn_sat_bf16x2", - "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d", - "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f", - "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", - "llvm.nvvm.fma.rz.d" => "__nvvm_fma_rz_d", - "llvm.nvvm.fma.rz.f" => "__nvvm_fma_rz_f", - "llvm.nvvm.fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f", - "llvm.nvvm.fmax.bf16" => "__nvvm_fmax_bf16", - "llvm.nvvm.fmax.bf16x2" => "__nvvm_fmax_bf16x2", - "llvm.nvvm.fmax.d" => "__nvvm_fmax_d", - "llvm.nvvm.fmax.f" => "__nvvm_fmax_f", - "llvm.nvvm.fmax.ftz.bf16" => "__nvvm_fmax_ftz_bf16", - "llvm.nvvm.fmax.ftz.bf16x2" => "__nvvm_fmax_ftz_bf16x2", - "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f", - "llvm.nvvm.fmax.ftz.nan.bf16" => "__nvvm_fmax_ftz_nan_bf16", - "llvm.nvvm.fmax.ftz.nan.bf16x2" => "__nvvm_fmax_ftz_nan_bf16x2", - "llvm.nvvm.fmax.ftz.nan.f" => "__nvvm_fmax_ftz_nan_f", - "llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16", - "llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16x2", - "llvm.nvvm.fmax.ftz.nan.xorsign.abs.f" => "__nvvm_fmax_ftz_nan_xorsign_abs_f", - "llvm.nvvm.fmax.ftz.xorsign.abs.bf16" => "__nvvm_fmax_ftz_xorsign_abs_bf16", - "llvm.nvvm.fmax.ftz.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_xorsign_abs_bf16x2", - "llvm.nvvm.fmax.ftz.xorsign.abs.f" => "__nvvm_fmax_ftz_xorsign_abs_f", - "llvm.nvvm.fmax.nan.bf16" => "__nvvm_fmax_nan_bf16", - "llvm.nvvm.fmax.nan.bf16x2" => "__nvvm_fmax_nan_bf16x2", - "llvm.nvvm.fmax.nan.f" => "__nvvm_fmax_nan_f", - "llvm.nvvm.fmax.nan.xorsign.abs.bf16" => "__nvvm_fmax_nan_xorsign_abs_bf16", - "llvm.nvvm.fmax.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_nan_xorsign_abs_bf16x2", - "llvm.nvvm.fmax.nan.xorsign.abs.f" => "__nvvm_fmax_nan_xorsign_abs_f", - "llvm.nvvm.fmax.xorsign.abs.bf16" => "__nvvm_fmax_xorsign_abs_bf16", - "llvm.nvvm.fmax.xorsign.abs.bf16x2" => "__nvvm_fmax_xorsign_abs_bf16x2", - "llvm.nvvm.fmax.xorsign.abs.f" => "__nvvm_fmax_xorsign_abs_f", - "llvm.nvvm.fmin.bf16" => "__nvvm_fmin_bf16", - "llvm.nvvm.fmin.bf16x2" => "__nvvm_fmin_bf16x2", - "llvm.nvvm.fmin.d" => "__nvvm_fmin_d", - "llvm.nvvm.fmin.f" => "__nvvm_fmin_f", - "llvm.nvvm.fmin.ftz.bf16" => "__nvvm_fmin_ftz_bf16", - "llvm.nvvm.fmin.ftz.bf16x2" => "__nvvm_fmin_ftz_bf16x2", - "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f", - "llvm.nvvm.fmin.ftz.nan.bf16" => "__nvvm_fmin_ftz_nan_bf16", - "llvm.nvvm.fmin.ftz.nan.bf16x2" => "__nvvm_fmin_ftz_nan_bf16x2", - "llvm.nvvm.fmin.ftz.nan.f" => "__nvvm_fmin_ftz_nan_f", - "llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16", - "llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16x2", - "llvm.nvvm.fmin.ftz.nan.xorsign.abs.f" => "__nvvm_fmin_ftz_nan_xorsign_abs_f", - "llvm.nvvm.fmin.ftz.xorsign.abs.bf16" => "__nvvm_fmin_ftz_xorsign_abs_bf16", - "llvm.nvvm.fmin.ftz.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_xorsign_abs_bf16x2", - "llvm.nvvm.fmin.ftz.xorsign.abs.f" => "__nvvm_fmin_ftz_xorsign_abs_f", - "llvm.nvvm.fmin.nan.bf16" => "__nvvm_fmin_nan_bf16", - "llvm.nvvm.fmin.nan.bf16x2" => "__nvvm_fmin_nan_bf16x2", - "llvm.nvvm.fmin.nan.f" => "__nvvm_fmin_nan_f", - "llvm.nvvm.fmin.nan.xorsign.abs.bf16" => "__nvvm_fmin_nan_xorsign_abs_bf16", - "llvm.nvvm.fmin.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_nan_xorsign_abs_bf16x2", - "llvm.nvvm.fmin.nan.xorsign.abs.f" => "__nvvm_fmin_nan_xorsign_abs_f", - "llvm.nvvm.fmin.xorsign.abs.bf16" => "__nvvm_fmin_xorsign_abs_bf16", - "llvm.nvvm.fmin.xorsign.abs.bf16x2" => "__nvvm_fmin_xorsign_abs_bf16x2", - "llvm.nvvm.fmin.xorsign.abs.f" => "__nvvm_fmin_xorsign_abs_f", - "llvm.nvvm.fns" => "__nvvm_fns", - "llvm.nvvm.h2f" => "__nvvm_h2f", - "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", - "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn", - "llvm.nvvm.i2d.rp" => "__nvvm_i2d_rp", - "llvm.nvvm.i2d.rz" => "__nvvm_i2d_rz", - "llvm.nvvm.i2f.rm" => "__nvvm_i2f_rm", - "llvm.nvvm.i2f.rn" => "__nvvm_i2f_rn", - "llvm.nvvm.i2f.rp" => "__nvvm_i2f_rp", - "llvm.nvvm.i2f.rz" => "__nvvm_i2f_rz", - "llvm.nvvm.isspacep.const" => "__nvvm_isspacep_const", - "llvm.nvvm.isspacep.global" => "__nvvm_isspacep_global", - "llvm.nvvm.isspacep.local" => "__nvvm_isspacep_local", - "llvm.nvvm.isspacep.shared" => "__nvvm_isspacep_shared", - "llvm.nvvm.istypep.sampler" => "__nvvm_istypep_sampler", - "llvm.nvvm.istypep.surface" => "__nvvm_istypep_surface", - "llvm.nvvm.istypep.texture" => "__nvvm_istypep_texture", - "llvm.nvvm.lg2.approx.d" => "__nvvm_lg2_approx_d", - "llvm.nvvm.lg2.approx.f" => "__nvvm_lg2_approx_f", - "llvm.nvvm.lg2.approx.ftz.f" => "__nvvm_lg2_approx_ftz_f", - "llvm.nvvm.ll2d.rm" => "__nvvm_ll2d_rm", - "llvm.nvvm.ll2d.rn" => "__nvvm_ll2d_rn", - "llvm.nvvm.ll2d.rp" => "__nvvm_ll2d_rp", - "llvm.nvvm.ll2d.rz" => "__nvvm_ll2d_rz", - "llvm.nvvm.ll2f.rm" => "__nvvm_ll2f_rm", - "llvm.nvvm.ll2f.rn" => "__nvvm_ll2f_rn", - "llvm.nvvm.ll2f.rp" => "__nvvm_ll2f_rp", - "llvm.nvvm.ll2f.rz" => "__nvvm_ll2f_rz", - "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d", - "llvm.nvvm.match.any.sync.i32" => "__nvvm_match_any_sync_i32", - "llvm.nvvm.match.any.sync.i64" => "__nvvm_match_any_sync_i64", - "llvm.nvvm.max.i" => "__nvvm_max_i", - "llvm.nvvm.max.ll" => "__nvvm_max_ll", - "llvm.nvvm.max.ui" => "__nvvm_max_ui", - "llvm.nvvm.max.ull" => "__nvvm_max_ull", - "llvm.nvvm.mbarrier.arrive" => "__nvvm_mbarrier_arrive", - "llvm.nvvm.mbarrier.arrive.drop" => "__nvvm_mbarrier_arrive_drop", - "llvm.nvvm.mbarrier.arrive.drop.noComplete" => "__nvvm_mbarrier_arrive_drop_noComplete", - "llvm.nvvm.mbarrier.arrive.drop.noComplete.shared" => "__nvvm_mbarrier_arrive_drop_noComplete_shared", - "llvm.nvvm.mbarrier.arrive.drop.shared" => "__nvvm_mbarrier_arrive_drop_shared", - "llvm.nvvm.mbarrier.arrive.noComplete" => "__nvvm_mbarrier_arrive_noComplete", - "llvm.nvvm.mbarrier.arrive.noComplete.shared" => "__nvvm_mbarrier_arrive_noComplete_shared", - "llvm.nvvm.mbarrier.arrive.shared" => "__nvvm_mbarrier_arrive_shared", - "llvm.nvvm.mbarrier.init" => "__nvvm_mbarrier_init", - "llvm.nvvm.mbarrier.init.shared" => "__nvvm_mbarrier_init_shared", - "llvm.nvvm.mbarrier.inval" => "__nvvm_mbarrier_inval", - "llvm.nvvm.mbarrier.inval.shared" => "__nvvm_mbarrier_inval_shared", - "llvm.nvvm.mbarrier.pending.count" => "__nvvm_mbarrier_pending_count", - "llvm.nvvm.mbarrier.test.wait" => "__nvvm_mbarrier_test_wait", - "llvm.nvvm.mbarrier.test.wait.shared" => "__nvvm_mbarrier_test_wait_shared", - "llvm.nvvm.membar.cta" => "__nvvm_membar_cta", - "llvm.nvvm.membar.gl" => "__nvvm_membar_gl", - "llvm.nvvm.membar.sys" => "__nvvm_membar_sys", - "llvm.nvvm.min.i" => "__nvvm_min_i", - "llvm.nvvm.min.ll" => "__nvvm_min_ll", - "llvm.nvvm.min.ui" => "__nvvm_min_ui", - "llvm.nvvm.min.ull" => "__nvvm_min_ull", - "llvm.nvvm.mul.rm.d" => "__nvvm_mul_rm_d", - "llvm.nvvm.mul.rm.f" => "__nvvm_mul_rm_f", - "llvm.nvvm.mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f", - "llvm.nvvm.mul.rn.d" => "__nvvm_mul_rn_d", - "llvm.nvvm.mul.rn.f" => "__nvvm_mul_rn_f", - "llvm.nvvm.mul.rn.ftz.f" => "__nvvm_mul_rn_ftz_f", - "llvm.nvvm.mul.rp.d" => "__nvvm_mul_rp_d", - "llvm.nvvm.mul.rp.f" => "__nvvm_mul_rp_f", - "llvm.nvvm.mul.rp.ftz.f" => "__nvvm_mul_rp_ftz_f", - "llvm.nvvm.mul.rz.d" => "__nvvm_mul_rz_d", - "llvm.nvvm.mul.rz.f" => "__nvvm_mul_rz_f", - "llvm.nvvm.mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f", - "llvm.nvvm.mul24.i" => "__nvvm_mul24_i", - "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui", - "llvm.nvvm.mulhi.i" => "__nvvm_mulhi_i", - "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll", - "llvm.nvvm.mulhi.s" => "__nvvm_mulhi_s", - "llvm.nvvm.mulhi.ui" => "__nvvm_mulhi_ui", - "llvm.nvvm.mulhi.ull" => "__nvvm_mulhi_ull", - "llvm.nvvm.mulhi.us" => "__nvvm_mulhi_us", - "llvm.nvvm.nanosleep" => "__nvvm_nanosleep", - "llvm.nvvm.neg.bf16" => "__nvvm_neg_bf16", - "llvm.nvvm.neg.bf16x2" => "__nvvm_neg_bf16x2", - "llvm.nvvm.popc.i" => "__nvvm_popc_i", - "llvm.nvvm.popc.ll" => "__nvvm_popc_ll", - "llvm.nvvm.prmt" => "__nvvm_prmt", - "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", - "llvm.nvvm.rcp.approx.ftz.f" => "__nvvm_rcp_approx_ftz_f", - "llvm.nvvm.rcp.rm.d" => "__nvvm_rcp_rm_d", - "llvm.nvvm.rcp.rm.f" => "__nvvm_rcp_rm_f", - "llvm.nvvm.rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f", - "llvm.nvvm.rcp.rn.d" => "__nvvm_rcp_rn_d", - "llvm.nvvm.rcp.rn.f" => "__nvvm_rcp_rn_f", - "llvm.nvvm.rcp.rn.ftz.f" => "__nvvm_rcp_rn_ftz_f", - "llvm.nvvm.rcp.rp.d" => "__nvvm_rcp_rp_d", - "llvm.nvvm.rcp.rp.f" => "__nvvm_rcp_rp_f", - "llvm.nvvm.rcp.rp.ftz.f" => "__nvvm_rcp_rp_ftz_f", - "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d", - "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", - "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", - "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_clock", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_clock64", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.ctaid.w" => "__nvvm_read_ptx_sreg_ctaid_w", - "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", - "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", - "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", - "llvm.nvvm.read.ptx.sreg.envreg0" => "__nvvm_read_ptx_sreg_envreg0", - "llvm.nvvm.read.ptx.sreg.envreg1" => "__nvvm_read_ptx_sreg_envreg1", - "llvm.nvvm.read.ptx.sreg.envreg10" => "__nvvm_read_ptx_sreg_envreg10", - "llvm.nvvm.read.ptx.sreg.envreg11" => "__nvvm_read_ptx_sreg_envreg11", - "llvm.nvvm.read.ptx.sreg.envreg12" => "__nvvm_read_ptx_sreg_envreg12", - "llvm.nvvm.read.ptx.sreg.envreg13" => "__nvvm_read_ptx_sreg_envreg13", - "llvm.nvvm.read.ptx.sreg.envreg14" => "__nvvm_read_ptx_sreg_envreg14", - "llvm.nvvm.read.ptx.sreg.envreg15" => "__nvvm_read_ptx_sreg_envreg15", - "llvm.nvvm.read.ptx.sreg.envreg16" => "__nvvm_read_ptx_sreg_envreg16", - "llvm.nvvm.read.ptx.sreg.envreg17" => "__nvvm_read_ptx_sreg_envreg17", - "llvm.nvvm.read.ptx.sreg.envreg18" => "__nvvm_read_ptx_sreg_envreg18", - "llvm.nvvm.read.ptx.sreg.envreg19" => "__nvvm_read_ptx_sreg_envreg19", - "llvm.nvvm.read.ptx.sreg.envreg2" => "__nvvm_read_ptx_sreg_envreg2", - "llvm.nvvm.read.ptx.sreg.envreg20" => "__nvvm_read_ptx_sreg_envreg20", - "llvm.nvvm.read.ptx.sreg.envreg21" => "__nvvm_read_ptx_sreg_envreg21", - "llvm.nvvm.read.ptx.sreg.envreg22" => "__nvvm_read_ptx_sreg_envreg22", - "llvm.nvvm.read.ptx.sreg.envreg23" => "__nvvm_read_ptx_sreg_envreg23", - "llvm.nvvm.read.ptx.sreg.envreg24" => "__nvvm_read_ptx_sreg_envreg24", - "llvm.nvvm.read.ptx.sreg.envreg25" => "__nvvm_read_ptx_sreg_envreg25", - "llvm.nvvm.read.ptx.sreg.envreg26" => "__nvvm_read_ptx_sreg_envreg26", - "llvm.nvvm.read.ptx.sreg.envreg27" => "__nvvm_read_ptx_sreg_envreg27", - "llvm.nvvm.read.ptx.sreg.envreg28" => "__nvvm_read_ptx_sreg_envreg28", - "llvm.nvvm.read.ptx.sreg.envreg29" => "__nvvm_read_ptx_sreg_envreg29", - "llvm.nvvm.read.ptx.sreg.envreg3" => "__nvvm_read_ptx_sreg_envreg3", - "llvm.nvvm.read.ptx.sreg.envreg30" => "__nvvm_read_ptx_sreg_envreg30", - "llvm.nvvm.read.ptx.sreg.envreg31" => "__nvvm_read_ptx_sreg_envreg31", - "llvm.nvvm.read.ptx.sreg.envreg4" => "__nvvm_read_ptx_sreg_envreg4", - "llvm.nvvm.read.ptx.sreg.envreg5" => "__nvvm_read_ptx_sreg_envreg5", - "llvm.nvvm.read.ptx.sreg.envreg6" => "__nvvm_read_ptx_sreg_envreg6", - "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", - "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", - "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", - "llvm.nvvm.read.ptx.sreg.globaltimer" => "__nvvm_read_ptx_sreg_globaltimer", - "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_gridid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_laneid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_lanemask_eq", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_lanemask_ge", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_lanemask_gt", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_lanemask_le", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_lanemask_lt", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.nctaid.w" => "__nvvm_read_ptx_sreg_nctaid_w", - "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", - "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", - "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", - "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_nsmid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.ntid.w" => "__nvvm_read_ptx_sreg_ntid_w", - "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", - "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", - "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", - "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_nwarpid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_pm0", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_pm1", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_pm2", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_pm3", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_smid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.tid.w" => "__nvvm_read_ptx_sreg_tid_w", - "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", - "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", - "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", - "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_warpid", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", - // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_", - "llvm.nvvm.redux.sync.add" => "__nvvm_redux_sync_add", - "llvm.nvvm.redux.sync.and" => "__nvvm_redux_sync_and", - "llvm.nvvm.redux.sync.fmax" => "__nvvm_redux_sync_fmax", - "llvm.nvvm.redux.sync.fmax.NaN" => "__nvvm_redux_sync_fmax_NaN", - "llvm.nvvm.redux.sync.fmax.abs" => "__nvvm_redux_sync_fmax_abs", - "llvm.nvvm.redux.sync.fmax.abs.NaN" => "__nvvm_redux_sync_fmax_abs_NaN", - "llvm.nvvm.redux.sync.fmin" => "__nvvm_redux_sync_fmin", - "llvm.nvvm.redux.sync.fmin.NaN" => "__nvvm_redux_sync_fmin_NaN", - "llvm.nvvm.redux.sync.fmin.abs" => "__nvvm_redux_sync_fmin_abs", - "llvm.nvvm.redux.sync.fmin.abs.NaN" => "__nvvm_redux_sync_fmin_abs_NaN", - "llvm.nvvm.redux.sync.max" => "__nvvm_redux_sync_max", - "llvm.nvvm.redux.sync.min" => "__nvvm_redux_sync_min", - "llvm.nvvm.redux.sync.or" => "__nvvm_redux_sync_or", - "llvm.nvvm.redux.sync.umax" => "__nvvm_redux_sync_umax", - "llvm.nvvm.redux.sync.umin" => "__nvvm_redux_sync_umin", - "llvm.nvvm.redux.sync.xor" => "__nvvm_redux_sync_xor", - "llvm.nvvm.reflect" => "__nvvm_reflect", - "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32", - "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64", - "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64", - "llvm.nvvm.round.d" => "__nvvm_round_d", - "llvm.nvvm.round.f" => "__nvvm_round_f", - "llvm.nvvm.round.ftz.f" => "__nvvm_round_ftz_f", - "llvm.nvvm.rsqrt.approx.d" => "__nvvm_rsqrt_approx_d", - "llvm.nvvm.rsqrt.approx.f" => "__nvvm_rsqrt_approx_f", - "llvm.nvvm.rsqrt.approx.ftz.d" => "__nvvm_rsqrt_approx_ftz_d", - "llvm.nvvm.rsqrt.approx.ftz.f" => "__nvvm_rsqrt_approx_ftz_f", - "llvm.nvvm.sad.i" => "__nvvm_sad_i", - "llvm.nvvm.sad.ll" => "__nvvm_sad_ll", - "llvm.nvvm.sad.s" => "__nvvm_sad_s", - "llvm.nvvm.sad.ui" => "__nvvm_sad_ui", - "llvm.nvvm.sad.ull" => "__nvvm_sad_ull", - "llvm.nvvm.sad.us" => "__nvvm_sad_us", - "llvm.nvvm.saturate.d" => "__nvvm_saturate_d", - "llvm.nvvm.saturate.f" => "__nvvm_saturate_f", - "llvm.nvvm.saturate.ftz.f" => "__nvvm_saturate_ftz_f", - "llvm.nvvm.shfl.bfly.f32" => "__nvvm_shfl_bfly_f32", - "llvm.nvvm.shfl.bfly.i32" => "__nvvm_shfl_bfly_i32", - "llvm.nvvm.shfl.down.f32" => "__nvvm_shfl_down_f32", - "llvm.nvvm.shfl.down.i32" => "__nvvm_shfl_down_i32", - "llvm.nvvm.shfl.idx.f32" => "__nvvm_shfl_idx_f32", - "llvm.nvvm.shfl.idx.i32" => "__nvvm_shfl_idx_i32", - "llvm.nvvm.shfl.sync.bfly.f32" => "__nvvm_shfl_sync_bfly_f32", - "llvm.nvvm.shfl.sync.bfly.i32" => "__nvvm_shfl_sync_bfly_i32", - "llvm.nvvm.shfl.sync.down.f32" => "__nvvm_shfl_sync_down_f32", - "llvm.nvvm.shfl.sync.down.i32" => "__nvvm_shfl_sync_down_i32", - "llvm.nvvm.shfl.sync.idx.f32" => "__nvvm_shfl_sync_idx_f32", - "llvm.nvvm.shfl.sync.idx.i32" => "__nvvm_shfl_sync_idx_i32", - "llvm.nvvm.shfl.sync.up.f32" => "__nvvm_shfl_sync_up_f32", - "llvm.nvvm.shfl.sync.up.i32" => "__nvvm_shfl_sync_up_i32", - "llvm.nvvm.shfl.up.f32" => "__nvvm_shfl_up_f32", - "llvm.nvvm.shfl.up.i32" => "__nvvm_shfl_up_i32", - "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f", - "llvm.nvvm.sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f", - "llvm.nvvm.sqrt.approx.f" => "__nvvm_sqrt_approx_f", - "llvm.nvvm.sqrt.approx.ftz.f" => "__nvvm_sqrt_approx_ftz_f", - "llvm.nvvm.sqrt.f" => "__nvvm_sqrt_f", - "llvm.nvvm.sqrt.rm.d" => "__nvvm_sqrt_rm_d", - "llvm.nvvm.sqrt.rm.f" => "__nvvm_sqrt_rm_f", - "llvm.nvvm.sqrt.rm.ftz.f" => "__nvvm_sqrt_rm_ftz_f", - "llvm.nvvm.sqrt.rn.d" => "__nvvm_sqrt_rn_d", - "llvm.nvvm.sqrt.rn.f" => "__nvvm_sqrt_rn_f", - "llvm.nvvm.sqrt.rn.ftz.f" => "__nvvm_sqrt_rn_ftz_f", - "llvm.nvvm.sqrt.rp.d" => "__nvvm_sqrt_rp_d", - "llvm.nvvm.sqrt.rp.f" => "__nvvm_sqrt_rp_f", - "llvm.nvvm.sqrt.rp.ftz.f" => "__nvvm_sqrt_rp_ftz_f", - "llvm.nvvm.sqrt.rz.d" => "__nvvm_sqrt_rz_d", - "llvm.nvvm.sqrt.rz.f" => "__nvvm_sqrt_rz_f", - "llvm.nvvm.sqrt.rz.ftz.f" => "__nvvm_sqrt_rz_ftz_f", - "llvm.nvvm.suq.array.size" => "__nvvm_suq_array_size", - "llvm.nvvm.suq.channel.data.type" => "__nvvm_suq_channel_data_type", - "llvm.nvvm.suq.channel.order" => "__nvvm_suq_channel_order", - "llvm.nvvm.suq.depth" => "__nvvm_suq_depth", - "llvm.nvvm.suq.height" => "__nvvm_suq_height", - "llvm.nvvm.suq.width" => "__nvvm_suq_width", - "llvm.nvvm.sust.b.1d.array.i16.clamp" => "__nvvm_sust_b_1d_array_i16_clamp", - "llvm.nvvm.sust.b.1d.array.i16.trap" => "__nvvm_sust_b_1d_array_i16_trap", - "llvm.nvvm.sust.b.1d.array.i16.zero" => "__nvvm_sust_b_1d_array_i16_zero", - "llvm.nvvm.sust.b.1d.array.i32.clamp" => "__nvvm_sust_b_1d_array_i32_clamp", - "llvm.nvvm.sust.b.1d.array.i32.trap" => "__nvvm_sust_b_1d_array_i32_trap", - "llvm.nvvm.sust.b.1d.array.i32.zero" => "__nvvm_sust_b_1d_array_i32_zero", - "llvm.nvvm.sust.b.1d.array.i64.clamp" => "__nvvm_sust_b_1d_array_i64_clamp", - "llvm.nvvm.sust.b.1d.array.i64.trap" => "__nvvm_sust_b_1d_array_i64_trap", - "llvm.nvvm.sust.b.1d.array.i64.zero" => "__nvvm_sust_b_1d_array_i64_zero", - "llvm.nvvm.sust.b.1d.array.i8.clamp" => "__nvvm_sust_b_1d_array_i8_clamp", - "llvm.nvvm.sust.b.1d.array.i8.trap" => "__nvvm_sust_b_1d_array_i8_trap", - "llvm.nvvm.sust.b.1d.array.i8.zero" => "__nvvm_sust_b_1d_array_i8_zero", - "llvm.nvvm.sust.b.1d.array.v2i16.clamp" => "__nvvm_sust_b_1d_array_v2i16_clamp", - "llvm.nvvm.sust.b.1d.array.v2i16.trap" => "__nvvm_sust_b_1d_array_v2i16_trap", - "llvm.nvvm.sust.b.1d.array.v2i16.zero" => "__nvvm_sust_b_1d_array_v2i16_zero", - "llvm.nvvm.sust.b.1d.array.v2i32.clamp" => "__nvvm_sust_b_1d_array_v2i32_clamp", - "llvm.nvvm.sust.b.1d.array.v2i32.trap" => "__nvvm_sust_b_1d_array_v2i32_trap", - "llvm.nvvm.sust.b.1d.array.v2i32.zero" => "__nvvm_sust_b_1d_array_v2i32_zero", - "llvm.nvvm.sust.b.1d.array.v2i64.clamp" => "__nvvm_sust_b_1d_array_v2i64_clamp", - "llvm.nvvm.sust.b.1d.array.v2i64.trap" => "__nvvm_sust_b_1d_array_v2i64_trap", - "llvm.nvvm.sust.b.1d.array.v2i64.zero" => "__nvvm_sust_b_1d_array_v2i64_zero", - "llvm.nvvm.sust.b.1d.array.v2i8.clamp" => "__nvvm_sust_b_1d_array_v2i8_clamp", - "llvm.nvvm.sust.b.1d.array.v2i8.trap" => "__nvvm_sust_b_1d_array_v2i8_trap", - "llvm.nvvm.sust.b.1d.array.v2i8.zero" => "__nvvm_sust_b_1d_array_v2i8_zero", - "llvm.nvvm.sust.b.1d.array.v4i16.clamp" => "__nvvm_sust_b_1d_array_v4i16_clamp", - "llvm.nvvm.sust.b.1d.array.v4i16.trap" => "__nvvm_sust_b_1d_array_v4i16_trap", - "llvm.nvvm.sust.b.1d.array.v4i16.zero" => "__nvvm_sust_b_1d_array_v4i16_zero", - "llvm.nvvm.sust.b.1d.array.v4i32.clamp" => "__nvvm_sust_b_1d_array_v4i32_clamp", - "llvm.nvvm.sust.b.1d.array.v4i32.trap" => "__nvvm_sust_b_1d_array_v4i32_trap", - "llvm.nvvm.sust.b.1d.array.v4i32.zero" => "__nvvm_sust_b_1d_array_v4i32_zero", - "llvm.nvvm.sust.b.1d.array.v4i8.clamp" => "__nvvm_sust_b_1d_array_v4i8_clamp", - "llvm.nvvm.sust.b.1d.array.v4i8.trap" => "__nvvm_sust_b_1d_array_v4i8_trap", - "llvm.nvvm.sust.b.1d.array.v4i8.zero" => "__nvvm_sust_b_1d_array_v4i8_zero", - "llvm.nvvm.sust.b.1d.i16.clamp" => "__nvvm_sust_b_1d_i16_clamp", - "llvm.nvvm.sust.b.1d.i16.trap" => "__nvvm_sust_b_1d_i16_trap", - "llvm.nvvm.sust.b.1d.i16.zero" => "__nvvm_sust_b_1d_i16_zero", - "llvm.nvvm.sust.b.1d.i32.clamp" => "__nvvm_sust_b_1d_i32_clamp", - "llvm.nvvm.sust.b.1d.i32.trap" => "__nvvm_sust_b_1d_i32_trap", - "llvm.nvvm.sust.b.1d.i32.zero" => "__nvvm_sust_b_1d_i32_zero", - "llvm.nvvm.sust.b.1d.i64.clamp" => "__nvvm_sust_b_1d_i64_clamp", - "llvm.nvvm.sust.b.1d.i64.trap" => "__nvvm_sust_b_1d_i64_trap", - "llvm.nvvm.sust.b.1d.i64.zero" => "__nvvm_sust_b_1d_i64_zero", - "llvm.nvvm.sust.b.1d.i8.clamp" => "__nvvm_sust_b_1d_i8_clamp", - "llvm.nvvm.sust.b.1d.i8.trap" => "__nvvm_sust_b_1d_i8_trap", - "llvm.nvvm.sust.b.1d.i8.zero" => "__nvvm_sust_b_1d_i8_zero", - "llvm.nvvm.sust.b.1d.v2i16.clamp" => "__nvvm_sust_b_1d_v2i16_clamp", - "llvm.nvvm.sust.b.1d.v2i16.trap" => "__nvvm_sust_b_1d_v2i16_trap", - "llvm.nvvm.sust.b.1d.v2i16.zero" => "__nvvm_sust_b_1d_v2i16_zero", - "llvm.nvvm.sust.b.1d.v2i32.clamp" => "__nvvm_sust_b_1d_v2i32_clamp", - "llvm.nvvm.sust.b.1d.v2i32.trap" => "__nvvm_sust_b_1d_v2i32_trap", - "llvm.nvvm.sust.b.1d.v2i32.zero" => "__nvvm_sust_b_1d_v2i32_zero", - "llvm.nvvm.sust.b.1d.v2i64.clamp" => "__nvvm_sust_b_1d_v2i64_clamp", - "llvm.nvvm.sust.b.1d.v2i64.trap" => "__nvvm_sust_b_1d_v2i64_trap", - "llvm.nvvm.sust.b.1d.v2i64.zero" => "__nvvm_sust_b_1d_v2i64_zero", - "llvm.nvvm.sust.b.1d.v2i8.clamp" => "__nvvm_sust_b_1d_v2i8_clamp", - "llvm.nvvm.sust.b.1d.v2i8.trap" => "__nvvm_sust_b_1d_v2i8_trap", - "llvm.nvvm.sust.b.1d.v2i8.zero" => "__nvvm_sust_b_1d_v2i8_zero", - "llvm.nvvm.sust.b.1d.v4i16.clamp" => "__nvvm_sust_b_1d_v4i16_clamp", - "llvm.nvvm.sust.b.1d.v4i16.trap" => "__nvvm_sust_b_1d_v4i16_trap", - "llvm.nvvm.sust.b.1d.v4i16.zero" => "__nvvm_sust_b_1d_v4i16_zero", - "llvm.nvvm.sust.b.1d.v4i32.clamp" => "__nvvm_sust_b_1d_v4i32_clamp", - "llvm.nvvm.sust.b.1d.v4i32.trap" => "__nvvm_sust_b_1d_v4i32_trap", - "llvm.nvvm.sust.b.1d.v4i32.zero" => "__nvvm_sust_b_1d_v4i32_zero", - "llvm.nvvm.sust.b.1d.v4i8.clamp" => "__nvvm_sust_b_1d_v4i8_clamp", - "llvm.nvvm.sust.b.1d.v4i8.trap" => "__nvvm_sust_b_1d_v4i8_trap", - "llvm.nvvm.sust.b.1d.v4i8.zero" => "__nvvm_sust_b_1d_v4i8_zero", - "llvm.nvvm.sust.b.2d.array.i16.clamp" => "__nvvm_sust_b_2d_array_i16_clamp", - "llvm.nvvm.sust.b.2d.array.i16.trap" => "__nvvm_sust_b_2d_array_i16_trap", - "llvm.nvvm.sust.b.2d.array.i16.zero" => "__nvvm_sust_b_2d_array_i16_zero", - "llvm.nvvm.sust.b.2d.array.i32.clamp" => "__nvvm_sust_b_2d_array_i32_clamp", - "llvm.nvvm.sust.b.2d.array.i32.trap" => "__nvvm_sust_b_2d_array_i32_trap", - "llvm.nvvm.sust.b.2d.array.i32.zero" => "__nvvm_sust_b_2d_array_i32_zero", - "llvm.nvvm.sust.b.2d.array.i64.clamp" => "__nvvm_sust_b_2d_array_i64_clamp", - "llvm.nvvm.sust.b.2d.array.i64.trap" => "__nvvm_sust_b_2d_array_i64_trap", - "llvm.nvvm.sust.b.2d.array.i64.zero" => "__nvvm_sust_b_2d_array_i64_zero", - "llvm.nvvm.sust.b.2d.array.i8.clamp" => "__nvvm_sust_b_2d_array_i8_clamp", - "llvm.nvvm.sust.b.2d.array.i8.trap" => "__nvvm_sust_b_2d_array_i8_trap", - "llvm.nvvm.sust.b.2d.array.i8.zero" => "__nvvm_sust_b_2d_array_i8_zero", - "llvm.nvvm.sust.b.2d.array.v2i16.clamp" => "__nvvm_sust_b_2d_array_v2i16_clamp", - "llvm.nvvm.sust.b.2d.array.v2i16.trap" => "__nvvm_sust_b_2d_array_v2i16_trap", - "llvm.nvvm.sust.b.2d.array.v2i16.zero" => "__nvvm_sust_b_2d_array_v2i16_zero", - "llvm.nvvm.sust.b.2d.array.v2i32.clamp" => "__nvvm_sust_b_2d_array_v2i32_clamp", - "llvm.nvvm.sust.b.2d.array.v2i32.trap" => "__nvvm_sust_b_2d_array_v2i32_trap", - "llvm.nvvm.sust.b.2d.array.v2i32.zero" => "__nvvm_sust_b_2d_array_v2i32_zero", - "llvm.nvvm.sust.b.2d.array.v2i64.clamp" => "__nvvm_sust_b_2d_array_v2i64_clamp", - "llvm.nvvm.sust.b.2d.array.v2i64.trap" => "__nvvm_sust_b_2d_array_v2i64_trap", - "llvm.nvvm.sust.b.2d.array.v2i64.zero" => "__nvvm_sust_b_2d_array_v2i64_zero", - "llvm.nvvm.sust.b.2d.array.v2i8.clamp" => "__nvvm_sust_b_2d_array_v2i8_clamp", - "llvm.nvvm.sust.b.2d.array.v2i8.trap" => "__nvvm_sust_b_2d_array_v2i8_trap", - "llvm.nvvm.sust.b.2d.array.v2i8.zero" => "__nvvm_sust_b_2d_array_v2i8_zero", - "llvm.nvvm.sust.b.2d.array.v4i16.clamp" => "__nvvm_sust_b_2d_array_v4i16_clamp", - "llvm.nvvm.sust.b.2d.array.v4i16.trap" => "__nvvm_sust_b_2d_array_v4i16_trap", - "llvm.nvvm.sust.b.2d.array.v4i16.zero" => "__nvvm_sust_b_2d_array_v4i16_zero", - "llvm.nvvm.sust.b.2d.array.v4i32.clamp" => "__nvvm_sust_b_2d_array_v4i32_clamp", - "llvm.nvvm.sust.b.2d.array.v4i32.trap" => "__nvvm_sust_b_2d_array_v4i32_trap", - "llvm.nvvm.sust.b.2d.array.v4i32.zero" => "__nvvm_sust_b_2d_array_v4i32_zero", - "llvm.nvvm.sust.b.2d.array.v4i8.clamp" => "__nvvm_sust_b_2d_array_v4i8_clamp", - "llvm.nvvm.sust.b.2d.array.v4i8.trap" => "__nvvm_sust_b_2d_array_v4i8_trap", - "llvm.nvvm.sust.b.2d.array.v4i8.zero" => "__nvvm_sust_b_2d_array_v4i8_zero", - "llvm.nvvm.sust.b.2d.i16.clamp" => "__nvvm_sust_b_2d_i16_clamp", - "llvm.nvvm.sust.b.2d.i16.trap" => "__nvvm_sust_b_2d_i16_trap", - "llvm.nvvm.sust.b.2d.i16.zero" => "__nvvm_sust_b_2d_i16_zero", - "llvm.nvvm.sust.b.2d.i32.clamp" => "__nvvm_sust_b_2d_i32_clamp", - "llvm.nvvm.sust.b.2d.i32.trap" => "__nvvm_sust_b_2d_i32_trap", - "llvm.nvvm.sust.b.2d.i32.zero" => "__nvvm_sust_b_2d_i32_zero", - "llvm.nvvm.sust.b.2d.i64.clamp" => "__nvvm_sust_b_2d_i64_clamp", - "llvm.nvvm.sust.b.2d.i64.trap" => "__nvvm_sust_b_2d_i64_trap", - "llvm.nvvm.sust.b.2d.i64.zero" => "__nvvm_sust_b_2d_i64_zero", - "llvm.nvvm.sust.b.2d.i8.clamp" => "__nvvm_sust_b_2d_i8_clamp", - "llvm.nvvm.sust.b.2d.i8.trap" => "__nvvm_sust_b_2d_i8_trap", - "llvm.nvvm.sust.b.2d.i8.zero" => "__nvvm_sust_b_2d_i8_zero", - "llvm.nvvm.sust.b.2d.v2i16.clamp" => "__nvvm_sust_b_2d_v2i16_clamp", - "llvm.nvvm.sust.b.2d.v2i16.trap" => "__nvvm_sust_b_2d_v2i16_trap", - "llvm.nvvm.sust.b.2d.v2i16.zero" => "__nvvm_sust_b_2d_v2i16_zero", - "llvm.nvvm.sust.b.2d.v2i32.clamp" => "__nvvm_sust_b_2d_v2i32_clamp", - "llvm.nvvm.sust.b.2d.v2i32.trap" => "__nvvm_sust_b_2d_v2i32_trap", - "llvm.nvvm.sust.b.2d.v2i32.zero" => "__nvvm_sust_b_2d_v2i32_zero", - "llvm.nvvm.sust.b.2d.v2i64.clamp" => "__nvvm_sust_b_2d_v2i64_clamp", - "llvm.nvvm.sust.b.2d.v2i64.trap" => "__nvvm_sust_b_2d_v2i64_trap", - "llvm.nvvm.sust.b.2d.v2i64.zero" => "__nvvm_sust_b_2d_v2i64_zero", - "llvm.nvvm.sust.b.2d.v2i8.clamp" => "__nvvm_sust_b_2d_v2i8_clamp", - "llvm.nvvm.sust.b.2d.v2i8.trap" => "__nvvm_sust_b_2d_v2i8_trap", - "llvm.nvvm.sust.b.2d.v2i8.zero" => "__nvvm_sust_b_2d_v2i8_zero", - "llvm.nvvm.sust.b.2d.v4i16.clamp" => "__nvvm_sust_b_2d_v4i16_clamp", - "llvm.nvvm.sust.b.2d.v4i16.trap" => "__nvvm_sust_b_2d_v4i16_trap", - "llvm.nvvm.sust.b.2d.v4i16.zero" => "__nvvm_sust_b_2d_v4i16_zero", - "llvm.nvvm.sust.b.2d.v4i32.clamp" => "__nvvm_sust_b_2d_v4i32_clamp", - "llvm.nvvm.sust.b.2d.v4i32.trap" => "__nvvm_sust_b_2d_v4i32_trap", - "llvm.nvvm.sust.b.2d.v4i32.zero" => "__nvvm_sust_b_2d_v4i32_zero", - "llvm.nvvm.sust.b.2d.v4i8.clamp" => "__nvvm_sust_b_2d_v4i8_clamp", - "llvm.nvvm.sust.b.2d.v4i8.trap" => "__nvvm_sust_b_2d_v4i8_trap", - "llvm.nvvm.sust.b.2d.v4i8.zero" => "__nvvm_sust_b_2d_v4i8_zero", - "llvm.nvvm.sust.b.3d.i16.clamp" => "__nvvm_sust_b_3d_i16_clamp", - "llvm.nvvm.sust.b.3d.i16.trap" => "__nvvm_sust_b_3d_i16_trap", - "llvm.nvvm.sust.b.3d.i16.zero" => "__nvvm_sust_b_3d_i16_zero", - "llvm.nvvm.sust.b.3d.i32.clamp" => "__nvvm_sust_b_3d_i32_clamp", - "llvm.nvvm.sust.b.3d.i32.trap" => "__nvvm_sust_b_3d_i32_trap", - "llvm.nvvm.sust.b.3d.i32.zero" => "__nvvm_sust_b_3d_i32_zero", - "llvm.nvvm.sust.b.3d.i64.clamp" => "__nvvm_sust_b_3d_i64_clamp", - "llvm.nvvm.sust.b.3d.i64.trap" => "__nvvm_sust_b_3d_i64_trap", - "llvm.nvvm.sust.b.3d.i64.zero" => "__nvvm_sust_b_3d_i64_zero", - "llvm.nvvm.sust.b.3d.i8.clamp" => "__nvvm_sust_b_3d_i8_clamp", - "llvm.nvvm.sust.b.3d.i8.trap" => "__nvvm_sust_b_3d_i8_trap", - "llvm.nvvm.sust.b.3d.i8.zero" => "__nvvm_sust_b_3d_i8_zero", - "llvm.nvvm.sust.b.3d.v2i16.clamp" => "__nvvm_sust_b_3d_v2i16_clamp", - "llvm.nvvm.sust.b.3d.v2i16.trap" => "__nvvm_sust_b_3d_v2i16_trap", - "llvm.nvvm.sust.b.3d.v2i16.zero" => "__nvvm_sust_b_3d_v2i16_zero", - "llvm.nvvm.sust.b.3d.v2i32.clamp" => "__nvvm_sust_b_3d_v2i32_clamp", - "llvm.nvvm.sust.b.3d.v2i32.trap" => "__nvvm_sust_b_3d_v2i32_trap", - "llvm.nvvm.sust.b.3d.v2i32.zero" => "__nvvm_sust_b_3d_v2i32_zero", - "llvm.nvvm.sust.b.3d.v2i64.clamp" => "__nvvm_sust_b_3d_v2i64_clamp", - "llvm.nvvm.sust.b.3d.v2i64.trap" => "__nvvm_sust_b_3d_v2i64_trap", - "llvm.nvvm.sust.b.3d.v2i64.zero" => "__nvvm_sust_b_3d_v2i64_zero", - "llvm.nvvm.sust.b.3d.v2i8.clamp" => "__nvvm_sust_b_3d_v2i8_clamp", - "llvm.nvvm.sust.b.3d.v2i8.trap" => "__nvvm_sust_b_3d_v2i8_trap", - "llvm.nvvm.sust.b.3d.v2i8.zero" => "__nvvm_sust_b_3d_v2i8_zero", - "llvm.nvvm.sust.b.3d.v4i16.clamp" => "__nvvm_sust_b_3d_v4i16_clamp", - "llvm.nvvm.sust.b.3d.v4i16.trap" => "__nvvm_sust_b_3d_v4i16_trap", - "llvm.nvvm.sust.b.3d.v4i16.zero" => "__nvvm_sust_b_3d_v4i16_zero", - "llvm.nvvm.sust.b.3d.v4i32.clamp" => "__nvvm_sust_b_3d_v4i32_clamp", - "llvm.nvvm.sust.b.3d.v4i32.trap" => "__nvvm_sust_b_3d_v4i32_trap", - "llvm.nvvm.sust.b.3d.v4i32.zero" => "__nvvm_sust_b_3d_v4i32_zero", - "llvm.nvvm.sust.b.3d.v4i8.clamp" => "__nvvm_sust_b_3d_v4i8_clamp", - "llvm.nvvm.sust.b.3d.v4i8.trap" => "__nvvm_sust_b_3d_v4i8_trap", - "llvm.nvvm.sust.b.3d.v4i8.zero" => "__nvvm_sust_b_3d_v4i8_zero", - "llvm.nvvm.sust.p.1d.array.i16.trap" => "__nvvm_sust_p_1d_array_i16_trap", - "llvm.nvvm.sust.p.1d.array.i32.trap" => "__nvvm_sust_p_1d_array_i32_trap", - "llvm.nvvm.sust.p.1d.array.i8.trap" => "__nvvm_sust_p_1d_array_i8_trap", - "llvm.nvvm.sust.p.1d.array.v2i16.trap" => "__nvvm_sust_p_1d_array_v2i16_trap", - "llvm.nvvm.sust.p.1d.array.v2i32.trap" => "__nvvm_sust_p_1d_array_v2i32_trap", - "llvm.nvvm.sust.p.1d.array.v2i8.trap" => "__nvvm_sust_p_1d_array_v2i8_trap", - "llvm.nvvm.sust.p.1d.array.v4i16.trap" => "__nvvm_sust_p_1d_array_v4i16_trap", - "llvm.nvvm.sust.p.1d.array.v4i32.trap" => "__nvvm_sust_p_1d_array_v4i32_trap", - "llvm.nvvm.sust.p.1d.array.v4i8.trap" => "__nvvm_sust_p_1d_array_v4i8_trap", - "llvm.nvvm.sust.p.1d.i16.trap" => "__nvvm_sust_p_1d_i16_trap", - "llvm.nvvm.sust.p.1d.i32.trap" => "__nvvm_sust_p_1d_i32_trap", - "llvm.nvvm.sust.p.1d.i8.trap" => "__nvvm_sust_p_1d_i8_trap", - "llvm.nvvm.sust.p.1d.v2i16.trap" => "__nvvm_sust_p_1d_v2i16_trap", - "llvm.nvvm.sust.p.1d.v2i32.trap" => "__nvvm_sust_p_1d_v2i32_trap", - "llvm.nvvm.sust.p.1d.v2i8.trap" => "__nvvm_sust_p_1d_v2i8_trap", - "llvm.nvvm.sust.p.1d.v4i16.trap" => "__nvvm_sust_p_1d_v4i16_trap", - "llvm.nvvm.sust.p.1d.v4i32.trap" => "__nvvm_sust_p_1d_v4i32_trap", - "llvm.nvvm.sust.p.1d.v4i8.trap" => "__nvvm_sust_p_1d_v4i8_trap", - "llvm.nvvm.sust.p.2d.array.i16.trap" => "__nvvm_sust_p_2d_array_i16_trap", - "llvm.nvvm.sust.p.2d.array.i32.trap" => "__nvvm_sust_p_2d_array_i32_trap", - "llvm.nvvm.sust.p.2d.array.i8.trap" => "__nvvm_sust_p_2d_array_i8_trap", - "llvm.nvvm.sust.p.2d.array.v2i16.trap" => "__nvvm_sust_p_2d_array_v2i16_trap", - "llvm.nvvm.sust.p.2d.array.v2i32.trap" => "__nvvm_sust_p_2d_array_v2i32_trap", - "llvm.nvvm.sust.p.2d.array.v2i8.trap" => "__nvvm_sust_p_2d_array_v2i8_trap", - "llvm.nvvm.sust.p.2d.array.v4i16.trap" => "__nvvm_sust_p_2d_array_v4i16_trap", - "llvm.nvvm.sust.p.2d.array.v4i32.trap" => "__nvvm_sust_p_2d_array_v4i32_trap", - "llvm.nvvm.sust.p.2d.array.v4i8.trap" => "__nvvm_sust_p_2d_array_v4i8_trap", - "llvm.nvvm.sust.p.2d.i16.trap" => "__nvvm_sust_p_2d_i16_trap", - "llvm.nvvm.sust.p.2d.i32.trap" => "__nvvm_sust_p_2d_i32_trap", - "llvm.nvvm.sust.p.2d.i8.trap" => "__nvvm_sust_p_2d_i8_trap", - "llvm.nvvm.sust.p.2d.v2i16.trap" => "__nvvm_sust_p_2d_v2i16_trap", - "llvm.nvvm.sust.p.2d.v2i32.trap" => "__nvvm_sust_p_2d_v2i32_trap", - "llvm.nvvm.sust.p.2d.v2i8.trap" => "__nvvm_sust_p_2d_v2i8_trap", - "llvm.nvvm.sust.p.2d.v4i16.trap" => "__nvvm_sust_p_2d_v4i16_trap", - "llvm.nvvm.sust.p.2d.v4i32.trap" => "__nvvm_sust_p_2d_v4i32_trap", - "llvm.nvvm.sust.p.2d.v4i8.trap" => "__nvvm_sust_p_2d_v4i8_trap", - "llvm.nvvm.sust.p.3d.i16.trap" => "__nvvm_sust_p_3d_i16_trap", - "llvm.nvvm.sust.p.3d.i32.trap" => "__nvvm_sust_p_3d_i32_trap", - "llvm.nvvm.sust.p.3d.i8.trap" => "__nvvm_sust_p_3d_i8_trap", - "llvm.nvvm.sust.p.3d.v2i16.trap" => "__nvvm_sust_p_3d_v2i16_trap", - "llvm.nvvm.sust.p.3d.v2i32.trap" => "__nvvm_sust_p_3d_v2i32_trap", - "llvm.nvvm.sust.p.3d.v2i8.trap" => "__nvvm_sust_p_3d_v2i8_trap", - "llvm.nvvm.sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap", - "llvm.nvvm.sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap", - "llvm.nvvm.sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap", - "llvm.nvvm.swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64", - "llvm.nvvm.trunc.d" => "__nvvm_trunc_d", - "llvm.nvvm.trunc.f" => "__nvvm_trunc_f", - "llvm.nvvm.trunc.ftz.f" => "__nvvm_trunc_ftz_f", - "llvm.nvvm.txq.array.size" => "__nvvm_txq_array_size", - "llvm.nvvm.txq.channel.data.type" => "__nvvm_txq_channel_data_type", - "llvm.nvvm.txq.channel.order" => "__nvvm_txq_channel_order", - "llvm.nvvm.txq.depth" => "__nvvm_txq_depth", - "llvm.nvvm.txq.height" => "__nvvm_txq_height", - "llvm.nvvm.txq.num.mipmap.levels" => "__nvvm_txq_num_mipmap_levels", - "llvm.nvvm.txq.num.samples" => "__nvvm_txq_num_samples", - "llvm.nvvm.txq.width" => "__nvvm_txq_width", - "llvm.nvvm.ue8m0x2.to.bf16x2" => "__nvvm_ue8m0x2_to_bf16x2", - "llvm.nvvm.ui2d.rm" => "__nvvm_ui2d_rm", - "llvm.nvvm.ui2d.rn" => "__nvvm_ui2d_rn", - "llvm.nvvm.ui2d.rp" => "__nvvm_ui2d_rp", - "llvm.nvvm.ui2d.rz" => "__nvvm_ui2d_rz", - "llvm.nvvm.ui2f.rm" => "__nvvm_ui2f_rm", - "llvm.nvvm.ui2f.rn" => "__nvvm_ui2f_rn", - "llvm.nvvm.ui2f.rp" => "__nvvm_ui2f_rp", - "llvm.nvvm.ui2f.rz" => "__nvvm_ui2f_rz", - "llvm.nvvm.ull2d.rm" => "__nvvm_ull2d_rm", - "llvm.nvvm.ull2d.rn" => "__nvvm_ull2d_rn", - "llvm.nvvm.ull2d.rp" => "__nvvm_ull2d_rp", - "llvm.nvvm.ull2d.rz" => "__nvvm_ull2d_rz", - "llvm.nvvm.ull2f.rm" => "__nvvm_ull2f_rm", - "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn", - "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", - "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", - "llvm.nvvm.vote.all" => "__nvvm_vote_all", - "llvm.nvvm.vote.all.sync" => "__nvvm_vote_all_sync", - "llvm.nvvm.vote.any" => "__nvvm_vote_any", - "llvm.nvvm.vote.any.sync" => "__nvvm_vote_any_sync", - "llvm.nvvm.vote.ballot" => "__nvvm_vote_ballot", - "llvm.nvvm.vote.ballot.sync" => "__nvvm_vote_ballot_sync", - "llvm.nvvm.vote.uni" => "__nvvm_vote_uni", - "llvm.nvvm.vote.uni.sync" => "__nvvm_vote_uni_sync", - // ppc - "llvm.ppc.addex" => "__builtin_ppc_addex", - "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", - "llvm.ppc.addg6s" => "__builtin_addg6s", - "llvm.ppc.addg6sd" => "__builtin_ppc_addg6s", - "llvm.ppc.altivec.crypto.vcipher" => "__builtin_altivec_crypto_vcipher", - "llvm.ppc.altivec.crypto.vcipherlast" => "__builtin_altivec_crypto_vcipherlast", - "llvm.ppc.altivec.crypto.vncipher" => "__builtin_altivec_crypto_vncipher", - "llvm.ppc.altivec.crypto.vncipherlast" => "__builtin_altivec_crypto_vncipherlast", - "llvm.ppc.altivec.crypto.vpermxor" => "__builtin_altivec_crypto_vpermxor", - "llvm.ppc.altivec.crypto.vpermxor.be" => "__builtin_altivec_crypto_vpermxor_be", - "llvm.ppc.altivec.crypto.vpmsumb" => "__builtin_altivec_crypto_vpmsumb", - "llvm.ppc.altivec.crypto.vpmsumd" => "__builtin_altivec_crypto_vpmsumd", - "llvm.ppc.altivec.crypto.vpmsumh" => "__builtin_altivec_crypto_vpmsumh", - "llvm.ppc.altivec.crypto.vpmsumw" => "__builtin_altivec_crypto_vpmsumw", - "llvm.ppc.altivec.crypto.vsbox" => "__builtin_altivec_crypto_vsbox", - "llvm.ppc.altivec.crypto.vshasigmad" => "__builtin_altivec_crypto_vshasigmad", - "llvm.ppc.altivec.crypto.vshasigmaw" => "__builtin_altivec_crypto_vshasigmaw", - "llvm.ppc.altivec.dss" => "__builtin_altivec_dss", - "llvm.ppc.altivec.dssall" => "__builtin_altivec_dssall", - "llvm.ppc.altivec.dst" => "__builtin_altivec_dst", - "llvm.ppc.altivec.dstst" => "__builtin_altivec_dstst", - "llvm.ppc.altivec.dststt" => "__builtin_altivec_dststt", - "llvm.ppc.altivec.dstt" => "__builtin_altivec_dstt", - "llvm.ppc.altivec.mfvscr" => "__builtin_altivec_mfvscr", - "llvm.ppc.altivec.mtvscr" => "__builtin_altivec_mtvscr", - "llvm.ppc.altivec.mtvsrbm" => "__builtin_altivec_mtvsrbm", - "llvm.ppc.altivec.mtvsrdm" => "__builtin_altivec_mtvsrdm", - "llvm.ppc.altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm", - "llvm.ppc.altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm", - "llvm.ppc.altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm", - "llvm.ppc.altivec.vabsdub" => "__builtin_altivec_vabsdub", - "llvm.ppc.altivec.vabsduh" => "__builtin_altivec_vabsduh", - "llvm.ppc.altivec.vabsduw" => "__builtin_altivec_vabsduw", - "llvm.ppc.altivec.vaddcuq" => "__builtin_altivec_vaddcuq", - "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", - "llvm.ppc.altivec.vaddecuq" => "__builtin_altivec_vaddecuq", - "llvm.ppc.altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm", - "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", - "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", - "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", - "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs", - "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs", - "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws", - "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb", - "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh", - "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw", - "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", - "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", - "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", - "llvm.ppc.altivec.vbpermd" => "__builtin_altivec_vbpermd", - "llvm.ppc.altivec.vbpermq" => "__builtin_altivec_vbpermq", - "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", - "llvm.ppc.altivec.vcfuged" => "__builtin_altivec_vcfuged", - "llvm.ppc.altivec.vcfux" => "__builtin_altivec_vcfux", - "llvm.ppc.altivec.vclrlb" => "__builtin_altivec_vclrlb", - "llvm.ppc.altivec.vclrrb" => "__builtin_altivec_vclrrb", - "llvm.ppc.altivec.vclzdm" => "__builtin_altivec_vclzdm", - "llvm.ppc.altivec.vclzlsbb" => "__builtin_altivec_vclzlsbb", - "llvm.ppc.altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp", - "llvm.ppc.altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p", - "llvm.ppc.altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp", - "llvm.ppc.altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p", - "llvm.ppc.altivec.vcmpequb" => "__builtin_altivec_vcmpequb", - "llvm.ppc.altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p", - "llvm.ppc.altivec.vcmpequd" => "__builtin_altivec_vcmpequd", - "llvm.ppc.altivec.vcmpequd.p" => "__builtin_altivec_vcmpequd_p", - "llvm.ppc.altivec.vcmpequh" => "__builtin_altivec_vcmpequh", - "llvm.ppc.altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p", - "llvm.ppc.altivec.vcmpequq" => "__builtin_altivec_vcmpequq", - "llvm.ppc.altivec.vcmpequq.p" => "__builtin_altivec_vcmpequq_p", - "llvm.ppc.altivec.vcmpequw" => "__builtin_altivec_vcmpequw", - "llvm.ppc.altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p", - "llvm.ppc.altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp", - "llvm.ppc.altivec.vcmpgefp.p" => "__builtin_altivec_vcmpgefp_p", - "llvm.ppc.altivec.vcmpgtfp" => "__builtin_altivec_vcmpgtfp", - "llvm.ppc.altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p", - "llvm.ppc.altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb", - "llvm.ppc.altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p", - "llvm.ppc.altivec.vcmpgtsd" => "__builtin_altivec_vcmpgtsd", - "llvm.ppc.altivec.vcmpgtsd.p" => "__builtin_altivec_vcmpgtsd_p", - "llvm.ppc.altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh", - "llvm.ppc.altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p", - "llvm.ppc.altivec.vcmpgtsq" => "__builtin_altivec_vcmpgtsq", - "llvm.ppc.altivec.vcmpgtsq.p" => "__builtin_altivec_vcmpgtsq_p", - "llvm.ppc.altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw", - "llvm.ppc.altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p", - "llvm.ppc.altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub", - "llvm.ppc.altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p", - "llvm.ppc.altivec.vcmpgtud" => "__builtin_altivec_vcmpgtud", - "llvm.ppc.altivec.vcmpgtud.p" => "__builtin_altivec_vcmpgtud_p", - "llvm.ppc.altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh", - "llvm.ppc.altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p", - "llvm.ppc.altivec.vcmpgtuq" => "__builtin_altivec_vcmpgtuq", - "llvm.ppc.altivec.vcmpgtuq.p" => "__builtin_altivec_vcmpgtuq_p", - "llvm.ppc.altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw", - "llvm.ppc.altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p", - "llvm.ppc.altivec.vcmpneb" => "__builtin_altivec_vcmpneb", - "llvm.ppc.altivec.vcmpneb.p" => "__builtin_altivec_vcmpneb_p", - "llvm.ppc.altivec.vcmpneh" => "__builtin_altivec_vcmpneh", - "llvm.ppc.altivec.vcmpneh.p" => "__builtin_altivec_vcmpneh_p", - "llvm.ppc.altivec.vcmpnew" => "__builtin_altivec_vcmpnew", - "llvm.ppc.altivec.vcmpnew.p" => "__builtin_altivec_vcmpnew_p", - "llvm.ppc.altivec.vcmpnezb" => "__builtin_altivec_vcmpnezb", - "llvm.ppc.altivec.vcmpnezb.p" => "__builtin_altivec_vcmpnezb_p", - "llvm.ppc.altivec.vcmpnezh" => "__builtin_altivec_vcmpnezh", - "llvm.ppc.altivec.vcmpnezh.p" => "__builtin_altivec_vcmpnezh_p", - "llvm.ppc.altivec.vcmpnezw" => "__builtin_altivec_vcmpnezw", - "llvm.ppc.altivec.vcmpnezw.p" => "__builtin_altivec_vcmpnezw_p", - "llvm.ppc.altivec.vcntmbb" => "__builtin_altivec_vcntmbb", - "llvm.ppc.altivec.vcntmbd" => "__builtin_altivec_vcntmbd", - "llvm.ppc.altivec.vcntmbh" => "__builtin_altivec_vcntmbh", - "llvm.ppc.altivec.vcntmbw" => "__builtin_altivec_vcntmbw", - "llvm.ppc.altivec.vctsxs" => "__builtin_altivec_vctsxs", - "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs", - "llvm.ppc.altivec.vctzdm" => "__builtin_altivec_vctzdm", - "llvm.ppc.altivec.vctzlsbb" => "__builtin_altivec_vctzlsbb", - "llvm.ppc.altivec.vdivesd" => "__builtin_altivec_vdivesd", - "llvm.ppc.altivec.vdivesq" => "__builtin_altivec_vdivesq", - "llvm.ppc.altivec.vdivesw" => "__builtin_altivec_vdivesw", - "llvm.ppc.altivec.vdiveud" => "__builtin_altivec_vdiveud", - "llvm.ppc.altivec.vdiveuq" => "__builtin_altivec_vdiveuq", - "llvm.ppc.altivec.vdiveuw" => "__builtin_altivec_vdiveuw", - "llvm.ppc.altivec.vexpandbm" => "__builtin_altivec_vexpandbm", - "llvm.ppc.altivec.vexpanddm" => "__builtin_altivec_vexpanddm", - "llvm.ppc.altivec.vexpandhm" => "__builtin_altivec_vexpandhm", - "llvm.ppc.altivec.vexpandqm" => "__builtin_altivec_vexpandqm", - "llvm.ppc.altivec.vexpandwm" => "__builtin_altivec_vexpandwm", - "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", - "llvm.ppc.altivec.vextddvlx" => "__builtin_altivec_vextddvlx", - "llvm.ppc.altivec.vextddvrx" => "__builtin_altivec_vextddvrx", - "llvm.ppc.altivec.vextdubvlx" => "__builtin_altivec_vextdubvlx", - "llvm.ppc.altivec.vextdubvrx" => "__builtin_altivec_vextdubvrx", - "llvm.ppc.altivec.vextduhvlx" => "__builtin_altivec_vextduhvlx", - "llvm.ppc.altivec.vextduhvrx" => "__builtin_altivec_vextduhvrx", - "llvm.ppc.altivec.vextduwvlx" => "__builtin_altivec_vextduwvlx", - "llvm.ppc.altivec.vextduwvrx" => "__builtin_altivec_vextduwvrx", - "llvm.ppc.altivec.vextractbm" => "__builtin_altivec_vextractbm", - "llvm.ppc.altivec.vextractdm" => "__builtin_altivec_vextractdm", - "llvm.ppc.altivec.vextracthm" => "__builtin_altivec_vextracthm", - "llvm.ppc.altivec.vextractqm" => "__builtin_altivec_vextractqm", - "llvm.ppc.altivec.vextractwm" => "__builtin_altivec_vextractwm", - "llvm.ppc.altivec.vextsb2d" => "__builtin_altivec_vextsb2d", - "llvm.ppc.altivec.vextsb2w" => "__builtin_altivec_vextsb2w", - "llvm.ppc.altivec.vextsd2q" => "__builtin_altivec_vextsd2q", - "llvm.ppc.altivec.vextsh2d" => "__builtin_altivec_vextsh2d", - "llvm.ppc.altivec.vextsh2w" => "__builtin_altivec_vextsh2w", - "llvm.ppc.altivec.vextsw2d" => "__builtin_altivec_vextsw2d", - "llvm.ppc.altivec.vgbbd" => "__builtin_altivec_vgbbd", - "llvm.ppc.altivec.vgnb" => "__builtin_altivec_vgnb", - "llvm.ppc.altivec.vinsblx" => "__builtin_altivec_vinsblx", - "llvm.ppc.altivec.vinsbrx" => "__builtin_altivec_vinsbrx", - "llvm.ppc.altivec.vinsbvlx" => "__builtin_altivec_vinsbvlx", - "llvm.ppc.altivec.vinsbvrx" => "__builtin_altivec_vinsbvrx", - "llvm.ppc.altivec.vinsdlx" => "__builtin_altivec_vinsdlx", - "llvm.ppc.altivec.vinsdrx" => "__builtin_altivec_vinsdrx", - "llvm.ppc.altivec.vinshlx" => "__builtin_altivec_vinshlx", - "llvm.ppc.altivec.vinshrx" => "__builtin_altivec_vinshrx", - "llvm.ppc.altivec.vinshvlx" => "__builtin_altivec_vinshvlx", - "llvm.ppc.altivec.vinshvrx" => "__builtin_altivec_vinshvrx", - "llvm.ppc.altivec.vinswlx" => "__builtin_altivec_vinswlx", - "llvm.ppc.altivec.vinswrx" => "__builtin_altivec_vinswrx", - "llvm.ppc.altivec.vinswvlx" => "__builtin_altivec_vinswvlx", - "llvm.ppc.altivec.vinswvrx" => "__builtin_altivec_vinswvrx", - "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", - "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", - "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", - "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", - "llvm.ppc.altivec.vmaxsd" => "__builtin_altivec_vmaxsd", - "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", - "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", - "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", - "llvm.ppc.altivec.vmaxud" => "__builtin_altivec_vmaxud", - "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", - "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", - "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", - "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", - "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", - "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", - "llvm.ppc.altivec.vminsd" => "__builtin_altivec_vminsd", - "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", - "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", - "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", - "llvm.ppc.altivec.vminud" => "__builtin_altivec_vminud", - "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", - "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", - "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", - "llvm.ppc.altivec.vmsumcud" => "__builtin_altivec_vmsumcud", - "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", - "llvm.ppc.altivec.vmsumshm" => "__builtin_altivec_vmsumshm", - "llvm.ppc.altivec.vmsumshs" => "__builtin_altivec_vmsumshs", - "llvm.ppc.altivec.vmsumubm" => "__builtin_altivec_vmsumubm", - "llvm.ppc.altivec.vmsumudm" => "__builtin_altivec_vmsumudm", - "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", - "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", - "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb", - "llvm.ppc.altivec.vmulesd" => "__builtin_altivec_vmulesd", - "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh", - "llvm.ppc.altivec.vmulesw" => "__builtin_altivec_vmulesw", - "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub", - "llvm.ppc.altivec.vmuleud" => "__builtin_altivec_vmuleud", - "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh", - "llvm.ppc.altivec.vmuleuw" => "__builtin_altivec_vmuleuw", - "llvm.ppc.altivec.vmulhsd" => "__builtin_altivec_vmulhsd", - "llvm.ppc.altivec.vmulhsw" => "__builtin_altivec_vmulhsw", - "llvm.ppc.altivec.vmulhud" => "__builtin_altivec_vmulhud", - "llvm.ppc.altivec.vmulhuw" => "__builtin_altivec_vmulhuw", - "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb", - "llvm.ppc.altivec.vmulosd" => "__builtin_altivec_vmulosd", - "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh", - "llvm.ppc.altivec.vmulosw" => "__builtin_altivec_vmulosw", - "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub", - "llvm.ppc.altivec.vmuloud" => "__builtin_altivec_vmuloud", - "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh", - "llvm.ppc.altivec.vmulouw" => "__builtin_altivec_vmulouw", - "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", - "llvm.ppc.altivec.vpdepd" => "__builtin_altivec_vpdepd", - "llvm.ppc.altivec.vperm" => "__builtin_altivec_vperm_4si", - "llvm.ppc.altivec.vpextd" => "__builtin_altivec_vpextd", - "llvm.ppc.altivec.vpkpx" => "__builtin_altivec_vpkpx", - "llvm.ppc.altivec.vpksdss" => "__builtin_altivec_vpksdss", - "llvm.ppc.altivec.vpksdus" => "__builtin_altivec_vpksdus", - "llvm.ppc.altivec.vpkshss" => "__builtin_altivec_vpkshss", - "llvm.ppc.altivec.vpkshus" => "__builtin_altivec_vpkshus", - "llvm.ppc.altivec.vpkswss" => "__builtin_altivec_vpkswss", - "llvm.ppc.altivec.vpkswus" => "__builtin_altivec_vpkswus", - "llvm.ppc.altivec.vpkudus" => "__builtin_altivec_vpkudus", - "llvm.ppc.altivec.vpkuhus" => "__builtin_altivec_vpkuhus", - "llvm.ppc.altivec.vpkuwus" => "__builtin_altivec_vpkuwus", - "llvm.ppc.altivec.vprtybd" => "__builtin_altivec_vprtybd", - "llvm.ppc.altivec.vprtybq" => "__builtin_altivec_vprtybq", - "llvm.ppc.altivec.vprtybw" => "__builtin_altivec_vprtybw", - "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", - "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", - "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", - "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", - "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", - "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", - "llvm.ppc.altivec.vrld" => "__builtin_altivec_vrld", - "llvm.ppc.altivec.vrldmi" => "__builtin_altivec_vrldmi", - "llvm.ppc.altivec.vrldnm" => "__builtin_altivec_vrldnm", - "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", - "llvm.ppc.altivec.vrlqmi" => "__builtin_altivec_vrlqmi", - "llvm.ppc.altivec.vrlqnm" => "__builtin_altivec_vrlqnm", - "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", - "llvm.ppc.altivec.vrlwmi" => "__builtin_altivec_vrlwmi", - "llvm.ppc.altivec.vrlwnm" => "__builtin_altivec_vrlwnm", - "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", - "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", - "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", - "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", - "llvm.ppc.altivec.vsldbi" => "__builtin_altivec_vsldbi", - "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", - "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", - "llvm.ppc.altivec.vslv" => "__builtin_altivec_vslv", - "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", - "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", - "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", - "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", - "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", - "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", - "llvm.ppc.altivec.vsrdbi" => "__builtin_altivec_vsrdbi", - "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", - "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", - "llvm.ppc.altivec.vsrv" => "__builtin_altivec_vsrv", - "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", - "llvm.ppc.altivec.vstribl" => "__builtin_altivec_vstribl", - "llvm.ppc.altivec.vstribl.p" => "__builtin_altivec_vstribl_p", - "llvm.ppc.altivec.vstribr" => "__builtin_altivec_vstribr", - "llvm.ppc.altivec.vstribr.p" => "__builtin_altivec_vstribr_p", - "llvm.ppc.altivec.vstrihl" => "__builtin_altivec_vstrihl", - "llvm.ppc.altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p", - "llvm.ppc.altivec.vstrihr" => "__builtin_altivec_vstrihr", - "llvm.ppc.altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p", - "llvm.ppc.altivec.vsubcuq" => "__builtin_altivec_vsubcuq", - "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", - "llvm.ppc.altivec.vsubecuq" => "__builtin_altivec_vsubecuq", - "llvm.ppc.altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm", - "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", - "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", - "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", - "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs", - "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs", - "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws", - "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws", - "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", - "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs", - "llvm.ppc.altivec.vsum4ubs" => "__builtin_altivec_vsum4ubs", - "llvm.ppc.altivec.vsumsws" => "__builtin_altivec_vsumsws", - "llvm.ppc.altivec.vupkhpx" => "__builtin_altivec_vupkhpx", - "llvm.ppc.altivec.vupkhsb" => "__builtin_altivec_vupkhsb", - "llvm.ppc.altivec.vupkhsh" => "__builtin_altivec_vupkhsh", - "llvm.ppc.altivec.vupkhsw" => "__builtin_altivec_vupkhsw", - "llvm.ppc.altivec.vupklpx" => "__builtin_altivec_vupklpx", - "llvm.ppc.altivec.vupklsb" => "__builtin_altivec_vupklsb", - "llvm.ppc.altivec.vupklsh" => "__builtin_altivec_vupklsh", - "llvm.ppc.altivec.vupklsw" => "__builtin_altivec_vupklsw", - "llvm.ppc.bcdadd" => "__builtin_ppc_bcdadd", - "llvm.ppc.bcdadd.p" => "__builtin_ppc_bcdadd_p", - "llvm.ppc.bcdsub" => "__builtin_ppc_bcdsub", - "llvm.ppc.bcdsub.p" => "__builtin_ppc_bcdsub_p", - "llvm.ppc.bpermd" => "__builtin_bpermd", - "llvm.ppc.cbcdtd" => "__builtin_cbcdtd", - "llvm.ppc.cbcdtdd" => "__builtin_ppc_cbcdtd", - "llvm.ppc.cdtbcd" => "__builtin_cdtbcd", - "llvm.ppc.cdtbcdd" => "__builtin_ppc_cdtbcd", - "llvm.ppc.cfuged" => "__builtin_cfuged", - "llvm.ppc.cmpeqb" => "__builtin_ppc_cmpeqb", - "llvm.ppc.cmprb" => "__builtin_ppc_cmprb", - "llvm.ppc.cntlzdm" => "__builtin_cntlzdm", - "llvm.ppc.cnttzdm" => "__builtin_cnttzdm", - "llvm.ppc.compare.exp.eq" => "__builtin_ppc_compare_exp_eq", - "llvm.ppc.compare.exp.gt" => "__builtin_ppc_compare_exp_gt", - "llvm.ppc.compare.exp.lt" => "__builtin_ppc_compare_exp_lt", - "llvm.ppc.compare.exp.uo" => "__builtin_ppc_compare_exp_uo", - "llvm.ppc.darn" => "__builtin_darn", - "llvm.ppc.darn32" => "__builtin_darn_32", - "llvm.ppc.darnraw" => "__builtin_darn_raw", - "llvm.ppc.dcbf" => "__builtin_dcbf", - "llvm.ppc.dcbfl" => "__builtin_ppc_dcbfl", - "llvm.ppc.dcbflp" => "__builtin_ppc_dcbflp", - "llvm.ppc.dcbst" => "__builtin_ppc_dcbst", - "llvm.ppc.dcbt" => "__builtin_ppc_dcbt", - "llvm.ppc.dcbtst" => "__builtin_ppc_dcbtst", - "llvm.ppc.dcbtstt" => "__builtin_ppc_dcbtstt", - "llvm.ppc.dcbtt" => "__builtin_ppc_dcbtt", - "llvm.ppc.dcbz" => "__builtin_ppc_dcbz", - "llvm.ppc.divde" => "__builtin_divde", - "llvm.ppc.divdeu" => "__builtin_divdeu", - "llvm.ppc.divf128.round.to.odd" => "__builtin_divf128_round_to_odd", - "llvm.ppc.divwe" => "__builtin_divwe", - "llvm.ppc.divweu" => "__builtin_divweu", - "llvm.ppc.eieio" => "__builtin_ppc_eieio", - "llvm.ppc.extract.exp" => "__builtin_ppc_extract_exp", - "llvm.ppc.extract.sig" => "__builtin_ppc_extract_sig", - "llvm.ppc.fcfid" => "__builtin_ppc_fcfid", - "llvm.ppc.fcfud" => "__builtin_ppc_fcfud", - "llvm.ppc.fctid" => "__builtin_ppc_fctid", - "llvm.ppc.fctidz" => "__builtin_ppc_fctidz", - "llvm.ppc.fctiw" => "__builtin_ppc_fctiw", - "llvm.ppc.fctiwz" => "__builtin_ppc_fctiwz", - "llvm.ppc.fctudz" => "__builtin_ppc_fctudz", - "llvm.ppc.fctuwz" => "__builtin_ppc_fctuwz", - "llvm.ppc.fence" => "__builtin_ppc_fence", - "llvm.ppc.fmaf128.round.to.odd" => "__builtin_fmaf128_round_to_odd", - "llvm.ppc.fmsub" => "__builtin_ppc_fmsub", - "llvm.ppc.fmsubs" => "__builtin_ppc_fmsubs", - "llvm.ppc.fnabs" => "__builtin_ppc_fnabs", - "llvm.ppc.fnabss" => "__builtin_ppc_fnabss", - "llvm.ppc.fnmadd" => "__builtin_ppc_fnmadd", - "llvm.ppc.fnmadds" => "__builtin_ppc_fnmadds", - "llvm.ppc.fre" => "__builtin_ppc_fre", - "llvm.ppc.fres" => "__builtin_ppc_fres", - "llvm.ppc.frsqrte" => "__builtin_ppc_frsqrte", - "llvm.ppc.frsqrtes" => "__builtin_ppc_frsqrtes", - "llvm.ppc.fsel" => "__builtin_ppc_fsel", - "llvm.ppc.fsels" => "__builtin_ppc_fsels", - "llvm.ppc.get.texasr" => "__builtin_get_texasr", - "llvm.ppc.get.texasru" => "__builtin_get_texasru", - "llvm.ppc.get.tfhar" => "__builtin_get_tfhar", - "llvm.ppc.get.tfiar" => "__builtin_get_tfiar", - "llvm.ppc.icbt" => "__builtin_ppc_icbt", - "llvm.ppc.insert.exp" => "__builtin_ppc_insert_exp", - "llvm.ppc.iospace.eieio" => "__builtin_ppc_iospace_eieio", - "llvm.ppc.iospace.lwsync" => "__builtin_ppc_iospace_lwsync", - "llvm.ppc.iospace.sync" => "__builtin_ppc_iospace_sync", - "llvm.ppc.isync" => "__builtin_ppc_isync", - "llvm.ppc.load4r" => "__builtin_ppc_load4r", - "llvm.ppc.load8r" => "__builtin_ppc_load8r", - "llvm.ppc.lwsync" => "__builtin_ppc_lwsync", - "llvm.ppc.maddhd" => "__builtin_ppc_maddhd", - "llvm.ppc.maddhdu" => "__builtin_ppc_maddhdu", - "llvm.ppc.maddld" => "__builtin_ppc_maddld", - "llvm.ppc.mffsl" => "__builtin_ppc_mffsl", - "llvm.ppc.mfmsr" => "__builtin_ppc_mfmsr", - "llvm.ppc.mftbu" => "__builtin_ppc_mftbu", - "llvm.ppc.mtfsb0" => "__builtin_ppc_mtfsb0", - "llvm.ppc.mtfsb1" => "__builtin_ppc_mtfsb1", - "llvm.ppc.mtfsfi" => "__builtin_ppc_mtfsfi", - "llvm.ppc.mtmsr" => "__builtin_ppc_mtmsr", - "llvm.ppc.mulf128.round.to.odd" => "__builtin_mulf128_round_to_odd", - "llvm.ppc.mulhd" => "__builtin_ppc_mulhd", - "llvm.ppc.mulhdu" => "__builtin_ppc_mulhdu", - "llvm.ppc.mulhw" => "__builtin_ppc_mulhw", - "llvm.ppc.mulhwu" => "__builtin_ppc_mulhwu", - "llvm.ppc.pack.longdouble" => "__builtin_pack_longdouble", - "llvm.ppc.pdepd" => "__builtin_pdepd", - "llvm.ppc.pextd" => "__builtin_pextd", - "llvm.ppc.qpx.qvfabs" => "__builtin_qpx_qvfabs", - "llvm.ppc.qpx.qvfadd" => "__builtin_qpx_qvfadd", - "llvm.ppc.qpx.qvfadds" => "__builtin_qpx_qvfadds", - "llvm.ppc.qpx.qvfcfid" => "__builtin_qpx_qvfcfid", - "llvm.ppc.qpx.qvfcfids" => "__builtin_qpx_qvfcfids", - "llvm.ppc.qpx.qvfcfidu" => "__builtin_qpx_qvfcfidu", - "llvm.ppc.qpx.qvfcfidus" => "__builtin_qpx_qvfcfidus", - "llvm.ppc.qpx.qvfcmpeq" => "__builtin_qpx_qvfcmpeq", - "llvm.ppc.qpx.qvfcmpgt" => "__builtin_qpx_qvfcmpgt", - "llvm.ppc.qpx.qvfcmplt" => "__builtin_qpx_qvfcmplt", - "llvm.ppc.qpx.qvfcpsgn" => "__builtin_qpx_qvfcpsgn", - "llvm.ppc.qpx.qvfctid" => "__builtin_qpx_qvfctid", - "llvm.ppc.qpx.qvfctidu" => "__builtin_qpx_qvfctidu", - "llvm.ppc.qpx.qvfctiduz" => "__builtin_qpx_qvfctiduz", - "llvm.ppc.qpx.qvfctidz" => "__builtin_qpx_qvfctidz", - "llvm.ppc.qpx.qvfctiw" => "__builtin_qpx_qvfctiw", - "llvm.ppc.qpx.qvfctiwu" => "__builtin_qpx_qvfctiwu", - "llvm.ppc.qpx.qvfctiwuz" => "__builtin_qpx_qvfctiwuz", - "llvm.ppc.qpx.qvfctiwz" => "__builtin_qpx_qvfctiwz", - "llvm.ppc.qpx.qvflogical" => "__builtin_qpx_qvflogical", - "llvm.ppc.qpx.qvfmadd" => "__builtin_qpx_qvfmadd", - "llvm.ppc.qpx.qvfmadds" => "__builtin_qpx_qvfmadds", - "llvm.ppc.qpx.qvfmsub" => "__builtin_qpx_qvfmsub", - "llvm.ppc.qpx.qvfmsubs" => "__builtin_qpx_qvfmsubs", - "llvm.ppc.qpx.qvfmul" => "__builtin_qpx_qvfmul", - "llvm.ppc.qpx.qvfmuls" => "__builtin_qpx_qvfmuls", - "llvm.ppc.qpx.qvfnabs" => "__builtin_qpx_qvfnabs", - "llvm.ppc.qpx.qvfneg" => "__builtin_qpx_qvfneg", - "llvm.ppc.qpx.qvfnmadd" => "__builtin_qpx_qvfnmadd", - "llvm.ppc.qpx.qvfnmadds" => "__builtin_qpx_qvfnmadds", - "llvm.ppc.qpx.qvfnmsub" => "__builtin_qpx_qvfnmsub", - "llvm.ppc.qpx.qvfnmsubs" => "__builtin_qpx_qvfnmsubs", - "llvm.ppc.qpx.qvfperm" => "__builtin_qpx_qvfperm", - "llvm.ppc.qpx.qvfre" => "__builtin_qpx_qvfre", - "llvm.ppc.qpx.qvfres" => "__builtin_qpx_qvfres", - "llvm.ppc.qpx.qvfrim" => "__builtin_qpx_qvfrim", - "llvm.ppc.qpx.qvfrin" => "__builtin_qpx_qvfrin", - "llvm.ppc.qpx.qvfrip" => "__builtin_qpx_qvfrip", - "llvm.ppc.qpx.qvfriz" => "__builtin_qpx_qvfriz", - "llvm.ppc.qpx.qvfrsp" => "__builtin_qpx_qvfrsp", - "llvm.ppc.qpx.qvfrsqrte" => "__builtin_qpx_qvfrsqrte", - "llvm.ppc.qpx.qvfrsqrtes" => "__builtin_qpx_qvfrsqrtes", - "llvm.ppc.qpx.qvfsel" => "__builtin_qpx_qvfsel", - "llvm.ppc.qpx.qvfsub" => "__builtin_qpx_qvfsub", - "llvm.ppc.qpx.qvfsubs" => "__builtin_qpx_qvfsubs", - "llvm.ppc.qpx.qvftstnan" => "__builtin_qpx_qvftstnan", - "llvm.ppc.qpx.qvfxmadd" => "__builtin_qpx_qvfxmadd", - "llvm.ppc.qpx.qvfxmadds" => "__builtin_qpx_qvfxmadds", - "llvm.ppc.qpx.qvfxmul" => "__builtin_qpx_qvfxmul", - "llvm.ppc.qpx.qvfxmuls" => "__builtin_qpx_qvfxmuls", - "llvm.ppc.qpx.qvfxxcpnmadd" => "__builtin_qpx_qvfxxcpnmadd", - "llvm.ppc.qpx.qvfxxcpnmadds" => "__builtin_qpx_qvfxxcpnmadds", - "llvm.ppc.qpx.qvfxxmadd" => "__builtin_qpx_qvfxxmadd", - "llvm.ppc.qpx.qvfxxmadds" => "__builtin_qpx_qvfxxmadds", - "llvm.ppc.qpx.qvfxxnpmadd" => "__builtin_qpx_qvfxxnpmadd", - "llvm.ppc.qpx.qvfxxnpmadds" => "__builtin_qpx_qvfxxnpmadds", - "llvm.ppc.qpx.qvgpci" => "__builtin_qpx_qvgpci", - "llvm.ppc.qpx.qvlfcd" => "__builtin_qpx_qvlfcd", - "llvm.ppc.qpx.qvlfcda" => "__builtin_qpx_qvlfcda", - "llvm.ppc.qpx.qvlfcs" => "__builtin_qpx_qvlfcs", - "llvm.ppc.qpx.qvlfcsa" => "__builtin_qpx_qvlfcsa", - "llvm.ppc.qpx.qvlfd" => "__builtin_qpx_qvlfd", - "llvm.ppc.qpx.qvlfda" => "__builtin_qpx_qvlfda", - "llvm.ppc.qpx.qvlfiwa" => "__builtin_qpx_qvlfiwa", - "llvm.ppc.qpx.qvlfiwaa" => "__builtin_qpx_qvlfiwaa", - "llvm.ppc.qpx.qvlfiwz" => "__builtin_qpx_qvlfiwz", - "llvm.ppc.qpx.qvlfiwza" => "__builtin_qpx_qvlfiwza", - "llvm.ppc.qpx.qvlfs" => "__builtin_qpx_qvlfs", - "llvm.ppc.qpx.qvlfsa" => "__builtin_qpx_qvlfsa", - "llvm.ppc.qpx.qvlpcld" => "__builtin_qpx_qvlpcld", - "llvm.ppc.qpx.qvlpcls" => "__builtin_qpx_qvlpcls", - "llvm.ppc.qpx.qvlpcrd" => "__builtin_qpx_qvlpcrd", - "llvm.ppc.qpx.qvlpcrs" => "__builtin_qpx_qvlpcrs", - "llvm.ppc.qpx.qvstfcd" => "__builtin_qpx_qvstfcd", - "llvm.ppc.qpx.qvstfcda" => "__builtin_qpx_qvstfcda", - "llvm.ppc.qpx.qvstfcs" => "__builtin_qpx_qvstfcs", - "llvm.ppc.qpx.qvstfcsa" => "__builtin_qpx_qvstfcsa", - "llvm.ppc.qpx.qvstfd" => "__builtin_qpx_qvstfd", - "llvm.ppc.qpx.qvstfda" => "__builtin_qpx_qvstfda", - "llvm.ppc.qpx.qvstfiw" => "__builtin_qpx_qvstfiw", - "llvm.ppc.qpx.qvstfiwa" => "__builtin_qpx_qvstfiwa", - "llvm.ppc.qpx.qvstfs" => "__builtin_qpx_qvstfs", - "llvm.ppc.qpx.qvstfsa" => "__builtin_qpx_qvstfsa", - "llvm.ppc.readflm" => "__builtin_readflm", - "llvm.ppc.rlwimi" => "__builtin_ppc_rlwimi", - "llvm.ppc.rlwnm" => "__builtin_ppc_rlwnm", - "llvm.ppc.scalar.extract.expq" => "__builtin_vsx_scalar_extract_expq", - "llvm.ppc.scalar.insert.exp.qp" => "__builtin_vsx_scalar_insert_exp_qp", - "llvm.ppc.set.texasr" => "__builtin_set_texasr", - "llvm.ppc.set.texasru" => "__builtin_set_texasru", - "llvm.ppc.set.tfhar" => "__builtin_set_tfhar", - "llvm.ppc.set.tfiar" => "__builtin_set_tfiar", - "llvm.ppc.setb" => "__builtin_ppc_setb", - "llvm.ppc.setflm" => "__builtin_setflm", - "llvm.ppc.setrnd" => "__builtin_setrnd", - "llvm.ppc.sqrtf128.round.to.odd" => "__builtin_sqrtf128_round_to_odd", - "llvm.ppc.stbcx" => "__builtin_ppc_stbcx", - "llvm.ppc.stdcx" => "__builtin_ppc_stdcx", - "llvm.ppc.stfiw" => "__builtin_ppc_stfiw", - "llvm.ppc.store2r" => "__builtin_ppc_store2r", - "llvm.ppc.store4r" => "__builtin_ppc_store4r", - "llvm.ppc.store8r" => "__builtin_ppc_store8r", - "llvm.ppc.stwcx" => "__builtin_ppc_stwcx", - "llvm.ppc.subf128.round.to.odd" => "__builtin_subf128_round_to_odd", - "llvm.ppc.sync" => "__builtin_ppc_sync", - "llvm.ppc.tabort" => "__builtin_tabort", - "llvm.ppc.tabortdc" => "__builtin_tabortdc", - "llvm.ppc.tabortdci" => "__builtin_tabortdci", - "llvm.ppc.tabortwc" => "__builtin_tabortwc", - "llvm.ppc.tabortwci" => "__builtin_tabortwci", - "llvm.ppc.tbegin" => "__builtin_tbegin", - "llvm.ppc.tcheck" => "__builtin_tcheck", - "llvm.ppc.tdw" => "__builtin_ppc_tdw", - "llvm.ppc.tend" => "__builtin_tend", - "llvm.ppc.tendall" => "__builtin_tendall", - "llvm.ppc.trap" => "__builtin_ppc_trap", - "llvm.ppc.trapd" => "__builtin_ppc_trapd", - "llvm.ppc.trechkpt" => "__builtin_trechkpt", - "llvm.ppc.treclaim" => "__builtin_treclaim", - "llvm.ppc.tresume" => "__builtin_tresume", - "llvm.ppc.truncf128.round.to.odd" => "__builtin_truncf128_round_to_odd", - "llvm.ppc.tsr" => "__builtin_tsr", - "llvm.ppc.tsuspend" => "__builtin_tsuspend", - "llvm.ppc.ttest" => "__builtin_ttest", - "llvm.ppc.tw" => "__builtin_ppc_tw", - "llvm.ppc.unpack.longdouble" => "__builtin_unpack_longdouble", - "llvm.ppc.vsx.xsmaxdp" => "__builtin_vsx_xsmaxdp", - "llvm.ppc.vsx.xsmindp" => "__builtin_vsx_xsmindp", - "llvm.ppc.vsx.xvcmpeqdp" => "__builtin_vsx_xvcmpeqdp", - "llvm.ppc.vsx.xvcmpeqdp.p" => "__builtin_vsx_xvcmpeqdp_p", - "llvm.ppc.vsx.xvcmpeqsp" => "__builtin_vsx_xvcmpeqsp", - "llvm.ppc.vsx.xvcmpeqsp.p" => "__builtin_vsx_xvcmpeqsp_p", - "llvm.ppc.vsx.xvcmpgedp" => "__builtin_vsx_xvcmpgedp", - "llvm.ppc.vsx.xvcmpgedp.p" => "__builtin_vsx_xvcmpgedp_p", - "llvm.ppc.vsx.xvcmpgesp" => "__builtin_vsx_xvcmpgesp", - "llvm.ppc.vsx.xvcmpgesp.p" => "__builtin_vsx_xvcmpgesp_p", - "llvm.ppc.vsx.xvcmpgtdp" => "__builtin_vsx_xvcmpgtdp", - "llvm.ppc.vsx.xvcmpgtdp.p" => "__builtin_vsx_xvcmpgtdp_p", - "llvm.ppc.vsx.xvcmpgtsp" => "__builtin_vsx_xvcmpgtsp", - "llvm.ppc.vsx.xvcmpgtsp.p" => "__builtin_vsx_xvcmpgtsp_p", - "llvm.ppc.vsx.xvcvbf16spn" => "__builtin_vsx_xvcvbf16spn", - "llvm.ppc.vsx.xvcvdpsp" => "__builtin_vsx_xvcvdpsp", - "llvm.ppc.vsx.xvcvdpsxws" => "__builtin_vsx_xvcvdpsxws", - "llvm.ppc.vsx.xvcvdpuxws" => "__builtin_vsx_xvcvdpuxws", - "llvm.ppc.vsx.xvcvhpsp" => "__builtin_vsx_xvcvhpsp", - "llvm.ppc.vsx.xvcvspbf16" => "__builtin_vsx_xvcvspbf16", - "llvm.ppc.vsx.xvcvspdp" => "__builtin_vsx_xvcvspdp", - "llvm.ppc.vsx.xvcvsphp" => "__builtin_vsx_xvcvsphp", - "llvm.ppc.vsx.xvcvspsxds" => "__builtin_vsx_xvcvspsxds", - "llvm.ppc.vsx.xvcvspuxds" => "__builtin_vsx_xvcvspuxds", - "llvm.ppc.vsx.xvcvsxdsp" => "__builtin_vsx_xvcvsxdsp", - "llvm.ppc.vsx.xvcvsxwdp" => "__builtin_vsx_xvcvsxwdp", - "llvm.ppc.vsx.xvcvuxdsp" => "__builtin_vsx_xvcvuxdsp", - "llvm.ppc.vsx.xvcvuxwdp" => "__builtin_vsx_xvcvuxwdp", - "llvm.ppc.vsx.xvdivdp" => "__builtin_vsx_xvdivdp", - "llvm.ppc.vsx.xvdivsp" => "__builtin_vsx_xvdivsp", - "llvm.ppc.vsx.xviexpdp" => "__builtin_vsx_xviexpdp", - "llvm.ppc.vsx.xviexpsp" => "__builtin_vsx_xviexpsp", - "llvm.ppc.vsx.xvmaxdp" => "__builtin_vsx_xvmaxdp", - "llvm.ppc.vsx.xvmaxsp" => "__builtin_vsx_xvmaxsp", - "llvm.ppc.vsx.xvmindp" => "__builtin_vsx_xvmindp", - "llvm.ppc.vsx.xvminsp" => "__builtin_vsx_xvminsp", - "llvm.ppc.vsx.xvredp" => "__builtin_vsx_xvredp", - "llvm.ppc.vsx.xvresp" => "__builtin_vsx_xvresp", - "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", - "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", - "llvm.ppc.vsx.xvtdivdp" => "__builtin_vsx_xvtdivdp", - "llvm.ppc.vsx.xvtdivsp" => "__builtin_vsx_xvtdivsp", - "llvm.ppc.vsx.xvtlsbb" => "__builtin_vsx_xvtlsbb", - "llvm.ppc.vsx.xvtsqrtdp" => "__builtin_vsx_xvtsqrtdp", - "llvm.ppc.vsx.xvtsqrtsp" => "__builtin_vsx_xvtsqrtsp", - "llvm.ppc.vsx.xvtstdcdp" => "__builtin_vsx_xvtstdcdp", - "llvm.ppc.vsx.xvtstdcsp" => "__builtin_vsx_xvtstdcsp", - "llvm.ppc.vsx.xvxexpdp" => "__builtin_vsx_xvxexpdp", - "llvm.ppc.vsx.xvxexpsp" => "__builtin_vsx_xvxexpsp", - "llvm.ppc.vsx.xvxsigdp" => "__builtin_vsx_xvxsigdp", - "llvm.ppc.vsx.xvxsigsp" => "__builtin_vsx_xvxsigsp", - "llvm.ppc.vsx.xxblendvb" => "__builtin_vsx_xxblendvb", - "llvm.ppc.vsx.xxblendvd" => "__builtin_vsx_xxblendvd", - "llvm.ppc.vsx.xxblendvh" => "__builtin_vsx_xxblendvh", - "llvm.ppc.vsx.xxblendvw" => "__builtin_vsx_xxblendvw", - "llvm.ppc.vsx.xxeval" => "__builtin_vsx_xxeval", - "llvm.ppc.vsx.xxextractuw" => "__builtin_vsx_xxextractuw", - "llvm.ppc.vsx.xxgenpcvbm" => "__builtin_vsx_xxgenpcvbm", - "llvm.ppc.vsx.xxgenpcvdm" => "__builtin_vsx_xxgenpcvdm", - "llvm.ppc.vsx.xxgenpcvhm" => "__builtin_vsx_xxgenpcvhm", - "llvm.ppc.vsx.xxgenpcvwm" => "__builtin_vsx_xxgenpcvwm", - "llvm.ppc.vsx.xxinsertw" => "__builtin_vsx_xxinsertw", - "llvm.ppc.vsx.xxleqv" => "__builtin_vsx_xxleqv", - "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", - // ptx - "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", - "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", - "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", - "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", - "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", - "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", - "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", - "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", - "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", - "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", - "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", - "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", - "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", - "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", - "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", - "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", - "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", - "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", - // r600 - "llvm.r600.group.barrier" => "__builtin_r600_group_barrier", - "llvm.r600.implicitarg.ptr" => "__builtin_r600_implicitarg_ptr", - "llvm.r600.rat.store.typed" => "__builtin_r600_rat_store_typed", - "llvm.r600.read.global.size.x" => "__builtin_r600_read_global_size_x", - "llvm.r600.read.global.size.y" => "__builtin_r600_read_global_size_y", - "llvm.r600.read.global.size.z" => "__builtin_r600_read_global_size_z", - "llvm.r600.read.ngroups.x" => "__builtin_r600_read_ngroups_x", - "llvm.r600.read.ngroups.y" => "__builtin_r600_read_ngroups_y", - "llvm.r600.read.ngroups.z" => "__builtin_r600_read_ngroups_z", - "llvm.r600.read.tgid.x" => "__builtin_r600_read_tgid_x", - "llvm.r600.read.tgid.y" => "__builtin_r600_read_tgid_y", - "llvm.r600.read.tgid.z" => "__builtin_r600_read_tgid_z", - "llvm.r600.read.tidig.x" => "__builtin_r600_read_tidig_x", - "llvm.r600.read.tidig.y" => "__builtin_r600_read_tidig_y", - "llvm.r600.read.tidig.z" => "__builtin_r600_read_tidig_z", - // riscv - "llvm.riscv.aes32dsi" => "__builtin_riscv_aes32dsi", - "llvm.riscv.aes32dsmi" => "__builtin_riscv_aes32dsmi", - "llvm.riscv.aes32esi" => "__builtin_riscv_aes32esi", - "llvm.riscv.aes32esmi" => "__builtin_riscv_aes32esmi", - "llvm.riscv.aes64ds" => "__builtin_riscv_aes64ds", - "llvm.riscv.aes64dsm" => "__builtin_riscv_aes64dsm", - "llvm.riscv.aes64es" => "__builtin_riscv_aes64es", - "llvm.riscv.aes64esm" => "__builtin_riscv_aes64esm", - "llvm.riscv.aes64im" => "__builtin_riscv_aes64im", - "llvm.riscv.aes64ks1i" => "__builtin_riscv_aes64ks1i", - "llvm.riscv.aes64ks2" => "__builtin_riscv_aes64ks2", - "llvm.riscv.sha512sig0" => "__builtin_riscv_sha512sig0", - "llvm.riscv.sha512sig0h" => "__builtin_riscv_sha512sig0h", - "llvm.riscv.sha512sig0l" => "__builtin_riscv_sha512sig0l", - "llvm.riscv.sha512sig1" => "__builtin_riscv_sha512sig1", - "llvm.riscv.sha512sig1h" => "__builtin_riscv_sha512sig1h", - "llvm.riscv.sha512sig1l" => "__builtin_riscv_sha512sig1l", - "llvm.riscv.sha512sum0" => "__builtin_riscv_sha512sum0", - "llvm.riscv.sha512sum0r" => "__builtin_riscv_sha512sum0r", - "llvm.riscv.sha512sum1" => "__builtin_riscv_sha512sum1", - "llvm.riscv.sha512sum1r" => "__builtin_riscv_sha512sum1r", - // s390 - "llvm.s390.bdepg" => "__builtin_s390_bdepg", - "llvm.s390.bextg" => "__builtin_s390_bextg", - "llvm.s390.efpc" => "__builtin_s390_efpc", - "llvm.s390.etnd" => "__builtin_tx_nesting_depth", - "llvm.s390.lcbb" => "__builtin_s390_lcbb", - "llvm.s390.ppa.txassist" => "__builtin_tx_assist", - "llvm.s390.sfpc" => "__builtin_s390_sfpc", - "llvm.s390.tend" => "__builtin_tend", - "llvm.s390.vaccb" => "__builtin_s390_vaccb", - "llvm.s390.vacccq" => "__builtin_s390_vacccq", - "llvm.s390.vaccf" => "__builtin_s390_vaccf", - "llvm.s390.vaccg" => "__builtin_s390_vaccg", - "llvm.s390.vacch" => "__builtin_s390_vacch", - "llvm.s390.vaccq" => "__builtin_s390_vaccq", - "llvm.s390.vacq" => "__builtin_s390_vacq", - "llvm.s390.vaq" => "__builtin_s390_vaq", - "llvm.s390.vavgb" => "__builtin_s390_vavgb", - "llvm.s390.vavgf" => "__builtin_s390_vavgf", - "llvm.s390.vavgg" => "__builtin_s390_vavgg", - "llvm.s390.vavgh" => "__builtin_s390_vavgh", - "llvm.s390.vavglb" => "__builtin_s390_vavglb", - "llvm.s390.vavglf" => "__builtin_s390_vavglf", - "llvm.s390.vavglg" => "__builtin_s390_vavglg", - "llvm.s390.vavglh" => "__builtin_s390_vavglh", - "llvm.s390.vavglq" => "__builtin_s390_vavglq", - "llvm.s390.vavgq" => "__builtin_s390_vavgq", - "llvm.s390.vbperm" => "__builtin_s390_vbperm", - "llvm.s390.vcfn" => "__builtin_s390_vcfn", - "llvm.s390.vcksm" => "__builtin_s390_vcksm", - "llvm.s390.vclfnhs" => "__builtin_s390_vclfnhs", - "llvm.s390.vclfnls" => "__builtin_s390_vclfnls", - "llvm.s390.vcnf" => "__builtin_s390_vcnf", - "llvm.s390.vcrnfs" => "__builtin_s390_vcrnfs", - "llvm.s390.verimb" => "__builtin_s390_verimb", - "llvm.s390.verimf" => "__builtin_s390_verimf", - "llvm.s390.verimg" => "__builtin_s390_verimg", - "llvm.s390.verimh" => "__builtin_s390_verimh", - "llvm.s390.veval" => "__builtin_s390_veval", - "llvm.s390.vfaeb" => "__builtin_s390_vfaeb", - "llvm.s390.vfaef" => "__builtin_s390_vfaef", - "llvm.s390.vfaeh" => "__builtin_s390_vfaeh", - "llvm.s390.vfaezb" => "__builtin_s390_vfaezb", - "llvm.s390.vfaezf" => "__builtin_s390_vfaezf", - "llvm.s390.vfaezh" => "__builtin_s390_vfaezh", - "llvm.s390.vfeeb" => "__builtin_s390_vfeeb", - "llvm.s390.vfeef" => "__builtin_s390_vfeef", - "llvm.s390.vfeeh" => "__builtin_s390_vfeeh", - "llvm.s390.vfeezb" => "__builtin_s390_vfeezb", - "llvm.s390.vfeezf" => "__builtin_s390_vfeezf", - "llvm.s390.vfeezh" => "__builtin_s390_vfeezh", - "llvm.s390.vfeneb" => "__builtin_s390_vfeneb", - "llvm.s390.vfenef" => "__builtin_s390_vfenef", - "llvm.s390.vfeneh" => "__builtin_s390_vfeneh", - "llvm.s390.vfenezb" => "__builtin_s390_vfenezb", - "llvm.s390.vfenezf" => "__builtin_s390_vfenezf", - "llvm.s390.vfenezh" => "__builtin_s390_vfenezh", - "llvm.s390.vgemb" => "__builtin_s390_vgemb", - "llvm.s390.vgemf" => "__builtin_s390_vgemf", - "llvm.s390.vgemg" => "__builtin_s390_vgemg", - "llvm.s390.vgemh" => "__builtin_s390_vgemh", - "llvm.s390.vgemq" => "__builtin_s390_vgemq", - "llvm.s390.vgfmab" => "__builtin_s390_vgfmab", - "llvm.s390.vgfmaf" => "__builtin_s390_vgfmaf", - "llvm.s390.vgfmag" => "__builtin_s390_vgfmag", - "llvm.s390.vgfmah" => "__builtin_s390_vgfmah", - "llvm.s390.vgfmb" => "__builtin_s390_vgfmb", - "llvm.s390.vgfmf" => "__builtin_s390_vgfmf", - "llvm.s390.vgfmg" => "__builtin_s390_vgfmg", - "llvm.s390.vgfmh" => "__builtin_s390_vgfmh", - "llvm.s390.vistrb" => "__builtin_s390_vistrb", - "llvm.s390.vistrf" => "__builtin_s390_vistrf", - "llvm.s390.vistrh" => "__builtin_s390_vistrh", - "llvm.s390.vlbb" => "__builtin_s390_vlbb", - "llvm.s390.vll" => "__builtin_s390_vll", - "llvm.s390.vlrl" => "__builtin_s390_vlrlr", - "llvm.s390.vmaeb" => "__builtin_s390_vmaeb", - "llvm.s390.vmaef" => "__builtin_s390_vmaef", - "llvm.s390.vmaeg" => "__builtin_s390_vmaeg", - "llvm.s390.vmaeh" => "__builtin_s390_vmaeh", - "llvm.s390.vmahb" => "__builtin_s390_vmahb", - "llvm.s390.vmahf" => "__builtin_s390_vmahf", - "llvm.s390.vmahg" => "__builtin_s390_vmahg", - "llvm.s390.vmahh" => "__builtin_s390_vmahh", - "llvm.s390.vmahq" => "__builtin_s390_vmahq", - "llvm.s390.vmaleb" => "__builtin_s390_vmaleb", - "llvm.s390.vmalef" => "__builtin_s390_vmalef", - "llvm.s390.vmaleg" => "__builtin_s390_vmaleg", - "llvm.s390.vmaleh" => "__builtin_s390_vmaleh", - "llvm.s390.vmalhb" => "__builtin_s390_vmalhb", - "llvm.s390.vmalhf" => "__builtin_s390_vmalhf", - "llvm.s390.vmalhg" => "__builtin_s390_vmalhg", - "llvm.s390.vmalhh" => "__builtin_s390_vmalhh", - "llvm.s390.vmalhq" => "__builtin_s390_vmalhq", - "llvm.s390.vmalob" => "__builtin_s390_vmalob", - "llvm.s390.vmalof" => "__builtin_s390_vmalof", - "llvm.s390.vmalog" => "__builtin_s390_vmalog", - "llvm.s390.vmaloh" => "__builtin_s390_vmaloh", - "llvm.s390.vmaob" => "__builtin_s390_vmaob", - "llvm.s390.vmaof" => "__builtin_s390_vmaof", - "llvm.s390.vmaog" => "__builtin_s390_vmaog", - "llvm.s390.vmaoh" => "__builtin_s390_vmaoh", - "llvm.s390.vmeb" => "__builtin_s390_vmeb", - "llvm.s390.vmef" => "__builtin_s390_vmef", - "llvm.s390.vmeg" => "__builtin_s390_vmeg", - "llvm.s390.vmeh" => "__builtin_s390_vmeh", - "llvm.s390.vmhb" => "__builtin_s390_vmhb", - "llvm.s390.vmhf" => "__builtin_s390_vmhf", - "llvm.s390.vmhg" => "__builtin_s390_vmhg", - "llvm.s390.vmhh" => "__builtin_s390_vmhh", - "llvm.s390.vmhq" => "__builtin_s390_vmhq", - "llvm.s390.vmleb" => "__builtin_s390_vmleb", - "llvm.s390.vmlef" => "__builtin_s390_vmlef", - "llvm.s390.vmleg" => "__builtin_s390_vmleg", - "llvm.s390.vmleh" => "__builtin_s390_vmleh", - "llvm.s390.vmlhb" => "__builtin_s390_vmlhb", - "llvm.s390.vmlhf" => "__builtin_s390_vmlhf", - "llvm.s390.vmlhg" => "__builtin_s390_vmlhg", - "llvm.s390.vmlhh" => "__builtin_s390_vmlhh", - "llvm.s390.vmlhq" => "__builtin_s390_vmlhq", - "llvm.s390.vmlob" => "__builtin_s390_vmlob", - "llvm.s390.vmlof" => "__builtin_s390_vmlof", - "llvm.s390.vmlog" => "__builtin_s390_vmlog", - "llvm.s390.vmloh" => "__builtin_s390_vmloh", - "llvm.s390.vmob" => "__builtin_s390_vmob", - "llvm.s390.vmof" => "__builtin_s390_vmof", - "llvm.s390.vmog" => "__builtin_s390_vmog", - "llvm.s390.vmoh" => "__builtin_s390_vmoh", - "llvm.s390.vmslg" => "__builtin_s390_vmslg", - "llvm.s390.vpdi" => "__builtin_s390_vpdi", - "llvm.s390.vperm" => "__builtin_s390_vperm", - "llvm.s390.vpklsf" => "__builtin_s390_vpklsf", - "llvm.s390.vpklsg" => "__builtin_s390_vpklsg", - "llvm.s390.vpklsh" => "__builtin_s390_vpklsh", - "llvm.s390.vpksf" => "__builtin_s390_vpksf", - "llvm.s390.vpksg" => "__builtin_s390_vpksg", - "llvm.s390.vpksh" => "__builtin_s390_vpksh", - "llvm.s390.vsbcbiq" => "__builtin_s390_vsbcbiq", - "llvm.s390.vsbiq" => "__builtin_s390_vsbiq", - "llvm.s390.vscbib" => "__builtin_s390_vscbib", - "llvm.s390.vscbif" => "__builtin_s390_vscbif", - "llvm.s390.vscbig" => "__builtin_s390_vscbig", - "llvm.s390.vscbih" => "__builtin_s390_vscbih", - "llvm.s390.vscbiq" => "__builtin_s390_vscbiq", - "llvm.s390.vsl" => "__builtin_s390_vsl", - "llvm.s390.vslb" => "__builtin_s390_vslb", - "llvm.s390.vsld" => "__builtin_s390_vsld", - "llvm.s390.vsldb" => "__builtin_s390_vsldb", - "llvm.s390.vsq" => "__builtin_s390_vsq", - "llvm.s390.vsra" => "__builtin_s390_vsra", - "llvm.s390.vsrab" => "__builtin_s390_vsrab", - "llvm.s390.vsrd" => "__builtin_s390_vsrd", - "llvm.s390.vsrl" => "__builtin_s390_vsrl", - "llvm.s390.vsrlb" => "__builtin_s390_vsrlb", - "llvm.s390.vstl" => "__builtin_s390_vstl", - "llvm.s390.vstrcb" => "__builtin_s390_vstrcb", - "llvm.s390.vstrcf" => "__builtin_s390_vstrcf", - "llvm.s390.vstrch" => "__builtin_s390_vstrch", - "llvm.s390.vstrczb" => "__builtin_s390_vstrczb", - "llvm.s390.vstrczf" => "__builtin_s390_vstrczf", - "llvm.s390.vstrczh" => "__builtin_s390_vstrczh", - "llvm.s390.vstrl" => "__builtin_s390_vstrlr", - "llvm.s390.vsumb" => "__builtin_s390_vsumb", - "llvm.s390.vsumgf" => "__builtin_s390_vsumgf", - "llvm.s390.vsumgh" => "__builtin_s390_vsumgh", - "llvm.s390.vsumh" => "__builtin_s390_vsumh", - "llvm.s390.vsumqf" => "__builtin_s390_vsumqf", - "llvm.s390.vsumqg" => "__builtin_s390_vsumqg", - "llvm.s390.vtm" => "__builtin_s390_vtm", - "llvm.s390.vuphb" => "__builtin_s390_vuphb", - "llvm.s390.vuphf" => "__builtin_s390_vuphf", - "llvm.s390.vuphg" => "__builtin_s390_vuphg", - "llvm.s390.vuphh" => "__builtin_s390_vuphh", - "llvm.s390.vuplb" => "__builtin_s390_vuplb", - "llvm.s390.vuplf" => "__builtin_s390_vuplf", - "llvm.s390.vuplg" => "__builtin_s390_vuplg", - "llvm.s390.vuplhb" => "__builtin_s390_vuplhb", - "llvm.s390.vuplhf" => "__builtin_s390_vuplhf", - "llvm.s390.vuplhg" => "__builtin_s390_vuplhg", - "llvm.s390.vuplhh" => "__builtin_s390_vuplhh", - "llvm.s390.vuplhw" => "__builtin_s390_vuplhw", - "llvm.s390.vupllb" => "__builtin_s390_vupllb", - "llvm.s390.vupllf" => "__builtin_s390_vupllf", - "llvm.s390.vupllg" => "__builtin_s390_vupllg", - "llvm.s390.vupllh" => "__builtin_s390_vupllh", - // ve - "llvm.ve.vl.andm.MMM" => "__builtin_ve_vl_andm_MMM", - "llvm.ve.vl.andm.mmm" => "__builtin_ve_vl_andm_mmm", - "llvm.ve.vl.eqvm.MMM" => "__builtin_ve_vl_eqvm_MMM", - "llvm.ve.vl.eqvm.mmm" => "__builtin_ve_vl_eqvm_mmm", - "llvm.ve.vl.extract.vm512l" => "__builtin_ve_vl_extract_vm512l", - "llvm.ve.vl.extract.vm512u" => "__builtin_ve_vl_extract_vm512u", - "llvm.ve.vl.fencec.s" => "__builtin_ve_vl_fencec_s", - "llvm.ve.vl.fencei" => "__builtin_ve_vl_fencei", - "llvm.ve.vl.fencem.s" => "__builtin_ve_vl_fencem_s", - "llvm.ve.vl.fidcr.sss" => "__builtin_ve_vl_fidcr_sss", - "llvm.ve.vl.insert.vm512l" => "__builtin_ve_vl_insert_vm512l", - "llvm.ve.vl.insert.vm512u" => "__builtin_ve_vl_insert_vm512u", - "llvm.ve.vl.lcr.sss" => "__builtin_ve_vl_lcr_sss", - "llvm.ve.vl.lsv.vvss" => "__builtin_ve_vl_lsv_vvss", - "llvm.ve.vl.lvm.MMss" => "__builtin_ve_vl_lvm_MMss", - "llvm.ve.vl.lvm.mmss" => "__builtin_ve_vl_lvm_mmss", - "llvm.ve.vl.lvsd.svs" => "__builtin_ve_vl_lvsd_svs", - "llvm.ve.vl.lvsl.svs" => "__builtin_ve_vl_lvsl_svs", - "llvm.ve.vl.lvss.svs" => "__builtin_ve_vl_lvss_svs", - "llvm.ve.vl.lzvm.sml" => "__builtin_ve_vl_lzvm_sml", - "llvm.ve.vl.negm.MM" => "__builtin_ve_vl_negm_MM", - "llvm.ve.vl.negm.mm" => "__builtin_ve_vl_negm_mm", - "llvm.ve.vl.nndm.MMM" => "__builtin_ve_vl_nndm_MMM", - "llvm.ve.vl.nndm.mmm" => "__builtin_ve_vl_nndm_mmm", - "llvm.ve.vl.orm.MMM" => "__builtin_ve_vl_orm_MMM", - "llvm.ve.vl.orm.mmm" => "__builtin_ve_vl_orm_mmm", - "llvm.ve.vl.pack.f32a" => "__builtin_ve_vl_pack_f32a", - "llvm.ve.vl.pack.f32p" => "__builtin_ve_vl_pack_f32p", - "llvm.ve.vl.pcvm.sml" => "__builtin_ve_vl_pcvm_sml", - "llvm.ve.vl.pfchv.ssl" => "__builtin_ve_vl_pfchv_ssl", - "llvm.ve.vl.pfchvnc.ssl" => "__builtin_ve_vl_pfchvnc_ssl", - "llvm.ve.vl.pvadds.vsvMvl" => "__builtin_ve_vl_pvadds_vsvMvl", - "llvm.ve.vl.pvadds.vsvl" => "__builtin_ve_vl_pvadds_vsvl", - "llvm.ve.vl.pvadds.vsvvl" => "__builtin_ve_vl_pvadds_vsvvl", - "llvm.ve.vl.pvadds.vvvMvl" => "__builtin_ve_vl_pvadds_vvvMvl", - "llvm.ve.vl.pvadds.vvvl" => "__builtin_ve_vl_pvadds_vvvl", - "llvm.ve.vl.pvadds.vvvvl" => "__builtin_ve_vl_pvadds_vvvvl", - "llvm.ve.vl.pvaddu.vsvMvl" => "__builtin_ve_vl_pvaddu_vsvMvl", - "llvm.ve.vl.pvaddu.vsvl" => "__builtin_ve_vl_pvaddu_vsvl", - "llvm.ve.vl.pvaddu.vsvvl" => "__builtin_ve_vl_pvaddu_vsvvl", - "llvm.ve.vl.pvaddu.vvvMvl" => "__builtin_ve_vl_pvaddu_vvvMvl", - "llvm.ve.vl.pvaddu.vvvl" => "__builtin_ve_vl_pvaddu_vvvl", - "llvm.ve.vl.pvaddu.vvvvl" => "__builtin_ve_vl_pvaddu_vvvvl", - "llvm.ve.vl.pvand.vsvMvl" => "__builtin_ve_vl_pvand_vsvMvl", - "llvm.ve.vl.pvand.vsvl" => "__builtin_ve_vl_pvand_vsvl", - "llvm.ve.vl.pvand.vsvvl" => "__builtin_ve_vl_pvand_vsvvl", - "llvm.ve.vl.pvand.vvvMvl" => "__builtin_ve_vl_pvand_vvvMvl", - "llvm.ve.vl.pvand.vvvl" => "__builtin_ve_vl_pvand_vvvl", - "llvm.ve.vl.pvand.vvvvl" => "__builtin_ve_vl_pvand_vvvvl", - "llvm.ve.vl.pvbrd.vsMvl" => "__builtin_ve_vl_pvbrd_vsMvl", - "llvm.ve.vl.pvbrd.vsl" => "__builtin_ve_vl_pvbrd_vsl", - "llvm.ve.vl.pvbrd.vsvl" => "__builtin_ve_vl_pvbrd_vsvl", - "llvm.ve.vl.pvbrv.vvMvl" => "__builtin_ve_vl_pvbrv_vvMvl", - "llvm.ve.vl.pvbrv.vvl" => "__builtin_ve_vl_pvbrv_vvl", - "llvm.ve.vl.pvbrv.vvvl" => "__builtin_ve_vl_pvbrv_vvvl", - "llvm.ve.vl.pvbrvlo.vvl" => "__builtin_ve_vl_pvbrvlo_vvl", - "llvm.ve.vl.pvbrvlo.vvmvl" => "__builtin_ve_vl_pvbrvlo_vvmvl", - "llvm.ve.vl.pvbrvlo.vvvl" => "__builtin_ve_vl_pvbrvlo_vvvl", - "llvm.ve.vl.pvbrvup.vvl" => "__builtin_ve_vl_pvbrvup_vvl", - "llvm.ve.vl.pvbrvup.vvmvl" => "__builtin_ve_vl_pvbrvup_vvmvl", - "llvm.ve.vl.pvbrvup.vvvl" => "__builtin_ve_vl_pvbrvup_vvvl", - "llvm.ve.vl.pvcmps.vsvMvl" => "__builtin_ve_vl_pvcmps_vsvMvl", - "llvm.ve.vl.pvcmps.vsvl" => "__builtin_ve_vl_pvcmps_vsvl", - "llvm.ve.vl.pvcmps.vsvvl" => "__builtin_ve_vl_pvcmps_vsvvl", - "llvm.ve.vl.pvcmps.vvvMvl" => "__builtin_ve_vl_pvcmps_vvvMvl", - "llvm.ve.vl.pvcmps.vvvl" => "__builtin_ve_vl_pvcmps_vvvl", - "llvm.ve.vl.pvcmps.vvvvl" => "__builtin_ve_vl_pvcmps_vvvvl", - "llvm.ve.vl.pvcmpu.vsvMvl" => "__builtin_ve_vl_pvcmpu_vsvMvl", - "llvm.ve.vl.pvcmpu.vsvl" => "__builtin_ve_vl_pvcmpu_vsvl", - "llvm.ve.vl.pvcmpu.vsvvl" => "__builtin_ve_vl_pvcmpu_vsvvl", - "llvm.ve.vl.pvcmpu.vvvMvl" => "__builtin_ve_vl_pvcmpu_vvvMvl", - "llvm.ve.vl.pvcmpu.vvvl" => "__builtin_ve_vl_pvcmpu_vvvl", - "llvm.ve.vl.pvcmpu.vvvvl" => "__builtin_ve_vl_pvcmpu_vvvvl", - "llvm.ve.vl.pvcvtsw.vvl" => "__builtin_ve_vl_pvcvtsw_vvl", - "llvm.ve.vl.pvcvtsw.vvvl" => "__builtin_ve_vl_pvcvtsw_vvvl", - "llvm.ve.vl.pvcvtws.vvMvl" => "__builtin_ve_vl_pvcvtws_vvMvl", - "llvm.ve.vl.pvcvtws.vvl" => "__builtin_ve_vl_pvcvtws_vvl", - "llvm.ve.vl.pvcvtws.vvvl" => "__builtin_ve_vl_pvcvtws_vvvl", - "llvm.ve.vl.pvcvtwsrz.vvMvl" => "__builtin_ve_vl_pvcvtwsrz_vvMvl", - "llvm.ve.vl.pvcvtwsrz.vvl" => "__builtin_ve_vl_pvcvtwsrz_vvl", - "llvm.ve.vl.pvcvtwsrz.vvvl" => "__builtin_ve_vl_pvcvtwsrz_vvvl", - "llvm.ve.vl.pveqv.vsvMvl" => "__builtin_ve_vl_pveqv_vsvMvl", - "llvm.ve.vl.pveqv.vsvl" => "__builtin_ve_vl_pveqv_vsvl", - "llvm.ve.vl.pveqv.vsvvl" => "__builtin_ve_vl_pveqv_vsvvl", - "llvm.ve.vl.pveqv.vvvMvl" => "__builtin_ve_vl_pveqv_vvvMvl", - "llvm.ve.vl.pveqv.vvvl" => "__builtin_ve_vl_pveqv_vvvl", - "llvm.ve.vl.pveqv.vvvvl" => "__builtin_ve_vl_pveqv_vvvvl", - "llvm.ve.vl.pvfadd.vsvMvl" => "__builtin_ve_vl_pvfadd_vsvMvl", - "llvm.ve.vl.pvfadd.vsvl" => "__builtin_ve_vl_pvfadd_vsvl", - "llvm.ve.vl.pvfadd.vsvvl" => "__builtin_ve_vl_pvfadd_vsvvl", - "llvm.ve.vl.pvfadd.vvvMvl" => "__builtin_ve_vl_pvfadd_vvvMvl", - "llvm.ve.vl.pvfadd.vvvl" => "__builtin_ve_vl_pvfadd_vvvl", - "llvm.ve.vl.pvfadd.vvvvl" => "__builtin_ve_vl_pvfadd_vvvvl", - "llvm.ve.vl.pvfcmp.vsvMvl" => "__builtin_ve_vl_pvfcmp_vsvMvl", - "llvm.ve.vl.pvfcmp.vsvl" => "__builtin_ve_vl_pvfcmp_vsvl", - "llvm.ve.vl.pvfcmp.vsvvl" => "__builtin_ve_vl_pvfcmp_vsvvl", - "llvm.ve.vl.pvfcmp.vvvMvl" => "__builtin_ve_vl_pvfcmp_vvvMvl", - "llvm.ve.vl.pvfcmp.vvvl" => "__builtin_ve_vl_pvfcmp_vvvl", - "llvm.ve.vl.pvfcmp.vvvvl" => "__builtin_ve_vl_pvfcmp_vvvvl", - "llvm.ve.vl.pvfmad.vsvvMvl" => "__builtin_ve_vl_pvfmad_vsvvMvl", - "llvm.ve.vl.pvfmad.vsvvl" => "__builtin_ve_vl_pvfmad_vsvvl", - "llvm.ve.vl.pvfmad.vsvvvl" => "__builtin_ve_vl_pvfmad_vsvvvl", - "llvm.ve.vl.pvfmad.vvsvMvl" => "__builtin_ve_vl_pvfmad_vvsvMvl", - "llvm.ve.vl.pvfmad.vvsvl" => "__builtin_ve_vl_pvfmad_vvsvl", - "llvm.ve.vl.pvfmad.vvsvvl" => "__builtin_ve_vl_pvfmad_vvsvvl", - "llvm.ve.vl.pvfmad.vvvvMvl" => "__builtin_ve_vl_pvfmad_vvvvMvl", - "llvm.ve.vl.pvfmad.vvvvl" => "__builtin_ve_vl_pvfmad_vvvvl", - "llvm.ve.vl.pvfmad.vvvvvl" => "__builtin_ve_vl_pvfmad_vvvvvl", - "llvm.ve.vl.pvfmax.vsvMvl" => "__builtin_ve_vl_pvfmax_vsvMvl", - "llvm.ve.vl.pvfmax.vsvl" => "__builtin_ve_vl_pvfmax_vsvl", - "llvm.ve.vl.pvfmax.vsvvl" => "__builtin_ve_vl_pvfmax_vsvvl", - "llvm.ve.vl.pvfmax.vvvMvl" => "__builtin_ve_vl_pvfmax_vvvMvl", - "llvm.ve.vl.pvfmax.vvvl" => "__builtin_ve_vl_pvfmax_vvvl", - "llvm.ve.vl.pvfmax.vvvvl" => "__builtin_ve_vl_pvfmax_vvvvl", - "llvm.ve.vl.pvfmin.vsvMvl" => "__builtin_ve_vl_pvfmin_vsvMvl", - "llvm.ve.vl.pvfmin.vsvl" => "__builtin_ve_vl_pvfmin_vsvl", - "llvm.ve.vl.pvfmin.vsvvl" => "__builtin_ve_vl_pvfmin_vsvvl", - "llvm.ve.vl.pvfmin.vvvMvl" => "__builtin_ve_vl_pvfmin_vvvMvl", - "llvm.ve.vl.pvfmin.vvvl" => "__builtin_ve_vl_pvfmin_vvvl", - "llvm.ve.vl.pvfmin.vvvvl" => "__builtin_ve_vl_pvfmin_vvvvl", - "llvm.ve.vl.pvfmkaf.Ml" => "__builtin_ve_vl_pvfmkaf_Ml", - "llvm.ve.vl.pvfmkat.Ml" => "__builtin_ve_vl_pvfmkat_Ml", - "llvm.ve.vl.pvfmkseq.MvMl" => "__builtin_ve_vl_pvfmkseq_MvMl", - "llvm.ve.vl.pvfmkseq.Mvl" => "__builtin_ve_vl_pvfmkseq_Mvl", - "llvm.ve.vl.pvfmkseqnan.MvMl" => "__builtin_ve_vl_pvfmkseqnan_MvMl", - "llvm.ve.vl.pvfmkseqnan.Mvl" => "__builtin_ve_vl_pvfmkseqnan_Mvl", - "llvm.ve.vl.pvfmksge.MvMl" => "__builtin_ve_vl_pvfmksge_MvMl", - "llvm.ve.vl.pvfmksge.Mvl" => "__builtin_ve_vl_pvfmksge_Mvl", - "llvm.ve.vl.pvfmksgenan.MvMl" => "__builtin_ve_vl_pvfmksgenan_MvMl", - "llvm.ve.vl.pvfmksgenan.Mvl" => "__builtin_ve_vl_pvfmksgenan_Mvl", - "llvm.ve.vl.pvfmksgt.MvMl" => "__builtin_ve_vl_pvfmksgt_MvMl", - "llvm.ve.vl.pvfmksgt.Mvl" => "__builtin_ve_vl_pvfmksgt_Mvl", - "llvm.ve.vl.pvfmksgtnan.MvMl" => "__builtin_ve_vl_pvfmksgtnan_MvMl", - "llvm.ve.vl.pvfmksgtnan.Mvl" => "__builtin_ve_vl_pvfmksgtnan_Mvl", - "llvm.ve.vl.pvfmksle.MvMl" => "__builtin_ve_vl_pvfmksle_MvMl", - "llvm.ve.vl.pvfmksle.Mvl" => "__builtin_ve_vl_pvfmksle_Mvl", - "llvm.ve.vl.pvfmkslenan.MvMl" => "__builtin_ve_vl_pvfmkslenan_MvMl", - "llvm.ve.vl.pvfmkslenan.Mvl" => "__builtin_ve_vl_pvfmkslenan_Mvl", - "llvm.ve.vl.pvfmksloeq.mvl" => "__builtin_ve_vl_pvfmksloeq_mvl", - "llvm.ve.vl.pvfmksloeq.mvml" => "__builtin_ve_vl_pvfmksloeq_mvml", - "llvm.ve.vl.pvfmksloeqnan.mvl" => "__builtin_ve_vl_pvfmksloeqnan_mvl", - "llvm.ve.vl.pvfmksloeqnan.mvml" => "__builtin_ve_vl_pvfmksloeqnan_mvml", - "llvm.ve.vl.pvfmksloge.mvl" => "__builtin_ve_vl_pvfmksloge_mvl", - "llvm.ve.vl.pvfmksloge.mvml" => "__builtin_ve_vl_pvfmksloge_mvml", - "llvm.ve.vl.pvfmkslogenan.mvl" => "__builtin_ve_vl_pvfmkslogenan_mvl", - "llvm.ve.vl.pvfmkslogenan.mvml" => "__builtin_ve_vl_pvfmkslogenan_mvml", - "llvm.ve.vl.pvfmkslogt.mvl" => "__builtin_ve_vl_pvfmkslogt_mvl", - "llvm.ve.vl.pvfmkslogt.mvml" => "__builtin_ve_vl_pvfmkslogt_mvml", - "llvm.ve.vl.pvfmkslogtnan.mvl" => "__builtin_ve_vl_pvfmkslogtnan_mvl", - "llvm.ve.vl.pvfmkslogtnan.mvml" => "__builtin_ve_vl_pvfmkslogtnan_mvml", - "llvm.ve.vl.pvfmkslole.mvl" => "__builtin_ve_vl_pvfmkslole_mvl", - "llvm.ve.vl.pvfmkslole.mvml" => "__builtin_ve_vl_pvfmkslole_mvml", - "llvm.ve.vl.pvfmkslolenan.mvl" => "__builtin_ve_vl_pvfmkslolenan_mvl", - "llvm.ve.vl.pvfmkslolenan.mvml" => "__builtin_ve_vl_pvfmkslolenan_mvml", - "llvm.ve.vl.pvfmkslolt.mvl" => "__builtin_ve_vl_pvfmkslolt_mvl", - "llvm.ve.vl.pvfmkslolt.mvml" => "__builtin_ve_vl_pvfmkslolt_mvml", - "llvm.ve.vl.pvfmksloltnan.mvl" => "__builtin_ve_vl_pvfmksloltnan_mvl", - "llvm.ve.vl.pvfmksloltnan.mvml" => "__builtin_ve_vl_pvfmksloltnan_mvml", - "llvm.ve.vl.pvfmkslonan.mvl" => "__builtin_ve_vl_pvfmkslonan_mvl", - "llvm.ve.vl.pvfmkslonan.mvml" => "__builtin_ve_vl_pvfmkslonan_mvml", - "llvm.ve.vl.pvfmkslone.mvl" => "__builtin_ve_vl_pvfmkslone_mvl", - "llvm.ve.vl.pvfmkslone.mvml" => "__builtin_ve_vl_pvfmkslone_mvml", - "llvm.ve.vl.pvfmkslonenan.mvl" => "__builtin_ve_vl_pvfmkslonenan_mvl", - "llvm.ve.vl.pvfmkslonenan.mvml" => "__builtin_ve_vl_pvfmkslonenan_mvml", - "llvm.ve.vl.pvfmkslonum.mvl" => "__builtin_ve_vl_pvfmkslonum_mvl", - "llvm.ve.vl.pvfmkslonum.mvml" => "__builtin_ve_vl_pvfmkslonum_mvml", - "llvm.ve.vl.pvfmkslt.MvMl" => "__builtin_ve_vl_pvfmkslt_MvMl", - "llvm.ve.vl.pvfmkslt.Mvl" => "__builtin_ve_vl_pvfmkslt_Mvl", - "llvm.ve.vl.pvfmksltnan.MvMl" => "__builtin_ve_vl_pvfmksltnan_MvMl", - "llvm.ve.vl.pvfmksltnan.Mvl" => "__builtin_ve_vl_pvfmksltnan_Mvl", - "llvm.ve.vl.pvfmksnan.MvMl" => "__builtin_ve_vl_pvfmksnan_MvMl", - "llvm.ve.vl.pvfmksnan.Mvl" => "__builtin_ve_vl_pvfmksnan_Mvl", - "llvm.ve.vl.pvfmksne.MvMl" => "__builtin_ve_vl_pvfmksne_MvMl", - "llvm.ve.vl.pvfmksne.Mvl" => "__builtin_ve_vl_pvfmksne_Mvl", - "llvm.ve.vl.pvfmksnenan.MvMl" => "__builtin_ve_vl_pvfmksnenan_MvMl", - "llvm.ve.vl.pvfmksnenan.Mvl" => "__builtin_ve_vl_pvfmksnenan_Mvl", - "llvm.ve.vl.pvfmksnum.MvMl" => "__builtin_ve_vl_pvfmksnum_MvMl", - "llvm.ve.vl.pvfmksnum.Mvl" => "__builtin_ve_vl_pvfmksnum_Mvl", - "llvm.ve.vl.pvfmksupeq.mvl" => "__builtin_ve_vl_pvfmksupeq_mvl", - "llvm.ve.vl.pvfmksupeq.mvml" => "__builtin_ve_vl_pvfmksupeq_mvml", - "llvm.ve.vl.pvfmksupeqnan.mvl" => "__builtin_ve_vl_pvfmksupeqnan_mvl", - "llvm.ve.vl.pvfmksupeqnan.mvml" => "__builtin_ve_vl_pvfmksupeqnan_mvml", - "llvm.ve.vl.pvfmksupge.mvl" => "__builtin_ve_vl_pvfmksupge_mvl", - "llvm.ve.vl.pvfmksupge.mvml" => "__builtin_ve_vl_pvfmksupge_mvml", - "llvm.ve.vl.pvfmksupgenan.mvl" => "__builtin_ve_vl_pvfmksupgenan_mvl", - "llvm.ve.vl.pvfmksupgenan.mvml" => "__builtin_ve_vl_pvfmksupgenan_mvml", - "llvm.ve.vl.pvfmksupgt.mvl" => "__builtin_ve_vl_pvfmksupgt_mvl", - "llvm.ve.vl.pvfmksupgt.mvml" => "__builtin_ve_vl_pvfmksupgt_mvml", - "llvm.ve.vl.pvfmksupgtnan.mvl" => "__builtin_ve_vl_pvfmksupgtnan_mvl", - "llvm.ve.vl.pvfmksupgtnan.mvml" => "__builtin_ve_vl_pvfmksupgtnan_mvml", - "llvm.ve.vl.pvfmksuple.mvl" => "__builtin_ve_vl_pvfmksuple_mvl", - "llvm.ve.vl.pvfmksuple.mvml" => "__builtin_ve_vl_pvfmksuple_mvml", - "llvm.ve.vl.pvfmksuplenan.mvl" => "__builtin_ve_vl_pvfmksuplenan_mvl", - "llvm.ve.vl.pvfmksuplenan.mvml" => "__builtin_ve_vl_pvfmksuplenan_mvml", - "llvm.ve.vl.pvfmksuplt.mvl" => "__builtin_ve_vl_pvfmksuplt_mvl", - "llvm.ve.vl.pvfmksuplt.mvml" => "__builtin_ve_vl_pvfmksuplt_mvml", - "llvm.ve.vl.pvfmksupltnan.mvl" => "__builtin_ve_vl_pvfmksupltnan_mvl", - "llvm.ve.vl.pvfmksupltnan.mvml" => "__builtin_ve_vl_pvfmksupltnan_mvml", - "llvm.ve.vl.pvfmksupnan.mvl" => "__builtin_ve_vl_pvfmksupnan_mvl", - "llvm.ve.vl.pvfmksupnan.mvml" => "__builtin_ve_vl_pvfmksupnan_mvml", - "llvm.ve.vl.pvfmksupne.mvl" => "__builtin_ve_vl_pvfmksupne_mvl", - "llvm.ve.vl.pvfmksupne.mvml" => "__builtin_ve_vl_pvfmksupne_mvml", - "llvm.ve.vl.pvfmksupnenan.mvl" => "__builtin_ve_vl_pvfmksupnenan_mvl", - "llvm.ve.vl.pvfmksupnenan.mvml" => "__builtin_ve_vl_pvfmksupnenan_mvml", - "llvm.ve.vl.pvfmksupnum.mvl" => "__builtin_ve_vl_pvfmksupnum_mvl", - "llvm.ve.vl.pvfmksupnum.mvml" => "__builtin_ve_vl_pvfmksupnum_mvml", - "llvm.ve.vl.pvfmkweq.MvMl" => "__builtin_ve_vl_pvfmkweq_MvMl", - "llvm.ve.vl.pvfmkweq.Mvl" => "__builtin_ve_vl_pvfmkweq_Mvl", - "llvm.ve.vl.pvfmkweqnan.MvMl" => "__builtin_ve_vl_pvfmkweqnan_MvMl", - "llvm.ve.vl.pvfmkweqnan.Mvl" => "__builtin_ve_vl_pvfmkweqnan_Mvl", - "llvm.ve.vl.pvfmkwge.MvMl" => "__builtin_ve_vl_pvfmkwge_MvMl", - "llvm.ve.vl.pvfmkwge.Mvl" => "__builtin_ve_vl_pvfmkwge_Mvl", - "llvm.ve.vl.pvfmkwgenan.MvMl" => "__builtin_ve_vl_pvfmkwgenan_MvMl", - "llvm.ve.vl.pvfmkwgenan.Mvl" => "__builtin_ve_vl_pvfmkwgenan_Mvl", - "llvm.ve.vl.pvfmkwgt.MvMl" => "__builtin_ve_vl_pvfmkwgt_MvMl", - "llvm.ve.vl.pvfmkwgt.Mvl" => "__builtin_ve_vl_pvfmkwgt_Mvl", - "llvm.ve.vl.pvfmkwgtnan.MvMl" => "__builtin_ve_vl_pvfmkwgtnan_MvMl", - "llvm.ve.vl.pvfmkwgtnan.Mvl" => "__builtin_ve_vl_pvfmkwgtnan_Mvl", - "llvm.ve.vl.pvfmkwle.MvMl" => "__builtin_ve_vl_pvfmkwle_MvMl", - "llvm.ve.vl.pvfmkwle.Mvl" => "__builtin_ve_vl_pvfmkwle_Mvl", - "llvm.ve.vl.pvfmkwlenan.MvMl" => "__builtin_ve_vl_pvfmkwlenan_MvMl", - "llvm.ve.vl.pvfmkwlenan.Mvl" => "__builtin_ve_vl_pvfmkwlenan_Mvl", - "llvm.ve.vl.pvfmkwloeq.mvl" => "__builtin_ve_vl_pvfmkwloeq_mvl", - "llvm.ve.vl.pvfmkwloeq.mvml" => "__builtin_ve_vl_pvfmkwloeq_mvml", - "llvm.ve.vl.pvfmkwloeqnan.mvl" => "__builtin_ve_vl_pvfmkwloeqnan_mvl", - "llvm.ve.vl.pvfmkwloeqnan.mvml" => "__builtin_ve_vl_pvfmkwloeqnan_mvml", - "llvm.ve.vl.pvfmkwloge.mvl" => "__builtin_ve_vl_pvfmkwloge_mvl", - "llvm.ve.vl.pvfmkwloge.mvml" => "__builtin_ve_vl_pvfmkwloge_mvml", - "llvm.ve.vl.pvfmkwlogenan.mvl" => "__builtin_ve_vl_pvfmkwlogenan_mvl", - "llvm.ve.vl.pvfmkwlogenan.mvml" => "__builtin_ve_vl_pvfmkwlogenan_mvml", - "llvm.ve.vl.pvfmkwlogt.mvl" => "__builtin_ve_vl_pvfmkwlogt_mvl", - "llvm.ve.vl.pvfmkwlogt.mvml" => "__builtin_ve_vl_pvfmkwlogt_mvml", - "llvm.ve.vl.pvfmkwlogtnan.mvl" => "__builtin_ve_vl_pvfmkwlogtnan_mvl", - "llvm.ve.vl.pvfmkwlogtnan.mvml" => "__builtin_ve_vl_pvfmkwlogtnan_mvml", - "llvm.ve.vl.pvfmkwlole.mvl" => "__builtin_ve_vl_pvfmkwlole_mvl", - "llvm.ve.vl.pvfmkwlole.mvml" => "__builtin_ve_vl_pvfmkwlole_mvml", - "llvm.ve.vl.pvfmkwlolenan.mvl" => "__builtin_ve_vl_pvfmkwlolenan_mvl", - "llvm.ve.vl.pvfmkwlolenan.mvml" => "__builtin_ve_vl_pvfmkwlolenan_mvml", - "llvm.ve.vl.pvfmkwlolt.mvl" => "__builtin_ve_vl_pvfmkwlolt_mvl", - "llvm.ve.vl.pvfmkwlolt.mvml" => "__builtin_ve_vl_pvfmkwlolt_mvml", - "llvm.ve.vl.pvfmkwloltnan.mvl" => "__builtin_ve_vl_pvfmkwloltnan_mvl", - "llvm.ve.vl.pvfmkwloltnan.mvml" => "__builtin_ve_vl_pvfmkwloltnan_mvml", - "llvm.ve.vl.pvfmkwlonan.mvl" => "__builtin_ve_vl_pvfmkwlonan_mvl", - "llvm.ve.vl.pvfmkwlonan.mvml" => "__builtin_ve_vl_pvfmkwlonan_mvml", - "llvm.ve.vl.pvfmkwlone.mvl" => "__builtin_ve_vl_pvfmkwlone_mvl", - "llvm.ve.vl.pvfmkwlone.mvml" => "__builtin_ve_vl_pvfmkwlone_mvml", - "llvm.ve.vl.pvfmkwlonenan.mvl" => "__builtin_ve_vl_pvfmkwlonenan_mvl", - "llvm.ve.vl.pvfmkwlonenan.mvml" => "__builtin_ve_vl_pvfmkwlonenan_mvml", - "llvm.ve.vl.pvfmkwlonum.mvl" => "__builtin_ve_vl_pvfmkwlonum_mvl", - "llvm.ve.vl.pvfmkwlonum.mvml" => "__builtin_ve_vl_pvfmkwlonum_mvml", - "llvm.ve.vl.pvfmkwlt.MvMl" => "__builtin_ve_vl_pvfmkwlt_MvMl", - "llvm.ve.vl.pvfmkwlt.Mvl" => "__builtin_ve_vl_pvfmkwlt_Mvl", - "llvm.ve.vl.pvfmkwltnan.MvMl" => "__builtin_ve_vl_pvfmkwltnan_MvMl", - "llvm.ve.vl.pvfmkwltnan.Mvl" => "__builtin_ve_vl_pvfmkwltnan_Mvl", - "llvm.ve.vl.pvfmkwnan.MvMl" => "__builtin_ve_vl_pvfmkwnan_MvMl", - "llvm.ve.vl.pvfmkwnan.Mvl" => "__builtin_ve_vl_pvfmkwnan_Mvl", - "llvm.ve.vl.pvfmkwne.MvMl" => "__builtin_ve_vl_pvfmkwne_MvMl", - "llvm.ve.vl.pvfmkwne.Mvl" => "__builtin_ve_vl_pvfmkwne_Mvl", - "llvm.ve.vl.pvfmkwnenan.MvMl" => "__builtin_ve_vl_pvfmkwnenan_MvMl", - "llvm.ve.vl.pvfmkwnenan.Mvl" => "__builtin_ve_vl_pvfmkwnenan_Mvl", - "llvm.ve.vl.pvfmkwnum.MvMl" => "__builtin_ve_vl_pvfmkwnum_MvMl", - "llvm.ve.vl.pvfmkwnum.Mvl" => "__builtin_ve_vl_pvfmkwnum_Mvl", - "llvm.ve.vl.pvfmkwupeq.mvl" => "__builtin_ve_vl_pvfmkwupeq_mvl", - "llvm.ve.vl.pvfmkwupeq.mvml" => "__builtin_ve_vl_pvfmkwupeq_mvml", - "llvm.ve.vl.pvfmkwupeqnan.mvl" => "__builtin_ve_vl_pvfmkwupeqnan_mvl", - "llvm.ve.vl.pvfmkwupeqnan.mvml" => "__builtin_ve_vl_pvfmkwupeqnan_mvml", - "llvm.ve.vl.pvfmkwupge.mvl" => "__builtin_ve_vl_pvfmkwupge_mvl", - "llvm.ve.vl.pvfmkwupge.mvml" => "__builtin_ve_vl_pvfmkwupge_mvml", - "llvm.ve.vl.pvfmkwupgenan.mvl" => "__builtin_ve_vl_pvfmkwupgenan_mvl", - "llvm.ve.vl.pvfmkwupgenan.mvml" => "__builtin_ve_vl_pvfmkwupgenan_mvml", - "llvm.ve.vl.pvfmkwupgt.mvl" => "__builtin_ve_vl_pvfmkwupgt_mvl", - "llvm.ve.vl.pvfmkwupgt.mvml" => "__builtin_ve_vl_pvfmkwupgt_mvml", - "llvm.ve.vl.pvfmkwupgtnan.mvl" => "__builtin_ve_vl_pvfmkwupgtnan_mvl", - "llvm.ve.vl.pvfmkwupgtnan.mvml" => "__builtin_ve_vl_pvfmkwupgtnan_mvml", - "llvm.ve.vl.pvfmkwuple.mvl" => "__builtin_ve_vl_pvfmkwuple_mvl", - "llvm.ve.vl.pvfmkwuple.mvml" => "__builtin_ve_vl_pvfmkwuple_mvml", - "llvm.ve.vl.pvfmkwuplenan.mvl" => "__builtin_ve_vl_pvfmkwuplenan_mvl", - "llvm.ve.vl.pvfmkwuplenan.mvml" => "__builtin_ve_vl_pvfmkwuplenan_mvml", - "llvm.ve.vl.pvfmkwuplt.mvl" => "__builtin_ve_vl_pvfmkwuplt_mvl", - "llvm.ve.vl.pvfmkwuplt.mvml" => "__builtin_ve_vl_pvfmkwuplt_mvml", - "llvm.ve.vl.pvfmkwupltnan.mvl" => "__builtin_ve_vl_pvfmkwupltnan_mvl", - "llvm.ve.vl.pvfmkwupltnan.mvml" => "__builtin_ve_vl_pvfmkwupltnan_mvml", - "llvm.ve.vl.pvfmkwupnan.mvl" => "__builtin_ve_vl_pvfmkwupnan_mvl", - "llvm.ve.vl.pvfmkwupnan.mvml" => "__builtin_ve_vl_pvfmkwupnan_mvml", - "llvm.ve.vl.pvfmkwupne.mvl" => "__builtin_ve_vl_pvfmkwupne_mvl", - "llvm.ve.vl.pvfmkwupne.mvml" => "__builtin_ve_vl_pvfmkwupne_mvml", - "llvm.ve.vl.pvfmkwupnenan.mvl" => "__builtin_ve_vl_pvfmkwupnenan_mvl", - "llvm.ve.vl.pvfmkwupnenan.mvml" => "__builtin_ve_vl_pvfmkwupnenan_mvml", - "llvm.ve.vl.pvfmkwupnum.mvl" => "__builtin_ve_vl_pvfmkwupnum_mvl", - "llvm.ve.vl.pvfmkwupnum.mvml" => "__builtin_ve_vl_pvfmkwupnum_mvml", - "llvm.ve.vl.pvfmsb.vsvvMvl" => "__builtin_ve_vl_pvfmsb_vsvvMvl", - "llvm.ve.vl.pvfmsb.vsvvl" => "__builtin_ve_vl_pvfmsb_vsvvl", - "llvm.ve.vl.pvfmsb.vsvvvl" => "__builtin_ve_vl_pvfmsb_vsvvvl", - "llvm.ve.vl.pvfmsb.vvsvMvl" => "__builtin_ve_vl_pvfmsb_vvsvMvl", - "llvm.ve.vl.pvfmsb.vvsvl" => "__builtin_ve_vl_pvfmsb_vvsvl", - "llvm.ve.vl.pvfmsb.vvsvvl" => "__builtin_ve_vl_pvfmsb_vvsvvl", - "llvm.ve.vl.pvfmsb.vvvvMvl" => "__builtin_ve_vl_pvfmsb_vvvvMvl", - "llvm.ve.vl.pvfmsb.vvvvl" => "__builtin_ve_vl_pvfmsb_vvvvl", - "llvm.ve.vl.pvfmsb.vvvvvl" => "__builtin_ve_vl_pvfmsb_vvvvvl", - "llvm.ve.vl.pvfmul.vsvMvl" => "__builtin_ve_vl_pvfmul_vsvMvl", - "llvm.ve.vl.pvfmul.vsvl" => "__builtin_ve_vl_pvfmul_vsvl", - "llvm.ve.vl.pvfmul.vsvvl" => "__builtin_ve_vl_pvfmul_vsvvl", - "llvm.ve.vl.pvfmul.vvvMvl" => "__builtin_ve_vl_pvfmul_vvvMvl", - "llvm.ve.vl.pvfmul.vvvl" => "__builtin_ve_vl_pvfmul_vvvl", - "llvm.ve.vl.pvfmul.vvvvl" => "__builtin_ve_vl_pvfmul_vvvvl", - "llvm.ve.vl.pvfnmad.vsvvMvl" => "__builtin_ve_vl_pvfnmad_vsvvMvl", - "llvm.ve.vl.pvfnmad.vsvvl" => "__builtin_ve_vl_pvfnmad_vsvvl", - "llvm.ve.vl.pvfnmad.vsvvvl" => "__builtin_ve_vl_pvfnmad_vsvvvl", - "llvm.ve.vl.pvfnmad.vvsvMvl" => "__builtin_ve_vl_pvfnmad_vvsvMvl", - "llvm.ve.vl.pvfnmad.vvsvl" => "__builtin_ve_vl_pvfnmad_vvsvl", - "llvm.ve.vl.pvfnmad.vvsvvl" => "__builtin_ve_vl_pvfnmad_vvsvvl", - "llvm.ve.vl.pvfnmad.vvvvMvl" => "__builtin_ve_vl_pvfnmad_vvvvMvl", - "llvm.ve.vl.pvfnmad.vvvvl" => "__builtin_ve_vl_pvfnmad_vvvvl", - "llvm.ve.vl.pvfnmad.vvvvvl" => "__builtin_ve_vl_pvfnmad_vvvvvl", - "llvm.ve.vl.pvfnmsb.vsvvMvl" => "__builtin_ve_vl_pvfnmsb_vsvvMvl", - "llvm.ve.vl.pvfnmsb.vsvvl" => "__builtin_ve_vl_pvfnmsb_vsvvl", - "llvm.ve.vl.pvfnmsb.vsvvvl" => "__builtin_ve_vl_pvfnmsb_vsvvvl", - "llvm.ve.vl.pvfnmsb.vvsvMvl" => "__builtin_ve_vl_pvfnmsb_vvsvMvl", - "llvm.ve.vl.pvfnmsb.vvsvl" => "__builtin_ve_vl_pvfnmsb_vvsvl", - "llvm.ve.vl.pvfnmsb.vvsvvl" => "__builtin_ve_vl_pvfnmsb_vvsvvl", - "llvm.ve.vl.pvfnmsb.vvvvMvl" => "__builtin_ve_vl_pvfnmsb_vvvvMvl", - "llvm.ve.vl.pvfnmsb.vvvvl" => "__builtin_ve_vl_pvfnmsb_vvvvl", - "llvm.ve.vl.pvfnmsb.vvvvvl" => "__builtin_ve_vl_pvfnmsb_vvvvvl", - "llvm.ve.vl.pvfsub.vsvMvl" => "__builtin_ve_vl_pvfsub_vsvMvl", - "llvm.ve.vl.pvfsub.vsvl" => "__builtin_ve_vl_pvfsub_vsvl", - "llvm.ve.vl.pvfsub.vsvvl" => "__builtin_ve_vl_pvfsub_vsvvl", - "llvm.ve.vl.pvfsub.vvvMvl" => "__builtin_ve_vl_pvfsub_vvvMvl", - "llvm.ve.vl.pvfsub.vvvl" => "__builtin_ve_vl_pvfsub_vvvl", - "llvm.ve.vl.pvfsub.vvvvl" => "__builtin_ve_vl_pvfsub_vvvvl", - "llvm.ve.vl.pvldz.vvMvl" => "__builtin_ve_vl_pvldz_vvMvl", - "llvm.ve.vl.pvldz.vvl" => "__builtin_ve_vl_pvldz_vvl", - "llvm.ve.vl.pvldz.vvvl" => "__builtin_ve_vl_pvldz_vvvl", - "llvm.ve.vl.pvldzlo.vvl" => "__builtin_ve_vl_pvldzlo_vvl", - "llvm.ve.vl.pvldzlo.vvmvl" => "__builtin_ve_vl_pvldzlo_vvmvl", - "llvm.ve.vl.pvldzlo.vvvl" => "__builtin_ve_vl_pvldzlo_vvvl", - "llvm.ve.vl.pvldzup.vvl" => "__builtin_ve_vl_pvldzup_vvl", - "llvm.ve.vl.pvldzup.vvmvl" => "__builtin_ve_vl_pvldzup_vvmvl", - "llvm.ve.vl.pvldzup.vvvl" => "__builtin_ve_vl_pvldzup_vvvl", - "llvm.ve.vl.pvmaxs.vsvMvl" => "__builtin_ve_vl_pvmaxs_vsvMvl", - "llvm.ve.vl.pvmaxs.vsvl" => "__builtin_ve_vl_pvmaxs_vsvl", - "llvm.ve.vl.pvmaxs.vsvvl" => "__builtin_ve_vl_pvmaxs_vsvvl", - "llvm.ve.vl.pvmaxs.vvvMvl" => "__builtin_ve_vl_pvmaxs_vvvMvl", - "llvm.ve.vl.pvmaxs.vvvl" => "__builtin_ve_vl_pvmaxs_vvvl", - "llvm.ve.vl.pvmaxs.vvvvl" => "__builtin_ve_vl_pvmaxs_vvvvl", - "llvm.ve.vl.pvmins.vsvMvl" => "__builtin_ve_vl_pvmins_vsvMvl", - "llvm.ve.vl.pvmins.vsvl" => "__builtin_ve_vl_pvmins_vsvl", - "llvm.ve.vl.pvmins.vsvvl" => "__builtin_ve_vl_pvmins_vsvvl", - "llvm.ve.vl.pvmins.vvvMvl" => "__builtin_ve_vl_pvmins_vvvMvl", - "llvm.ve.vl.pvmins.vvvl" => "__builtin_ve_vl_pvmins_vvvl", - "llvm.ve.vl.pvmins.vvvvl" => "__builtin_ve_vl_pvmins_vvvvl", - "llvm.ve.vl.pvor.vsvMvl" => "__builtin_ve_vl_pvor_vsvMvl", - "llvm.ve.vl.pvor.vsvl" => "__builtin_ve_vl_pvor_vsvl", - "llvm.ve.vl.pvor.vsvvl" => "__builtin_ve_vl_pvor_vsvvl", - "llvm.ve.vl.pvor.vvvMvl" => "__builtin_ve_vl_pvor_vvvMvl", - "llvm.ve.vl.pvor.vvvl" => "__builtin_ve_vl_pvor_vvvl", - "llvm.ve.vl.pvor.vvvvl" => "__builtin_ve_vl_pvor_vvvvl", - "llvm.ve.vl.pvpcnt.vvMvl" => "__builtin_ve_vl_pvpcnt_vvMvl", - "llvm.ve.vl.pvpcnt.vvl" => "__builtin_ve_vl_pvpcnt_vvl", - "llvm.ve.vl.pvpcnt.vvvl" => "__builtin_ve_vl_pvpcnt_vvvl", - "llvm.ve.vl.pvpcntlo.vvl" => "__builtin_ve_vl_pvpcntlo_vvl", - "llvm.ve.vl.pvpcntlo.vvmvl" => "__builtin_ve_vl_pvpcntlo_vvmvl", - "llvm.ve.vl.pvpcntlo.vvvl" => "__builtin_ve_vl_pvpcntlo_vvvl", - "llvm.ve.vl.pvpcntup.vvl" => "__builtin_ve_vl_pvpcntup_vvl", - "llvm.ve.vl.pvpcntup.vvmvl" => "__builtin_ve_vl_pvpcntup_vvmvl", - "llvm.ve.vl.pvpcntup.vvvl" => "__builtin_ve_vl_pvpcntup_vvvl", - "llvm.ve.vl.pvrcp.vvl" => "__builtin_ve_vl_pvrcp_vvl", - "llvm.ve.vl.pvrcp.vvvl" => "__builtin_ve_vl_pvrcp_vvvl", - "llvm.ve.vl.pvrsqrt.vvl" => "__builtin_ve_vl_pvrsqrt_vvl", - "llvm.ve.vl.pvrsqrt.vvvl" => "__builtin_ve_vl_pvrsqrt_vvvl", - "llvm.ve.vl.pvrsqrtnex.vvl" => "__builtin_ve_vl_pvrsqrtnex_vvl", - "llvm.ve.vl.pvrsqrtnex.vvvl" => "__builtin_ve_vl_pvrsqrtnex_vvvl", - "llvm.ve.vl.pvseq.vl" => "__builtin_ve_vl_pvseq_vl", - "llvm.ve.vl.pvseq.vvl" => "__builtin_ve_vl_pvseq_vvl", - "llvm.ve.vl.pvseqlo.vl" => "__builtin_ve_vl_pvseqlo_vl", - "llvm.ve.vl.pvseqlo.vvl" => "__builtin_ve_vl_pvseqlo_vvl", - "llvm.ve.vl.pvsequp.vl" => "__builtin_ve_vl_pvsequp_vl", - "llvm.ve.vl.pvsequp.vvl" => "__builtin_ve_vl_pvsequp_vvl", - "llvm.ve.vl.pvsla.vvsMvl" => "__builtin_ve_vl_pvsla_vvsMvl", - "llvm.ve.vl.pvsla.vvsl" => "__builtin_ve_vl_pvsla_vvsl", - "llvm.ve.vl.pvsla.vvsvl" => "__builtin_ve_vl_pvsla_vvsvl", - "llvm.ve.vl.pvsla.vvvMvl" => "__builtin_ve_vl_pvsla_vvvMvl", - "llvm.ve.vl.pvsla.vvvl" => "__builtin_ve_vl_pvsla_vvvl", - "llvm.ve.vl.pvsla.vvvvl" => "__builtin_ve_vl_pvsla_vvvvl", - "llvm.ve.vl.pvsll.vvsMvl" => "__builtin_ve_vl_pvsll_vvsMvl", - "llvm.ve.vl.pvsll.vvsl" => "__builtin_ve_vl_pvsll_vvsl", - "llvm.ve.vl.pvsll.vvsvl" => "__builtin_ve_vl_pvsll_vvsvl", - "llvm.ve.vl.pvsll.vvvMvl" => "__builtin_ve_vl_pvsll_vvvMvl", - "llvm.ve.vl.pvsll.vvvl" => "__builtin_ve_vl_pvsll_vvvl", - "llvm.ve.vl.pvsll.vvvvl" => "__builtin_ve_vl_pvsll_vvvvl", - "llvm.ve.vl.pvsra.vvsMvl" => "__builtin_ve_vl_pvsra_vvsMvl", - "llvm.ve.vl.pvsra.vvsl" => "__builtin_ve_vl_pvsra_vvsl", - "llvm.ve.vl.pvsra.vvsvl" => "__builtin_ve_vl_pvsra_vvsvl", - "llvm.ve.vl.pvsra.vvvMvl" => "__builtin_ve_vl_pvsra_vvvMvl", - "llvm.ve.vl.pvsra.vvvl" => "__builtin_ve_vl_pvsra_vvvl", - "llvm.ve.vl.pvsra.vvvvl" => "__builtin_ve_vl_pvsra_vvvvl", - "llvm.ve.vl.pvsrl.vvsMvl" => "__builtin_ve_vl_pvsrl_vvsMvl", - "llvm.ve.vl.pvsrl.vvsl" => "__builtin_ve_vl_pvsrl_vvsl", - "llvm.ve.vl.pvsrl.vvsvl" => "__builtin_ve_vl_pvsrl_vvsvl", - "llvm.ve.vl.pvsrl.vvvMvl" => "__builtin_ve_vl_pvsrl_vvvMvl", - "llvm.ve.vl.pvsrl.vvvl" => "__builtin_ve_vl_pvsrl_vvvl", - "llvm.ve.vl.pvsrl.vvvvl" => "__builtin_ve_vl_pvsrl_vvvvl", - "llvm.ve.vl.pvsubs.vsvMvl" => "__builtin_ve_vl_pvsubs_vsvMvl", - "llvm.ve.vl.pvsubs.vsvl" => "__builtin_ve_vl_pvsubs_vsvl", - "llvm.ve.vl.pvsubs.vsvvl" => "__builtin_ve_vl_pvsubs_vsvvl", - "llvm.ve.vl.pvsubs.vvvMvl" => "__builtin_ve_vl_pvsubs_vvvMvl", - "llvm.ve.vl.pvsubs.vvvl" => "__builtin_ve_vl_pvsubs_vvvl", - "llvm.ve.vl.pvsubs.vvvvl" => "__builtin_ve_vl_pvsubs_vvvvl", - "llvm.ve.vl.pvsubu.vsvMvl" => "__builtin_ve_vl_pvsubu_vsvMvl", - "llvm.ve.vl.pvsubu.vsvl" => "__builtin_ve_vl_pvsubu_vsvl", - "llvm.ve.vl.pvsubu.vsvvl" => "__builtin_ve_vl_pvsubu_vsvvl", - "llvm.ve.vl.pvsubu.vvvMvl" => "__builtin_ve_vl_pvsubu_vvvMvl", - "llvm.ve.vl.pvsubu.vvvl" => "__builtin_ve_vl_pvsubu_vvvl", - "llvm.ve.vl.pvsubu.vvvvl" => "__builtin_ve_vl_pvsubu_vvvvl", - "llvm.ve.vl.pvxor.vsvMvl" => "__builtin_ve_vl_pvxor_vsvMvl", - "llvm.ve.vl.pvxor.vsvl" => "__builtin_ve_vl_pvxor_vsvl", - "llvm.ve.vl.pvxor.vsvvl" => "__builtin_ve_vl_pvxor_vsvvl", - "llvm.ve.vl.pvxor.vvvMvl" => "__builtin_ve_vl_pvxor_vvvMvl", - "llvm.ve.vl.pvxor.vvvl" => "__builtin_ve_vl_pvxor_vvvl", - "llvm.ve.vl.pvxor.vvvvl" => "__builtin_ve_vl_pvxor_vvvvl", - "llvm.ve.vl.scr.sss" => "__builtin_ve_vl_scr_sss", - "llvm.ve.vl.svm.sMs" => "__builtin_ve_vl_svm_sMs", - "llvm.ve.vl.svm.sms" => "__builtin_ve_vl_svm_sms", - "llvm.ve.vl.svob" => "__builtin_ve_vl_svob", - "llvm.ve.vl.tovm.sml" => "__builtin_ve_vl_tovm_sml", - "llvm.ve.vl.tscr.ssss" => "__builtin_ve_vl_tscr_ssss", - "llvm.ve.vl.vaddsl.vsvl" => "__builtin_ve_vl_vaddsl_vsvl", - "llvm.ve.vl.vaddsl.vsvmvl" => "__builtin_ve_vl_vaddsl_vsvmvl", - "llvm.ve.vl.vaddsl.vsvvl" => "__builtin_ve_vl_vaddsl_vsvvl", - "llvm.ve.vl.vaddsl.vvvl" => "__builtin_ve_vl_vaddsl_vvvl", - "llvm.ve.vl.vaddsl.vvvmvl" => "__builtin_ve_vl_vaddsl_vvvmvl", - "llvm.ve.vl.vaddsl.vvvvl" => "__builtin_ve_vl_vaddsl_vvvvl", - "llvm.ve.vl.vaddswsx.vsvl" => "__builtin_ve_vl_vaddswsx_vsvl", - "llvm.ve.vl.vaddswsx.vsvmvl" => "__builtin_ve_vl_vaddswsx_vsvmvl", - "llvm.ve.vl.vaddswsx.vsvvl" => "__builtin_ve_vl_vaddswsx_vsvvl", - "llvm.ve.vl.vaddswsx.vvvl" => "__builtin_ve_vl_vaddswsx_vvvl", - "llvm.ve.vl.vaddswsx.vvvmvl" => "__builtin_ve_vl_vaddswsx_vvvmvl", - "llvm.ve.vl.vaddswsx.vvvvl" => "__builtin_ve_vl_vaddswsx_vvvvl", - "llvm.ve.vl.vaddswzx.vsvl" => "__builtin_ve_vl_vaddswzx_vsvl", - "llvm.ve.vl.vaddswzx.vsvmvl" => "__builtin_ve_vl_vaddswzx_vsvmvl", - "llvm.ve.vl.vaddswzx.vsvvl" => "__builtin_ve_vl_vaddswzx_vsvvl", - "llvm.ve.vl.vaddswzx.vvvl" => "__builtin_ve_vl_vaddswzx_vvvl", - "llvm.ve.vl.vaddswzx.vvvmvl" => "__builtin_ve_vl_vaddswzx_vvvmvl", - "llvm.ve.vl.vaddswzx.vvvvl" => "__builtin_ve_vl_vaddswzx_vvvvl", - "llvm.ve.vl.vaddul.vsvl" => "__builtin_ve_vl_vaddul_vsvl", - "llvm.ve.vl.vaddul.vsvmvl" => "__builtin_ve_vl_vaddul_vsvmvl", - "llvm.ve.vl.vaddul.vsvvl" => "__builtin_ve_vl_vaddul_vsvvl", - "llvm.ve.vl.vaddul.vvvl" => "__builtin_ve_vl_vaddul_vvvl", - "llvm.ve.vl.vaddul.vvvmvl" => "__builtin_ve_vl_vaddul_vvvmvl", - "llvm.ve.vl.vaddul.vvvvl" => "__builtin_ve_vl_vaddul_vvvvl", - "llvm.ve.vl.vadduw.vsvl" => "__builtin_ve_vl_vadduw_vsvl", - "llvm.ve.vl.vadduw.vsvmvl" => "__builtin_ve_vl_vadduw_vsvmvl", - "llvm.ve.vl.vadduw.vsvvl" => "__builtin_ve_vl_vadduw_vsvvl", - "llvm.ve.vl.vadduw.vvvl" => "__builtin_ve_vl_vadduw_vvvl", - "llvm.ve.vl.vadduw.vvvmvl" => "__builtin_ve_vl_vadduw_vvvmvl", - "llvm.ve.vl.vadduw.vvvvl" => "__builtin_ve_vl_vadduw_vvvvl", - "llvm.ve.vl.vand.vsvl" => "__builtin_ve_vl_vand_vsvl", - "llvm.ve.vl.vand.vsvmvl" => "__builtin_ve_vl_vand_vsvmvl", - "llvm.ve.vl.vand.vsvvl" => "__builtin_ve_vl_vand_vsvvl", - "llvm.ve.vl.vand.vvvl" => "__builtin_ve_vl_vand_vvvl", - "llvm.ve.vl.vand.vvvmvl" => "__builtin_ve_vl_vand_vvvmvl", - "llvm.ve.vl.vand.vvvvl" => "__builtin_ve_vl_vand_vvvvl", - "llvm.ve.vl.vbrdd.vsl" => "__builtin_ve_vl_vbrdd_vsl", - "llvm.ve.vl.vbrdd.vsmvl" => "__builtin_ve_vl_vbrdd_vsmvl", - "llvm.ve.vl.vbrdd.vsvl" => "__builtin_ve_vl_vbrdd_vsvl", - "llvm.ve.vl.vbrdl.vsl" => "__builtin_ve_vl_vbrdl_vsl", - "llvm.ve.vl.vbrdl.vsmvl" => "__builtin_ve_vl_vbrdl_vsmvl", - "llvm.ve.vl.vbrdl.vsvl" => "__builtin_ve_vl_vbrdl_vsvl", - "llvm.ve.vl.vbrds.vsl" => "__builtin_ve_vl_vbrds_vsl", - "llvm.ve.vl.vbrds.vsmvl" => "__builtin_ve_vl_vbrds_vsmvl", - "llvm.ve.vl.vbrds.vsvl" => "__builtin_ve_vl_vbrds_vsvl", - "llvm.ve.vl.vbrdw.vsl" => "__builtin_ve_vl_vbrdw_vsl", - "llvm.ve.vl.vbrdw.vsmvl" => "__builtin_ve_vl_vbrdw_vsmvl", - "llvm.ve.vl.vbrdw.vsvl" => "__builtin_ve_vl_vbrdw_vsvl", - "llvm.ve.vl.vbrv.vvl" => "__builtin_ve_vl_vbrv_vvl", - "llvm.ve.vl.vbrv.vvmvl" => "__builtin_ve_vl_vbrv_vvmvl", - "llvm.ve.vl.vbrv.vvvl" => "__builtin_ve_vl_vbrv_vvvl", - "llvm.ve.vl.vcmpsl.vsvl" => "__builtin_ve_vl_vcmpsl_vsvl", - "llvm.ve.vl.vcmpsl.vsvmvl" => "__builtin_ve_vl_vcmpsl_vsvmvl", - "llvm.ve.vl.vcmpsl.vsvvl" => "__builtin_ve_vl_vcmpsl_vsvvl", - "llvm.ve.vl.vcmpsl.vvvl" => "__builtin_ve_vl_vcmpsl_vvvl", - "llvm.ve.vl.vcmpsl.vvvmvl" => "__builtin_ve_vl_vcmpsl_vvvmvl", - "llvm.ve.vl.vcmpsl.vvvvl" => "__builtin_ve_vl_vcmpsl_vvvvl", - "llvm.ve.vl.vcmpswsx.vsvl" => "__builtin_ve_vl_vcmpswsx_vsvl", - "llvm.ve.vl.vcmpswsx.vsvmvl" => "__builtin_ve_vl_vcmpswsx_vsvmvl", - "llvm.ve.vl.vcmpswsx.vsvvl" => "__builtin_ve_vl_vcmpswsx_vsvvl", - "llvm.ve.vl.vcmpswsx.vvvl" => "__builtin_ve_vl_vcmpswsx_vvvl", - "llvm.ve.vl.vcmpswsx.vvvmvl" => "__builtin_ve_vl_vcmpswsx_vvvmvl", - "llvm.ve.vl.vcmpswsx.vvvvl" => "__builtin_ve_vl_vcmpswsx_vvvvl", - "llvm.ve.vl.vcmpswzx.vsvl" => "__builtin_ve_vl_vcmpswzx_vsvl", - "llvm.ve.vl.vcmpswzx.vsvmvl" => "__builtin_ve_vl_vcmpswzx_vsvmvl", - "llvm.ve.vl.vcmpswzx.vsvvl" => "__builtin_ve_vl_vcmpswzx_vsvvl", - "llvm.ve.vl.vcmpswzx.vvvl" => "__builtin_ve_vl_vcmpswzx_vvvl", - "llvm.ve.vl.vcmpswzx.vvvmvl" => "__builtin_ve_vl_vcmpswzx_vvvmvl", - "llvm.ve.vl.vcmpswzx.vvvvl" => "__builtin_ve_vl_vcmpswzx_vvvvl", - "llvm.ve.vl.vcmpul.vsvl" => "__builtin_ve_vl_vcmpul_vsvl", - "llvm.ve.vl.vcmpul.vsvmvl" => "__builtin_ve_vl_vcmpul_vsvmvl", - "llvm.ve.vl.vcmpul.vsvvl" => "__builtin_ve_vl_vcmpul_vsvvl", - "llvm.ve.vl.vcmpul.vvvl" => "__builtin_ve_vl_vcmpul_vvvl", - "llvm.ve.vl.vcmpul.vvvmvl" => "__builtin_ve_vl_vcmpul_vvvmvl", - "llvm.ve.vl.vcmpul.vvvvl" => "__builtin_ve_vl_vcmpul_vvvvl", - "llvm.ve.vl.vcmpuw.vsvl" => "__builtin_ve_vl_vcmpuw_vsvl", - "llvm.ve.vl.vcmpuw.vsvmvl" => "__builtin_ve_vl_vcmpuw_vsvmvl", - "llvm.ve.vl.vcmpuw.vsvvl" => "__builtin_ve_vl_vcmpuw_vsvvl", - "llvm.ve.vl.vcmpuw.vvvl" => "__builtin_ve_vl_vcmpuw_vvvl", - "llvm.ve.vl.vcmpuw.vvvmvl" => "__builtin_ve_vl_vcmpuw_vvvmvl", - "llvm.ve.vl.vcmpuw.vvvvl" => "__builtin_ve_vl_vcmpuw_vvvvl", - "llvm.ve.vl.vcp.vvmvl" => "__builtin_ve_vl_vcp_vvmvl", - "llvm.ve.vl.vcvtdl.vvl" => "__builtin_ve_vl_vcvtdl_vvl", - "llvm.ve.vl.vcvtdl.vvvl" => "__builtin_ve_vl_vcvtdl_vvvl", - "llvm.ve.vl.vcvtds.vvl" => "__builtin_ve_vl_vcvtds_vvl", - "llvm.ve.vl.vcvtds.vvvl" => "__builtin_ve_vl_vcvtds_vvvl", - "llvm.ve.vl.vcvtdw.vvl" => "__builtin_ve_vl_vcvtdw_vvl", - "llvm.ve.vl.vcvtdw.vvvl" => "__builtin_ve_vl_vcvtdw_vvvl", - "llvm.ve.vl.vcvtld.vvl" => "__builtin_ve_vl_vcvtld_vvl", - "llvm.ve.vl.vcvtld.vvmvl" => "__builtin_ve_vl_vcvtld_vvmvl", - "llvm.ve.vl.vcvtld.vvvl" => "__builtin_ve_vl_vcvtld_vvvl", - "llvm.ve.vl.vcvtldrz.vvl" => "__builtin_ve_vl_vcvtldrz_vvl", - "llvm.ve.vl.vcvtldrz.vvmvl" => "__builtin_ve_vl_vcvtldrz_vvmvl", - "llvm.ve.vl.vcvtldrz.vvvl" => "__builtin_ve_vl_vcvtldrz_vvvl", - "llvm.ve.vl.vcvtsd.vvl" => "__builtin_ve_vl_vcvtsd_vvl", - "llvm.ve.vl.vcvtsd.vvvl" => "__builtin_ve_vl_vcvtsd_vvvl", - "llvm.ve.vl.vcvtsw.vvl" => "__builtin_ve_vl_vcvtsw_vvl", - "llvm.ve.vl.vcvtsw.vvvl" => "__builtin_ve_vl_vcvtsw_vvvl", - "llvm.ve.vl.vcvtwdsx.vvl" => "__builtin_ve_vl_vcvtwdsx_vvl", - "llvm.ve.vl.vcvtwdsx.vvmvl" => "__builtin_ve_vl_vcvtwdsx_vvmvl", - "llvm.ve.vl.vcvtwdsx.vvvl" => "__builtin_ve_vl_vcvtwdsx_vvvl", - "llvm.ve.vl.vcvtwdsxrz.vvl" => "__builtin_ve_vl_vcvtwdsxrz_vvl", - "llvm.ve.vl.vcvtwdsxrz.vvmvl" => "__builtin_ve_vl_vcvtwdsxrz_vvmvl", - "llvm.ve.vl.vcvtwdsxrz.vvvl" => "__builtin_ve_vl_vcvtwdsxrz_vvvl", - "llvm.ve.vl.vcvtwdzx.vvl" => "__builtin_ve_vl_vcvtwdzx_vvl", - "llvm.ve.vl.vcvtwdzx.vvmvl" => "__builtin_ve_vl_vcvtwdzx_vvmvl", - "llvm.ve.vl.vcvtwdzx.vvvl" => "__builtin_ve_vl_vcvtwdzx_vvvl", - "llvm.ve.vl.vcvtwdzxrz.vvl" => "__builtin_ve_vl_vcvtwdzxrz_vvl", - "llvm.ve.vl.vcvtwdzxrz.vvmvl" => "__builtin_ve_vl_vcvtwdzxrz_vvmvl", - "llvm.ve.vl.vcvtwdzxrz.vvvl" => "__builtin_ve_vl_vcvtwdzxrz_vvvl", - "llvm.ve.vl.vcvtwssx.vvl" => "__builtin_ve_vl_vcvtwssx_vvl", - "llvm.ve.vl.vcvtwssx.vvmvl" => "__builtin_ve_vl_vcvtwssx_vvmvl", - "llvm.ve.vl.vcvtwssx.vvvl" => "__builtin_ve_vl_vcvtwssx_vvvl", - "llvm.ve.vl.vcvtwssxrz.vvl" => "__builtin_ve_vl_vcvtwssxrz_vvl", - "llvm.ve.vl.vcvtwssxrz.vvmvl" => "__builtin_ve_vl_vcvtwssxrz_vvmvl", - "llvm.ve.vl.vcvtwssxrz.vvvl" => "__builtin_ve_vl_vcvtwssxrz_vvvl", - "llvm.ve.vl.vcvtwszx.vvl" => "__builtin_ve_vl_vcvtwszx_vvl", - "llvm.ve.vl.vcvtwszx.vvmvl" => "__builtin_ve_vl_vcvtwszx_vvmvl", - "llvm.ve.vl.vcvtwszx.vvvl" => "__builtin_ve_vl_vcvtwszx_vvvl", - "llvm.ve.vl.vcvtwszxrz.vvl" => "__builtin_ve_vl_vcvtwszxrz_vvl", - "llvm.ve.vl.vcvtwszxrz.vvmvl" => "__builtin_ve_vl_vcvtwszxrz_vvmvl", - "llvm.ve.vl.vcvtwszxrz.vvvl" => "__builtin_ve_vl_vcvtwszxrz_vvvl", - "llvm.ve.vl.vdivsl.vsvl" => "__builtin_ve_vl_vdivsl_vsvl", - "llvm.ve.vl.vdivsl.vsvmvl" => "__builtin_ve_vl_vdivsl_vsvmvl", - "llvm.ve.vl.vdivsl.vsvvl" => "__builtin_ve_vl_vdivsl_vsvvl", - "llvm.ve.vl.vdivsl.vvsl" => "__builtin_ve_vl_vdivsl_vvsl", - "llvm.ve.vl.vdivsl.vvsmvl" => "__builtin_ve_vl_vdivsl_vvsmvl", - "llvm.ve.vl.vdivsl.vvsvl" => "__builtin_ve_vl_vdivsl_vvsvl", - "llvm.ve.vl.vdivsl.vvvl" => "__builtin_ve_vl_vdivsl_vvvl", - "llvm.ve.vl.vdivsl.vvvmvl" => "__builtin_ve_vl_vdivsl_vvvmvl", - "llvm.ve.vl.vdivsl.vvvvl" => "__builtin_ve_vl_vdivsl_vvvvl", - "llvm.ve.vl.vdivswsx.vsvl" => "__builtin_ve_vl_vdivswsx_vsvl", - "llvm.ve.vl.vdivswsx.vsvmvl" => "__builtin_ve_vl_vdivswsx_vsvmvl", - "llvm.ve.vl.vdivswsx.vsvvl" => "__builtin_ve_vl_vdivswsx_vsvvl", - "llvm.ve.vl.vdivswsx.vvsl" => "__builtin_ve_vl_vdivswsx_vvsl", - "llvm.ve.vl.vdivswsx.vvsmvl" => "__builtin_ve_vl_vdivswsx_vvsmvl", - "llvm.ve.vl.vdivswsx.vvsvl" => "__builtin_ve_vl_vdivswsx_vvsvl", - "llvm.ve.vl.vdivswsx.vvvl" => "__builtin_ve_vl_vdivswsx_vvvl", - "llvm.ve.vl.vdivswsx.vvvmvl" => "__builtin_ve_vl_vdivswsx_vvvmvl", - "llvm.ve.vl.vdivswsx.vvvvl" => "__builtin_ve_vl_vdivswsx_vvvvl", - "llvm.ve.vl.vdivswzx.vsvl" => "__builtin_ve_vl_vdivswzx_vsvl", - "llvm.ve.vl.vdivswzx.vsvmvl" => "__builtin_ve_vl_vdivswzx_vsvmvl", - "llvm.ve.vl.vdivswzx.vsvvl" => "__builtin_ve_vl_vdivswzx_vsvvl", - "llvm.ve.vl.vdivswzx.vvsl" => "__builtin_ve_vl_vdivswzx_vvsl", - "llvm.ve.vl.vdivswzx.vvsmvl" => "__builtin_ve_vl_vdivswzx_vvsmvl", - "llvm.ve.vl.vdivswzx.vvsvl" => "__builtin_ve_vl_vdivswzx_vvsvl", - "llvm.ve.vl.vdivswzx.vvvl" => "__builtin_ve_vl_vdivswzx_vvvl", - "llvm.ve.vl.vdivswzx.vvvmvl" => "__builtin_ve_vl_vdivswzx_vvvmvl", - "llvm.ve.vl.vdivswzx.vvvvl" => "__builtin_ve_vl_vdivswzx_vvvvl", - "llvm.ve.vl.vdivul.vsvl" => "__builtin_ve_vl_vdivul_vsvl", - "llvm.ve.vl.vdivul.vsvmvl" => "__builtin_ve_vl_vdivul_vsvmvl", - "llvm.ve.vl.vdivul.vsvvl" => "__builtin_ve_vl_vdivul_vsvvl", - "llvm.ve.vl.vdivul.vvsl" => "__builtin_ve_vl_vdivul_vvsl", - "llvm.ve.vl.vdivul.vvsmvl" => "__builtin_ve_vl_vdivul_vvsmvl", - "llvm.ve.vl.vdivul.vvsvl" => "__builtin_ve_vl_vdivul_vvsvl", - "llvm.ve.vl.vdivul.vvvl" => "__builtin_ve_vl_vdivul_vvvl", - "llvm.ve.vl.vdivul.vvvmvl" => "__builtin_ve_vl_vdivul_vvvmvl", - "llvm.ve.vl.vdivul.vvvvl" => "__builtin_ve_vl_vdivul_vvvvl", - "llvm.ve.vl.vdivuw.vsvl" => "__builtin_ve_vl_vdivuw_vsvl", - "llvm.ve.vl.vdivuw.vsvmvl" => "__builtin_ve_vl_vdivuw_vsvmvl", - "llvm.ve.vl.vdivuw.vsvvl" => "__builtin_ve_vl_vdivuw_vsvvl", - "llvm.ve.vl.vdivuw.vvsl" => "__builtin_ve_vl_vdivuw_vvsl", - "llvm.ve.vl.vdivuw.vvsmvl" => "__builtin_ve_vl_vdivuw_vvsmvl", - "llvm.ve.vl.vdivuw.vvsvl" => "__builtin_ve_vl_vdivuw_vvsvl", - "llvm.ve.vl.vdivuw.vvvl" => "__builtin_ve_vl_vdivuw_vvvl", - "llvm.ve.vl.vdivuw.vvvmvl" => "__builtin_ve_vl_vdivuw_vvvmvl", - "llvm.ve.vl.vdivuw.vvvvl" => "__builtin_ve_vl_vdivuw_vvvvl", - "llvm.ve.vl.veqv.vsvl" => "__builtin_ve_vl_veqv_vsvl", - "llvm.ve.vl.veqv.vsvmvl" => "__builtin_ve_vl_veqv_vsvmvl", - "llvm.ve.vl.veqv.vsvvl" => "__builtin_ve_vl_veqv_vsvvl", - "llvm.ve.vl.veqv.vvvl" => "__builtin_ve_vl_veqv_vvvl", - "llvm.ve.vl.veqv.vvvmvl" => "__builtin_ve_vl_veqv_vvvmvl", - "llvm.ve.vl.veqv.vvvvl" => "__builtin_ve_vl_veqv_vvvvl", - "llvm.ve.vl.vex.vvmvl" => "__builtin_ve_vl_vex_vvmvl", - "llvm.ve.vl.vfaddd.vsvl" => "__builtin_ve_vl_vfaddd_vsvl", - "llvm.ve.vl.vfaddd.vsvmvl" => "__builtin_ve_vl_vfaddd_vsvmvl", - "llvm.ve.vl.vfaddd.vsvvl" => "__builtin_ve_vl_vfaddd_vsvvl", - "llvm.ve.vl.vfaddd.vvvl" => "__builtin_ve_vl_vfaddd_vvvl", - "llvm.ve.vl.vfaddd.vvvmvl" => "__builtin_ve_vl_vfaddd_vvvmvl", - "llvm.ve.vl.vfaddd.vvvvl" => "__builtin_ve_vl_vfaddd_vvvvl", - "llvm.ve.vl.vfadds.vsvl" => "__builtin_ve_vl_vfadds_vsvl", - "llvm.ve.vl.vfadds.vsvmvl" => "__builtin_ve_vl_vfadds_vsvmvl", - "llvm.ve.vl.vfadds.vsvvl" => "__builtin_ve_vl_vfadds_vsvvl", - "llvm.ve.vl.vfadds.vvvl" => "__builtin_ve_vl_vfadds_vvvl", - "llvm.ve.vl.vfadds.vvvmvl" => "__builtin_ve_vl_vfadds_vvvmvl", - "llvm.ve.vl.vfadds.vvvvl" => "__builtin_ve_vl_vfadds_vvvvl", - "llvm.ve.vl.vfcmpd.vsvl" => "__builtin_ve_vl_vfcmpd_vsvl", - "llvm.ve.vl.vfcmpd.vsvmvl" => "__builtin_ve_vl_vfcmpd_vsvmvl", - "llvm.ve.vl.vfcmpd.vsvvl" => "__builtin_ve_vl_vfcmpd_vsvvl", - "llvm.ve.vl.vfcmpd.vvvl" => "__builtin_ve_vl_vfcmpd_vvvl", - "llvm.ve.vl.vfcmpd.vvvmvl" => "__builtin_ve_vl_vfcmpd_vvvmvl", - "llvm.ve.vl.vfcmpd.vvvvl" => "__builtin_ve_vl_vfcmpd_vvvvl", - "llvm.ve.vl.vfcmps.vsvl" => "__builtin_ve_vl_vfcmps_vsvl", - "llvm.ve.vl.vfcmps.vsvmvl" => "__builtin_ve_vl_vfcmps_vsvmvl", - "llvm.ve.vl.vfcmps.vsvvl" => "__builtin_ve_vl_vfcmps_vsvvl", - "llvm.ve.vl.vfcmps.vvvl" => "__builtin_ve_vl_vfcmps_vvvl", - "llvm.ve.vl.vfcmps.vvvmvl" => "__builtin_ve_vl_vfcmps_vvvmvl", - "llvm.ve.vl.vfcmps.vvvvl" => "__builtin_ve_vl_vfcmps_vvvvl", - "llvm.ve.vl.vfdivd.vsvl" => "__builtin_ve_vl_vfdivd_vsvl", - "llvm.ve.vl.vfdivd.vsvmvl" => "__builtin_ve_vl_vfdivd_vsvmvl", - "llvm.ve.vl.vfdivd.vsvvl" => "__builtin_ve_vl_vfdivd_vsvvl", - "llvm.ve.vl.vfdivd.vvvl" => "__builtin_ve_vl_vfdivd_vvvl", - "llvm.ve.vl.vfdivd.vvvmvl" => "__builtin_ve_vl_vfdivd_vvvmvl", - "llvm.ve.vl.vfdivd.vvvvl" => "__builtin_ve_vl_vfdivd_vvvvl", - "llvm.ve.vl.vfdivs.vsvl" => "__builtin_ve_vl_vfdivs_vsvl", - "llvm.ve.vl.vfdivs.vsvmvl" => "__builtin_ve_vl_vfdivs_vsvmvl", - "llvm.ve.vl.vfdivs.vsvvl" => "__builtin_ve_vl_vfdivs_vsvvl", - "llvm.ve.vl.vfdivs.vvvl" => "__builtin_ve_vl_vfdivs_vvvl", - "llvm.ve.vl.vfdivs.vvvmvl" => "__builtin_ve_vl_vfdivs_vvvmvl", - "llvm.ve.vl.vfdivs.vvvvl" => "__builtin_ve_vl_vfdivs_vvvvl", - "llvm.ve.vl.vfmadd.vsvvl" => "__builtin_ve_vl_vfmadd_vsvvl", - "llvm.ve.vl.vfmadd.vsvvmvl" => "__builtin_ve_vl_vfmadd_vsvvmvl", - "llvm.ve.vl.vfmadd.vsvvvl" => "__builtin_ve_vl_vfmadd_vsvvvl", - "llvm.ve.vl.vfmadd.vvsvl" => "__builtin_ve_vl_vfmadd_vvsvl", - "llvm.ve.vl.vfmadd.vvsvmvl" => "__builtin_ve_vl_vfmadd_vvsvmvl", - "llvm.ve.vl.vfmadd.vvsvvl" => "__builtin_ve_vl_vfmadd_vvsvvl", - "llvm.ve.vl.vfmadd.vvvvl" => "__builtin_ve_vl_vfmadd_vvvvl", - "llvm.ve.vl.vfmadd.vvvvmvl" => "__builtin_ve_vl_vfmadd_vvvvmvl", - "llvm.ve.vl.vfmadd.vvvvvl" => "__builtin_ve_vl_vfmadd_vvvvvl", - "llvm.ve.vl.vfmads.vsvvl" => "__builtin_ve_vl_vfmads_vsvvl", - "llvm.ve.vl.vfmads.vsvvmvl" => "__builtin_ve_vl_vfmads_vsvvmvl", - "llvm.ve.vl.vfmads.vsvvvl" => "__builtin_ve_vl_vfmads_vsvvvl", - "llvm.ve.vl.vfmads.vvsvl" => "__builtin_ve_vl_vfmads_vvsvl", - "llvm.ve.vl.vfmads.vvsvmvl" => "__builtin_ve_vl_vfmads_vvsvmvl", - "llvm.ve.vl.vfmads.vvsvvl" => "__builtin_ve_vl_vfmads_vvsvvl", - "llvm.ve.vl.vfmads.vvvvl" => "__builtin_ve_vl_vfmads_vvvvl", - "llvm.ve.vl.vfmads.vvvvmvl" => "__builtin_ve_vl_vfmads_vvvvmvl", - "llvm.ve.vl.vfmads.vvvvvl" => "__builtin_ve_vl_vfmads_vvvvvl", - "llvm.ve.vl.vfmaxd.vsvl" => "__builtin_ve_vl_vfmaxd_vsvl", - "llvm.ve.vl.vfmaxd.vsvmvl" => "__builtin_ve_vl_vfmaxd_vsvmvl", - "llvm.ve.vl.vfmaxd.vsvvl" => "__builtin_ve_vl_vfmaxd_vsvvl", - "llvm.ve.vl.vfmaxd.vvvl" => "__builtin_ve_vl_vfmaxd_vvvl", - "llvm.ve.vl.vfmaxd.vvvmvl" => "__builtin_ve_vl_vfmaxd_vvvmvl", - "llvm.ve.vl.vfmaxd.vvvvl" => "__builtin_ve_vl_vfmaxd_vvvvl", - "llvm.ve.vl.vfmaxs.vsvl" => "__builtin_ve_vl_vfmaxs_vsvl", - "llvm.ve.vl.vfmaxs.vsvmvl" => "__builtin_ve_vl_vfmaxs_vsvmvl", - "llvm.ve.vl.vfmaxs.vsvvl" => "__builtin_ve_vl_vfmaxs_vsvvl", - "llvm.ve.vl.vfmaxs.vvvl" => "__builtin_ve_vl_vfmaxs_vvvl", - "llvm.ve.vl.vfmaxs.vvvmvl" => "__builtin_ve_vl_vfmaxs_vvvmvl", - "llvm.ve.vl.vfmaxs.vvvvl" => "__builtin_ve_vl_vfmaxs_vvvvl", - "llvm.ve.vl.vfmind.vsvl" => "__builtin_ve_vl_vfmind_vsvl", - "llvm.ve.vl.vfmind.vsvmvl" => "__builtin_ve_vl_vfmind_vsvmvl", - "llvm.ve.vl.vfmind.vsvvl" => "__builtin_ve_vl_vfmind_vsvvl", - "llvm.ve.vl.vfmind.vvvl" => "__builtin_ve_vl_vfmind_vvvl", - "llvm.ve.vl.vfmind.vvvmvl" => "__builtin_ve_vl_vfmind_vvvmvl", - "llvm.ve.vl.vfmind.vvvvl" => "__builtin_ve_vl_vfmind_vvvvl", - "llvm.ve.vl.vfmins.vsvl" => "__builtin_ve_vl_vfmins_vsvl", - "llvm.ve.vl.vfmins.vsvmvl" => "__builtin_ve_vl_vfmins_vsvmvl", - "llvm.ve.vl.vfmins.vsvvl" => "__builtin_ve_vl_vfmins_vsvvl", - "llvm.ve.vl.vfmins.vvvl" => "__builtin_ve_vl_vfmins_vvvl", - "llvm.ve.vl.vfmins.vvvmvl" => "__builtin_ve_vl_vfmins_vvvmvl", - "llvm.ve.vl.vfmins.vvvvl" => "__builtin_ve_vl_vfmins_vvvvl", - "llvm.ve.vl.vfmkdeq.mvl" => "__builtin_ve_vl_vfmkdeq_mvl", - "llvm.ve.vl.vfmkdeq.mvml" => "__builtin_ve_vl_vfmkdeq_mvml", - "llvm.ve.vl.vfmkdeqnan.mvl" => "__builtin_ve_vl_vfmkdeqnan_mvl", - "llvm.ve.vl.vfmkdeqnan.mvml" => "__builtin_ve_vl_vfmkdeqnan_mvml", - "llvm.ve.vl.vfmkdge.mvl" => "__builtin_ve_vl_vfmkdge_mvl", - "llvm.ve.vl.vfmkdge.mvml" => "__builtin_ve_vl_vfmkdge_mvml", - "llvm.ve.vl.vfmkdgenan.mvl" => "__builtin_ve_vl_vfmkdgenan_mvl", - "llvm.ve.vl.vfmkdgenan.mvml" => "__builtin_ve_vl_vfmkdgenan_mvml", - "llvm.ve.vl.vfmkdgt.mvl" => "__builtin_ve_vl_vfmkdgt_mvl", - "llvm.ve.vl.vfmkdgt.mvml" => "__builtin_ve_vl_vfmkdgt_mvml", - "llvm.ve.vl.vfmkdgtnan.mvl" => "__builtin_ve_vl_vfmkdgtnan_mvl", - "llvm.ve.vl.vfmkdgtnan.mvml" => "__builtin_ve_vl_vfmkdgtnan_mvml", - "llvm.ve.vl.vfmkdle.mvl" => "__builtin_ve_vl_vfmkdle_mvl", - "llvm.ve.vl.vfmkdle.mvml" => "__builtin_ve_vl_vfmkdle_mvml", - "llvm.ve.vl.vfmkdlenan.mvl" => "__builtin_ve_vl_vfmkdlenan_mvl", - "llvm.ve.vl.vfmkdlenan.mvml" => "__builtin_ve_vl_vfmkdlenan_mvml", - "llvm.ve.vl.vfmkdlt.mvl" => "__builtin_ve_vl_vfmkdlt_mvl", - "llvm.ve.vl.vfmkdlt.mvml" => "__builtin_ve_vl_vfmkdlt_mvml", - "llvm.ve.vl.vfmkdltnan.mvl" => "__builtin_ve_vl_vfmkdltnan_mvl", - "llvm.ve.vl.vfmkdltnan.mvml" => "__builtin_ve_vl_vfmkdltnan_mvml", - "llvm.ve.vl.vfmkdnan.mvl" => "__builtin_ve_vl_vfmkdnan_mvl", - "llvm.ve.vl.vfmkdnan.mvml" => "__builtin_ve_vl_vfmkdnan_mvml", - "llvm.ve.vl.vfmkdne.mvl" => "__builtin_ve_vl_vfmkdne_mvl", - "llvm.ve.vl.vfmkdne.mvml" => "__builtin_ve_vl_vfmkdne_mvml", - "llvm.ve.vl.vfmkdnenan.mvl" => "__builtin_ve_vl_vfmkdnenan_mvl", - "llvm.ve.vl.vfmkdnenan.mvml" => "__builtin_ve_vl_vfmkdnenan_mvml", - "llvm.ve.vl.vfmkdnum.mvl" => "__builtin_ve_vl_vfmkdnum_mvl", - "llvm.ve.vl.vfmkdnum.mvml" => "__builtin_ve_vl_vfmkdnum_mvml", - "llvm.ve.vl.vfmklaf.ml" => "__builtin_ve_vl_vfmklaf_ml", - "llvm.ve.vl.vfmklat.ml" => "__builtin_ve_vl_vfmklat_ml", - "llvm.ve.vl.vfmkleq.mvl" => "__builtin_ve_vl_vfmkleq_mvl", - "llvm.ve.vl.vfmkleq.mvml" => "__builtin_ve_vl_vfmkleq_mvml", - "llvm.ve.vl.vfmkleqnan.mvl" => "__builtin_ve_vl_vfmkleqnan_mvl", - "llvm.ve.vl.vfmkleqnan.mvml" => "__builtin_ve_vl_vfmkleqnan_mvml", - "llvm.ve.vl.vfmklge.mvl" => "__builtin_ve_vl_vfmklge_mvl", - "llvm.ve.vl.vfmklge.mvml" => "__builtin_ve_vl_vfmklge_mvml", - "llvm.ve.vl.vfmklgenan.mvl" => "__builtin_ve_vl_vfmklgenan_mvl", - "llvm.ve.vl.vfmklgenan.mvml" => "__builtin_ve_vl_vfmklgenan_mvml", - "llvm.ve.vl.vfmklgt.mvl" => "__builtin_ve_vl_vfmklgt_mvl", - "llvm.ve.vl.vfmklgt.mvml" => "__builtin_ve_vl_vfmklgt_mvml", - "llvm.ve.vl.vfmklgtnan.mvl" => "__builtin_ve_vl_vfmklgtnan_mvl", - "llvm.ve.vl.vfmklgtnan.mvml" => "__builtin_ve_vl_vfmklgtnan_mvml", - "llvm.ve.vl.vfmklle.mvl" => "__builtin_ve_vl_vfmklle_mvl", - "llvm.ve.vl.vfmklle.mvml" => "__builtin_ve_vl_vfmklle_mvml", - "llvm.ve.vl.vfmkllenan.mvl" => "__builtin_ve_vl_vfmkllenan_mvl", - "llvm.ve.vl.vfmkllenan.mvml" => "__builtin_ve_vl_vfmkllenan_mvml", - "llvm.ve.vl.vfmkllt.mvl" => "__builtin_ve_vl_vfmkllt_mvl", - "llvm.ve.vl.vfmkllt.mvml" => "__builtin_ve_vl_vfmkllt_mvml", - "llvm.ve.vl.vfmklltnan.mvl" => "__builtin_ve_vl_vfmklltnan_mvl", - "llvm.ve.vl.vfmklltnan.mvml" => "__builtin_ve_vl_vfmklltnan_mvml", - "llvm.ve.vl.vfmklnan.mvl" => "__builtin_ve_vl_vfmklnan_mvl", - "llvm.ve.vl.vfmklnan.mvml" => "__builtin_ve_vl_vfmklnan_mvml", - "llvm.ve.vl.vfmklne.mvl" => "__builtin_ve_vl_vfmklne_mvl", - "llvm.ve.vl.vfmklne.mvml" => "__builtin_ve_vl_vfmklne_mvml", - "llvm.ve.vl.vfmklnenan.mvl" => "__builtin_ve_vl_vfmklnenan_mvl", - "llvm.ve.vl.vfmklnenan.mvml" => "__builtin_ve_vl_vfmklnenan_mvml", - "llvm.ve.vl.vfmklnum.mvl" => "__builtin_ve_vl_vfmklnum_mvl", - "llvm.ve.vl.vfmklnum.mvml" => "__builtin_ve_vl_vfmklnum_mvml", - "llvm.ve.vl.vfmkseq.mvl" => "__builtin_ve_vl_vfmkseq_mvl", - "llvm.ve.vl.vfmkseq.mvml" => "__builtin_ve_vl_vfmkseq_mvml", - "llvm.ve.vl.vfmkseqnan.mvl" => "__builtin_ve_vl_vfmkseqnan_mvl", - "llvm.ve.vl.vfmkseqnan.mvml" => "__builtin_ve_vl_vfmkseqnan_mvml", - "llvm.ve.vl.vfmksge.mvl" => "__builtin_ve_vl_vfmksge_mvl", - "llvm.ve.vl.vfmksge.mvml" => "__builtin_ve_vl_vfmksge_mvml", - "llvm.ve.vl.vfmksgenan.mvl" => "__builtin_ve_vl_vfmksgenan_mvl", - "llvm.ve.vl.vfmksgenan.mvml" => "__builtin_ve_vl_vfmksgenan_mvml", - "llvm.ve.vl.vfmksgt.mvl" => "__builtin_ve_vl_vfmksgt_mvl", - "llvm.ve.vl.vfmksgt.mvml" => "__builtin_ve_vl_vfmksgt_mvml", - "llvm.ve.vl.vfmksgtnan.mvl" => "__builtin_ve_vl_vfmksgtnan_mvl", - "llvm.ve.vl.vfmksgtnan.mvml" => "__builtin_ve_vl_vfmksgtnan_mvml", - "llvm.ve.vl.vfmksle.mvl" => "__builtin_ve_vl_vfmksle_mvl", - "llvm.ve.vl.vfmksle.mvml" => "__builtin_ve_vl_vfmksle_mvml", - "llvm.ve.vl.vfmkslenan.mvl" => "__builtin_ve_vl_vfmkslenan_mvl", - "llvm.ve.vl.vfmkslenan.mvml" => "__builtin_ve_vl_vfmkslenan_mvml", - "llvm.ve.vl.vfmkslt.mvl" => "__builtin_ve_vl_vfmkslt_mvl", - "llvm.ve.vl.vfmkslt.mvml" => "__builtin_ve_vl_vfmkslt_mvml", - "llvm.ve.vl.vfmksltnan.mvl" => "__builtin_ve_vl_vfmksltnan_mvl", - "llvm.ve.vl.vfmksltnan.mvml" => "__builtin_ve_vl_vfmksltnan_mvml", - "llvm.ve.vl.vfmksnan.mvl" => "__builtin_ve_vl_vfmksnan_mvl", - "llvm.ve.vl.vfmksnan.mvml" => "__builtin_ve_vl_vfmksnan_mvml", - "llvm.ve.vl.vfmksne.mvl" => "__builtin_ve_vl_vfmksne_mvl", - "llvm.ve.vl.vfmksne.mvml" => "__builtin_ve_vl_vfmksne_mvml", - "llvm.ve.vl.vfmksnenan.mvl" => "__builtin_ve_vl_vfmksnenan_mvl", - "llvm.ve.vl.vfmksnenan.mvml" => "__builtin_ve_vl_vfmksnenan_mvml", - "llvm.ve.vl.vfmksnum.mvl" => "__builtin_ve_vl_vfmksnum_mvl", - "llvm.ve.vl.vfmksnum.mvml" => "__builtin_ve_vl_vfmksnum_mvml", - "llvm.ve.vl.vfmkweq.mvl" => "__builtin_ve_vl_vfmkweq_mvl", - "llvm.ve.vl.vfmkweq.mvml" => "__builtin_ve_vl_vfmkweq_mvml", - "llvm.ve.vl.vfmkweqnan.mvl" => "__builtin_ve_vl_vfmkweqnan_mvl", - "llvm.ve.vl.vfmkweqnan.mvml" => "__builtin_ve_vl_vfmkweqnan_mvml", - "llvm.ve.vl.vfmkwge.mvl" => "__builtin_ve_vl_vfmkwge_mvl", - "llvm.ve.vl.vfmkwge.mvml" => "__builtin_ve_vl_vfmkwge_mvml", - "llvm.ve.vl.vfmkwgenan.mvl" => "__builtin_ve_vl_vfmkwgenan_mvl", - "llvm.ve.vl.vfmkwgenan.mvml" => "__builtin_ve_vl_vfmkwgenan_mvml", - "llvm.ve.vl.vfmkwgt.mvl" => "__builtin_ve_vl_vfmkwgt_mvl", - "llvm.ve.vl.vfmkwgt.mvml" => "__builtin_ve_vl_vfmkwgt_mvml", - "llvm.ve.vl.vfmkwgtnan.mvl" => "__builtin_ve_vl_vfmkwgtnan_mvl", - "llvm.ve.vl.vfmkwgtnan.mvml" => "__builtin_ve_vl_vfmkwgtnan_mvml", - "llvm.ve.vl.vfmkwle.mvl" => "__builtin_ve_vl_vfmkwle_mvl", - "llvm.ve.vl.vfmkwle.mvml" => "__builtin_ve_vl_vfmkwle_mvml", - "llvm.ve.vl.vfmkwlenan.mvl" => "__builtin_ve_vl_vfmkwlenan_mvl", - "llvm.ve.vl.vfmkwlenan.mvml" => "__builtin_ve_vl_vfmkwlenan_mvml", - "llvm.ve.vl.vfmkwlt.mvl" => "__builtin_ve_vl_vfmkwlt_mvl", - "llvm.ve.vl.vfmkwlt.mvml" => "__builtin_ve_vl_vfmkwlt_mvml", - "llvm.ve.vl.vfmkwltnan.mvl" => "__builtin_ve_vl_vfmkwltnan_mvl", - "llvm.ve.vl.vfmkwltnan.mvml" => "__builtin_ve_vl_vfmkwltnan_mvml", - "llvm.ve.vl.vfmkwnan.mvl" => "__builtin_ve_vl_vfmkwnan_mvl", - "llvm.ve.vl.vfmkwnan.mvml" => "__builtin_ve_vl_vfmkwnan_mvml", - "llvm.ve.vl.vfmkwne.mvl" => "__builtin_ve_vl_vfmkwne_mvl", - "llvm.ve.vl.vfmkwne.mvml" => "__builtin_ve_vl_vfmkwne_mvml", - "llvm.ve.vl.vfmkwnenan.mvl" => "__builtin_ve_vl_vfmkwnenan_mvl", - "llvm.ve.vl.vfmkwnenan.mvml" => "__builtin_ve_vl_vfmkwnenan_mvml", - "llvm.ve.vl.vfmkwnum.mvl" => "__builtin_ve_vl_vfmkwnum_mvl", - "llvm.ve.vl.vfmkwnum.mvml" => "__builtin_ve_vl_vfmkwnum_mvml", - "llvm.ve.vl.vfmsbd.vsvvl" => "__builtin_ve_vl_vfmsbd_vsvvl", - "llvm.ve.vl.vfmsbd.vsvvmvl" => "__builtin_ve_vl_vfmsbd_vsvvmvl", - "llvm.ve.vl.vfmsbd.vsvvvl" => "__builtin_ve_vl_vfmsbd_vsvvvl", - "llvm.ve.vl.vfmsbd.vvsvl" => "__builtin_ve_vl_vfmsbd_vvsvl", - "llvm.ve.vl.vfmsbd.vvsvmvl" => "__builtin_ve_vl_vfmsbd_vvsvmvl", - "llvm.ve.vl.vfmsbd.vvsvvl" => "__builtin_ve_vl_vfmsbd_vvsvvl", - "llvm.ve.vl.vfmsbd.vvvvl" => "__builtin_ve_vl_vfmsbd_vvvvl", - "llvm.ve.vl.vfmsbd.vvvvmvl" => "__builtin_ve_vl_vfmsbd_vvvvmvl", - "llvm.ve.vl.vfmsbd.vvvvvl" => "__builtin_ve_vl_vfmsbd_vvvvvl", - "llvm.ve.vl.vfmsbs.vsvvl" => "__builtin_ve_vl_vfmsbs_vsvvl", - "llvm.ve.vl.vfmsbs.vsvvmvl" => "__builtin_ve_vl_vfmsbs_vsvvmvl", - "llvm.ve.vl.vfmsbs.vsvvvl" => "__builtin_ve_vl_vfmsbs_vsvvvl", - "llvm.ve.vl.vfmsbs.vvsvl" => "__builtin_ve_vl_vfmsbs_vvsvl", - "llvm.ve.vl.vfmsbs.vvsvmvl" => "__builtin_ve_vl_vfmsbs_vvsvmvl", - "llvm.ve.vl.vfmsbs.vvsvvl" => "__builtin_ve_vl_vfmsbs_vvsvvl", - "llvm.ve.vl.vfmsbs.vvvvl" => "__builtin_ve_vl_vfmsbs_vvvvl", - "llvm.ve.vl.vfmsbs.vvvvmvl" => "__builtin_ve_vl_vfmsbs_vvvvmvl", - "llvm.ve.vl.vfmsbs.vvvvvl" => "__builtin_ve_vl_vfmsbs_vvvvvl", - "llvm.ve.vl.vfmuld.vsvl" => "__builtin_ve_vl_vfmuld_vsvl", - "llvm.ve.vl.vfmuld.vsvmvl" => "__builtin_ve_vl_vfmuld_vsvmvl", - "llvm.ve.vl.vfmuld.vsvvl" => "__builtin_ve_vl_vfmuld_vsvvl", - "llvm.ve.vl.vfmuld.vvvl" => "__builtin_ve_vl_vfmuld_vvvl", - "llvm.ve.vl.vfmuld.vvvmvl" => "__builtin_ve_vl_vfmuld_vvvmvl", - "llvm.ve.vl.vfmuld.vvvvl" => "__builtin_ve_vl_vfmuld_vvvvl", - "llvm.ve.vl.vfmuls.vsvl" => "__builtin_ve_vl_vfmuls_vsvl", - "llvm.ve.vl.vfmuls.vsvmvl" => "__builtin_ve_vl_vfmuls_vsvmvl", - "llvm.ve.vl.vfmuls.vsvvl" => "__builtin_ve_vl_vfmuls_vsvvl", - "llvm.ve.vl.vfmuls.vvvl" => "__builtin_ve_vl_vfmuls_vvvl", - "llvm.ve.vl.vfmuls.vvvmvl" => "__builtin_ve_vl_vfmuls_vvvmvl", - "llvm.ve.vl.vfmuls.vvvvl" => "__builtin_ve_vl_vfmuls_vvvvl", - "llvm.ve.vl.vfnmadd.vsvvl" => "__builtin_ve_vl_vfnmadd_vsvvl", - "llvm.ve.vl.vfnmadd.vsvvmvl" => "__builtin_ve_vl_vfnmadd_vsvvmvl", - "llvm.ve.vl.vfnmadd.vsvvvl" => "__builtin_ve_vl_vfnmadd_vsvvvl", - "llvm.ve.vl.vfnmadd.vvsvl" => "__builtin_ve_vl_vfnmadd_vvsvl", - "llvm.ve.vl.vfnmadd.vvsvmvl" => "__builtin_ve_vl_vfnmadd_vvsvmvl", - "llvm.ve.vl.vfnmadd.vvsvvl" => "__builtin_ve_vl_vfnmadd_vvsvvl", - "llvm.ve.vl.vfnmadd.vvvvl" => "__builtin_ve_vl_vfnmadd_vvvvl", - "llvm.ve.vl.vfnmadd.vvvvmvl" => "__builtin_ve_vl_vfnmadd_vvvvmvl", - "llvm.ve.vl.vfnmadd.vvvvvl" => "__builtin_ve_vl_vfnmadd_vvvvvl", - "llvm.ve.vl.vfnmads.vsvvl" => "__builtin_ve_vl_vfnmads_vsvvl", - "llvm.ve.vl.vfnmads.vsvvmvl" => "__builtin_ve_vl_vfnmads_vsvvmvl", - "llvm.ve.vl.vfnmads.vsvvvl" => "__builtin_ve_vl_vfnmads_vsvvvl", - "llvm.ve.vl.vfnmads.vvsvl" => "__builtin_ve_vl_vfnmads_vvsvl", - "llvm.ve.vl.vfnmads.vvsvmvl" => "__builtin_ve_vl_vfnmads_vvsvmvl", - "llvm.ve.vl.vfnmads.vvsvvl" => "__builtin_ve_vl_vfnmads_vvsvvl", - "llvm.ve.vl.vfnmads.vvvvl" => "__builtin_ve_vl_vfnmads_vvvvl", - "llvm.ve.vl.vfnmads.vvvvmvl" => "__builtin_ve_vl_vfnmads_vvvvmvl", - "llvm.ve.vl.vfnmads.vvvvvl" => "__builtin_ve_vl_vfnmads_vvvvvl", - "llvm.ve.vl.vfnmsbd.vsvvl" => "__builtin_ve_vl_vfnmsbd_vsvvl", - "llvm.ve.vl.vfnmsbd.vsvvmvl" => "__builtin_ve_vl_vfnmsbd_vsvvmvl", - "llvm.ve.vl.vfnmsbd.vsvvvl" => "__builtin_ve_vl_vfnmsbd_vsvvvl", - "llvm.ve.vl.vfnmsbd.vvsvl" => "__builtin_ve_vl_vfnmsbd_vvsvl", - "llvm.ve.vl.vfnmsbd.vvsvmvl" => "__builtin_ve_vl_vfnmsbd_vvsvmvl", - "llvm.ve.vl.vfnmsbd.vvsvvl" => "__builtin_ve_vl_vfnmsbd_vvsvvl", - "llvm.ve.vl.vfnmsbd.vvvvl" => "__builtin_ve_vl_vfnmsbd_vvvvl", - "llvm.ve.vl.vfnmsbd.vvvvmvl" => "__builtin_ve_vl_vfnmsbd_vvvvmvl", - "llvm.ve.vl.vfnmsbd.vvvvvl" => "__builtin_ve_vl_vfnmsbd_vvvvvl", - "llvm.ve.vl.vfnmsbs.vsvvl" => "__builtin_ve_vl_vfnmsbs_vsvvl", - "llvm.ve.vl.vfnmsbs.vsvvmvl" => "__builtin_ve_vl_vfnmsbs_vsvvmvl", - "llvm.ve.vl.vfnmsbs.vsvvvl" => "__builtin_ve_vl_vfnmsbs_vsvvvl", - "llvm.ve.vl.vfnmsbs.vvsvl" => "__builtin_ve_vl_vfnmsbs_vvsvl", - "llvm.ve.vl.vfnmsbs.vvsvmvl" => "__builtin_ve_vl_vfnmsbs_vvsvmvl", - "llvm.ve.vl.vfnmsbs.vvsvvl" => "__builtin_ve_vl_vfnmsbs_vvsvvl", - "llvm.ve.vl.vfnmsbs.vvvvl" => "__builtin_ve_vl_vfnmsbs_vvvvl", - "llvm.ve.vl.vfnmsbs.vvvvmvl" => "__builtin_ve_vl_vfnmsbs_vvvvmvl", - "llvm.ve.vl.vfnmsbs.vvvvvl" => "__builtin_ve_vl_vfnmsbs_vvvvvl", - "llvm.ve.vl.vfrmaxdfst.vvl" => "__builtin_ve_vl_vfrmaxdfst_vvl", - "llvm.ve.vl.vfrmaxdfst.vvvl" => "__builtin_ve_vl_vfrmaxdfst_vvvl", - "llvm.ve.vl.vfrmaxdlst.vvl" => "__builtin_ve_vl_vfrmaxdlst_vvl", - "llvm.ve.vl.vfrmaxdlst.vvvl" => "__builtin_ve_vl_vfrmaxdlst_vvvl", - "llvm.ve.vl.vfrmaxsfst.vvl" => "__builtin_ve_vl_vfrmaxsfst_vvl", - "llvm.ve.vl.vfrmaxsfst.vvvl" => "__builtin_ve_vl_vfrmaxsfst_vvvl", - "llvm.ve.vl.vfrmaxslst.vvl" => "__builtin_ve_vl_vfrmaxslst_vvl", - "llvm.ve.vl.vfrmaxslst.vvvl" => "__builtin_ve_vl_vfrmaxslst_vvvl", - "llvm.ve.vl.vfrmindfst.vvl" => "__builtin_ve_vl_vfrmindfst_vvl", - "llvm.ve.vl.vfrmindfst.vvvl" => "__builtin_ve_vl_vfrmindfst_vvvl", - "llvm.ve.vl.vfrmindlst.vvl" => "__builtin_ve_vl_vfrmindlst_vvl", - "llvm.ve.vl.vfrmindlst.vvvl" => "__builtin_ve_vl_vfrmindlst_vvvl", - "llvm.ve.vl.vfrminsfst.vvl" => "__builtin_ve_vl_vfrminsfst_vvl", - "llvm.ve.vl.vfrminsfst.vvvl" => "__builtin_ve_vl_vfrminsfst_vvvl", - "llvm.ve.vl.vfrminslst.vvl" => "__builtin_ve_vl_vfrminslst_vvl", - "llvm.ve.vl.vfrminslst.vvvl" => "__builtin_ve_vl_vfrminslst_vvvl", - "llvm.ve.vl.vfsqrtd.vvl" => "__builtin_ve_vl_vfsqrtd_vvl", - "llvm.ve.vl.vfsqrtd.vvvl" => "__builtin_ve_vl_vfsqrtd_vvvl", - "llvm.ve.vl.vfsqrts.vvl" => "__builtin_ve_vl_vfsqrts_vvl", - "llvm.ve.vl.vfsqrts.vvvl" => "__builtin_ve_vl_vfsqrts_vvvl", - "llvm.ve.vl.vfsubd.vsvl" => "__builtin_ve_vl_vfsubd_vsvl", - "llvm.ve.vl.vfsubd.vsvmvl" => "__builtin_ve_vl_vfsubd_vsvmvl", - "llvm.ve.vl.vfsubd.vsvvl" => "__builtin_ve_vl_vfsubd_vsvvl", - "llvm.ve.vl.vfsubd.vvvl" => "__builtin_ve_vl_vfsubd_vvvl", - "llvm.ve.vl.vfsubd.vvvmvl" => "__builtin_ve_vl_vfsubd_vvvmvl", - "llvm.ve.vl.vfsubd.vvvvl" => "__builtin_ve_vl_vfsubd_vvvvl", - "llvm.ve.vl.vfsubs.vsvl" => "__builtin_ve_vl_vfsubs_vsvl", - "llvm.ve.vl.vfsubs.vsvmvl" => "__builtin_ve_vl_vfsubs_vsvmvl", - "llvm.ve.vl.vfsubs.vsvvl" => "__builtin_ve_vl_vfsubs_vsvvl", - "llvm.ve.vl.vfsubs.vvvl" => "__builtin_ve_vl_vfsubs_vvvl", - "llvm.ve.vl.vfsubs.vvvmvl" => "__builtin_ve_vl_vfsubs_vvvmvl", - "llvm.ve.vl.vfsubs.vvvvl" => "__builtin_ve_vl_vfsubs_vvvvl", - "llvm.ve.vl.vfsumd.vvl" => "__builtin_ve_vl_vfsumd_vvl", - "llvm.ve.vl.vfsumd.vvml" => "__builtin_ve_vl_vfsumd_vvml", - "llvm.ve.vl.vfsums.vvl" => "__builtin_ve_vl_vfsums_vvl", - "llvm.ve.vl.vfsums.vvml" => "__builtin_ve_vl_vfsums_vvml", - "llvm.ve.vl.vgt.vvssl" => "__builtin_ve_vl_vgt_vvssl", - "llvm.ve.vl.vgt.vvssml" => "__builtin_ve_vl_vgt_vvssml", - "llvm.ve.vl.vgt.vvssmvl" => "__builtin_ve_vl_vgt_vvssmvl", - "llvm.ve.vl.vgt.vvssvl" => "__builtin_ve_vl_vgt_vvssvl", - "llvm.ve.vl.vgtlsx.vvssl" => "__builtin_ve_vl_vgtlsx_vvssl", - "llvm.ve.vl.vgtlsx.vvssml" => "__builtin_ve_vl_vgtlsx_vvssml", - "llvm.ve.vl.vgtlsx.vvssmvl" => "__builtin_ve_vl_vgtlsx_vvssmvl", - "llvm.ve.vl.vgtlsx.vvssvl" => "__builtin_ve_vl_vgtlsx_vvssvl", - "llvm.ve.vl.vgtlsxnc.vvssl" => "__builtin_ve_vl_vgtlsxnc_vvssl", - "llvm.ve.vl.vgtlsxnc.vvssml" => "__builtin_ve_vl_vgtlsxnc_vvssml", - "llvm.ve.vl.vgtlsxnc.vvssmvl" => "__builtin_ve_vl_vgtlsxnc_vvssmvl", - "llvm.ve.vl.vgtlsxnc.vvssvl" => "__builtin_ve_vl_vgtlsxnc_vvssvl", - "llvm.ve.vl.vgtlzx.vvssl" => "__builtin_ve_vl_vgtlzx_vvssl", - "llvm.ve.vl.vgtlzx.vvssml" => "__builtin_ve_vl_vgtlzx_vvssml", - "llvm.ve.vl.vgtlzx.vvssmvl" => "__builtin_ve_vl_vgtlzx_vvssmvl", - "llvm.ve.vl.vgtlzx.vvssvl" => "__builtin_ve_vl_vgtlzx_vvssvl", - "llvm.ve.vl.vgtlzxnc.vvssl" => "__builtin_ve_vl_vgtlzxnc_vvssl", - "llvm.ve.vl.vgtlzxnc.vvssml" => "__builtin_ve_vl_vgtlzxnc_vvssml", - "llvm.ve.vl.vgtlzxnc.vvssmvl" => "__builtin_ve_vl_vgtlzxnc_vvssmvl", - "llvm.ve.vl.vgtlzxnc.vvssvl" => "__builtin_ve_vl_vgtlzxnc_vvssvl", - "llvm.ve.vl.vgtnc.vvssl" => "__builtin_ve_vl_vgtnc_vvssl", - "llvm.ve.vl.vgtnc.vvssml" => "__builtin_ve_vl_vgtnc_vvssml", - "llvm.ve.vl.vgtnc.vvssmvl" => "__builtin_ve_vl_vgtnc_vvssmvl", - "llvm.ve.vl.vgtnc.vvssvl" => "__builtin_ve_vl_vgtnc_vvssvl", - "llvm.ve.vl.vgtu.vvssl" => "__builtin_ve_vl_vgtu_vvssl", - "llvm.ve.vl.vgtu.vvssml" => "__builtin_ve_vl_vgtu_vvssml", - "llvm.ve.vl.vgtu.vvssmvl" => "__builtin_ve_vl_vgtu_vvssmvl", - "llvm.ve.vl.vgtu.vvssvl" => "__builtin_ve_vl_vgtu_vvssvl", - "llvm.ve.vl.vgtunc.vvssl" => "__builtin_ve_vl_vgtunc_vvssl", - "llvm.ve.vl.vgtunc.vvssml" => "__builtin_ve_vl_vgtunc_vvssml", - "llvm.ve.vl.vgtunc.vvssmvl" => "__builtin_ve_vl_vgtunc_vvssmvl", - "llvm.ve.vl.vgtunc.vvssvl" => "__builtin_ve_vl_vgtunc_vvssvl", - "llvm.ve.vl.vld.vssl" => "__builtin_ve_vl_vld_vssl", - "llvm.ve.vl.vld.vssvl" => "__builtin_ve_vl_vld_vssvl", - "llvm.ve.vl.vld2d.vssl" => "__builtin_ve_vl_vld2d_vssl", - "llvm.ve.vl.vld2d.vssvl" => "__builtin_ve_vl_vld2d_vssvl", - "llvm.ve.vl.vld2dnc.vssl" => "__builtin_ve_vl_vld2dnc_vssl", - "llvm.ve.vl.vld2dnc.vssvl" => "__builtin_ve_vl_vld2dnc_vssvl", - "llvm.ve.vl.vldl2dsx.vssl" => "__builtin_ve_vl_vldl2dsx_vssl", - "llvm.ve.vl.vldl2dsx.vssvl" => "__builtin_ve_vl_vldl2dsx_vssvl", - "llvm.ve.vl.vldl2dsxnc.vssl" => "__builtin_ve_vl_vldl2dsxnc_vssl", - "llvm.ve.vl.vldl2dsxnc.vssvl" => "__builtin_ve_vl_vldl2dsxnc_vssvl", - "llvm.ve.vl.vldl2dzx.vssl" => "__builtin_ve_vl_vldl2dzx_vssl", - "llvm.ve.vl.vldl2dzx.vssvl" => "__builtin_ve_vl_vldl2dzx_vssvl", - "llvm.ve.vl.vldl2dzxnc.vssl" => "__builtin_ve_vl_vldl2dzxnc_vssl", - "llvm.ve.vl.vldl2dzxnc.vssvl" => "__builtin_ve_vl_vldl2dzxnc_vssvl", - "llvm.ve.vl.vldlsx.vssl" => "__builtin_ve_vl_vldlsx_vssl", - "llvm.ve.vl.vldlsx.vssvl" => "__builtin_ve_vl_vldlsx_vssvl", - "llvm.ve.vl.vldlsxnc.vssl" => "__builtin_ve_vl_vldlsxnc_vssl", - "llvm.ve.vl.vldlsxnc.vssvl" => "__builtin_ve_vl_vldlsxnc_vssvl", - "llvm.ve.vl.vldlzx.vssl" => "__builtin_ve_vl_vldlzx_vssl", - "llvm.ve.vl.vldlzx.vssvl" => "__builtin_ve_vl_vldlzx_vssvl", - "llvm.ve.vl.vldlzxnc.vssl" => "__builtin_ve_vl_vldlzxnc_vssl", - "llvm.ve.vl.vldlzxnc.vssvl" => "__builtin_ve_vl_vldlzxnc_vssvl", - "llvm.ve.vl.vldnc.vssl" => "__builtin_ve_vl_vldnc_vssl", - "llvm.ve.vl.vldnc.vssvl" => "__builtin_ve_vl_vldnc_vssvl", - "llvm.ve.vl.vldu.vssl" => "__builtin_ve_vl_vldu_vssl", - "llvm.ve.vl.vldu.vssvl" => "__builtin_ve_vl_vldu_vssvl", - "llvm.ve.vl.vldu2d.vssl" => "__builtin_ve_vl_vldu2d_vssl", - "llvm.ve.vl.vldu2d.vssvl" => "__builtin_ve_vl_vldu2d_vssvl", - "llvm.ve.vl.vldu2dnc.vssl" => "__builtin_ve_vl_vldu2dnc_vssl", - "llvm.ve.vl.vldu2dnc.vssvl" => "__builtin_ve_vl_vldu2dnc_vssvl", - "llvm.ve.vl.vldunc.vssl" => "__builtin_ve_vl_vldunc_vssl", - "llvm.ve.vl.vldunc.vssvl" => "__builtin_ve_vl_vldunc_vssvl", - "llvm.ve.vl.vldz.vvl" => "__builtin_ve_vl_vldz_vvl", - "llvm.ve.vl.vldz.vvmvl" => "__builtin_ve_vl_vldz_vvmvl", - "llvm.ve.vl.vldz.vvvl" => "__builtin_ve_vl_vldz_vvvl", - "llvm.ve.vl.vmaxsl.vsvl" => "__builtin_ve_vl_vmaxsl_vsvl", - "llvm.ve.vl.vmaxsl.vsvmvl" => "__builtin_ve_vl_vmaxsl_vsvmvl", - "llvm.ve.vl.vmaxsl.vsvvl" => "__builtin_ve_vl_vmaxsl_vsvvl", - "llvm.ve.vl.vmaxsl.vvvl" => "__builtin_ve_vl_vmaxsl_vvvl", - "llvm.ve.vl.vmaxsl.vvvmvl" => "__builtin_ve_vl_vmaxsl_vvvmvl", - "llvm.ve.vl.vmaxsl.vvvvl" => "__builtin_ve_vl_vmaxsl_vvvvl", - "llvm.ve.vl.vmaxswsx.vsvl" => "__builtin_ve_vl_vmaxswsx_vsvl", - "llvm.ve.vl.vmaxswsx.vsvmvl" => "__builtin_ve_vl_vmaxswsx_vsvmvl", - "llvm.ve.vl.vmaxswsx.vsvvl" => "__builtin_ve_vl_vmaxswsx_vsvvl", - "llvm.ve.vl.vmaxswsx.vvvl" => "__builtin_ve_vl_vmaxswsx_vvvl", - "llvm.ve.vl.vmaxswsx.vvvmvl" => "__builtin_ve_vl_vmaxswsx_vvvmvl", - "llvm.ve.vl.vmaxswsx.vvvvl" => "__builtin_ve_vl_vmaxswsx_vvvvl", - "llvm.ve.vl.vmaxswzx.vsvl" => "__builtin_ve_vl_vmaxswzx_vsvl", - "llvm.ve.vl.vmaxswzx.vsvmvl" => "__builtin_ve_vl_vmaxswzx_vsvmvl", - "llvm.ve.vl.vmaxswzx.vsvvl" => "__builtin_ve_vl_vmaxswzx_vsvvl", - "llvm.ve.vl.vmaxswzx.vvvl" => "__builtin_ve_vl_vmaxswzx_vvvl", - "llvm.ve.vl.vmaxswzx.vvvmvl" => "__builtin_ve_vl_vmaxswzx_vvvmvl", - "llvm.ve.vl.vmaxswzx.vvvvl" => "__builtin_ve_vl_vmaxswzx_vvvvl", - "llvm.ve.vl.vminsl.vsvl" => "__builtin_ve_vl_vminsl_vsvl", - "llvm.ve.vl.vminsl.vsvmvl" => "__builtin_ve_vl_vminsl_vsvmvl", - "llvm.ve.vl.vminsl.vsvvl" => "__builtin_ve_vl_vminsl_vsvvl", - "llvm.ve.vl.vminsl.vvvl" => "__builtin_ve_vl_vminsl_vvvl", - "llvm.ve.vl.vminsl.vvvmvl" => "__builtin_ve_vl_vminsl_vvvmvl", - "llvm.ve.vl.vminsl.vvvvl" => "__builtin_ve_vl_vminsl_vvvvl", - "llvm.ve.vl.vminswsx.vsvl" => "__builtin_ve_vl_vminswsx_vsvl", - "llvm.ve.vl.vminswsx.vsvmvl" => "__builtin_ve_vl_vminswsx_vsvmvl", - "llvm.ve.vl.vminswsx.vsvvl" => "__builtin_ve_vl_vminswsx_vsvvl", - "llvm.ve.vl.vminswsx.vvvl" => "__builtin_ve_vl_vminswsx_vvvl", - "llvm.ve.vl.vminswsx.vvvmvl" => "__builtin_ve_vl_vminswsx_vvvmvl", - "llvm.ve.vl.vminswsx.vvvvl" => "__builtin_ve_vl_vminswsx_vvvvl", - "llvm.ve.vl.vminswzx.vsvl" => "__builtin_ve_vl_vminswzx_vsvl", - "llvm.ve.vl.vminswzx.vsvmvl" => "__builtin_ve_vl_vminswzx_vsvmvl", - "llvm.ve.vl.vminswzx.vsvvl" => "__builtin_ve_vl_vminswzx_vsvvl", - "llvm.ve.vl.vminswzx.vvvl" => "__builtin_ve_vl_vminswzx_vvvl", - "llvm.ve.vl.vminswzx.vvvmvl" => "__builtin_ve_vl_vminswzx_vvvmvl", - "llvm.ve.vl.vminswzx.vvvvl" => "__builtin_ve_vl_vminswzx_vvvvl", - "llvm.ve.vl.vmrg.vsvml" => "__builtin_ve_vl_vmrg_vsvml", - "llvm.ve.vl.vmrg.vsvmvl" => "__builtin_ve_vl_vmrg_vsvmvl", - "llvm.ve.vl.vmrg.vvvml" => "__builtin_ve_vl_vmrg_vvvml", - "llvm.ve.vl.vmrg.vvvmvl" => "__builtin_ve_vl_vmrg_vvvmvl", - "llvm.ve.vl.vmrgw.vsvMl" => "__builtin_ve_vl_vmrgw_vsvMl", - "llvm.ve.vl.vmrgw.vsvMvl" => "__builtin_ve_vl_vmrgw_vsvMvl", - "llvm.ve.vl.vmrgw.vvvMl" => "__builtin_ve_vl_vmrgw_vvvMl", - "llvm.ve.vl.vmrgw.vvvMvl" => "__builtin_ve_vl_vmrgw_vvvMvl", - "llvm.ve.vl.vmulsl.vsvl" => "__builtin_ve_vl_vmulsl_vsvl", - "llvm.ve.vl.vmulsl.vsvmvl" => "__builtin_ve_vl_vmulsl_vsvmvl", - "llvm.ve.vl.vmulsl.vsvvl" => "__builtin_ve_vl_vmulsl_vsvvl", - "llvm.ve.vl.vmulsl.vvvl" => "__builtin_ve_vl_vmulsl_vvvl", - "llvm.ve.vl.vmulsl.vvvmvl" => "__builtin_ve_vl_vmulsl_vvvmvl", - "llvm.ve.vl.vmulsl.vvvvl" => "__builtin_ve_vl_vmulsl_vvvvl", - "llvm.ve.vl.vmulslw.vsvl" => "__builtin_ve_vl_vmulslw_vsvl", - "llvm.ve.vl.vmulslw.vsvvl" => "__builtin_ve_vl_vmulslw_vsvvl", - "llvm.ve.vl.vmulslw.vvvl" => "__builtin_ve_vl_vmulslw_vvvl", - "llvm.ve.vl.vmulslw.vvvvl" => "__builtin_ve_vl_vmulslw_vvvvl", - "llvm.ve.vl.vmulswsx.vsvl" => "__builtin_ve_vl_vmulswsx_vsvl", - "llvm.ve.vl.vmulswsx.vsvmvl" => "__builtin_ve_vl_vmulswsx_vsvmvl", - "llvm.ve.vl.vmulswsx.vsvvl" => "__builtin_ve_vl_vmulswsx_vsvvl", - "llvm.ve.vl.vmulswsx.vvvl" => "__builtin_ve_vl_vmulswsx_vvvl", - "llvm.ve.vl.vmulswsx.vvvmvl" => "__builtin_ve_vl_vmulswsx_vvvmvl", - "llvm.ve.vl.vmulswsx.vvvvl" => "__builtin_ve_vl_vmulswsx_vvvvl", - "llvm.ve.vl.vmulswzx.vsvl" => "__builtin_ve_vl_vmulswzx_vsvl", - "llvm.ve.vl.vmulswzx.vsvmvl" => "__builtin_ve_vl_vmulswzx_vsvmvl", - "llvm.ve.vl.vmulswzx.vsvvl" => "__builtin_ve_vl_vmulswzx_vsvvl", - "llvm.ve.vl.vmulswzx.vvvl" => "__builtin_ve_vl_vmulswzx_vvvl", - "llvm.ve.vl.vmulswzx.vvvmvl" => "__builtin_ve_vl_vmulswzx_vvvmvl", - "llvm.ve.vl.vmulswzx.vvvvl" => "__builtin_ve_vl_vmulswzx_vvvvl", - "llvm.ve.vl.vmulul.vsvl" => "__builtin_ve_vl_vmulul_vsvl", - "llvm.ve.vl.vmulul.vsvmvl" => "__builtin_ve_vl_vmulul_vsvmvl", - "llvm.ve.vl.vmulul.vsvvl" => "__builtin_ve_vl_vmulul_vsvvl", - "llvm.ve.vl.vmulul.vvvl" => "__builtin_ve_vl_vmulul_vvvl", - "llvm.ve.vl.vmulul.vvvmvl" => "__builtin_ve_vl_vmulul_vvvmvl", - "llvm.ve.vl.vmulul.vvvvl" => "__builtin_ve_vl_vmulul_vvvvl", - "llvm.ve.vl.vmuluw.vsvl" => "__builtin_ve_vl_vmuluw_vsvl", - "llvm.ve.vl.vmuluw.vsvmvl" => "__builtin_ve_vl_vmuluw_vsvmvl", - "llvm.ve.vl.vmuluw.vsvvl" => "__builtin_ve_vl_vmuluw_vsvvl", - "llvm.ve.vl.vmuluw.vvvl" => "__builtin_ve_vl_vmuluw_vvvl", - "llvm.ve.vl.vmuluw.vvvmvl" => "__builtin_ve_vl_vmuluw_vvvmvl", - "llvm.ve.vl.vmuluw.vvvvl" => "__builtin_ve_vl_vmuluw_vvvvl", - "llvm.ve.vl.vmv.vsvl" => "__builtin_ve_vl_vmv_vsvl", - "llvm.ve.vl.vmv.vsvmvl" => "__builtin_ve_vl_vmv_vsvmvl", - "llvm.ve.vl.vmv.vsvvl" => "__builtin_ve_vl_vmv_vsvvl", - "llvm.ve.vl.vor.vsvl" => "__builtin_ve_vl_vor_vsvl", - "llvm.ve.vl.vor.vsvmvl" => "__builtin_ve_vl_vor_vsvmvl", - "llvm.ve.vl.vor.vsvvl" => "__builtin_ve_vl_vor_vsvvl", - "llvm.ve.vl.vor.vvvl" => "__builtin_ve_vl_vor_vvvl", - "llvm.ve.vl.vor.vvvmvl" => "__builtin_ve_vl_vor_vvvmvl", - "llvm.ve.vl.vor.vvvvl" => "__builtin_ve_vl_vor_vvvvl", - "llvm.ve.vl.vpcnt.vvl" => "__builtin_ve_vl_vpcnt_vvl", - "llvm.ve.vl.vpcnt.vvmvl" => "__builtin_ve_vl_vpcnt_vvmvl", - "llvm.ve.vl.vpcnt.vvvl" => "__builtin_ve_vl_vpcnt_vvvl", - "llvm.ve.vl.vrand.vvl" => "__builtin_ve_vl_vrand_vvl", - "llvm.ve.vl.vrand.vvml" => "__builtin_ve_vl_vrand_vvml", - "llvm.ve.vl.vrcpd.vvl" => "__builtin_ve_vl_vrcpd_vvl", - "llvm.ve.vl.vrcpd.vvvl" => "__builtin_ve_vl_vrcpd_vvvl", - "llvm.ve.vl.vrcps.vvl" => "__builtin_ve_vl_vrcps_vvl", - "llvm.ve.vl.vrcps.vvvl" => "__builtin_ve_vl_vrcps_vvvl", - "llvm.ve.vl.vrmaxslfst.vvl" => "__builtin_ve_vl_vrmaxslfst_vvl", - "llvm.ve.vl.vrmaxslfst.vvvl" => "__builtin_ve_vl_vrmaxslfst_vvvl", - "llvm.ve.vl.vrmaxsllst.vvl" => "__builtin_ve_vl_vrmaxsllst_vvl", - "llvm.ve.vl.vrmaxsllst.vvvl" => "__builtin_ve_vl_vrmaxsllst_vvvl", - "llvm.ve.vl.vrmaxswfstsx.vvl" => "__builtin_ve_vl_vrmaxswfstsx_vvl", - "llvm.ve.vl.vrmaxswfstsx.vvvl" => "__builtin_ve_vl_vrmaxswfstsx_vvvl", - "llvm.ve.vl.vrmaxswfstzx.vvl" => "__builtin_ve_vl_vrmaxswfstzx_vvl", - "llvm.ve.vl.vrmaxswfstzx.vvvl" => "__builtin_ve_vl_vrmaxswfstzx_vvvl", - "llvm.ve.vl.vrmaxswlstsx.vvl" => "__builtin_ve_vl_vrmaxswlstsx_vvl", - "llvm.ve.vl.vrmaxswlstsx.vvvl" => "__builtin_ve_vl_vrmaxswlstsx_vvvl", - "llvm.ve.vl.vrmaxswlstzx.vvl" => "__builtin_ve_vl_vrmaxswlstzx_vvl", - "llvm.ve.vl.vrmaxswlstzx.vvvl" => "__builtin_ve_vl_vrmaxswlstzx_vvvl", - "llvm.ve.vl.vrminslfst.vvl" => "__builtin_ve_vl_vrminslfst_vvl", - "llvm.ve.vl.vrminslfst.vvvl" => "__builtin_ve_vl_vrminslfst_vvvl", - "llvm.ve.vl.vrminsllst.vvl" => "__builtin_ve_vl_vrminsllst_vvl", - "llvm.ve.vl.vrminsllst.vvvl" => "__builtin_ve_vl_vrminsllst_vvvl", - "llvm.ve.vl.vrminswfstsx.vvl" => "__builtin_ve_vl_vrminswfstsx_vvl", - "llvm.ve.vl.vrminswfstsx.vvvl" => "__builtin_ve_vl_vrminswfstsx_vvvl", - "llvm.ve.vl.vrminswfstzx.vvl" => "__builtin_ve_vl_vrminswfstzx_vvl", - "llvm.ve.vl.vrminswfstzx.vvvl" => "__builtin_ve_vl_vrminswfstzx_vvvl", - "llvm.ve.vl.vrminswlstsx.vvl" => "__builtin_ve_vl_vrminswlstsx_vvl", - "llvm.ve.vl.vrminswlstsx.vvvl" => "__builtin_ve_vl_vrminswlstsx_vvvl", - "llvm.ve.vl.vrminswlstzx.vvl" => "__builtin_ve_vl_vrminswlstzx_vvl", - "llvm.ve.vl.vrminswlstzx.vvvl" => "__builtin_ve_vl_vrminswlstzx_vvvl", - "llvm.ve.vl.vror.vvl" => "__builtin_ve_vl_vror_vvl", - "llvm.ve.vl.vror.vvml" => "__builtin_ve_vl_vror_vvml", - "llvm.ve.vl.vrsqrtd.vvl" => "__builtin_ve_vl_vrsqrtd_vvl", - "llvm.ve.vl.vrsqrtd.vvvl" => "__builtin_ve_vl_vrsqrtd_vvvl", - "llvm.ve.vl.vrsqrtdnex.vvl" => "__builtin_ve_vl_vrsqrtdnex_vvl", - "llvm.ve.vl.vrsqrtdnex.vvvl" => "__builtin_ve_vl_vrsqrtdnex_vvvl", - "llvm.ve.vl.vrsqrts.vvl" => "__builtin_ve_vl_vrsqrts_vvl", - "llvm.ve.vl.vrsqrts.vvvl" => "__builtin_ve_vl_vrsqrts_vvvl", - "llvm.ve.vl.vrsqrtsnex.vvl" => "__builtin_ve_vl_vrsqrtsnex_vvl", - "llvm.ve.vl.vrsqrtsnex.vvvl" => "__builtin_ve_vl_vrsqrtsnex_vvvl", - "llvm.ve.vl.vrxor.vvl" => "__builtin_ve_vl_vrxor_vvl", - "llvm.ve.vl.vrxor.vvml" => "__builtin_ve_vl_vrxor_vvml", - "llvm.ve.vl.vsc.vvssl" => "__builtin_ve_vl_vsc_vvssl", - "llvm.ve.vl.vsc.vvssml" => "__builtin_ve_vl_vsc_vvssml", - "llvm.ve.vl.vscl.vvssl" => "__builtin_ve_vl_vscl_vvssl", - "llvm.ve.vl.vscl.vvssml" => "__builtin_ve_vl_vscl_vvssml", - "llvm.ve.vl.vsclnc.vvssl" => "__builtin_ve_vl_vsclnc_vvssl", - "llvm.ve.vl.vsclnc.vvssml" => "__builtin_ve_vl_vsclnc_vvssml", - "llvm.ve.vl.vsclncot.vvssl" => "__builtin_ve_vl_vsclncot_vvssl", - "llvm.ve.vl.vsclncot.vvssml" => "__builtin_ve_vl_vsclncot_vvssml", - "llvm.ve.vl.vsclot.vvssl" => "__builtin_ve_vl_vsclot_vvssl", - "llvm.ve.vl.vsclot.vvssml" => "__builtin_ve_vl_vsclot_vvssml", - "llvm.ve.vl.vscnc.vvssl" => "__builtin_ve_vl_vscnc_vvssl", - "llvm.ve.vl.vscnc.vvssml" => "__builtin_ve_vl_vscnc_vvssml", - "llvm.ve.vl.vscncot.vvssl" => "__builtin_ve_vl_vscncot_vvssl", - "llvm.ve.vl.vscncot.vvssml" => "__builtin_ve_vl_vscncot_vvssml", - "llvm.ve.vl.vscot.vvssl" => "__builtin_ve_vl_vscot_vvssl", - "llvm.ve.vl.vscot.vvssml" => "__builtin_ve_vl_vscot_vvssml", - "llvm.ve.vl.vscu.vvssl" => "__builtin_ve_vl_vscu_vvssl", - "llvm.ve.vl.vscu.vvssml" => "__builtin_ve_vl_vscu_vvssml", - "llvm.ve.vl.vscunc.vvssl" => "__builtin_ve_vl_vscunc_vvssl", - "llvm.ve.vl.vscunc.vvssml" => "__builtin_ve_vl_vscunc_vvssml", - "llvm.ve.vl.vscuncot.vvssl" => "__builtin_ve_vl_vscuncot_vvssl", - "llvm.ve.vl.vscuncot.vvssml" => "__builtin_ve_vl_vscuncot_vvssml", - "llvm.ve.vl.vscuot.vvssl" => "__builtin_ve_vl_vscuot_vvssl", - "llvm.ve.vl.vscuot.vvssml" => "__builtin_ve_vl_vscuot_vvssml", - "llvm.ve.vl.vseq.vl" => "__builtin_ve_vl_vseq_vl", - "llvm.ve.vl.vseq.vvl" => "__builtin_ve_vl_vseq_vvl", - "llvm.ve.vl.vsfa.vvssl" => "__builtin_ve_vl_vsfa_vvssl", - "llvm.ve.vl.vsfa.vvssmvl" => "__builtin_ve_vl_vsfa_vvssmvl", - "llvm.ve.vl.vsfa.vvssvl" => "__builtin_ve_vl_vsfa_vvssvl", - "llvm.ve.vl.vshf.vvvsl" => "__builtin_ve_vl_vshf_vvvsl", - "llvm.ve.vl.vshf.vvvsvl" => "__builtin_ve_vl_vshf_vvvsvl", - "llvm.ve.vl.vslal.vvsl" => "__builtin_ve_vl_vslal_vvsl", - "llvm.ve.vl.vslal.vvsmvl" => "__builtin_ve_vl_vslal_vvsmvl", - "llvm.ve.vl.vslal.vvsvl" => "__builtin_ve_vl_vslal_vvsvl", - "llvm.ve.vl.vslal.vvvl" => "__builtin_ve_vl_vslal_vvvl", - "llvm.ve.vl.vslal.vvvmvl" => "__builtin_ve_vl_vslal_vvvmvl", - "llvm.ve.vl.vslal.vvvvl" => "__builtin_ve_vl_vslal_vvvvl", - "llvm.ve.vl.vslawsx.vvsl" => "__builtin_ve_vl_vslawsx_vvsl", - "llvm.ve.vl.vslawsx.vvsmvl" => "__builtin_ve_vl_vslawsx_vvsmvl", - "llvm.ve.vl.vslawsx.vvsvl" => "__builtin_ve_vl_vslawsx_vvsvl", - "llvm.ve.vl.vslawsx.vvvl" => "__builtin_ve_vl_vslawsx_vvvl", - "llvm.ve.vl.vslawsx.vvvmvl" => "__builtin_ve_vl_vslawsx_vvvmvl", - "llvm.ve.vl.vslawsx.vvvvl" => "__builtin_ve_vl_vslawsx_vvvvl", - "llvm.ve.vl.vslawzx.vvsl" => "__builtin_ve_vl_vslawzx_vvsl", - "llvm.ve.vl.vslawzx.vvsmvl" => "__builtin_ve_vl_vslawzx_vvsmvl", - "llvm.ve.vl.vslawzx.vvsvl" => "__builtin_ve_vl_vslawzx_vvsvl", - "llvm.ve.vl.vslawzx.vvvl" => "__builtin_ve_vl_vslawzx_vvvl", - "llvm.ve.vl.vslawzx.vvvmvl" => "__builtin_ve_vl_vslawzx_vvvmvl", - "llvm.ve.vl.vslawzx.vvvvl" => "__builtin_ve_vl_vslawzx_vvvvl", - "llvm.ve.vl.vsll.vvsl" => "__builtin_ve_vl_vsll_vvsl", - "llvm.ve.vl.vsll.vvsmvl" => "__builtin_ve_vl_vsll_vvsmvl", - "llvm.ve.vl.vsll.vvsvl" => "__builtin_ve_vl_vsll_vvsvl", - "llvm.ve.vl.vsll.vvvl" => "__builtin_ve_vl_vsll_vvvl", - "llvm.ve.vl.vsll.vvvmvl" => "__builtin_ve_vl_vsll_vvvmvl", - "llvm.ve.vl.vsll.vvvvl" => "__builtin_ve_vl_vsll_vvvvl", - "llvm.ve.vl.vsral.vvsl" => "__builtin_ve_vl_vsral_vvsl", - "llvm.ve.vl.vsral.vvsmvl" => "__builtin_ve_vl_vsral_vvsmvl", - "llvm.ve.vl.vsral.vvsvl" => "__builtin_ve_vl_vsral_vvsvl", - "llvm.ve.vl.vsral.vvvl" => "__builtin_ve_vl_vsral_vvvl", - "llvm.ve.vl.vsral.vvvmvl" => "__builtin_ve_vl_vsral_vvvmvl", - "llvm.ve.vl.vsral.vvvvl" => "__builtin_ve_vl_vsral_vvvvl", - "llvm.ve.vl.vsrawsx.vvsl" => "__builtin_ve_vl_vsrawsx_vvsl", - "llvm.ve.vl.vsrawsx.vvsmvl" => "__builtin_ve_vl_vsrawsx_vvsmvl", - "llvm.ve.vl.vsrawsx.vvsvl" => "__builtin_ve_vl_vsrawsx_vvsvl", - "llvm.ve.vl.vsrawsx.vvvl" => "__builtin_ve_vl_vsrawsx_vvvl", - "llvm.ve.vl.vsrawsx.vvvmvl" => "__builtin_ve_vl_vsrawsx_vvvmvl", - "llvm.ve.vl.vsrawsx.vvvvl" => "__builtin_ve_vl_vsrawsx_vvvvl", - "llvm.ve.vl.vsrawzx.vvsl" => "__builtin_ve_vl_vsrawzx_vvsl", - "llvm.ve.vl.vsrawzx.vvsmvl" => "__builtin_ve_vl_vsrawzx_vvsmvl", - "llvm.ve.vl.vsrawzx.vvsvl" => "__builtin_ve_vl_vsrawzx_vvsvl", - "llvm.ve.vl.vsrawzx.vvvl" => "__builtin_ve_vl_vsrawzx_vvvl", - "llvm.ve.vl.vsrawzx.vvvmvl" => "__builtin_ve_vl_vsrawzx_vvvmvl", - "llvm.ve.vl.vsrawzx.vvvvl" => "__builtin_ve_vl_vsrawzx_vvvvl", - "llvm.ve.vl.vsrl.vvsl" => "__builtin_ve_vl_vsrl_vvsl", - "llvm.ve.vl.vsrl.vvsmvl" => "__builtin_ve_vl_vsrl_vvsmvl", - "llvm.ve.vl.vsrl.vvsvl" => "__builtin_ve_vl_vsrl_vvsvl", - "llvm.ve.vl.vsrl.vvvl" => "__builtin_ve_vl_vsrl_vvvl", - "llvm.ve.vl.vsrl.vvvmvl" => "__builtin_ve_vl_vsrl_vvvmvl", - "llvm.ve.vl.vsrl.vvvvl" => "__builtin_ve_vl_vsrl_vvvvl", - "llvm.ve.vl.vst.vssl" => "__builtin_ve_vl_vst_vssl", - "llvm.ve.vl.vst.vssml" => "__builtin_ve_vl_vst_vssml", - "llvm.ve.vl.vst2d.vssl" => "__builtin_ve_vl_vst2d_vssl", - "llvm.ve.vl.vst2d.vssml" => "__builtin_ve_vl_vst2d_vssml", - "llvm.ve.vl.vst2dnc.vssl" => "__builtin_ve_vl_vst2dnc_vssl", - "llvm.ve.vl.vst2dnc.vssml" => "__builtin_ve_vl_vst2dnc_vssml", - "llvm.ve.vl.vst2dncot.vssl" => "__builtin_ve_vl_vst2dncot_vssl", - "llvm.ve.vl.vst2dncot.vssml" => "__builtin_ve_vl_vst2dncot_vssml", - "llvm.ve.vl.vst2dot.vssl" => "__builtin_ve_vl_vst2dot_vssl", - "llvm.ve.vl.vst2dot.vssml" => "__builtin_ve_vl_vst2dot_vssml", - "llvm.ve.vl.vstl.vssl" => "__builtin_ve_vl_vstl_vssl", - "llvm.ve.vl.vstl.vssml" => "__builtin_ve_vl_vstl_vssml", - "llvm.ve.vl.vstl2d.vssl" => "__builtin_ve_vl_vstl2d_vssl", - "llvm.ve.vl.vstl2d.vssml" => "__builtin_ve_vl_vstl2d_vssml", - "llvm.ve.vl.vstl2dnc.vssl" => "__builtin_ve_vl_vstl2dnc_vssl", - "llvm.ve.vl.vstl2dnc.vssml" => "__builtin_ve_vl_vstl2dnc_vssml", - "llvm.ve.vl.vstl2dncot.vssl" => "__builtin_ve_vl_vstl2dncot_vssl", - "llvm.ve.vl.vstl2dncot.vssml" => "__builtin_ve_vl_vstl2dncot_vssml", - "llvm.ve.vl.vstl2dot.vssl" => "__builtin_ve_vl_vstl2dot_vssl", - "llvm.ve.vl.vstl2dot.vssml" => "__builtin_ve_vl_vstl2dot_vssml", - "llvm.ve.vl.vstlnc.vssl" => "__builtin_ve_vl_vstlnc_vssl", - "llvm.ve.vl.vstlnc.vssml" => "__builtin_ve_vl_vstlnc_vssml", - "llvm.ve.vl.vstlncot.vssl" => "__builtin_ve_vl_vstlncot_vssl", - "llvm.ve.vl.vstlncot.vssml" => "__builtin_ve_vl_vstlncot_vssml", - "llvm.ve.vl.vstlot.vssl" => "__builtin_ve_vl_vstlot_vssl", - "llvm.ve.vl.vstlot.vssml" => "__builtin_ve_vl_vstlot_vssml", - "llvm.ve.vl.vstnc.vssl" => "__builtin_ve_vl_vstnc_vssl", - "llvm.ve.vl.vstnc.vssml" => "__builtin_ve_vl_vstnc_vssml", - "llvm.ve.vl.vstncot.vssl" => "__builtin_ve_vl_vstncot_vssl", - "llvm.ve.vl.vstncot.vssml" => "__builtin_ve_vl_vstncot_vssml", - "llvm.ve.vl.vstot.vssl" => "__builtin_ve_vl_vstot_vssl", - "llvm.ve.vl.vstot.vssml" => "__builtin_ve_vl_vstot_vssml", - "llvm.ve.vl.vstu.vssl" => "__builtin_ve_vl_vstu_vssl", - "llvm.ve.vl.vstu.vssml" => "__builtin_ve_vl_vstu_vssml", - "llvm.ve.vl.vstu2d.vssl" => "__builtin_ve_vl_vstu2d_vssl", - "llvm.ve.vl.vstu2d.vssml" => "__builtin_ve_vl_vstu2d_vssml", - "llvm.ve.vl.vstu2dnc.vssl" => "__builtin_ve_vl_vstu2dnc_vssl", - "llvm.ve.vl.vstu2dnc.vssml" => "__builtin_ve_vl_vstu2dnc_vssml", - "llvm.ve.vl.vstu2dncot.vssl" => "__builtin_ve_vl_vstu2dncot_vssl", - "llvm.ve.vl.vstu2dncot.vssml" => "__builtin_ve_vl_vstu2dncot_vssml", - "llvm.ve.vl.vstu2dot.vssl" => "__builtin_ve_vl_vstu2dot_vssl", - "llvm.ve.vl.vstu2dot.vssml" => "__builtin_ve_vl_vstu2dot_vssml", - "llvm.ve.vl.vstunc.vssl" => "__builtin_ve_vl_vstunc_vssl", - "llvm.ve.vl.vstunc.vssml" => "__builtin_ve_vl_vstunc_vssml", - "llvm.ve.vl.vstuncot.vssl" => "__builtin_ve_vl_vstuncot_vssl", - "llvm.ve.vl.vstuncot.vssml" => "__builtin_ve_vl_vstuncot_vssml", - "llvm.ve.vl.vstuot.vssl" => "__builtin_ve_vl_vstuot_vssl", - "llvm.ve.vl.vstuot.vssml" => "__builtin_ve_vl_vstuot_vssml", - "llvm.ve.vl.vsubsl.vsvl" => "__builtin_ve_vl_vsubsl_vsvl", - "llvm.ve.vl.vsubsl.vsvmvl" => "__builtin_ve_vl_vsubsl_vsvmvl", - "llvm.ve.vl.vsubsl.vsvvl" => "__builtin_ve_vl_vsubsl_vsvvl", - "llvm.ve.vl.vsubsl.vvvl" => "__builtin_ve_vl_vsubsl_vvvl", - "llvm.ve.vl.vsubsl.vvvmvl" => "__builtin_ve_vl_vsubsl_vvvmvl", - "llvm.ve.vl.vsubsl.vvvvl" => "__builtin_ve_vl_vsubsl_vvvvl", - "llvm.ve.vl.vsubswsx.vsvl" => "__builtin_ve_vl_vsubswsx_vsvl", - "llvm.ve.vl.vsubswsx.vsvmvl" => "__builtin_ve_vl_vsubswsx_vsvmvl", - "llvm.ve.vl.vsubswsx.vsvvl" => "__builtin_ve_vl_vsubswsx_vsvvl", - "llvm.ve.vl.vsubswsx.vvvl" => "__builtin_ve_vl_vsubswsx_vvvl", - "llvm.ve.vl.vsubswsx.vvvmvl" => "__builtin_ve_vl_vsubswsx_vvvmvl", - "llvm.ve.vl.vsubswsx.vvvvl" => "__builtin_ve_vl_vsubswsx_vvvvl", - "llvm.ve.vl.vsubswzx.vsvl" => "__builtin_ve_vl_vsubswzx_vsvl", - "llvm.ve.vl.vsubswzx.vsvmvl" => "__builtin_ve_vl_vsubswzx_vsvmvl", - "llvm.ve.vl.vsubswzx.vsvvl" => "__builtin_ve_vl_vsubswzx_vsvvl", - "llvm.ve.vl.vsubswzx.vvvl" => "__builtin_ve_vl_vsubswzx_vvvl", - "llvm.ve.vl.vsubswzx.vvvmvl" => "__builtin_ve_vl_vsubswzx_vvvmvl", - "llvm.ve.vl.vsubswzx.vvvvl" => "__builtin_ve_vl_vsubswzx_vvvvl", - "llvm.ve.vl.vsubul.vsvl" => "__builtin_ve_vl_vsubul_vsvl", - "llvm.ve.vl.vsubul.vsvmvl" => "__builtin_ve_vl_vsubul_vsvmvl", - "llvm.ve.vl.vsubul.vsvvl" => "__builtin_ve_vl_vsubul_vsvvl", - "llvm.ve.vl.vsubul.vvvl" => "__builtin_ve_vl_vsubul_vvvl", - "llvm.ve.vl.vsubul.vvvmvl" => "__builtin_ve_vl_vsubul_vvvmvl", - "llvm.ve.vl.vsubul.vvvvl" => "__builtin_ve_vl_vsubul_vvvvl", - "llvm.ve.vl.vsubuw.vsvl" => "__builtin_ve_vl_vsubuw_vsvl", - "llvm.ve.vl.vsubuw.vsvmvl" => "__builtin_ve_vl_vsubuw_vsvmvl", - "llvm.ve.vl.vsubuw.vsvvl" => "__builtin_ve_vl_vsubuw_vsvvl", - "llvm.ve.vl.vsubuw.vvvl" => "__builtin_ve_vl_vsubuw_vvvl", - "llvm.ve.vl.vsubuw.vvvmvl" => "__builtin_ve_vl_vsubuw_vvvmvl", - "llvm.ve.vl.vsubuw.vvvvl" => "__builtin_ve_vl_vsubuw_vvvvl", - "llvm.ve.vl.vsuml.vvl" => "__builtin_ve_vl_vsuml_vvl", - "llvm.ve.vl.vsuml.vvml" => "__builtin_ve_vl_vsuml_vvml", - "llvm.ve.vl.vsumwsx.vvl" => "__builtin_ve_vl_vsumwsx_vvl", - "llvm.ve.vl.vsumwsx.vvml" => "__builtin_ve_vl_vsumwsx_vvml", - "llvm.ve.vl.vsumwzx.vvl" => "__builtin_ve_vl_vsumwzx_vvl", - "llvm.ve.vl.vsumwzx.vvml" => "__builtin_ve_vl_vsumwzx_vvml", - "llvm.ve.vl.vxor.vsvl" => "__builtin_ve_vl_vxor_vsvl", - "llvm.ve.vl.vxor.vsvmvl" => "__builtin_ve_vl_vxor_vsvmvl", - "llvm.ve.vl.vxor.vsvvl" => "__builtin_ve_vl_vxor_vsvvl", - "llvm.ve.vl.vxor.vvvl" => "__builtin_ve_vl_vxor_vvvl", - "llvm.ve.vl.vxor.vvvmvl" => "__builtin_ve_vl_vxor_vvvmvl", - "llvm.ve.vl.vxor.vvvvl" => "__builtin_ve_vl_vxor_vvvvl", - "llvm.ve.vl.xorm.MMM" => "__builtin_ve_vl_xorm_MMM", - "llvm.ve.vl.xorm.mmm" => "__builtin_ve_vl_xorm_mmm", - // x86 - "llvm.x86.aadd32" => "__builtin_ia32_aadd32", - "llvm.x86.aadd64" => "__builtin_ia32_aadd64", - "llvm.x86.aand32" => "__builtin_ia32_aand32", - "llvm.x86.aand64" => "__builtin_ia32_aand64", - "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", - "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", - "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", - "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", - "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", - "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_aesdec256", - "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_aesdec512", - "llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", - "llvm.x86.aesni.aesdeclast.256" => "__builtin_ia32_aesdeclast256", - "llvm.x86.aesni.aesdeclast.512" => "__builtin_ia32_aesdeclast512", - "llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128", - "llvm.x86.aesni.aesenc.256" => "__builtin_ia32_aesenc256", - "llvm.x86.aesni.aesenc.512" => "__builtin_ia32_aesenc512", - "llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128", - "llvm.x86.aesni.aesenclast.256" => "__builtin_ia32_aesenclast256", - "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_aesenclast512", - "llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", - "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", - "llvm.x86.aor32" => "__builtin_ia32_aor32", - "llvm.x86.aor64" => "__builtin_ia32_aor64", - "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", - "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", - "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", - "llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", - "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", - "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", - "llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", - "llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", - "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", - "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", - "llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", - "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", - "llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", - "llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", - "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", - "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", - "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", - "llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256", - "llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256", - "llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", - "llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256", - "llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256", - "llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd", - "llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", - "llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps", - "llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", - "llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd", - "llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", - "llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps", - "llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", - "llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256", - "llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256", - "llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256", - "llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256", - "llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", - "llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", - "llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256", - "llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", - "llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256", - "llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256", - "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", - "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", - "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", - "llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", - "llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", - "llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", - "llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", - "llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", - "llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", - "llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", - "llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", - "llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", - "llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", - "llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", - "llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", - "llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", - "llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", - "llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", - "llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", - "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", - "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", - "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", - "llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", - "llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd", - "llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", - "llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps", - "llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", - "llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", - "llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", - "llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", - "llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", - "llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd", - "llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", - "llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps", - "llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", - "llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall", - "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper", - "llvm.x86.avx10.mask.getexp.bf16.128" => "__builtin_ia32_vgetexpbf16128_mask", - "llvm.x86.avx10.mask.getexp.bf16.256" => "__builtin_ia32_vgetexpbf16256_mask", - "llvm.x86.avx10.mask.getexp.bf16.512" => "__builtin_ia32_vgetexpbf16512_mask", - "llvm.x86.avx10.mask.getmant.bf16.128" => "__builtin_ia32_vgetmantbf16128_mask", - "llvm.x86.avx10.mask.getmant.bf16.256" => "__builtin_ia32_vgetmantbf16256_mask", - "llvm.x86.avx10.mask.getmant.bf16.512" => "__builtin_ia32_vgetmantbf16512_mask", - "llvm.x86.avx10.mask.rcp.bf16.128" => "__builtin_ia32_vrcpbf16128_mask", - "llvm.x86.avx10.mask.rcp.bf16.256" => "__builtin_ia32_vrcpbf16256_mask", - "llvm.x86.avx10.mask.rcp.bf16.512" => "__builtin_ia32_vrcpbf16512_mask", - "llvm.x86.avx10.mask.reduce.bf16.128" => "__builtin_ia32_vreducebf16128_mask", - "llvm.x86.avx10.mask.reduce.bf16.256" => "__builtin_ia32_vreducebf16256_mask", - "llvm.x86.avx10.mask.reduce.bf16.512" => "__builtin_ia32_vreducebf16512_mask", - "llvm.x86.avx10.mask.rndscale.bf16.128" => "__builtin_ia32_vrndscalebf16_128_mask", - "llvm.x86.avx10.mask.rndscale.bf16.256" => "__builtin_ia32_vrndscalebf16_256_mask", - "llvm.x86.avx10.mask.rndscale.bf16.512" => "__builtin_ia32_vrndscalebf16_mask", - "llvm.x86.avx10.mask.rsqrt.bf16.128" => "__builtin_ia32_vrsqrtbf16128_mask", - "llvm.x86.avx10.mask.rsqrt.bf16.256" => "__builtin_ia32_vrsqrtbf16256_mask", - "llvm.x86.avx10.mask.rsqrt.bf16.512" => "__builtin_ia32_vrsqrtbf16512_mask", - "llvm.x86.avx10.mask.scalef.bf16.128" => "__builtin_ia32_vscalefbf16128_mask", - "llvm.x86.avx10.mask.scalef.bf16.256" => "__builtin_ia32_vscalefbf16256_mask", - "llvm.x86.avx10.mask.scalef.bf16.512" => "__builtin_ia32_vscalefbf16512_mask", - "llvm.x86.avx10.mask.vcvt2ps2phx.128" => "__builtin_ia32_vcvt2ps2phx128_mask", - "llvm.x86.avx10.mask.vcvt2ps2phx.256" => "__builtin_ia32_vcvt2ps2phx256_mask", - "llvm.x86.avx10.mask.vcvt2ps2phx.512" => "__builtin_ia32_vcvt2ps2phx512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8128" => "__builtin_ia32_vcvtbiasph2bf8_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8256" => "__builtin_ia32_vcvtbiasph2bf8_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8512" => "__builtin_ia32_vcvtbiasph2bf8_512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8s128" => "__builtin_ia32_vcvtbiasph2bf8s_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8s256" => "__builtin_ia32_vcvtbiasph2bf8s_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2bf8s512" => "__builtin_ia32_vcvtbiasph2bf8s_512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8128" => "__builtin_ia32_vcvtbiasph2hf8_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8256" => "__builtin_ia32_vcvtbiasph2hf8_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8512" => "__builtin_ia32_vcvtbiasph2hf8_512_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8s128" => "__builtin_ia32_vcvtbiasph2hf8s_128_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8s256" => "__builtin_ia32_vcvtbiasph2hf8s_256_mask", - "llvm.x86.avx10.mask.vcvtbiasph2hf8s512" => "__builtin_ia32_vcvtbiasph2hf8s_512_mask", - "llvm.x86.avx10.mask.vcvthf82ph128" => "__builtin_ia32_vcvthf8_2ph128_mask", - "llvm.x86.avx10.mask.vcvthf82ph256" => "__builtin_ia32_vcvthf8_2ph256_mask", - "llvm.x86.avx10.mask.vcvthf82ph512" => "__builtin_ia32_vcvthf8_2ph512_mask", - "llvm.x86.avx10.mask.vcvtph2bf8128" => "__builtin_ia32_vcvtph2bf8_128_mask", - "llvm.x86.avx10.mask.vcvtph2bf8256" => "__builtin_ia32_vcvtph2bf8_256_mask", - "llvm.x86.avx10.mask.vcvtph2bf8512" => "__builtin_ia32_vcvtph2bf8_512_mask", - "llvm.x86.avx10.mask.vcvtph2bf8s128" => "__builtin_ia32_vcvtph2bf8s_128_mask", - "llvm.x86.avx10.mask.vcvtph2bf8s256" => "__builtin_ia32_vcvtph2bf8s_256_mask", - "llvm.x86.avx10.mask.vcvtph2bf8s512" => "__builtin_ia32_vcvtph2bf8s_512_mask", - "llvm.x86.avx10.mask.vcvtph2hf8128" => "__builtin_ia32_vcvtph2hf8_128_mask", - "llvm.x86.avx10.mask.vcvtph2hf8256" => "__builtin_ia32_vcvtph2hf8_256_mask", - "llvm.x86.avx10.mask.vcvtph2hf8512" => "__builtin_ia32_vcvtph2hf8_512_mask", - "llvm.x86.avx10.mask.vcvtph2hf8s128" => "__builtin_ia32_vcvtph2hf8s_128_mask", - "llvm.x86.avx10.mask.vcvtph2hf8s256" => "__builtin_ia32_vcvtph2hf8s_256_mask", - "llvm.x86.avx10.mask.vcvtph2hf8s512" => "__builtin_ia32_vcvtph2hf8s_512_mask", - "llvm.x86.avx10.mask.vcvtph2ibs128" => "__builtin_ia32_vcvtph2ibs128_mask", - "llvm.x86.avx10.mask.vcvtph2ibs256" => "__builtin_ia32_vcvtph2ibs256_mask", - "llvm.x86.avx10.mask.vcvtph2ibs512" => "__builtin_ia32_vcvtph2ibs512_mask", - "llvm.x86.avx10.mask.vcvtph2iubs128" => "__builtin_ia32_vcvtph2iubs128_mask", - "llvm.x86.avx10.mask.vcvtph2iubs256" => "__builtin_ia32_vcvtph2iubs256_mask", - "llvm.x86.avx10.mask.vcvtph2iubs512" => "__builtin_ia32_vcvtph2iubs512_mask", - "llvm.x86.avx10.mask.vcvtps2ibs128" => "__builtin_ia32_vcvtps2ibs128_mask", - "llvm.x86.avx10.mask.vcvtps2ibs256" => "__builtin_ia32_vcvtps2ibs256_mask", - "llvm.x86.avx10.mask.vcvtps2ibs512" => "__builtin_ia32_vcvtps2ibs512_mask", - "llvm.x86.avx10.mask.vcvtps2iubs128" => "__builtin_ia32_vcvtps2iubs128_mask", - "llvm.x86.avx10.mask.vcvtps2iubs256" => "__builtin_ia32_vcvtps2iubs256_mask", - "llvm.x86.avx10.mask.vcvtps2iubs512" => "__builtin_ia32_vcvtps2iubs512_mask", - "llvm.x86.avx10.mask.vcvttpd2dqs.128" => "__builtin_ia32_vcvttpd2dqs128_mask", - "llvm.x86.avx10.mask.vcvttpd2dqs.256" => "__builtin_ia32_vcvttpd2dqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2dqs.round.512" => "__builtin_ia32_vcvttpd2dqs512_round_mask", - "llvm.x86.avx10.mask.vcvttpd2qqs.128" => "__builtin_ia32_vcvttpd2qqs128_mask", - "llvm.x86.avx10.mask.vcvttpd2qqs.256" => "__builtin_ia32_vcvttpd2qqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2qqs.round.512" => "__builtin_ia32_vcvttpd2qqs512_round_mask", - "llvm.x86.avx10.mask.vcvttpd2udqs.128" => "__builtin_ia32_vcvttpd2udqs128_mask", - "llvm.x86.avx10.mask.vcvttpd2udqs.256" => "__builtin_ia32_vcvttpd2udqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2udqs.round.512" => "__builtin_ia32_vcvttpd2udqs512_round_mask", - "llvm.x86.avx10.mask.vcvttpd2uqqs.128" => "__builtin_ia32_vcvttpd2uqqs128_mask", - "llvm.x86.avx10.mask.vcvttpd2uqqs.256" => "__builtin_ia32_vcvttpd2uqqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttpd2uqqs.round.512" => "__builtin_ia32_vcvttpd2uqqs512_round_mask", - "llvm.x86.avx10.mask.vcvttph2ibs128" => "__builtin_ia32_vcvttph2ibs128_mask", - "llvm.x86.avx10.mask.vcvttph2ibs256" => "__builtin_ia32_vcvttph2ibs256_mask", - "llvm.x86.avx10.mask.vcvttph2ibs512" => "__builtin_ia32_vcvttph2ibs512_mask", - "llvm.x86.avx10.mask.vcvttph2iubs128" => "__builtin_ia32_vcvttph2iubs128_mask", - "llvm.x86.avx10.mask.vcvttph2iubs256" => "__builtin_ia32_vcvttph2iubs256_mask", - "llvm.x86.avx10.mask.vcvttph2iubs512" => "__builtin_ia32_vcvttph2iubs512_mask", - "llvm.x86.avx10.mask.vcvttps2dqs.128" => "__builtin_ia32_vcvttps2dqs128_mask", - "llvm.x86.avx10.mask.vcvttps2dqs.256" => "__builtin_ia32_vcvttps2dqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2dqs.round.512" => "__builtin_ia32_vcvttps2dqs512_round_mask", - "llvm.x86.avx10.mask.vcvttps2ibs128" => "__builtin_ia32_vcvttps2ibs128_mask", - "llvm.x86.avx10.mask.vcvttps2ibs256" => "__builtin_ia32_vcvttps2ibs256_mask", - "llvm.x86.avx10.mask.vcvttps2ibs512" => "__builtin_ia32_vcvttps2ibs512_mask", - "llvm.x86.avx10.mask.vcvttps2iubs128" => "__builtin_ia32_vcvttps2iubs128_mask", - "llvm.x86.avx10.mask.vcvttps2iubs256" => "__builtin_ia32_vcvttps2iubs256_mask", - "llvm.x86.avx10.mask.vcvttps2iubs512" => "__builtin_ia32_vcvttps2iubs512_mask", - "llvm.x86.avx10.mask.vcvttps2qqs.128" => "__builtin_ia32_vcvttps2qqs128_mask", - "llvm.x86.avx10.mask.vcvttps2qqs.256" => "__builtin_ia32_vcvttps2qqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2qqs.round.512" => "__builtin_ia32_vcvttps2qqs512_round_mask", - "llvm.x86.avx10.mask.vcvttps2udqs.128" => "__builtin_ia32_vcvttps2udqs128_mask", - "llvm.x86.avx10.mask.vcvttps2udqs.256" => "__builtin_ia32_vcvttps2udqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2udqs.round.512" => "__builtin_ia32_vcvttps2udqs512_round_mask", - "llvm.x86.avx10.mask.vcvttps2uqqs.128" => "__builtin_ia32_vcvttps2uqqs128_mask", - "llvm.x86.avx10.mask.vcvttps2uqqs.256" => "__builtin_ia32_vcvttps2uqqs256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vcvttps2uqqs.round.512" => "__builtin_ia32_vcvttps2uqqs512_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxpd.round" => "__builtin_ia32_vminmaxpd512_round_mask", - "llvm.x86.avx10.mask.vminmaxpd128" => "__builtin_ia32_vminmaxpd128_mask", - "llvm.x86.avx10.mask.vminmaxpd256" => "__builtin_ia32_vminmaxpd256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxph.round" => "__builtin_ia32_vminmaxph512_round_mask", - "llvm.x86.avx10.mask.vminmaxph128" => "__builtin_ia32_vminmaxph128_mask", - "llvm.x86.avx10.mask.vminmaxph256" => "__builtin_ia32_vminmaxph256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxps.round" => "__builtin_ia32_vminmaxps512_round_mask", - "llvm.x86.avx10.mask.vminmaxps128" => "__builtin_ia32_vminmaxps128_mask", - "llvm.x86.avx10.mask.vminmaxps256" => "__builtin_ia32_vminmaxps256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxsd.round" => "__builtin_ia32_vminmaxsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxsh.round" => "__builtin_ia32_vminmaxsh_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx10.mask.vminmaxss.round" => "__builtin_ia32_vminmaxss_round_mask", - "llvm.x86.avx10.vaddbf16128" => "__builtin_ia32_vaddbf16128", - "llvm.x86.avx10.vaddbf16256" => "__builtin_ia32_vaddbf16256", - "llvm.x86.avx10.vaddbf16512" => "__builtin_ia32_vaddbf16512", - "llvm.x86.avx10.vaddpd256" => "__builtin_ia32_vaddpd256_round", - "llvm.x86.avx10.vaddph256" => "__builtin_ia32_vaddph256_round", - "llvm.x86.avx10.vaddps256" => "__builtin_ia32_vaddps256_round", - "llvm.x86.avx10.vcomisbf16eq" => "__builtin_ia32_vcomisbf16eq", - "llvm.x86.avx10.vcomisbf16ge" => "__builtin_ia32_vcomisbf16ge", - "llvm.x86.avx10.vcomisbf16gt" => "__builtin_ia32_vcomisbf16gt", - "llvm.x86.avx10.vcomisbf16le" => "__builtin_ia32_vcomisbf16le", - "llvm.x86.avx10.vcomisbf16lt" => "__builtin_ia32_vcomisbf16lt", - "llvm.x86.avx10.vcomisbf16neq" => "__builtin_ia32_vcomisbf16neq", - "llvm.x86.avx10.vcvt2ph2bf8128" => "__builtin_ia32_vcvt2ph2bf8_128", - "llvm.x86.avx10.vcvt2ph2bf8256" => "__builtin_ia32_vcvt2ph2bf8_256", - "llvm.x86.avx10.vcvt2ph2bf8512" => "__builtin_ia32_vcvt2ph2bf8_512", - "llvm.x86.avx10.vcvt2ph2bf8s128" => "__builtin_ia32_vcvt2ph2bf8s_128", - "llvm.x86.avx10.vcvt2ph2bf8s256" => "__builtin_ia32_vcvt2ph2bf8s_256", - "llvm.x86.avx10.vcvt2ph2bf8s512" => "__builtin_ia32_vcvt2ph2bf8s_512", - "llvm.x86.avx10.vcvt2ph2hf8128" => "__builtin_ia32_vcvt2ph2hf8_128", - "llvm.x86.avx10.vcvt2ph2hf8256" => "__builtin_ia32_vcvt2ph2hf8_256", - "llvm.x86.avx10.vcvt2ph2hf8512" => "__builtin_ia32_vcvt2ph2hf8_512", - "llvm.x86.avx10.vcvt2ph2hf8s128" => "__builtin_ia32_vcvt2ph2hf8s_128", - "llvm.x86.avx10.vcvt2ph2hf8s256" => "__builtin_ia32_vcvt2ph2hf8s_256", - "llvm.x86.avx10.vcvt2ph2hf8s512" => "__builtin_ia32_vcvt2ph2hf8s_512", - "llvm.x86.avx10.vcvtbf162ibs128" => "__builtin_ia32_vcvtbf162ibs128", - "llvm.x86.avx10.vcvtbf162ibs256" => "__builtin_ia32_vcvtbf162ibs256", - "llvm.x86.avx10.vcvtbf162ibs512" => "__builtin_ia32_vcvtbf162ibs512", - "llvm.x86.avx10.vcvtbf162iubs128" => "__builtin_ia32_vcvtbf162iubs128", - "llvm.x86.avx10.vcvtbf162iubs256" => "__builtin_ia32_vcvtbf162iubs256", - "llvm.x86.avx10.vcvtbf162iubs512" => "__builtin_ia32_vcvtbf162iubs512", - "llvm.x86.avx10.vcvttbf162ibs128" => "__builtin_ia32_vcvttbf162ibs128", - "llvm.x86.avx10.vcvttbf162ibs256" => "__builtin_ia32_vcvttbf162ibs256", - "llvm.x86.avx10.vcvttbf162ibs512" => "__builtin_ia32_vcvttbf162ibs512", - "llvm.x86.avx10.vcvttbf162iubs128" => "__builtin_ia32_vcvttbf162iubs128", - "llvm.x86.avx10.vcvttbf162iubs256" => "__builtin_ia32_vcvttbf162iubs256", - "llvm.x86.avx10.vcvttbf162iubs512" => "__builtin_ia32_vcvttbf162iubs512", - "llvm.x86.avx10.vcvttsd2sis" => "__builtin_ia32_vcvttsd2sis32", - "llvm.x86.avx10.vcvttsd2sis64" => "__builtin_ia32_vcvttsd2sis64", - "llvm.x86.avx10.vcvttsd2usis" => "__builtin_ia32_vcvttsd2usis32", - "llvm.x86.avx10.vcvttsd2usis64" => "__builtin_ia32_vcvttsd2usis64", - "llvm.x86.avx10.vcvttss2sis" => "__builtin_ia32_vcvttss2sis32", - "llvm.x86.avx10.vcvttss2sis64" => "__builtin_ia32_vcvttss2sis64", - "llvm.x86.avx10.vcvttss2usis" => "__builtin_ia32_vcvttss2usis32", - "llvm.x86.avx10.vcvttss2usis64" => "__builtin_ia32_vcvttss2usis64", - "llvm.x86.avx10.vdivbf16128" => "__builtin_ia32_vdivbf16128", - "llvm.x86.avx10.vdivbf16256" => "__builtin_ia32_vdivbf16256", - "llvm.x86.avx10.vdivbf16512" => "__builtin_ia32_vdivbf16512", - "llvm.x86.avx10.vdpphps.128" => "__builtin_ia32_vdpphps128", - "llvm.x86.avx10.vdpphps.256" => "__builtin_ia32_vdpphps256", - "llvm.x86.avx10.vdpphps.512" => "__builtin_ia32_vdpphps512", - "llvm.x86.avx10.vfmadd132bf16128" => "__builtin_ia32_vfmadd132bf16128", - "llvm.x86.avx10.vfmadd132bf16256" => "__builtin_ia32_vfmadd132bf16256", - "llvm.x86.avx10.vfmadd132bf16512" => "__builtin_ia32_vfmadd132bf16512", - "llvm.x86.avx10.vfmadd213bf16128" => "__builtin_ia32_vfmadd213bf16128", - "llvm.x86.avx10.vfmadd213bf16256" => "__builtin_ia32_vfmadd213bf16256", - "llvm.x86.avx10.vfmadd231bf16128" => "__builtin_ia32_vfmadd231bf16128", - "llvm.x86.avx10.vfmadd231bf16256" => "__builtin_ia32_vfmadd231bf16256", - "llvm.x86.avx10.vfmadd231bf16512" => "__builtin_ia32_vfmadd231bf16512", - "llvm.x86.avx10.vfmsub132bf16128" => "__builtin_ia32_vfmsub132bf16128", - "llvm.x86.avx10.vfmsub132bf16256" => "__builtin_ia32_vfmsub132bf16256", - "llvm.x86.avx10.vfmsub132bf16512" => "__builtin_ia32_vfmsub132bf16512", - "llvm.x86.avx10.vfmsub213bf16128" => "__builtin_ia32_vfmsub213bf16128", - "llvm.x86.avx10.vfmsub213bf16256" => "__builtin_ia32_vfmsub213bf16256", - "llvm.x86.avx10.vfmsub213bf16512" => "__builtin_ia32_vfmsub213bf16512", - "llvm.x86.avx10.vfmsub231bf16128" => "__builtin_ia32_vfmsub231bf16128", - "llvm.x86.avx10.vfmsub231bf16256" => "__builtin_ia32_vfmsub231bf16256", - "llvm.x86.avx10.vfmsub231bf16512" => "__builtin_ia32_vfmsub231bf16512", - "llvm.x86.avx10.vfnmadd132bf16128" => "__builtin_ia32_vfnmadd132bf16128", - "llvm.x86.avx10.vfnmadd132bf16256" => "__builtin_ia32_vfnmadd132bf16256", - "llvm.x86.avx10.vfnmadd132bf16512" => "__builtin_ia32_vfnmadd132bf16512", - "llvm.x86.avx10.vfnmadd213bf16128" => "__builtin_ia32_vfnmadd213bf16128", - "llvm.x86.avx10.vfnmadd213bf16256" => "__builtin_ia32_vfnmadd213bf16256", - "llvm.x86.avx10.vfnmadd213bf16512" => "__builtin_ia32_vfnmadd213bf16512", - "llvm.x86.avx10.vfnmadd231bf16128" => "__builtin_ia32_vfnmadd231bf16128", - "llvm.x86.avx10.vfnmadd231bf16256" => "__builtin_ia32_vfnmadd231bf16256", - "llvm.x86.avx10.vfnmadd231bf16512" => "__builtin_ia32_vfnmadd231bf16512", - "llvm.x86.avx10.vfnmsub132bf16128" => "__builtin_ia32_vfnmsub132bf16128", - "llvm.x86.avx10.vfnmsub132bf16256" => "__builtin_ia32_vfnmsub132bf16256", - "llvm.x86.avx10.vfnmsub132bf16512" => "__builtin_ia32_vfnmsub132bf16512", - "llvm.x86.avx10.vfnmsub213bf16128" => "__builtin_ia32_vfnmsub213bf16128", - "llvm.x86.avx10.vfnmsub213bf16256" => "__builtin_ia32_vfnmsub213bf16256", - "llvm.x86.avx10.vfnmsub213bf16512" => "__builtin_ia32_vfnmsub213bf16512", - "llvm.x86.avx10.vfnmsub231bf16128" => "__builtin_ia32_vfnmsub231bf16128", - "llvm.x86.avx10.vfnmsub231bf16256" => "__builtin_ia32_vfnmsub231bf16256", - "llvm.x86.avx10.vfnmsub231bf16512" => "__builtin_ia32_vfnmsub231bf16512", - "llvm.x86.avx10.vmaxbf16128" => "__builtin_ia32_vmaxbf16128", - "llvm.x86.avx10.vmaxbf16256" => "__builtin_ia32_vmaxbf16256", - "llvm.x86.avx10.vmaxbf16512" => "__builtin_ia32_vmaxbf16512", - "llvm.x86.avx10.vminbf16128" => "__builtin_ia32_vminbf16128", - "llvm.x86.avx10.vminbf16256" => "__builtin_ia32_vminbf16256", - "llvm.x86.avx10.vminbf16512" => "__builtin_ia32_vminbf16512", - "llvm.x86.avx10.vminmaxbf16128" => "__builtin_ia32_vminmaxbf16128", - "llvm.x86.avx10.vminmaxbf16256" => "__builtin_ia32_vminmaxbf16256", - "llvm.x86.avx10.vminmaxbf16512" => "__builtin_ia32_vminmaxbf16512", - "llvm.x86.avx10.vminmaxpd128" => "__builtin_ia32_vminmaxpd128", - "llvm.x86.avx10.vminmaxpd256" => "__builtin_ia32_vminmaxpd256", - "llvm.x86.avx10.vminmaxph128" => "__builtin_ia32_vminmaxph128", - "llvm.x86.avx10.vminmaxph256" => "__builtin_ia32_vminmaxph256", - "llvm.x86.avx10.vminmaxps128" => "__builtin_ia32_vminmaxps128", - "llvm.x86.avx10.vminmaxps256" => "__builtin_ia32_vminmaxps256", - "llvm.x86.avx10.vmovrsb128" => "__builtin_ia32_vmovrsb128", - "llvm.x86.avx10.vmovrsb256" => "__builtin_ia32_vmovrsb256", - "llvm.x86.avx10.vmovrsb512" => "__builtin_ia32_vmovrsb512", - "llvm.x86.avx10.vmovrsd128" => "__builtin_ia32_vmovrsd128", - "llvm.x86.avx10.vmovrsd256" => "__builtin_ia32_vmovrsd256", - "llvm.x86.avx10.vmovrsd512" => "__builtin_ia32_vmovrsd512", - "llvm.x86.avx10.vmovrsq128" => "__builtin_ia32_vmovrsq128", - "llvm.x86.avx10.vmovrsq256" => "__builtin_ia32_vmovrsq256", - "llvm.x86.avx10.vmovrsq512" => "__builtin_ia32_vmovrsq512", - "llvm.x86.avx10.vmovrsw128" => "__builtin_ia32_vmovrsw128", - "llvm.x86.avx10.vmovrsw256" => "__builtin_ia32_vmovrsw256", - "llvm.x86.avx10.vmovrsw512" => "__builtin_ia32_vmovrsw512", - "llvm.x86.avx10.vmpsadbw.512" => "__builtin_ia32_mpsadbw512", - "llvm.x86.avx10.vmulbf16128" => "__builtin_ia32_vmulbf16128", - "llvm.x86.avx10.vmulbf16256" => "__builtin_ia32_vmulbf16256", - "llvm.x86.avx10.vmulbf16512" => "__builtin_ia32_vmulbf16512", - "llvm.x86.avx10.vpdpbssd.512" => "__builtin_ia32_vpdpbssd512", - "llvm.x86.avx10.vpdpbssds.512" => "__builtin_ia32_vpdpbssds512", - "llvm.x86.avx10.vpdpbsud.512" => "__builtin_ia32_vpdpbsud512", - "llvm.x86.avx10.vpdpbsuds.512" => "__builtin_ia32_vpdpbsuds512", - "llvm.x86.avx10.vpdpbuud.512" => "__builtin_ia32_vpdpbuud512", - "llvm.x86.avx10.vpdpbuuds.512" => "__builtin_ia32_vpdpbuuds512", - "llvm.x86.avx10.vpdpwsud.512" => "__builtin_ia32_vpdpwsud512", - "llvm.x86.avx10.vpdpwsuds.512" => "__builtin_ia32_vpdpwsuds512", - "llvm.x86.avx10.vpdpwusd.512" => "__builtin_ia32_vpdpwusd512", - "llvm.x86.avx10.vpdpwusds.512" => "__builtin_ia32_vpdpwusds512", - "llvm.x86.avx10.vpdpwuud.512" => "__builtin_ia32_vpdpwuud512", - "llvm.x86.avx10.vpdpwuuds.512" => "__builtin_ia32_vpdpwuuds512", - "llvm.x86.avx10.vsubbf16128" => "__builtin_ia32_vsubbf16128", - "llvm.x86.avx10.vsubbf16256" => "__builtin_ia32_vsubbf16256", - "llvm.x86.avx10.vsubbf16512" => "__builtin_ia32_vsubbf16512", - "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d", - "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", - "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", - "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", - "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", - "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", - "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q", - "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", - "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d", - "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", - "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", - "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", - "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", - "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", - "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q", - "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", - "llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd", - "llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", - "llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq", - "llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", - "llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored", - "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", - "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", - "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", - "llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", - "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", - "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", - "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", - "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", - "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", - "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", - "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", - "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", - "llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", - "llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", - "llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", - "llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", - "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", - "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", - "llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", - "llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", - "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", - "llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", - "llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", - "llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", - "llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", - "llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", - "llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", - "llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", - "llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", - "llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", - "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", - "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", - "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", - "llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256", - "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256", - "llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256", - "llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256", - "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", - "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", - "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", - "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", - "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", - "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", - "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", - "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", - "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", - "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", - "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", - "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", - "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", - "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", - "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", - "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", - "llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", - "llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", - "llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", - "llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", - "llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", - "llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", - "llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", - "llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", - "llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", - "llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", - "llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", - "llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", - "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", - "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", - "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", - "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", - "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", - "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", - "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", - "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", - "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", - "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", - "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", - "llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", - "llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", - "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", - "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", - "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", - "llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256", - "llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256", - "llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si", - "llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si", - "llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di", - "llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di", - "llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256", - "llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256", - "llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256", - "llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256", - "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", - "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", - "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", - "llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", - "llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", - "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", - "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", - "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", - "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256", - "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256", - "llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si", - "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", - "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", - "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", - "llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", - "llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", - "llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", - "llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", - "llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", - "llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", - "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", - "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", - "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", - "llvm.x86.avx2.vpdpbssd.128" => "__builtin_ia32_vpdpbssd128", - "llvm.x86.avx2.vpdpbssd.256" => "__builtin_ia32_vpdpbssd256", - "llvm.x86.avx2.vpdpbssds.128" => "__builtin_ia32_vpdpbssds128", - "llvm.x86.avx2.vpdpbssds.256" => "__builtin_ia32_vpdpbssds256", - "llvm.x86.avx2.vpdpbsud.128" => "__builtin_ia32_vpdpbsud128", - "llvm.x86.avx2.vpdpbsud.256" => "__builtin_ia32_vpdpbsud256", - "llvm.x86.avx2.vpdpbsuds.128" => "__builtin_ia32_vpdpbsuds128", - "llvm.x86.avx2.vpdpbsuds.256" => "__builtin_ia32_vpdpbsuds256", - "llvm.x86.avx2.vpdpbuud.128" => "__builtin_ia32_vpdpbuud128", - "llvm.x86.avx2.vpdpbuud.256" => "__builtin_ia32_vpdpbuud256", - "llvm.x86.avx2.vpdpbuuds.128" => "__builtin_ia32_vpdpbuuds128", - "llvm.x86.avx2.vpdpbuuds.256" => "__builtin_ia32_vpdpbuuds256", - "llvm.x86.avx2.vpdpwsud.128" => "__builtin_ia32_vpdpwsud128", - "llvm.x86.avx2.vpdpwsud.256" => "__builtin_ia32_vpdpwsud256", - "llvm.x86.avx2.vpdpwsuds.128" => "__builtin_ia32_vpdpwsuds128", - "llvm.x86.avx2.vpdpwsuds.256" => "__builtin_ia32_vpdpwsuds256", - "llvm.x86.avx2.vpdpwusd.128" => "__builtin_ia32_vpdpwusd128", - "llvm.x86.avx2.vpdpwusd.256" => "__builtin_ia32_vpdpwusd256", - "llvm.x86.avx2.vpdpwusds.128" => "__builtin_ia32_vpdpwusds128", - "llvm.x86.avx2.vpdpwusds.256" => "__builtin_ia32_vpdpwusds256", - "llvm.x86.avx2.vpdpwuud.128" => "__builtin_ia32_vpdpwuud128", - "llvm.x86.avx2.vpdpwuud.256" => "__builtin_ia32_vpdpwuud256", - "llvm.x86.avx2.vpdpwuuds.128" => "__builtin_ia32_vpdpwuuds128", - "llvm.x86.avx2.vpdpwuuds.256" => "__builtin_ia32_vpdpwuuds256", - "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", - "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512", - "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512", - "llvm.x86.avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128", - "llvm.x86.avx512.broadcastmb.256" => "__builtin_ia32_broadcastmb256", - "llvm.x86.avx512.broadcastmb.512" => "__builtin_ia32_broadcastmb512", - "llvm.x86.avx512.broadcastmw.128" => "__builtin_ia32_broadcastmw128", - "llvm.x86.avx512.broadcastmw.256" => "__builtin_ia32_broadcastmw256", - "llvm.x86.avx512.broadcastmw.512" => "__builtin_ia32_broadcastmw512", - "llvm.x86.avx512.conflict.d.128" => "__builtin_ia32_vpconflictsi_128", - "llvm.x86.avx512.conflict.d.256" => "__builtin_ia32_vpconflictsi_256", - "llvm.x86.avx512.conflict.d.512" => "__builtin_ia32_vpconflictsi_512", - "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", - "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", - "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", - "llvm.x86.avx512.cvtb2mask.128" => "__builtin_ia32_cvtb2mask128", - "llvm.x86.avx512.cvtb2mask.256" => "__builtin_ia32_cvtb2mask256", - "llvm.x86.avx512.cvtb2mask.512" => "__builtin_ia32_cvtb2mask512", - "llvm.x86.avx512.cvtd2mask.128" => "__builtin_ia32_cvtd2mask128", - "llvm.x86.avx512.cvtd2mask.256" => "__builtin_ia32_cvtd2mask256", - "llvm.x86.avx512.cvtd2mask.512" => "__builtin_ia32_cvtd2mask512", - "llvm.x86.avx512.cvtmask2b.128" => "__builtin_ia32_cvtmask2b128", - "llvm.x86.avx512.cvtmask2b.256" => "__builtin_ia32_cvtmask2b256", - "llvm.x86.avx512.cvtmask2b.512" => "__builtin_ia32_cvtmask2b512", - "llvm.x86.avx512.cvtmask2d.128" => "__builtin_ia32_cvtmask2d128", - "llvm.x86.avx512.cvtmask2d.256" => "__builtin_ia32_cvtmask2d256", - "llvm.x86.avx512.cvtmask2d.512" => "__builtin_ia32_cvtmask2d512", - "llvm.x86.avx512.cvtmask2q.128" => "__builtin_ia32_cvtmask2q128", - "llvm.x86.avx512.cvtmask2q.256" => "__builtin_ia32_cvtmask2q256", - "llvm.x86.avx512.cvtmask2q.512" => "__builtin_ia32_cvtmask2q512", - "llvm.x86.avx512.cvtmask2w.128" => "__builtin_ia32_cvtmask2w128", - "llvm.x86.avx512.cvtmask2w.256" => "__builtin_ia32_cvtmask2w256", - "llvm.x86.avx512.cvtmask2w.512" => "__builtin_ia32_cvtmask2w512", - "llvm.x86.avx512.cvtq2mask.128" => "__builtin_ia32_cvtq2mask128", - "llvm.x86.avx512.cvtq2mask.256" => "__builtin_ia32_cvtq2mask256", - "llvm.x86.avx512.cvtq2mask.512" => "__builtin_ia32_cvtq2mask512", - "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", - "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", - "llvm.x86.avx512.cvtsi2sd32" => "__builtin_ia32_cvtsi2sd32", - "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", - "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", - "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", - "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", - "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", - "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", - "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", - "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", - // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", - "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", - // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", - "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", - "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", - "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", - // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", - "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", - // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", - "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd32", - "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", - "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", - "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", - // [DUPLICATE]: "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", - "llvm.x86.avx512.cvtw2mask.128" => "__builtin_ia32_cvtw2mask128", - "llvm.x86.avx512.cvtw2mask.256" => "__builtin_ia32_cvtw2mask256", - "llvm.x86.avx512.cvtw2mask.512" => "__builtin_ia32_cvtw2mask512", - "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", - "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", - "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", - "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512", - "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512", - "llvm.x86.avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask", - "llvm.x86.avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask", - "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", - "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", - "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", - "llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", - "llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", - "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", - "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", - "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", - "llvm.x86.avx512.gather3div2.df" => "__builtin_ia32_gather3div2df", - "llvm.x86.avx512.gather3div2.di" => "__builtin_ia32_gather3div2di", - "llvm.x86.avx512.gather3div4.df" => "__builtin_ia32_gather3div4df", - "llvm.x86.avx512.gather3div4.di" => "__builtin_ia32_gather3div4di", - "llvm.x86.avx512.gather3div4.sf" => "__builtin_ia32_gather3div4sf", - "llvm.x86.avx512.gather3div4.si" => "__builtin_ia32_gather3div4si", - "llvm.x86.avx512.gather3div8.sf" => "__builtin_ia32_gather3div8sf", - "llvm.x86.avx512.gather3div8.si" => "__builtin_ia32_gather3div8si", - "llvm.x86.avx512.gather3siv2.df" => "__builtin_ia32_gather3siv2df", - "llvm.x86.avx512.gather3siv2.di" => "__builtin_ia32_gather3siv2di", - "llvm.x86.avx512.gather3siv4.df" => "__builtin_ia32_gather3siv4df", - "llvm.x86.avx512.gather3siv4.di" => "__builtin_ia32_gather3siv4di", - "llvm.x86.avx512.gather3siv4.sf" => "__builtin_ia32_gather3siv4sf", - "llvm.x86.avx512.gather3siv4.si" => "__builtin_ia32_gather3siv4si", - "llvm.x86.avx512.gather3siv8.sf" => "__builtin_ia32_gather3siv8sf", - "llvm.x86.avx512.gather3siv8.si" => "__builtin_ia32_gather3siv8si", - "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", - "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", - "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", - "llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", - "llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", - "llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", - "llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", - "llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", - "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", - "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", - "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", - "llvm.x86.avx512.kunpck.dq" => "__builtin_ia32_kunpckdi", - "llvm.x86.avx512.kunpck.wd" => "__builtin_ia32_kunpcksi", - "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", - "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", - "llvm.x86.avx512.mask.add.pd.128" => "__builtin_ia32_addpd128_mask", - "llvm.x86.avx512.mask.add.pd.256" => "__builtin_ia32_addpd256_mask", - "llvm.x86.avx512.mask.add.pd.512" => "__builtin_ia32_addpd512_mask", - "llvm.x86.avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask", - "llvm.x86.avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask", - "llvm.x86.avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", - "llvm.x86.avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask", - "llvm.x86.avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask", - "llvm.x86.avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask", - "llvm.x86.avx512.mask.and.ps.128" => "__builtin_ia32_andps128_mask", - "llvm.x86.avx512.mask.and.ps.256" => "__builtin_ia32_andps256_mask", - "llvm.x86.avx512.mask.and.ps.512" => "__builtin_ia32_andps512_mask", - "llvm.x86.avx512.mask.andn.pd.128" => "__builtin_ia32_andnpd128_mask", - "llvm.x86.avx512.mask.andn.pd.256" => "__builtin_ia32_andnpd256_mask", - "llvm.x86.avx512.mask.andn.pd.512" => "__builtin_ia32_andnpd512_mask", - "llvm.x86.avx512.mask.andn.ps.128" => "__builtin_ia32_andnps128_mask", - "llvm.x86.avx512.mask.andn.ps.256" => "__builtin_ia32_andnps256_mask", - "llvm.x86.avx512.mask.andn.ps.512" => "__builtin_ia32_andnps512_mask", - "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", - "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", - "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", - "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", - "llvm.x86.avx512.mask.broadcastf32x2.256" => "__builtin_ia32_broadcastf32x2_256_mask", - "llvm.x86.avx512.mask.broadcastf32x2.512" => "__builtin_ia32_broadcastf32x2_512_mask", - "llvm.x86.avx512.mask.broadcastf32x4.256" => "__builtin_ia32_broadcastf32x4_256_mask", - "llvm.x86.avx512.mask.broadcastf32x4.512" => "__builtin_ia32_broadcastf32x4_512", - "llvm.x86.avx512.mask.broadcastf32x8.512" => "__builtin_ia32_broadcastf32x8_512_mask", - "llvm.x86.avx512.mask.broadcastf64x2.256" => "__builtin_ia32_broadcastf64x2_256_mask", - "llvm.x86.avx512.mask.broadcastf64x2.512" => "__builtin_ia32_broadcastf64x2_512_mask", - "llvm.x86.avx512.mask.broadcastf64x4.512" => "__builtin_ia32_broadcastf64x4_512", - "llvm.x86.avx512.mask.broadcasti32x2.128" => "__builtin_ia32_broadcasti32x2_128_mask", - "llvm.x86.avx512.mask.broadcasti32x2.256" => "__builtin_ia32_broadcasti32x2_256_mask", - "llvm.x86.avx512.mask.broadcasti32x2.512" => "__builtin_ia32_broadcasti32x2_512_mask", - "llvm.x86.avx512.mask.broadcasti32x4.256" => "__builtin_ia32_broadcasti32x4_256_mask", - "llvm.x86.avx512.mask.broadcasti32x4.512" => "__builtin_ia32_broadcasti32x4_512", - "llvm.x86.avx512.mask.broadcasti32x8.512" => "__builtin_ia32_broadcasti32x8_512_mask", - "llvm.x86.avx512.mask.broadcasti64x2.256" => "__builtin_ia32_broadcasti64x2_256_mask", - "llvm.x86.avx512.mask.broadcasti64x2.512" => "__builtin_ia32_broadcasti64x2_512_mask", - "llvm.x86.avx512.mask.broadcasti64x4.512" => "__builtin_ia32_broadcasti64x4_512", - "llvm.x86.avx512.mask.cmp.pd.128" => "__builtin_ia32_cmppd128_mask", - "llvm.x86.avx512.mask.cmp.pd.256" => "__builtin_ia32_cmppd256_mask", - "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", - "llvm.x86.avx512.mask.cmp.ps.128" => "__builtin_ia32_cmpps128_mask", - "llvm.x86.avx512.mask.cmp.ps.256" => "__builtin_ia32_cmpps256_mask", - "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", - "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", - "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", - "llvm.x86.avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask", - "llvm.x86.avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask", - "llvm.x86.avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask", - "llvm.x86.avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask", - "llvm.x86.avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask", - "llvm.x86.avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask", - "llvm.x86.avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask", - "llvm.x86.avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask", - "llvm.x86.avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask", - "llvm.x86.avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask", - "llvm.x86.avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask", - "llvm.x86.avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask", - "llvm.x86.avx512.mask.compress.store.d.128" => "__builtin_ia32_compressstoresi128_mask", - "llvm.x86.avx512.mask.compress.store.d.256" => "__builtin_ia32_compressstoresi256_mask", - "llvm.x86.avx512.mask.compress.store.d.512" => "__builtin_ia32_compressstoresi512_mask", - "llvm.x86.avx512.mask.compress.store.pd.128" => "__builtin_ia32_compressstoredf128_mask", - "llvm.x86.avx512.mask.compress.store.pd.256" => "__builtin_ia32_compressstoredf256_mask", - "llvm.x86.avx512.mask.compress.store.pd.512" => "__builtin_ia32_compressstoredf512_mask", - "llvm.x86.avx512.mask.compress.store.ps.128" => "__builtin_ia32_compressstoresf128_mask", - "llvm.x86.avx512.mask.compress.store.ps.256" => "__builtin_ia32_compressstoresf256_mask", - "llvm.x86.avx512.mask.compress.store.ps.512" => "__builtin_ia32_compressstoresf512_mask", - "llvm.x86.avx512.mask.compress.store.q.128" => "__builtin_ia32_compressstoredi128_mask", - "llvm.x86.avx512.mask.compress.store.q.256" => "__builtin_ia32_compressstoredi256_mask", - "llvm.x86.avx512.mask.compress.store.q.512" => "__builtin_ia32_compressstoredi512_mask", - "llvm.x86.avx512.mask.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask", - "llvm.x86.avx512.mask.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask", - "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", - "llvm.x86.avx512.mask.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask", - "llvm.x86.avx512.mask.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask", - "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", - "llvm.x86.avx512.mask.cvtdq2pd.128" => "__builtin_ia32_cvtdq2pd128_mask", - "llvm.x86.avx512.mask.cvtdq2pd.256" => "__builtin_ia32_cvtdq2pd256_mask", - "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", - "llvm.x86.avx512.mask.cvtdq2ps.128" => "__builtin_ia32_cvtdq2ps128_mask", - "llvm.x86.avx512.mask.cvtdq2ps.256" => "__builtin_ia32_cvtdq2ps256_mask", - "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", - "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", - "llvm.x86.avx512.mask.cvtpd2dq.256" => "__builtin_ia32_cvtpd2dq256_mask", - "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", - "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", - "llvm.x86.avx512.mask.cvtpd2ps.256" => "__builtin_ia32_cvtpd2ps256_mask", - "llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", - "llvm.x86.avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask", - "llvm.x86.avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask", - "llvm.x86.avx512.mask.cvtpd2qq.512" => "__builtin_ia32_cvtpd2qq512_mask", - "llvm.x86.avx512.mask.cvtpd2udq.128" => "__builtin_ia32_cvtpd2udq128_mask", - "llvm.x86.avx512.mask.cvtpd2udq.256" => "__builtin_ia32_cvtpd2udq256_mask", - "llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", - "llvm.x86.avx512.mask.cvtpd2uqq.128" => "__builtin_ia32_cvtpd2uqq128_mask", - "llvm.x86.avx512.mask.cvtpd2uqq.256" => "__builtin_ia32_cvtpd2uqq256_mask", - "llvm.x86.avx512.mask.cvtpd2uqq.512" => "__builtin_ia32_cvtpd2uqq512_mask", - "llvm.x86.avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask", - "llvm.x86.avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask", - "llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", - "llvm.x86.avx512.mask.cvtps2pd.128" => "__builtin_ia32_cvtps2pd128_mask", - "llvm.x86.avx512.mask.cvtps2pd.256" => "__builtin_ia32_cvtps2pd256_mask", - "llvm.x86.avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask", - "llvm.x86.avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask", - "llvm.x86.avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask", - "llvm.x86.avx512.mask.cvtps2qq.512" => "__builtin_ia32_cvtps2qq512_mask", - "llvm.x86.avx512.mask.cvtps2udq.128" => "__builtin_ia32_cvtps2udq128_mask", - "llvm.x86.avx512.mask.cvtps2udq.256" => "__builtin_ia32_cvtps2udq256_mask", - "llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", - "llvm.x86.avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask", - "llvm.x86.avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask", - "llvm.x86.avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask", - "llvm.x86.avx512.mask.cvtqq2pd.128" => "__builtin_ia32_cvtqq2pd128_mask", - "llvm.x86.avx512.mask.cvtqq2pd.256" => "__builtin_ia32_cvtqq2pd256_mask", - "llvm.x86.avx512.mask.cvtqq2pd.512" => "__builtin_ia32_cvtqq2pd512_mask", - "llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask", - "llvm.x86.avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask", - "llvm.x86.avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", - "llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask", - "llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask", - "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", - "llvm.x86.avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask", - "llvm.x86.avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask", - "llvm.x86.avx512.mask.cvttpd2qq.512" => "__builtin_ia32_cvttpd2qq512_mask", - "llvm.x86.avx512.mask.cvttpd2udq.128" => "__builtin_ia32_cvttpd2udq128_mask", - "llvm.x86.avx512.mask.cvttpd2udq.256" => "__builtin_ia32_cvttpd2udq256_mask", - "llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", - "llvm.x86.avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask", - "llvm.x86.avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask", - "llvm.x86.avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask", - "llvm.x86.avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask", - "llvm.x86.avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask", - "llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", - "llvm.x86.avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask", - "llvm.x86.avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask", - "llvm.x86.avx512.mask.cvttps2qq.512" => "__builtin_ia32_cvttps2qq512_mask", - "llvm.x86.avx512.mask.cvttps2udq.128" => "__builtin_ia32_cvttps2udq128_mask", - "llvm.x86.avx512.mask.cvttps2udq.256" => "__builtin_ia32_cvttps2udq256_mask", - "llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", - "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", - "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", - "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", - "llvm.x86.avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask", - "llvm.x86.avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask", - "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", - "llvm.x86.avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask", - "llvm.x86.avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask", - "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", - "llvm.x86.avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask", - "llvm.x86.avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask", - "llvm.x86.avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask", - "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", - "llvm.x86.avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask", - "llvm.x86.avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask", - "llvm.x86.avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask", - "llvm.x86.avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask", - "llvm.x86.avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask", - "llvm.x86.avx512.mask.div.pd.128" => "__builtin_ia32_divpd_mask", - "llvm.x86.avx512.mask.div.pd.256" => "__builtin_ia32_divpd256_mask", - "llvm.x86.avx512.mask.div.pd.512" => "__builtin_ia32_divpd512_mask", - "llvm.x86.avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask", - "llvm.x86.avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask", - "llvm.x86.avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", - "llvm.x86.avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask", - "llvm.x86.avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask", - "llvm.x86.avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask", - "llvm.x86.avx512.mask.expand.load.d.128" => "__builtin_ia32_expandloadsi128_mask", - "llvm.x86.avx512.mask.expand.load.d.256" => "__builtin_ia32_expandloadsi256_mask", - "llvm.x86.avx512.mask.expand.load.d.512" => "__builtin_ia32_expandloadsi512_mask", - "llvm.x86.avx512.mask.expand.load.pd.128" => "__builtin_ia32_expandloaddf128_mask", - "llvm.x86.avx512.mask.expand.load.pd.256" => "__builtin_ia32_expandloaddf256_mask", - "llvm.x86.avx512.mask.expand.load.pd.512" => "__builtin_ia32_expandloaddf512_mask", - "llvm.x86.avx512.mask.expand.load.ps.128" => "__builtin_ia32_expandloadsf128_mask", - "llvm.x86.avx512.mask.expand.load.ps.256" => "__builtin_ia32_expandloadsf256_mask", - "llvm.x86.avx512.mask.expand.load.ps.512" => "__builtin_ia32_expandloadsf512_mask", - "llvm.x86.avx512.mask.expand.load.q.128" => "__builtin_ia32_expandloaddi128_mask", - "llvm.x86.avx512.mask.expand.load.q.256" => "__builtin_ia32_expandloaddi256_mask", - "llvm.x86.avx512.mask.expand.load.q.512" => "__builtin_ia32_expandloaddi512_mask", - "llvm.x86.avx512.mask.expand.pd.128" => "__builtin_ia32_expanddf128_mask", - "llvm.x86.avx512.mask.expand.pd.256" => "__builtin_ia32_expanddf256_mask", - "llvm.x86.avx512.mask.expand.pd.512" => "__builtin_ia32_expanddf512_mask", - "llvm.x86.avx512.mask.expand.ps.128" => "__builtin_ia32_expandsf128_mask", - "llvm.x86.avx512.mask.expand.ps.256" => "__builtin_ia32_expandsf256_mask", - "llvm.x86.avx512.mask.expand.ps.512" => "__builtin_ia32_expandsf512_mask", - "llvm.x86.avx512.mask.expand.q.128" => "__builtin_ia32_expanddi128_mask", - "llvm.x86.avx512.mask.expand.q.256" => "__builtin_ia32_expanddi256_mask", - "llvm.x86.avx512.mask.expand.q.512" => "__builtin_ia32_expanddi512_mask", - "llvm.x86.avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask", - "llvm.x86.avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask", - "llvm.x86.avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask", - "llvm.x86.avx512.mask.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_mask", - "llvm.x86.avx512.mask.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_mask", - "llvm.x86.avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask", - "llvm.x86.avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask", - "llvm.x86.avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask", - "llvm.x86.avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask", - "llvm.x86.avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask", - "llvm.x86.avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask", - "llvm.x86.avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask", - "llvm.x86.avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask", - "llvm.x86.avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask", - "llvm.x86.avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask", - "llvm.x86.avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask", - "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", - "llvm.x86.avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask", - "llvm.x86.avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask", - "llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask", - "llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask", - "llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask", - "llvm.x86.avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask", - "llvm.x86.avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask", - "llvm.x86.avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask", - "llvm.x86.avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask", - "llvm.x86.avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask", - "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", - "llvm.x86.avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask", - "llvm.x86.avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask", - "llvm.x86.avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask", - "llvm.x86.avx512.mask.insertf64x2.256" => "__builtin_ia32_insertf64x2_256_mask", - "llvm.x86.avx512.mask.insertf64x2.512" => "__builtin_ia32_insertf64x2_512_mask", - "llvm.x86.avx512.mask.insertf64x4.512" => "__builtin_ia32_insertf64x4_mask", - "llvm.x86.avx512.mask.inserti32x4.256" => "__builtin_ia32_inserti32x4_256_mask", - "llvm.x86.avx512.mask.inserti32x4.512" => "__builtin_ia32_inserti32x4_mask", - "llvm.x86.avx512.mask.inserti32x8.512" => "__builtin_ia32_inserti32x8_mask", - "llvm.x86.avx512.mask.inserti64x2.256" => "__builtin_ia32_inserti64x2_256_mask", - "llvm.x86.avx512.mask.inserti64x2.512" => "__builtin_ia32_inserti64x2_512_mask", - "llvm.x86.avx512.mask.inserti64x4.512" => "__builtin_ia32_inserti64x4_mask", - "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", - "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", - "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", - "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", - "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", - "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", - "llvm.x86.avx512.mask.max.pd.128" => "__builtin_ia32_maxpd_mask", - "llvm.x86.avx512.mask.max.pd.256" => "__builtin_ia32_maxpd256_mask", - "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", - "llvm.x86.avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask", - "llvm.x86.avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask", - "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", - "llvm.x86.avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask", - "llvm.x86.avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask", - "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", - "llvm.x86.avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask", - "llvm.x86.avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask", - "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", - "llvm.x86.avx512.mask.move.sd" => "__builtin_ia32_movsd_mask", - "llvm.x86.avx512.mask.move.ss" => "__builtin_ia32_movss_mask", - "llvm.x86.avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask", - "llvm.x86.avx512.mask.mul.pd.256" => "__builtin_ia32_mulpd256_mask", - "llvm.x86.avx512.mask.mul.pd.512" => "__builtin_ia32_mulpd512_mask", - "llvm.x86.avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask", - "llvm.x86.avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask", - "llvm.x86.avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", - "llvm.x86.avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask", - "llvm.x86.avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask", - "llvm.x86.avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask", - "llvm.x86.avx512.mask.or.ps.128" => "__builtin_ia32_orps128_mask", - "llvm.x86.avx512.mask.or.ps.256" => "__builtin_ia32_orps256_mask", - "llvm.x86.avx512.mask.or.ps.512" => "__builtin_ia32_orps512_mask", - "llvm.x86.avx512.mask.pabs.b.128" => "__builtin_ia32_pabsb128_mask", - "llvm.x86.avx512.mask.pabs.b.256" => "__builtin_ia32_pabsb256_mask", - "llvm.x86.avx512.mask.pabs.b.512" => "__builtin_ia32_pabsb512_mask", - "llvm.x86.avx512.mask.pabs.d.128" => "__builtin_ia32_pabsd128_mask", - "llvm.x86.avx512.mask.pabs.d.256" => "__builtin_ia32_pabsd256_mask", - "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", - "llvm.x86.avx512.mask.pabs.q.128" => "__builtin_ia32_pabsq128_mask", - "llvm.x86.avx512.mask.pabs.q.256" => "__builtin_ia32_pabsq256_mask", - "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", - "llvm.x86.avx512.mask.pabs.w.128" => "__builtin_ia32_pabsw128_mask", - "llvm.x86.avx512.mask.pabs.w.256" => "__builtin_ia32_pabsw256_mask", - "llvm.x86.avx512.mask.pabs.w.512" => "__builtin_ia32_pabsw512_mask", - "llvm.x86.avx512.mask.packssdw.128" => "__builtin_ia32_packssdw128_mask", - "llvm.x86.avx512.mask.packssdw.256" => "__builtin_ia32_packssdw256_mask", - "llvm.x86.avx512.mask.packssdw.512" => "__builtin_ia32_packssdw512_mask", - "llvm.x86.avx512.mask.packsswb.128" => "__builtin_ia32_packsswb128_mask", - "llvm.x86.avx512.mask.packsswb.256" => "__builtin_ia32_packsswb256_mask", - "llvm.x86.avx512.mask.packsswb.512" => "__builtin_ia32_packsswb512_mask", - "llvm.x86.avx512.mask.packusdw.128" => "__builtin_ia32_packusdw128_mask", - "llvm.x86.avx512.mask.packusdw.256" => "__builtin_ia32_packusdw256_mask", - "llvm.x86.avx512.mask.packusdw.512" => "__builtin_ia32_packusdw512_mask", - "llvm.x86.avx512.mask.packuswb.128" => "__builtin_ia32_packuswb128_mask", - "llvm.x86.avx512.mask.packuswb.256" => "__builtin_ia32_packuswb256_mask", - "llvm.x86.avx512.mask.packuswb.512" => "__builtin_ia32_packuswb512_mask", - "llvm.x86.avx512.mask.padd.b.128" => "__builtin_ia32_paddb128_mask", - "llvm.x86.avx512.mask.padd.b.256" => "__builtin_ia32_paddb256_mask", - "llvm.x86.avx512.mask.padd.b.512" => "__builtin_ia32_paddb512_mask", - "llvm.x86.avx512.mask.padd.d.128" => "__builtin_ia32_paddd128_mask", - "llvm.x86.avx512.mask.padd.d.256" => "__builtin_ia32_paddd256_mask", - "llvm.x86.avx512.mask.padd.d.512" => "__builtin_ia32_paddd512_mask", - "llvm.x86.avx512.mask.padd.q.128" => "__builtin_ia32_paddq128_mask", - "llvm.x86.avx512.mask.padd.q.256" => "__builtin_ia32_paddq256_mask", - "llvm.x86.avx512.mask.padd.q.512" => "__builtin_ia32_paddq512_mask", - "llvm.x86.avx512.mask.padd.w.128" => "__builtin_ia32_paddw128_mask", - "llvm.x86.avx512.mask.padd.w.256" => "__builtin_ia32_paddw256_mask", - "llvm.x86.avx512.mask.padd.w.512" => "__builtin_ia32_paddw512_mask", - "llvm.x86.avx512.mask.padds.b.128" => "__builtin_ia32_paddsb128_mask", - "llvm.x86.avx512.mask.padds.b.256" => "__builtin_ia32_paddsb256_mask", - "llvm.x86.avx512.mask.padds.b.512" => "__builtin_ia32_paddsb512_mask", - "llvm.x86.avx512.mask.padds.w.128" => "__builtin_ia32_paddsw128_mask", - "llvm.x86.avx512.mask.padds.w.256" => "__builtin_ia32_paddsw256_mask", - "llvm.x86.avx512.mask.padds.w.512" => "__builtin_ia32_paddsw512_mask", - "llvm.x86.avx512.mask.paddus.b.128" => "__builtin_ia32_paddusb128_mask", - "llvm.x86.avx512.mask.paddus.b.256" => "__builtin_ia32_paddusb256_mask", - "llvm.x86.avx512.mask.paddus.b.512" => "__builtin_ia32_paddusb512_mask", - "llvm.x86.avx512.mask.paddus.w.128" => "__builtin_ia32_paddusw128_mask", - "llvm.x86.avx512.mask.paddus.w.256" => "__builtin_ia32_paddusw256_mask", - "llvm.x86.avx512.mask.paddus.w.512" => "__builtin_ia32_paddusw512_mask", - "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", - "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", - "llvm.x86.avx512.mask.pavg.b.128" => "__builtin_ia32_pavgb128_mask", - "llvm.x86.avx512.mask.pavg.b.256" => "__builtin_ia32_pavgb256_mask", - "llvm.x86.avx512.mask.pavg.b.512" => "__builtin_ia32_pavgb512_mask", - "llvm.x86.avx512.mask.pavg.w.128" => "__builtin_ia32_pavgw128_mask", - "llvm.x86.avx512.mask.pavg.w.256" => "__builtin_ia32_pavgw256_mask", - "llvm.x86.avx512.mask.pavg.w.512" => "__builtin_ia32_pavgw512_mask", - "llvm.x86.avx512.mask.pbroadcast.b.gpr.128" => "__builtin_ia32_pbroadcastb128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.b.gpr.256" => "__builtin_ia32_pbroadcastb256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.b.gpr.512" => "__builtin_ia32_pbroadcastb512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.d.gpr.128" => "__builtin_ia32_pbroadcastd128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.d.gpr.256" => "__builtin_ia32_pbroadcastd256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.gpr.128" => "__builtin_ia32_pbroadcastq128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.gpr.256" => "__builtin_ia32_pbroadcastq256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", - "llvm.x86.avx512.mask.pbroadcast.w.gpr.128" => "__builtin_ia32_pbroadcastw128_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.w.gpr.256" => "__builtin_ia32_pbroadcastw256_gpr_mask", - "llvm.x86.avx512.mask.pbroadcast.w.gpr.512" => "__builtin_ia32_pbroadcastw512_gpr_mask", - "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", - "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", - "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", - "llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", - "llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", - "llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", - "llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", - "llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", - "llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", - "llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", - "llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", - "llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", - "llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", - "llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", - "llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", - "llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", - "llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", - "llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", - "llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", - "llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", - "llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", - "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", - "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", - "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", - "llvm.x86.avx512.mask.permvar.df.256" => "__builtin_ia32_permvardf256_mask", - "llvm.x86.avx512.mask.permvar.df.512" => "__builtin_ia32_permvardf512_mask", - "llvm.x86.avx512.mask.permvar.di.256" => "__builtin_ia32_permvardi256_mask", - "llvm.x86.avx512.mask.permvar.di.512" => "__builtin_ia32_permvardi512_mask", - "llvm.x86.avx512.mask.permvar.hi.128" => "__builtin_ia32_permvarhi128_mask", - "llvm.x86.avx512.mask.permvar.hi.256" => "__builtin_ia32_permvarhi256_mask", - "llvm.x86.avx512.mask.permvar.hi.512" => "__builtin_ia32_permvarhi512_mask", - "llvm.x86.avx512.mask.permvar.qi.128" => "__builtin_ia32_permvarqi128_mask", - "llvm.x86.avx512.mask.permvar.qi.256" => "__builtin_ia32_permvarqi256_mask", - "llvm.x86.avx512.mask.permvar.qi.512" => "__builtin_ia32_permvarqi512_mask", - "llvm.x86.avx512.mask.permvar.sf.256" => "__builtin_ia32_permvarsf256_mask", - "llvm.x86.avx512.mask.permvar.sf.512" => "__builtin_ia32_permvarsf512_mask", - "llvm.x86.avx512.mask.permvar.si.256" => "__builtin_ia32_permvarsi256_mask", - "llvm.x86.avx512.mask.permvar.si.512" => "__builtin_ia32_permvarsi512_mask", - "llvm.x86.avx512.mask.pmaddubs.w.128" => "__builtin_ia32_pmaddubsw128_mask", - "llvm.x86.avx512.mask.pmaddubs.w.256" => "__builtin_ia32_pmaddubsw256_mask", - "llvm.x86.avx512.mask.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512_mask", - "llvm.x86.avx512.mask.pmaddw.d.128" => "__builtin_ia32_pmaddwd128_mask", - "llvm.x86.avx512.mask.pmaddw.d.256" => "__builtin_ia32_pmaddwd256_mask", - "llvm.x86.avx512.mask.pmaddw.d.512" => "__builtin_ia32_pmaddwd512_mask", - "llvm.x86.avx512.mask.pmaxs.b.128" => "__builtin_ia32_pmaxsb128_mask", - "llvm.x86.avx512.mask.pmaxs.b.256" => "__builtin_ia32_pmaxsb256_mask", - "llvm.x86.avx512.mask.pmaxs.b.512" => "__builtin_ia32_pmaxsb512_mask", - "llvm.x86.avx512.mask.pmaxs.d.128" => "__builtin_ia32_pmaxsd128_mask", - "llvm.x86.avx512.mask.pmaxs.d.256" => "__builtin_ia32_pmaxsd256_mask", - "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", - "llvm.x86.avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask", - "llvm.x86.avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask", - "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", - "llvm.x86.avx512.mask.pmaxs.w.128" => "__builtin_ia32_pmaxsw128_mask", - "llvm.x86.avx512.mask.pmaxs.w.256" => "__builtin_ia32_pmaxsw256_mask", - "llvm.x86.avx512.mask.pmaxs.w.512" => "__builtin_ia32_pmaxsw512_mask", - "llvm.x86.avx512.mask.pmaxu.b.128" => "__builtin_ia32_pmaxub128_mask", - "llvm.x86.avx512.mask.pmaxu.b.256" => "__builtin_ia32_pmaxub256_mask", - "llvm.x86.avx512.mask.pmaxu.b.512" => "__builtin_ia32_pmaxub512_mask", - "llvm.x86.avx512.mask.pmaxu.d.128" => "__builtin_ia32_pmaxud128_mask", - "llvm.x86.avx512.mask.pmaxu.d.256" => "__builtin_ia32_pmaxud256_mask", - "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", - "llvm.x86.avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask", - "llvm.x86.avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask", - "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", - "llvm.x86.avx512.mask.pmaxu.w.128" => "__builtin_ia32_pmaxuw128_mask", - "llvm.x86.avx512.mask.pmaxu.w.256" => "__builtin_ia32_pmaxuw256_mask", - "llvm.x86.avx512.mask.pmaxu.w.512" => "__builtin_ia32_pmaxuw512_mask", - "llvm.x86.avx512.mask.pmins.b.128" => "__builtin_ia32_pminsb128_mask", - "llvm.x86.avx512.mask.pmins.b.256" => "__builtin_ia32_pminsb256_mask", - "llvm.x86.avx512.mask.pmins.b.512" => "__builtin_ia32_pminsb512_mask", - "llvm.x86.avx512.mask.pmins.d.128" => "__builtin_ia32_pminsd128_mask", - "llvm.x86.avx512.mask.pmins.d.256" => "__builtin_ia32_pminsd256_mask", - "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", - "llvm.x86.avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask", - "llvm.x86.avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask", - "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", - "llvm.x86.avx512.mask.pmins.w.128" => "__builtin_ia32_pminsw128_mask", - "llvm.x86.avx512.mask.pmins.w.256" => "__builtin_ia32_pminsw256_mask", - "llvm.x86.avx512.mask.pmins.w.512" => "__builtin_ia32_pminsw512_mask", - "llvm.x86.avx512.mask.pminu.b.128" => "__builtin_ia32_pminub128_mask", - "llvm.x86.avx512.mask.pminu.b.256" => "__builtin_ia32_pminub256_mask", - "llvm.x86.avx512.mask.pminu.b.512" => "__builtin_ia32_pminub512_mask", - "llvm.x86.avx512.mask.pminu.d.128" => "__builtin_ia32_pminud128_mask", - "llvm.x86.avx512.mask.pminu.d.256" => "__builtin_ia32_pminud256_mask", - "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", - "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask", - "llvm.x86.avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask", - "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", - "llvm.x86.avx512.mask.pminu.w.128" => "__builtin_ia32_pminuw128_mask", - "llvm.x86.avx512.mask.pminu.w.256" => "__builtin_ia32_pminuw256_mask", - "llvm.x86.avx512.mask.pminu.w.512" => "__builtin_ia32_pminuw512_mask", - "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", - "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", - "llvm.x86.avx512.mask.pmov.db.512" => "__builtin_ia32_pmovdb512_mask", - "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", - "llvm.x86.avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask", - "llvm.x86.avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask", - "llvm.x86.avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask", - "llvm.x86.avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask", - "llvm.x86.avx512.mask.pmov.dw.512" => "__builtin_ia32_pmovdw512_mask", - "llvm.x86.avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask", - "llvm.x86.avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask", - "llvm.x86.avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask", - "llvm.x86.avx512.mask.pmov.qb.128" => "__builtin_ia32_pmovqb128_mask", - "llvm.x86.avx512.mask.pmov.qb.256" => "__builtin_ia32_pmovqb256_mask", - "llvm.x86.avx512.mask.pmov.qb.512" => "__builtin_ia32_pmovqb512_mask", - "llvm.x86.avx512.mask.pmov.qb.mem.128" => "__builtin_ia32_pmovqb128mem_mask", - "llvm.x86.avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask", - "llvm.x86.avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask", - "llvm.x86.avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask", - "llvm.x86.avx512.mask.pmov.qd.256" => "__builtin_ia32_pmovqd256_mask", - "llvm.x86.avx512.mask.pmov.qd.512" => "__builtin_ia32_pmovqd512_mask", - "llvm.x86.avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask", - "llvm.x86.avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask", - "llvm.x86.avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask", - "llvm.x86.avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask", - "llvm.x86.avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask", - "llvm.x86.avx512.mask.pmov.qw.512" => "__builtin_ia32_pmovqw512_mask", - "llvm.x86.avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask", - "llvm.x86.avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask", - "llvm.x86.avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask", - "llvm.x86.avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask", - "llvm.x86.avx512.mask.pmov.wb.256" => "__builtin_ia32_pmovwb256_mask", - "llvm.x86.avx512.mask.pmov.wb.512" => "__builtin_ia32_pmovwb512_mask", - "llvm.x86.avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask", - "llvm.x86.avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask", - "llvm.x86.avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask", - "llvm.x86.avx512.mask.pmovs.db.128" => "__builtin_ia32_pmovsdb128_mask", - "llvm.x86.avx512.mask.pmovs.db.256" => "__builtin_ia32_pmovsdb256_mask", - "llvm.x86.avx512.mask.pmovs.db.512" => "__builtin_ia32_pmovsdb512_mask", - "llvm.x86.avx512.mask.pmovs.db.mem.128" => "__builtin_ia32_pmovsdb128mem_mask", - "llvm.x86.avx512.mask.pmovs.db.mem.256" => "__builtin_ia32_pmovsdb256mem_mask", - "llvm.x86.avx512.mask.pmovs.db.mem.512" => "__builtin_ia32_pmovsdb512mem_mask", - "llvm.x86.avx512.mask.pmovs.dw.128" => "__builtin_ia32_pmovsdw128_mask", - "llvm.x86.avx512.mask.pmovs.dw.256" => "__builtin_ia32_pmovsdw256_mask", - "llvm.x86.avx512.mask.pmovs.dw.512" => "__builtin_ia32_pmovsdw512_mask", - "llvm.x86.avx512.mask.pmovs.dw.mem.128" => "__builtin_ia32_pmovsdw128mem_mask", - "llvm.x86.avx512.mask.pmovs.dw.mem.256" => "__builtin_ia32_pmovsdw256mem_mask", - "llvm.x86.avx512.mask.pmovs.dw.mem.512" => "__builtin_ia32_pmovsdw512mem_mask", - "llvm.x86.avx512.mask.pmovs.qb.128" => "__builtin_ia32_pmovsqb128_mask", - "llvm.x86.avx512.mask.pmovs.qb.256" => "__builtin_ia32_pmovsqb256_mask", - "llvm.x86.avx512.mask.pmovs.qb.512" => "__builtin_ia32_pmovsqb512_mask", - "llvm.x86.avx512.mask.pmovs.qb.mem.128" => "__builtin_ia32_pmovsqb128mem_mask", - "llvm.x86.avx512.mask.pmovs.qb.mem.256" => "__builtin_ia32_pmovsqb256mem_mask", - "llvm.x86.avx512.mask.pmovs.qb.mem.512" => "__builtin_ia32_pmovsqb512mem_mask", - "llvm.x86.avx512.mask.pmovs.qd.128" => "__builtin_ia32_pmovsqd128_mask", - "llvm.x86.avx512.mask.pmovs.qd.256" => "__builtin_ia32_pmovsqd256_mask", - "llvm.x86.avx512.mask.pmovs.qd.512" => "__builtin_ia32_pmovsqd512_mask", - "llvm.x86.avx512.mask.pmovs.qd.mem.128" => "__builtin_ia32_pmovsqd128mem_mask", - "llvm.x86.avx512.mask.pmovs.qd.mem.256" => "__builtin_ia32_pmovsqd256mem_mask", - "llvm.x86.avx512.mask.pmovs.qd.mem.512" => "__builtin_ia32_pmovsqd512mem_mask", - "llvm.x86.avx512.mask.pmovs.qw.128" => "__builtin_ia32_pmovsqw128_mask", - "llvm.x86.avx512.mask.pmovs.qw.256" => "__builtin_ia32_pmovsqw256_mask", - "llvm.x86.avx512.mask.pmovs.qw.512" => "__builtin_ia32_pmovsqw512_mask", - "llvm.x86.avx512.mask.pmovs.qw.mem.128" => "__builtin_ia32_pmovsqw128mem_mask", - "llvm.x86.avx512.mask.pmovs.qw.mem.256" => "__builtin_ia32_pmovsqw256mem_mask", - "llvm.x86.avx512.mask.pmovs.qw.mem.512" => "__builtin_ia32_pmovsqw512mem_mask", - "llvm.x86.avx512.mask.pmovs.wb.128" => "__builtin_ia32_pmovswb128_mask", - "llvm.x86.avx512.mask.pmovs.wb.256" => "__builtin_ia32_pmovswb256_mask", - "llvm.x86.avx512.mask.pmovs.wb.512" => "__builtin_ia32_pmovswb512_mask", - "llvm.x86.avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask", - "llvm.x86.avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask", - "llvm.x86.avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask", - "llvm.x86.avx512.mask.pmovsxb.d.128" => "__builtin_ia32_pmovsxbd128_mask", - "llvm.x86.avx512.mask.pmovsxb.d.256" => "__builtin_ia32_pmovsxbd256_mask", - "llvm.x86.avx512.mask.pmovsxb.d.512" => "__builtin_ia32_pmovsxbd512_mask", - "llvm.x86.avx512.mask.pmovsxb.q.128" => "__builtin_ia32_pmovsxbq128_mask", - "llvm.x86.avx512.mask.pmovsxb.q.256" => "__builtin_ia32_pmovsxbq256_mask", - "llvm.x86.avx512.mask.pmovsxb.q.512" => "__builtin_ia32_pmovsxbq512_mask", - "llvm.x86.avx512.mask.pmovsxb.w.128" => "__builtin_ia32_pmovsxbw128_mask", - "llvm.x86.avx512.mask.pmovsxb.w.256" => "__builtin_ia32_pmovsxbw256_mask", - "llvm.x86.avx512.mask.pmovsxb.w.512" => "__builtin_ia32_pmovsxbw512_mask", - "llvm.x86.avx512.mask.pmovsxd.q.128" => "__builtin_ia32_pmovsxdq128_mask", - "llvm.x86.avx512.mask.pmovsxd.q.256" => "__builtin_ia32_pmovsxdq256_mask", - "llvm.x86.avx512.mask.pmovsxd.q.512" => "__builtin_ia32_pmovsxdq512_mask", - "llvm.x86.avx512.mask.pmovsxw.d.128" => "__builtin_ia32_pmovsxwd128_mask", - "llvm.x86.avx512.mask.pmovsxw.d.256" => "__builtin_ia32_pmovsxwd256_mask", - "llvm.x86.avx512.mask.pmovsxw.d.512" => "__builtin_ia32_pmovsxwd512_mask", - "llvm.x86.avx512.mask.pmovsxw.q.128" => "__builtin_ia32_pmovsxwq128_mask", - "llvm.x86.avx512.mask.pmovsxw.q.256" => "__builtin_ia32_pmovsxwq256_mask", - "llvm.x86.avx512.mask.pmovsxw.q.512" => "__builtin_ia32_pmovsxwq512_mask", - "llvm.x86.avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask", - "llvm.x86.avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask", - "llvm.x86.avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask", - "llvm.x86.avx512.mask.pmovus.db.mem.128" => "__builtin_ia32_pmovusdb128mem_mask", - "llvm.x86.avx512.mask.pmovus.db.mem.256" => "__builtin_ia32_pmovusdb256mem_mask", - "llvm.x86.avx512.mask.pmovus.db.mem.512" => "__builtin_ia32_pmovusdb512mem_mask", - "llvm.x86.avx512.mask.pmovus.dw.128" => "__builtin_ia32_pmovusdw128_mask", - "llvm.x86.avx512.mask.pmovus.dw.256" => "__builtin_ia32_pmovusdw256_mask", - "llvm.x86.avx512.mask.pmovus.dw.512" => "__builtin_ia32_pmovusdw512_mask", - "llvm.x86.avx512.mask.pmovus.dw.mem.128" => "__builtin_ia32_pmovusdw128mem_mask", - "llvm.x86.avx512.mask.pmovus.dw.mem.256" => "__builtin_ia32_pmovusdw256mem_mask", - "llvm.x86.avx512.mask.pmovus.dw.mem.512" => "__builtin_ia32_pmovusdw512mem_mask", - "llvm.x86.avx512.mask.pmovus.qb.128" => "__builtin_ia32_pmovusqb128_mask", - "llvm.x86.avx512.mask.pmovus.qb.256" => "__builtin_ia32_pmovusqb256_mask", - "llvm.x86.avx512.mask.pmovus.qb.512" => "__builtin_ia32_pmovusqb512_mask", - "llvm.x86.avx512.mask.pmovus.qb.mem.128" => "__builtin_ia32_pmovusqb128mem_mask", - "llvm.x86.avx512.mask.pmovus.qb.mem.256" => "__builtin_ia32_pmovusqb256mem_mask", - "llvm.x86.avx512.mask.pmovus.qb.mem.512" => "__builtin_ia32_pmovusqb512mem_mask", - "llvm.x86.avx512.mask.pmovus.qd.128" => "__builtin_ia32_pmovusqd128_mask", - "llvm.x86.avx512.mask.pmovus.qd.256" => "__builtin_ia32_pmovusqd256_mask", - "llvm.x86.avx512.mask.pmovus.qd.512" => "__builtin_ia32_pmovusqd512_mask", - "llvm.x86.avx512.mask.pmovus.qd.mem.128" => "__builtin_ia32_pmovusqd128mem_mask", - "llvm.x86.avx512.mask.pmovus.qd.mem.256" => "__builtin_ia32_pmovusqd256mem_mask", - "llvm.x86.avx512.mask.pmovus.qd.mem.512" => "__builtin_ia32_pmovusqd512mem_mask", - "llvm.x86.avx512.mask.pmovus.qw.128" => "__builtin_ia32_pmovusqw128_mask", - "llvm.x86.avx512.mask.pmovus.qw.256" => "__builtin_ia32_pmovusqw256_mask", - "llvm.x86.avx512.mask.pmovus.qw.512" => "__builtin_ia32_pmovusqw512_mask", - "llvm.x86.avx512.mask.pmovus.qw.mem.128" => "__builtin_ia32_pmovusqw128mem_mask", - "llvm.x86.avx512.mask.pmovus.qw.mem.256" => "__builtin_ia32_pmovusqw256mem_mask", - "llvm.x86.avx512.mask.pmovus.qw.mem.512" => "__builtin_ia32_pmovusqw512mem_mask", - "llvm.x86.avx512.mask.pmovus.wb.128" => "__builtin_ia32_pmovuswb128_mask", - "llvm.x86.avx512.mask.pmovus.wb.256" => "__builtin_ia32_pmovuswb256_mask", - "llvm.x86.avx512.mask.pmovus.wb.512" => "__builtin_ia32_pmovuswb512_mask", - "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", - "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", - "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", - "llvm.x86.avx512.mask.pmovzxb.d.128" => "__builtin_ia32_pmovzxbd128_mask", - "llvm.x86.avx512.mask.pmovzxb.d.256" => "__builtin_ia32_pmovzxbd256_mask", - "llvm.x86.avx512.mask.pmovzxb.d.512" => "__builtin_ia32_pmovzxbd512_mask", - "llvm.x86.avx512.mask.pmovzxb.q.128" => "__builtin_ia32_pmovzxbq128_mask", - "llvm.x86.avx512.mask.pmovzxb.q.256" => "__builtin_ia32_pmovzxbq256_mask", - "llvm.x86.avx512.mask.pmovzxb.q.512" => "__builtin_ia32_pmovzxbq512_mask", - "llvm.x86.avx512.mask.pmovzxb.w.128" => "__builtin_ia32_pmovzxbw128_mask", - "llvm.x86.avx512.mask.pmovzxb.w.256" => "__builtin_ia32_pmovzxbw256_mask", - "llvm.x86.avx512.mask.pmovzxb.w.512" => "__builtin_ia32_pmovzxbw512_mask", - "llvm.x86.avx512.mask.pmovzxd.q.128" => "__builtin_ia32_pmovzxdq128_mask", - "llvm.x86.avx512.mask.pmovzxd.q.256" => "__builtin_ia32_pmovzxdq256_mask", - "llvm.x86.avx512.mask.pmovzxd.q.512" => "__builtin_ia32_pmovzxdq512_mask", - "llvm.x86.avx512.mask.pmovzxw.d.128" => "__builtin_ia32_pmovzxwd128_mask", - "llvm.x86.avx512.mask.pmovzxw.d.256" => "__builtin_ia32_pmovzxwd256_mask", - "llvm.x86.avx512.mask.pmovzxw.d.512" => "__builtin_ia32_pmovzxwd512_mask", - "llvm.x86.avx512.mask.pmovzxw.q.128" => "__builtin_ia32_pmovzxwq128_mask", - "llvm.x86.avx512.mask.pmovzxw.q.256" => "__builtin_ia32_pmovzxwq256_mask", - "llvm.x86.avx512.mask.pmovzxw.q.512" => "__builtin_ia32_pmovzxwq512_mask", - "llvm.x86.avx512.mask.pmul.dq.128" => "__builtin_ia32_pmuldq128_mask", - "llvm.x86.avx512.mask.pmul.dq.256" => "__builtin_ia32_pmuldq256_mask", - "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", - "llvm.x86.avx512.mask.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128_mask", - "llvm.x86.avx512.mask.pmul.hr.sw.256" => "__builtin_ia32_pmulhrsw256_mask", - "llvm.x86.avx512.mask.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask", - "llvm.x86.avx512.mask.pmulh.w.128" => "__builtin_ia32_pmulhw128_mask", - "llvm.x86.avx512.mask.pmulh.w.256" => "__builtin_ia32_pmulhw256_mask", - "llvm.x86.avx512.mask.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask", - "llvm.x86.avx512.mask.pmulhu.w.128" => "__builtin_ia32_pmulhuw128_mask", - "llvm.x86.avx512.mask.pmulhu.w.256" => "__builtin_ia32_pmulhuw256_mask", - "llvm.x86.avx512.mask.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask", - "llvm.x86.avx512.mask.pmull.d.128" => "__builtin_ia32_pmulld128_mask", - "llvm.x86.avx512.mask.pmull.d.256" => "__builtin_ia32_pmulld256_mask", - "llvm.x86.avx512.mask.pmull.d.512" => "__builtin_ia32_pmulld512_mask", - "llvm.x86.avx512.mask.pmull.q.128" => "__builtin_ia32_pmullq128_mask", - "llvm.x86.avx512.mask.pmull.q.256" => "__builtin_ia32_pmullq256_mask", - "llvm.x86.avx512.mask.pmull.q.512" => "__builtin_ia32_pmullq512_mask", - "llvm.x86.avx512.mask.pmull.w.128" => "__builtin_ia32_pmullw128_mask", - "llvm.x86.avx512.mask.pmull.w.256" => "__builtin_ia32_pmullw256_mask", - "llvm.x86.avx512.mask.pmull.w.512" => "__builtin_ia32_pmullw512_mask", - "llvm.x86.avx512.mask.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask", - "llvm.x86.avx512.mask.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask", - "llvm.x86.avx512.mask.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask", - "llvm.x86.avx512.mask.pmulu.dq.128" => "__builtin_ia32_pmuludq128_mask", - "llvm.x86.avx512.mask.pmulu.dq.256" => "__builtin_ia32_pmuludq256_mask", - "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", - "llvm.x86.avx512.mask.prol.d.128" => "__builtin_ia32_prold128_mask", - "llvm.x86.avx512.mask.prol.d.256" => "__builtin_ia32_prold256_mask", - "llvm.x86.avx512.mask.prol.d.512" => "__builtin_ia32_prold512_mask", - "llvm.x86.avx512.mask.prol.q.128" => "__builtin_ia32_prolq128_mask", - "llvm.x86.avx512.mask.prol.q.256" => "__builtin_ia32_prolq256_mask", - "llvm.x86.avx512.mask.prol.q.512" => "__builtin_ia32_prolq512_mask", - "llvm.x86.avx512.mask.prolv.d.128" => "__builtin_ia32_prolvd128_mask", - "llvm.x86.avx512.mask.prolv.d.256" => "__builtin_ia32_prolvd256_mask", - "llvm.x86.avx512.mask.prolv.d.512" => "__builtin_ia32_prolvd512_mask", - "llvm.x86.avx512.mask.prolv.q.128" => "__builtin_ia32_prolvq128_mask", - "llvm.x86.avx512.mask.prolv.q.256" => "__builtin_ia32_prolvq256_mask", - "llvm.x86.avx512.mask.prolv.q.512" => "__builtin_ia32_prolvq512_mask", - "llvm.x86.avx512.mask.pror.d.128" => "__builtin_ia32_prord128_mask", - "llvm.x86.avx512.mask.pror.d.256" => "__builtin_ia32_prord256_mask", - "llvm.x86.avx512.mask.pror.d.512" => "__builtin_ia32_prord512_mask", - "llvm.x86.avx512.mask.pror.q.128" => "__builtin_ia32_prorq128_mask", - "llvm.x86.avx512.mask.pror.q.256" => "__builtin_ia32_prorq256_mask", - "llvm.x86.avx512.mask.pror.q.512" => "__builtin_ia32_prorq512_mask", - "llvm.x86.avx512.mask.prorv.d.128" => "__builtin_ia32_prorvd128_mask", - "llvm.x86.avx512.mask.prorv.d.256" => "__builtin_ia32_prorvd256_mask", - "llvm.x86.avx512.mask.prorv.d.512" => "__builtin_ia32_prorvd512_mask", - "llvm.x86.avx512.mask.prorv.q.128" => "__builtin_ia32_prorvq128_mask", - "llvm.x86.avx512.mask.prorv.q.256" => "__builtin_ia32_prorvq256_mask", - "llvm.x86.avx512.mask.prorv.q.512" => "__builtin_ia32_prorvq512_mask", - "llvm.x86.avx512.mask.pshuf.b.128" => "__builtin_ia32_pshufb128_mask", - "llvm.x86.avx512.mask.pshuf.b.256" => "__builtin_ia32_pshufb256_mask", - "llvm.x86.avx512.mask.pshuf.b.512" => "__builtin_ia32_pshufb512_mask", - "llvm.x86.avx512.mask.psll.d" => "__builtin_ia32_pslld512_mask", - "llvm.x86.avx512.mask.psll.d.128" => "__builtin_ia32_pslld128_mask", - "llvm.x86.avx512.mask.psll.d.256" => "__builtin_ia32_pslld256_mask", - "llvm.x86.avx512.mask.psll.di.128" => "__builtin_ia32_pslldi128_mask", - "llvm.x86.avx512.mask.psll.di.256" => "__builtin_ia32_pslldi256_mask", - "llvm.x86.avx512.mask.psll.di.512" => "__builtin_ia32_pslldi512_mask", - "llvm.x86.avx512.mask.psll.q" => "__builtin_ia32_psllq512_mask", - "llvm.x86.avx512.mask.psll.q.128" => "__builtin_ia32_psllq128_mask", - "llvm.x86.avx512.mask.psll.q.256" => "__builtin_ia32_psllq256_mask", - "llvm.x86.avx512.mask.psll.qi.128" => "__builtin_ia32_psllqi128_mask", - "llvm.x86.avx512.mask.psll.qi.256" => "__builtin_ia32_psllqi256_mask", - "llvm.x86.avx512.mask.psll.qi.512" => "__builtin_ia32_psllqi512_mask", - "llvm.x86.avx512.mask.psll.w.128" => "__builtin_ia32_psllw128_mask", - "llvm.x86.avx512.mask.psll.w.256" => "__builtin_ia32_psllw256_mask", - "llvm.x86.avx512.mask.psll.w.512" => "__builtin_ia32_psllw512_mask", - "llvm.x86.avx512.mask.psll.wi.128" => "__builtin_ia32_psllwi128_mask", - "llvm.x86.avx512.mask.psll.wi.256" => "__builtin_ia32_psllwi256_mask", - "llvm.x86.avx512.mask.psll.wi.512" => "__builtin_ia32_psllwi512_mask", - "llvm.x86.avx512.mask.psllv.d" => "__builtin_ia32_psllv16si_mask", - "llvm.x86.avx512.mask.psllv.q" => "__builtin_ia32_psllv8di_mask", - "llvm.x86.avx512.mask.psllv16.hi" => "__builtin_ia32_psllv16hi_mask", - "llvm.x86.avx512.mask.psllv2.di" => "__builtin_ia32_psllv2di_mask", - "llvm.x86.avx512.mask.psllv32hi" => "__builtin_ia32_psllv32hi_mask", - "llvm.x86.avx512.mask.psllv4.di" => "__builtin_ia32_psllv4di_mask", - "llvm.x86.avx512.mask.psllv4.si" => "__builtin_ia32_psllv4si_mask", - "llvm.x86.avx512.mask.psllv8.hi" => "__builtin_ia32_psllv8hi_mask", - "llvm.x86.avx512.mask.psllv8.si" => "__builtin_ia32_psllv8si_mask", - "llvm.x86.avx512.mask.psra.d" => "__builtin_ia32_psrad512_mask", - "llvm.x86.avx512.mask.psra.d.128" => "__builtin_ia32_psrad128_mask", - "llvm.x86.avx512.mask.psra.d.256" => "__builtin_ia32_psrad256_mask", - "llvm.x86.avx512.mask.psra.di.128" => "__builtin_ia32_psradi128_mask", - "llvm.x86.avx512.mask.psra.di.256" => "__builtin_ia32_psradi256_mask", - "llvm.x86.avx512.mask.psra.di.512" => "__builtin_ia32_psradi512_mask", - "llvm.x86.avx512.mask.psra.q" => "__builtin_ia32_psraq512_mask", - "llvm.x86.avx512.mask.psra.q.128" => "__builtin_ia32_psraq128_mask", - "llvm.x86.avx512.mask.psra.q.256" => "__builtin_ia32_psraq256_mask", - "llvm.x86.avx512.mask.psra.qi.128" => "__builtin_ia32_psraqi128_mask", - "llvm.x86.avx512.mask.psra.qi.256" => "__builtin_ia32_psraqi256_mask", - "llvm.x86.avx512.mask.psra.qi.512" => "__builtin_ia32_psraqi512_mask", - "llvm.x86.avx512.mask.psra.w.128" => "__builtin_ia32_psraw128_mask", - "llvm.x86.avx512.mask.psra.w.256" => "__builtin_ia32_psraw256_mask", - "llvm.x86.avx512.mask.psra.w.512" => "__builtin_ia32_psraw512_mask", - "llvm.x86.avx512.mask.psra.wi.128" => "__builtin_ia32_psrawi128_mask", - "llvm.x86.avx512.mask.psra.wi.256" => "__builtin_ia32_psrawi256_mask", - "llvm.x86.avx512.mask.psra.wi.512" => "__builtin_ia32_psrawi512_mask", - "llvm.x86.avx512.mask.psrav.d" => "__builtin_ia32_psrav16si_mask", - "llvm.x86.avx512.mask.psrav.q" => "__builtin_ia32_psrav8di_mask", - "llvm.x86.avx512.mask.psrav.q.128" => "__builtin_ia32_psravq128_mask", - "llvm.x86.avx512.mask.psrav.q.256" => "__builtin_ia32_psravq256_mask", - "llvm.x86.avx512.mask.psrav16.hi" => "__builtin_ia32_psrav16hi_mask", - "llvm.x86.avx512.mask.psrav32.hi" => "__builtin_ia32_psrav32hi_mask", - "llvm.x86.avx512.mask.psrav4.si" => "__builtin_ia32_psrav4si_mask", - "llvm.x86.avx512.mask.psrav8.hi" => "__builtin_ia32_psrav8hi_mask", - "llvm.x86.avx512.mask.psrav8.si" => "__builtin_ia32_psrav8si_mask", - "llvm.x86.avx512.mask.psrl.d" => "__builtin_ia32_psrld512_mask", - "llvm.x86.avx512.mask.psrl.d.128" => "__builtin_ia32_psrld128_mask", - "llvm.x86.avx512.mask.psrl.d.256" => "__builtin_ia32_psrld256_mask", - "llvm.x86.avx512.mask.psrl.di.128" => "__builtin_ia32_psrldi128_mask", - "llvm.x86.avx512.mask.psrl.di.256" => "__builtin_ia32_psrldi256_mask", - "llvm.x86.avx512.mask.psrl.di.512" => "__builtin_ia32_psrldi512_mask", - "llvm.x86.avx512.mask.psrl.q" => "__builtin_ia32_psrlq512_mask", - "llvm.x86.avx512.mask.psrl.q.128" => "__builtin_ia32_psrlq128_mask", - "llvm.x86.avx512.mask.psrl.q.256" => "__builtin_ia32_psrlq256_mask", - "llvm.x86.avx512.mask.psrl.qi.128" => "__builtin_ia32_psrlqi128_mask", - "llvm.x86.avx512.mask.psrl.qi.256" => "__builtin_ia32_psrlqi256_mask", - "llvm.x86.avx512.mask.psrl.qi.512" => "__builtin_ia32_psrlqi512_mask", - "llvm.x86.avx512.mask.psrl.w.128" => "__builtin_ia32_psrlw128_mask", - "llvm.x86.avx512.mask.psrl.w.256" => "__builtin_ia32_psrlw256_mask", - "llvm.x86.avx512.mask.psrl.w.512" => "__builtin_ia32_psrlw512_mask", - "llvm.x86.avx512.mask.psrl.wi.128" => "__builtin_ia32_psrlwi128_mask", - "llvm.x86.avx512.mask.psrl.wi.256" => "__builtin_ia32_psrlwi256_mask", - "llvm.x86.avx512.mask.psrl.wi.512" => "__builtin_ia32_psrlwi512_mask", - "llvm.x86.avx512.mask.psrlv.d" => "__builtin_ia32_psrlv16si_mask", - "llvm.x86.avx512.mask.psrlv.q" => "__builtin_ia32_psrlv8di_mask", - "llvm.x86.avx512.mask.psrlv16.hi" => "__builtin_ia32_psrlv16hi_mask", - "llvm.x86.avx512.mask.psrlv2.di" => "__builtin_ia32_psrlv2di_mask", - "llvm.x86.avx512.mask.psrlv32hi" => "__builtin_ia32_psrlv32hi_mask", - "llvm.x86.avx512.mask.psrlv4.di" => "__builtin_ia32_psrlv4di_mask", - "llvm.x86.avx512.mask.psrlv4.si" => "__builtin_ia32_psrlv4si_mask", - "llvm.x86.avx512.mask.psrlv8.hi" => "__builtin_ia32_psrlv8hi_mask", - "llvm.x86.avx512.mask.psrlv8.si" => "__builtin_ia32_psrlv8si_mask", - "llvm.x86.avx512.mask.psub.b.128" => "__builtin_ia32_psubb128_mask", - "llvm.x86.avx512.mask.psub.b.256" => "__builtin_ia32_psubb256_mask", - "llvm.x86.avx512.mask.psub.b.512" => "__builtin_ia32_psubb512_mask", - "llvm.x86.avx512.mask.psub.d.128" => "__builtin_ia32_psubd128_mask", - "llvm.x86.avx512.mask.psub.d.256" => "__builtin_ia32_psubd256_mask", - "llvm.x86.avx512.mask.psub.d.512" => "__builtin_ia32_psubd512_mask", - "llvm.x86.avx512.mask.psub.q.128" => "__builtin_ia32_psubq128_mask", - "llvm.x86.avx512.mask.psub.q.256" => "__builtin_ia32_psubq256_mask", - "llvm.x86.avx512.mask.psub.q.512" => "__builtin_ia32_psubq512_mask", - "llvm.x86.avx512.mask.psub.w.128" => "__builtin_ia32_psubw128_mask", - "llvm.x86.avx512.mask.psub.w.256" => "__builtin_ia32_psubw256_mask", - "llvm.x86.avx512.mask.psub.w.512" => "__builtin_ia32_psubw512_mask", - "llvm.x86.avx512.mask.psubs.b.128" => "__builtin_ia32_psubsb128_mask", - "llvm.x86.avx512.mask.psubs.b.256" => "__builtin_ia32_psubsb256_mask", - "llvm.x86.avx512.mask.psubs.b.512" => "__builtin_ia32_psubsb512_mask", - "llvm.x86.avx512.mask.psubs.w.128" => "__builtin_ia32_psubsw128_mask", - "llvm.x86.avx512.mask.psubs.w.256" => "__builtin_ia32_psubsw256_mask", - "llvm.x86.avx512.mask.psubs.w.512" => "__builtin_ia32_psubsw512_mask", - "llvm.x86.avx512.mask.psubus.b.128" => "__builtin_ia32_psubusb128_mask", - "llvm.x86.avx512.mask.psubus.b.256" => "__builtin_ia32_psubusb256_mask", - "llvm.x86.avx512.mask.psubus.b.512" => "__builtin_ia32_psubusb512_mask", - "llvm.x86.avx512.mask.psubus.w.128" => "__builtin_ia32_psubusw128_mask", - "llvm.x86.avx512.mask.psubus.w.256" => "__builtin_ia32_psubusw256_mask", - "llvm.x86.avx512.mask.psubus.w.512" => "__builtin_ia32_psubusw512_mask", - "llvm.x86.avx512.mask.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask", - "llvm.x86.avx512.mask.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask", - "llvm.x86.avx512.mask.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask", - "llvm.x86.avx512.mask.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask", - "llvm.x86.avx512.mask.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask", - "llvm.x86.avx512.mask.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask", - "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", - "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", - "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", - "llvm.x86.avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask", - "llvm.x86.avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask", - "llvm.x86.avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask", - "llvm.x86.avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask", - "llvm.x86.avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask", - "llvm.x86.avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask", - "llvm.x86.avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask", - "llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask", - "llvm.x86.avx512.mask.reduce.ps.128" => "__builtin_ia32_reduceps128_mask", - "llvm.x86.avx512.mask.reduce.ps.256" => "__builtin_ia32_reduceps256_mask", - "llvm.x86.avx512.mask.reduce.ps.512" => "__builtin_ia32_reduceps512_mask", - "llvm.x86.avx512.mask.reduce.sd" => "__builtin_ia32_reducesd_mask", - "llvm.x86.avx512.mask.reduce.ss" => "__builtin_ia32_reducess_mask", - "llvm.x86.avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask", - "llvm.x86.avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask", - "llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", - "llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask", - "llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask", - "llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask", - "llvm.x86.avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask", - "llvm.x86.avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask", - "llvm.x86.avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask", - "llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask", - "llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask", - "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", - "llvm.x86.avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask", - "llvm.x86.avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask", - "llvm.x86.avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask", - "llvm.x86.avx512.mask.shuf.f64x2.256" => "__builtin_ia32_shuf_f64x2_256_mask", - "llvm.x86.avx512.mask.shuf.i32x4" => "__builtin_ia32_shuf_i32x4_mask", - "llvm.x86.avx512.mask.shuf.i32x4.256" => "__builtin_ia32_shuf_i32x4_256_mask", - "llvm.x86.avx512.mask.shuf.i64x2" => "__builtin_ia32_shuf_i64x2_mask", - "llvm.x86.avx512.mask.shuf.i64x2.256" => "__builtin_ia32_shuf_i64x2_256_mask", - "llvm.x86.avx512.mask.shuf.pd.128" => "__builtin_ia32_shufpd128_mask", - "llvm.x86.avx512.mask.shuf.pd.256" => "__builtin_ia32_shufpd256_mask", - "llvm.x86.avx512.mask.shuf.pd.512" => "__builtin_ia32_shufpd512_mask", - "llvm.x86.avx512.mask.shuf.ps.128" => "__builtin_ia32_shufps128_mask", - "llvm.x86.avx512.mask.shuf.ps.256" => "__builtin_ia32_shufps256_mask", - "llvm.x86.avx512.mask.shuf.ps.512" => "__builtin_ia32_shufps512_mask", - "llvm.x86.avx512.mask.sqrt.pd.128" => "__builtin_ia32_sqrtpd128_mask", - "llvm.x86.avx512.mask.sqrt.pd.256" => "__builtin_ia32_sqrtpd256_mask", - "llvm.x86.avx512.mask.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", - "llvm.x86.avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask", - "llvm.x86.avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask", - "llvm.x86.avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask", - "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", - "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", - "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", - "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", - "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", - "llvm.x86.avx512.mask.sub.pd.128" => "__builtin_ia32_subpd128_mask", - "llvm.x86.avx512.mask.sub.pd.256" => "__builtin_ia32_subpd256_mask", - "llvm.x86.avx512.mask.sub.pd.512" => "__builtin_ia32_subpd512_mask", - "llvm.x86.avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask", - "llvm.x86.avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask", - "llvm.x86.avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", - "llvm.x86.avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask", - "llvm.x86.avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask", - "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", - "llvm.x86.avx512.mask.valign.q.128" => "__builtin_ia32_alignq128_mask", - "llvm.x86.avx512.mask.valign.q.256" => "__builtin_ia32_alignq256_mask", - "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", - "llvm.x86.avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask", - "llvm.x86.avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask", - "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", - "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", - "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", - "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", - "llvm.x86.avx512.mask.vextractf32x4.256" => "__builtin_ia32_extractf32x4_256_mask", - "llvm.x86.avx512.mask.vextractf32x4.512" => "__builtin_ia32_extractf32x4_mask", - "llvm.x86.avx512.mask.vextractf32x8.512" => "__builtin_ia32_extractf32x8_mask", - "llvm.x86.avx512.mask.vextractf64x2.256" => "__builtin_ia32_extractf64x2_256_mask", - "llvm.x86.avx512.mask.vextractf64x2.512" => "__builtin_ia32_extractf64x2_512_mask", - "llvm.x86.avx512.mask.vextractf64x4.512" => "__builtin_ia32_extractf64x4_mask", - "llvm.x86.avx512.mask.vextracti32x4.256" => "__builtin_ia32_extracti32x4_256_mask", - "llvm.x86.avx512.mask.vextracti32x4.512" => "__builtin_ia32_extracti32x4_mask", - "llvm.x86.avx512.mask.vextracti32x8.512" => "__builtin_ia32_extracti32x8_mask", - "llvm.x86.avx512.mask.vextracti64x2.256" => "__builtin_ia32_extracti64x2_256_mask", - "llvm.x86.avx512.mask.vextracti64x2.512" => "__builtin_ia32_extracti64x2_512_mask", - "llvm.x86.avx512.mask.vextracti64x4.512" => "__builtin_ia32_extracti64x4_mask", - "llvm.x86.avx512.mask.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask", - "llvm.x86.avx512.mask.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask", - "llvm.x86.avx512.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", - "llvm.x86.avx512.mask.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask", - "llvm.x86.avx512.mask.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask", - "llvm.x86.avx512.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", - "llvm.x86.avx512.mask.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask", - "llvm.x86.avx512.mask.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask", - "llvm.x86.avx512.mask.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask", - "llvm.x86.avx512.mask.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask", - "llvm.x86.avx512.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", - "llvm.x86.avx512.mask.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask", - "llvm.x86.avx512.mask.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask", - "llvm.x86.avx512.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", - "llvm.x86.avx512.mask.vfnmadd.pd.128" => "__builtin_ia32_vfnmaddpd128_mask", - "llvm.x86.avx512.mask.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256_mask", - "llvm.x86.avx512.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", - "llvm.x86.avx512.mask.vfnmadd.ps.128" => "__builtin_ia32_vfnmaddps128_mask", - "llvm.x86.avx512.mask.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256_mask", - "llvm.x86.avx512.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", - "llvm.x86.avx512.mask.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask", - "llvm.x86.avx512.mask.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask", - "llvm.x86.avx512.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", - "llvm.x86.avx512.mask.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask", - "llvm.x86.avx512.mask.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask", - "llvm.x86.avx512.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", - "llvm.x86.avx512.mask.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask", - "llvm.x86.avx512.mask.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask", - "llvm.x86.avx512.mask.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask", - "llvm.x86.avx512.mask.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128_mask", - "llvm.x86.avx512.mask.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256_mask", - "llvm.x86.avx512.mask.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512_mask", - "llvm.x86.avx512.mask.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask", - "llvm.x86.avx512.mask.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask", - "llvm.x86.avx512.mask.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask", - "llvm.x86.avx512.mask.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask", - "llvm.x86.avx512.mask.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask", - "llvm.x86.avx512.mask.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask", - "llvm.x86.avx512.mask.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask", - "llvm.x86.avx512.mask.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask", - "llvm.x86.avx512.mask.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask", - "llvm.x86.avx512.mask.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128_mask", - "llvm.x86.avx512.mask.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256_mask", - "llvm.x86.avx512.mask.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512_mask", - "llvm.x86.avx512.mask.vpermilvar.pd.128" => "__builtin_ia32_vpermilvarpd_mask", - "llvm.x86.avx512.mask.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256_mask", - "llvm.x86.avx512.mask.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask", - "llvm.x86.avx512.mask.vpermilvar.ps.128" => "__builtin_ia32_vpermilvarps_mask", - "llvm.x86.avx512.mask.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256_mask", - "llvm.x86.avx512.mask.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask", - "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", - "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", - "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", - "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", - "llvm.x86.avx512.mask.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_mask", - "llvm.x86.avx512.mask.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_mask", - "llvm.x86.avx512.mask.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_mask", - "llvm.x86.avx512.mask.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask", - "llvm.x86.avx512.mask.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask", - "llvm.x86.avx512.mask.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask", - "llvm.x86.avx512.mask.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_mask", - "llvm.x86.avx512.mask.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_mask", - "llvm.x86.avx512.mask.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", - "llvm.x86.avx512.mask.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_mask", - "llvm.x86.avx512.mask.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_mask", - "llvm.x86.avx512.mask.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_mask", - "llvm.x86.avx512.mask.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_mask", - "llvm.x86.avx512.mask.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_mask", - "llvm.x86.avx512.mask.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_mask", - "llvm.x86.avx512.mask.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask", - "llvm.x86.avx512.mask.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask", - "llvm.x86.avx512.mask.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask", - "llvm.x86.avx512.mask.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask", - "llvm.x86.avx512.mask.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask", - "llvm.x86.avx512.mask.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask", - "llvm.x86.avx512.mask.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_mask", - "llvm.x86.avx512.mask.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask", - "llvm.x86.avx512.mask.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask", - "llvm.x86.avx512.mask.xor.pd.128" => "__builtin_ia32_xorpd128_mask", - "llvm.x86.avx512.mask.xor.pd.256" => "__builtin_ia32_xorpd256_mask", - "llvm.x86.avx512.mask.xor.pd.512" => "__builtin_ia32_xorpd512_mask", - "llvm.x86.avx512.mask.xor.ps.128" => "__builtin_ia32_xorps128_mask", - "llvm.x86.avx512.mask.xor.ps.256" => "__builtin_ia32_xorps256_mask", - "llvm.x86.avx512.mask.xor.ps.512" => "__builtin_ia32_xorps512_mask", - "llvm.x86.avx512.mask3.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask3", - "llvm.x86.avx512.mask3.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask3", - "llvm.x86.avx512.mask3.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask3", - "llvm.x86.avx512.mask3.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask3", - "llvm.x86.avx512.mask3.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask3", - "llvm.x86.avx512.mask3.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask3", - "llvm.x86.avx512.mask3.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask3", - "llvm.x86.avx512.mask3.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask3", - "llvm.x86.avx512.mask3.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask3", - "llvm.x86.avx512.mask3.vfmsub.pd.128" => "__builtin_ia32_vfmsubpd128_mask3", - "llvm.x86.avx512.mask3.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256_mask3", - "llvm.x86.avx512.mask3.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask3", - "llvm.x86.avx512.mask3.vfmsub.ps.128" => "__builtin_ia32_vfmsubps128_mask3", - "llvm.x86.avx512.mask3.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256_mask3", - "llvm.x86.avx512.mask3.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.pd.128" => "__builtin_ia32_vfmsubaddpd128_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.ps.128" => "__builtin_ia32_vfmsubaddps128_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256_mask3", - "llvm.x86.avx512.mask3.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask3", - "llvm.x86.avx512.mask3.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask3", - "llvm.x86.avx512.mask3.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask3", - "llvm.x86.avx512.mask3.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask3", - "llvm.x86.avx512.mask3.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask3", - "llvm.x86.avx512.mask3.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask3", - "llvm.x86.avx512.mask3.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask3", - "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", - "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", - "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", - "llvm.x86.avx512.maskz.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_maskz", - "llvm.x86.avx512.maskz.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_maskz", - "llvm.x86.avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz", - "llvm.x86.avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz", - "llvm.x86.avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz", - "llvm.x86.avx512.maskz.pternlog.d.128" => "__builtin_ia32_pternlogd128_maskz", - "llvm.x86.avx512.maskz.pternlog.d.256" => "__builtin_ia32_pternlogd256_maskz", - "llvm.x86.avx512.maskz.pternlog.d.512" => "__builtin_ia32_pternlogd512_maskz", - "llvm.x86.avx512.maskz.pternlog.q.128" => "__builtin_ia32_pternlogq128_maskz", - "llvm.x86.avx512.maskz.pternlog.q.256" => "__builtin_ia32_pternlogq256_maskz", - "llvm.x86.avx512.maskz.pternlog.q.512" => "__builtin_ia32_pternlogq512_maskz", - "llvm.x86.avx512.maskz.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_maskz", - "llvm.x86.avx512.maskz.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_maskz", - "llvm.x86.avx512.maskz.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_maskz", - "llvm.x86.avx512.maskz.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_maskz", - "llvm.x86.avx512.maskz.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_maskz", - "llvm.x86.avx512.maskz.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_maskz", - "llvm.x86.avx512.maskz.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_maskz", - "llvm.x86.avx512.maskz.vfmadd.ss" => "__builtin_ia32_vfmaddss3_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_maskz", - "llvm.x86.avx512.maskz.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_maskz", - "llvm.x86.avx512.maskz.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_maskz", - "llvm.x86.avx512.maskz.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_maskz", - "llvm.x86.avx512.maskz.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_maskz", - "llvm.x86.avx512.maskz.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_maskz", - "llvm.x86.avx512.maskz.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_maskz", - "llvm.x86.avx512.maskz.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_maskz", - "llvm.x86.avx512.maskz.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_maskz", - "llvm.x86.avx512.maskz.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_maskz", - "llvm.x86.avx512.maskz.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_maskz", - "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512", - "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512", - "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512", - "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512", - "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", - "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512", - "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512", - "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512", - "llvm.x86.avx512.packsswb.512" => "__builtin_ia32_packsswb512", - "llvm.x86.avx512.packusdw.512" => "__builtin_ia32_packusdw512", - "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512", - "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512", - "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512", - "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", - "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", - "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256", - "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512", - "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256", - "llvm.x86.avx512.permvar.di.512" => "__builtin_ia32_permvardi512", - "llvm.x86.avx512.permvar.hi.128" => "__builtin_ia32_permvarhi128", - "llvm.x86.avx512.permvar.hi.256" => "__builtin_ia32_permvarhi256", - "llvm.x86.avx512.permvar.hi.512" => "__builtin_ia32_permvarhi512", - "llvm.x86.avx512.permvar.qi.128" => "__builtin_ia32_permvarqi128", - "llvm.x86.avx512.permvar.qi.256" => "__builtin_ia32_permvarqi256", - "llvm.x86.avx512.permvar.qi.512" => "__builtin_ia32_permvarqi512", - "llvm.x86.avx512.permvar.sf.512" => "__builtin_ia32_permvarsf512", - "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512", - "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512", - "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512", - "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", - "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", - "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", - "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", - "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", - "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512", - "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512", - "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512", - "llvm.x86.avx512.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128", - "llvm.x86.avx512.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256", - "llvm.x86.avx512.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512", - "llvm.x86.avx512.psad.bw.512" => "__builtin_ia32_psadbw512", - "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512", - "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512", - "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", - "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", - "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512", - "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512", - "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512", - "llvm.x86.avx512.pslli.q.512" => "__builtin_ia32_psllqi512", - "llvm.x86.avx512.pslli.w.512" => "__builtin_ia32_psllwi512", - "llvm.x86.avx512.psllv.d.512" => "__builtin_ia32_psllv16si", - "llvm.x86.avx512.psllv.q.512" => "__builtin_ia32_psllv8di", - "llvm.x86.avx512.psllv.w.128" => "__builtin_ia32_psllv8hi", - "llvm.x86.avx512.psllv.w.256" => "__builtin_ia32_psllv16hi", - "llvm.x86.avx512.psllv.w.512" => "__builtin_ia32_psllv32hi", - "llvm.x86.avx512.psra.d.512" => "__builtin_ia32_psrad512", - "llvm.x86.avx512.psra.q.128" => "__builtin_ia32_psraq128", - "llvm.x86.avx512.psra.q.256" => "__builtin_ia32_psraq256", - "llvm.x86.avx512.psra.q.512" => "__builtin_ia32_psraq512", - "llvm.x86.avx512.psra.w.512" => "__builtin_ia32_psraw512", - "llvm.x86.avx512.psrai.d.512" => "__builtin_ia32_psradi512", - "llvm.x86.avx512.psrai.q.128" => "__builtin_ia32_psraqi128", - "llvm.x86.avx512.psrai.q.256" => "__builtin_ia32_psraqi256", - "llvm.x86.avx512.psrai.q.512" => "__builtin_ia32_psraqi512", - "llvm.x86.avx512.psrai.w.512" => "__builtin_ia32_psrawi512", - "llvm.x86.avx512.psrav.d.512" => "__builtin_ia32_psrav16si", - "llvm.x86.avx512.psrav.q.128" => "__builtin_ia32_psravq128", - "llvm.x86.avx512.psrav.q.256" => "__builtin_ia32_psravq256", - "llvm.x86.avx512.psrav.q.512" => "__builtin_ia32_psrav8di", - "llvm.x86.avx512.psrav.w.128" => "__builtin_ia32_psrav8hi", - "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi", - "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi", - "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512", - "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", - "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", - "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512", - "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512", - "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512", - "llvm.x86.avx512.psrli.q.512" => "__builtin_ia32_psrlqi512", - "llvm.x86.avx512.psrli.w.512" => "__builtin_ia32_psrlwi512", - "llvm.x86.avx512.psrlv.d.512" => "__builtin_ia32_psrlv16si", - "llvm.x86.avx512.psrlv.q.512" => "__builtin_ia32_psrlv8di", - "llvm.x86.avx512.psrlv.w.128" => "__builtin_ia32_psrlv8hi", - "llvm.x86.avx512.psrlv.w.256" => "__builtin_ia32_psrlv16hi", - "llvm.x86.avx512.psrlv.w.512" => "__builtin_ia32_psrlv32hi", - "llvm.x86.avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128", - "llvm.x86.avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256", - "llvm.x86.avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512", - "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128", - "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256", - "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512", - "llvm.x86.avx512.ptestm.b.128" => "__builtin_ia32_ptestmb128", - "llvm.x86.avx512.ptestm.b.256" => "__builtin_ia32_ptestmb256", - "llvm.x86.avx512.ptestm.b.512" => "__builtin_ia32_ptestmb512", - "llvm.x86.avx512.ptestm.d.128" => "__builtin_ia32_ptestmd128", - "llvm.x86.avx512.ptestm.d.256" => "__builtin_ia32_ptestmd256", - "llvm.x86.avx512.ptestm.d.512" => "__builtin_ia32_ptestmd512", - "llvm.x86.avx512.ptestm.q.128" => "__builtin_ia32_ptestmq128", - "llvm.x86.avx512.ptestm.q.256" => "__builtin_ia32_ptestmq256", - "llvm.x86.avx512.ptestm.q.512" => "__builtin_ia32_ptestmq512", - "llvm.x86.avx512.ptestm.w.128" => "__builtin_ia32_ptestmw128", - "llvm.x86.avx512.ptestm.w.256" => "__builtin_ia32_ptestmw256", - "llvm.x86.avx512.ptestm.w.512" => "__builtin_ia32_ptestmw512", - "llvm.x86.avx512.ptestnm.b.128" => "__builtin_ia32_ptestnmb128", - "llvm.x86.avx512.ptestnm.b.256" => "__builtin_ia32_ptestnmb256", - "llvm.x86.avx512.ptestnm.b.512" => "__builtin_ia32_ptestnmb512", - "llvm.x86.avx512.ptestnm.d.128" => "__builtin_ia32_ptestnmd128", - "llvm.x86.avx512.ptestnm.d.256" => "__builtin_ia32_ptestnmd256", - "llvm.x86.avx512.ptestnm.d.512" => "__builtin_ia32_ptestnmd512", - "llvm.x86.avx512.ptestnm.q.128" => "__builtin_ia32_ptestnmq128", - "llvm.x86.avx512.ptestnm.q.256" => "__builtin_ia32_ptestnmq256", - "llvm.x86.avx512.ptestnm.q.512" => "__builtin_ia32_ptestnmq512", - "llvm.x86.avx512.ptestnm.w.128" => "__builtin_ia32_ptestnmw128", - "llvm.x86.avx512.ptestnm.w.256" => "__builtin_ia32_ptestnmw256", - "llvm.x86.avx512.ptestnm.w.512" => "__builtin_ia32_ptestnmw512", - "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", - "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", - "llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", - "llvm.x86.avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask", - "llvm.x86.avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask", - "llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", - "llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", - "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", - "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", - "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", - // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", - // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", - "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", - "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", - "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", - "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", - "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", - "llvm.x86.avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask", - "llvm.x86.avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask", - "llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", - "llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", - "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", - "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", - "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", - // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", - // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", - "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", - "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", - "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", - "llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", - "llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", - "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", - "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", - "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", - "llvm.x86.avx512.scatterdiv2.df" => "__builtin_ia32_scatterdiv2df", - "llvm.x86.avx512.scatterdiv2.di" => "__builtin_ia32_scatterdiv2di", - "llvm.x86.avx512.scatterdiv4.df" => "__builtin_ia32_scatterdiv4df", - "llvm.x86.avx512.scatterdiv4.di" => "__builtin_ia32_scatterdiv4di", - "llvm.x86.avx512.scatterdiv4.sf" => "__builtin_ia32_scatterdiv4sf", - "llvm.x86.avx512.scatterdiv4.si" => "__builtin_ia32_scatterdiv4si", - "llvm.x86.avx512.scatterdiv8.sf" => "__builtin_ia32_scatterdiv8sf", - "llvm.x86.avx512.scatterdiv8.si" => "__builtin_ia32_scatterdiv8si", - "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", - "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", - "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", - "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", - "llvm.x86.avx512.scattersiv2.df" => "__builtin_ia32_scattersiv2df", - "llvm.x86.avx512.scattersiv2.di" => "__builtin_ia32_scattersiv2di", - "llvm.x86.avx512.scattersiv4.df" => "__builtin_ia32_scattersiv4df", - "llvm.x86.avx512.scattersiv4.di" => "__builtin_ia32_scattersiv4di", - "llvm.x86.avx512.scattersiv4.sf" => "__builtin_ia32_scattersiv4sf", - "llvm.x86.avx512.scattersiv4.si" => "__builtin_ia32_scattersiv4si", - "llvm.x86.avx512.scattersiv8.sf" => "__builtin_ia32_scattersiv8sf", - "llvm.x86.avx512.scattersiv8.si" => "__builtin_ia32_scattersiv8si", - "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", - "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", - "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", - "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", - "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512", - "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512", - "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", - "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", - "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", - "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", - "llvm.x86.avx512.vcomi.sd" => "__builtin_ia32_vcomisd", - "llvm.x86.avx512.vcomi.ss" => "__builtin_ia32_vcomiss", - "llvm.x86.avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32", - "llvm.x86.avx512.vcvtsd2si64" => "__builtin_ia32_vcvtsd2si64", - "llvm.x86.avx512.vcvtsd2usi32" => "__builtin_ia32_vcvtsd2usi32", - "llvm.x86.avx512.vcvtsd2usi64" => "__builtin_ia32_vcvtsd2usi64", - "llvm.x86.avx512.vcvtss2si32" => "__builtin_ia32_vcvtss2si32", - "llvm.x86.avx512.vcvtss2si64" => "__builtin_ia32_vcvtss2si64", - "llvm.x86.avx512.vcvtss2usi32" => "__builtin_ia32_vcvtss2usi32", - "llvm.x86.avx512.vcvtss2usi64" => "__builtin_ia32_vcvtss2usi64", - "llvm.x86.avx512.vpdpbusd.128" => "__builtin_ia32_vpdpbusd128", - "llvm.x86.avx512.vpdpbusd.256" => "__builtin_ia32_vpdpbusd256", - "llvm.x86.avx512.vpdpbusd.512" => "__builtin_ia32_vpdpbusd512", - "llvm.x86.avx512.vpdpbusds.128" => "__builtin_ia32_vpdpbusds128", - "llvm.x86.avx512.vpdpbusds.256" => "__builtin_ia32_vpdpbusds256", - "llvm.x86.avx512.vpdpbusds.512" => "__builtin_ia32_vpdpbusds512", - "llvm.x86.avx512.vpdpwssd.128" => "__builtin_ia32_vpdpwssd128", - "llvm.x86.avx512.vpdpwssd.256" => "__builtin_ia32_vpdpwssd256", - "llvm.x86.avx512.vpdpwssd.512" => "__builtin_ia32_vpdpwssd512", - "llvm.x86.avx512.vpdpwssds.128" => "__builtin_ia32_vpdpwssds128", - "llvm.x86.avx512.vpdpwssds.256" => "__builtin_ia32_vpdpwssds256", - "llvm.x86.avx512.vpdpwssds.512" => "__builtin_ia32_vpdpwssds512", - "llvm.x86.avx512.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128", - "llvm.x86.avx512.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256", - "llvm.x86.avx512.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512", - "llvm.x86.avx512.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128", - "llvm.x86.avx512.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256", - "llvm.x86.avx512.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512", - "llvm.x86.avx512.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128", - "llvm.x86.avx512.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256", - "llvm.x86.avx512.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512", - "llvm.x86.avx512.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128", - "llvm.x86.avx512.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256", - "llvm.x86.avx512.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512", - "llvm.x86.avx512.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128", - "llvm.x86.avx512.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256", - "llvm.x86.avx512.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512", - "llvm.x86.avx512.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128", - "llvm.x86.avx512.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256", - "llvm.x86.avx512.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512", - "llvm.x86.avx512.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512", - "llvm.x86.avx512.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512", - "llvm.x86.avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128", - "llvm.x86.avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256", - "llvm.x86.avx512.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512", - "llvm.x86.avx512.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128", - "llvm.x86.avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256", - "llvm.x86.avx512.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512", - "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_128", - "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_256", - "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_512", - "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_256", - "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_512", - "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_128", - "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_256", - "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512", - "llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512", - "llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask", - "llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask", - "llvm.x86.avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask", - "llvm.x86.avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask", - "llvm.x86.avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask", - "llvm.x86.avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask", - "llvm.x86.avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask", - "llvm.x86.avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask", - "llvm.x86.avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask", - "llvm.x86.avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask", - "llvm.x86.avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask", - "llvm.x86.avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask", - "llvm.x86.avx512fp16.mask.rcp.sh" => "__builtin_ia32_rcpsh_mask", - "llvm.x86.avx512fp16.mask.reduce.ph.128" => "__builtin_ia32_reduceph128_mask", - "llvm.x86.avx512fp16.mask.reduce.ph.256" => "__builtin_ia32_reduceph256_mask", - "llvm.x86.avx512fp16.mask.reduce.ph.512" => "__builtin_ia32_reduceph512_mask", - "llvm.x86.avx512fp16.mask.reduce.sh" => "__builtin_ia32_reducesh_mask", - "llvm.x86.avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask", - "llvm.x86.avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask", - "llvm.x86.avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask", - "llvm.x86.avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask", - "llvm.x86.avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask", - "llvm.x86.avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask", - "llvm.x86.avx512fp16.mask.rsqrt.sh" => "__builtin_ia32_rsqrtsh_mask", - "llvm.x86.avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask", - "llvm.x86.avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask", - "llvm.x86.avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask", - "llvm.x86.avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask", - "llvm.x86.avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask", - "llvm.x86.avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask", - "llvm.x86.avx512fp16.mask.vcvtpd2ph.512" => "__builtin_ia32_vcvtpd2ph512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2dq.128" => "__builtin_ia32_vcvtph2dq128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2dq.256" => "__builtin_ia32_vcvtph2dq256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2dq.512" => "__builtin_ia32_vcvtph2dq512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2pd.128" => "__builtin_ia32_vcvtph2pd128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2pd.256" => "__builtin_ia32_vcvtph2pd256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2pd.512" => "__builtin_ia32_vcvtph2pd512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2psx.128" => "__builtin_ia32_vcvtph2psx128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2psx.256" => "__builtin_ia32_vcvtph2psx256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2psx.512" => "__builtin_ia32_vcvtph2psx512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2qq.128" => "__builtin_ia32_vcvtph2qq128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2qq.256" => "__builtin_ia32_vcvtph2qq256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2qq.512" => "__builtin_ia32_vcvtph2qq512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2udq.128" => "__builtin_ia32_vcvtph2udq128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2udq.256" => "__builtin_ia32_vcvtph2udq256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2udq.512" => "__builtin_ia32_vcvtph2udq512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2uqq.128" => "__builtin_ia32_vcvtph2uqq128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2uqq.256" => "__builtin_ia32_vcvtph2uqq256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2uqq.512" => "__builtin_ia32_vcvtph2uqq512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2uw.128" => "__builtin_ia32_vcvtph2uw128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2uw.256" => "__builtin_ia32_vcvtph2uw256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2uw.512" => "__builtin_ia32_vcvtph2uw512_mask", - "llvm.x86.avx512fp16.mask.vcvtph2w.128" => "__builtin_ia32_vcvtph2w128_mask", - "llvm.x86.avx512fp16.mask.vcvtph2w.256" => "__builtin_ia32_vcvtph2w256_mask", - "llvm.x86.avx512fp16.mask.vcvtph2w.512" => "__builtin_ia32_vcvtph2w512_mask", - "llvm.x86.avx512fp16.mask.vcvtps2phx.128" => "__builtin_ia32_vcvtps2phx128_mask", - "llvm.x86.avx512fp16.mask.vcvtps2phx.256" => "__builtin_ia32_vcvtps2phx256_mask", - "llvm.x86.avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask", - "llvm.x86.avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask", - "llvm.x86.avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask", - // [INVALID CONVERSION]: "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask", - "llvm.x86.avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask", - "llvm.x86.avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask", - "llvm.x86.avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask", - "llvm.x86.avx512fp16.mask.vcvttph2qq.128" => "__builtin_ia32_vcvttph2qq128_mask", - "llvm.x86.avx512fp16.mask.vcvttph2qq.256" => "__builtin_ia32_vcvttph2qq256_mask", - "llvm.x86.avx512fp16.mask.vcvttph2qq.512" => "__builtin_ia32_vcvttph2qq512_mask", - "llvm.x86.avx512fp16.mask.vcvttph2udq.128" => "__builtin_ia32_vcvttph2udq128_mask", - "llvm.x86.avx512fp16.mask.vcvttph2udq.256" => "__builtin_ia32_vcvttph2udq256_mask", - "llvm.x86.avx512fp16.mask.vcvttph2udq.512" => "__builtin_ia32_vcvttph2udq512_mask", - "llvm.x86.avx512fp16.mask.vcvttph2uqq.128" => "__builtin_ia32_vcvttph2uqq128_mask", - "llvm.x86.avx512fp16.mask.vcvttph2uqq.256" => "__builtin_ia32_vcvttph2uqq256_mask", - "llvm.x86.avx512fp16.mask.vcvttph2uqq.512" => "__builtin_ia32_vcvttph2uqq512_mask", - "llvm.x86.avx512fp16.mask.vcvttph2uw.128" => "__builtin_ia32_vcvttph2uw128_mask", - "llvm.x86.avx512fp16.mask.vcvttph2uw.256" => "__builtin_ia32_vcvttph2uw256_mask", - "llvm.x86.avx512fp16.mask.vcvttph2uw.512" => "__builtin_ia32_vcvttph2uw512_mask", - "llvm.x86.avx512fp16.mask.vcvttph2w.128" => "__builtin_ia32_vcvttph2w128_mask", - "llvm.x86.avx512fp16.mask.vcvttph2w.256" => "__builtin_ia32_vcvttph2w256_mask", - "llvm.x86.avx512fp16.mask.vcvttph2w.512" => "__builtin_ia32_vcvttph2w512_mask", - "llvm.x86.avx512fp16.mask.vcvtudq2ph.128" => "__builtin_ia32_vcvtudq2ph128_mask", - "llvm.x86.avx512fp16.mask.vcvtuqq2ph.128" => "__builtin_ia32_vcvtuqq2ph128_mask", - "llvm.x86.avx512fp16.mask.vcvtuqq2ph.256" => "__builtin_ia32_vcvtuqq2ph256_mask", - "llvm.x86.avx512fp16.mask.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_mask", - "llvm.x86.avx512fp16.mask.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_mask", - "llvm.x86.avx512fp16.mask.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_mask3", - "llvm.x86.avx512fp16.mask.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_mask", - "llvm.x86.avx512fp16.mask.vfcmul.cph.128" => "__builtin_ia32_vfcmulcph128_mask", - "llvm.x86.avx512fp16.mask.vfcmul.cph.256" => "__builtin_ia32_vfcmulcph256_mask", - "llvm.x86.avx512fp16.mask.vfcmul.cph.512" => "__builtin_ia32_vfcmulcph512_mask", - "llvm.x86.avx512fp16.mask.vfcmul.csh" => "__builtin_ia32_vfcmulcsh_mask", - "llvm.x86.avx512fp16.mask.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_mask", - "llvm.x86.avx512fp16.mask.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_mask", - "llvm.x86.avx512fp16.mask.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_mask3", - "llvm.x86.avx512fp16.mask.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_mask", - "llvm.x86.avx512fp16.mask.vfmul.cph.128" => "__builtin_ia32_vfmulcph128_mask", - "llvm.x86.avx512fp16.mask.vfmul.cph.256" => "__builtin_ia32_vfmulcph256_mask", - "llvm.x86.avx512fp16.mask.vfmul.cph.512" => "__builtin_ia32_vfmulcph512_mask", - "llvm.x86.avx512fp16.mask.vfmul.csh" => "__builtin_ia32_vfmulcsh_mask", - "llvm.x86.avx512fp16.maskz.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_maskz", - "llvm.x86.avx512fp16.maskz.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_maskz", - "llvm.x86.avx512fp16.maskz.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_maskz", - "llvm.x86.avx512fp16.maskz.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_maskz", - "llvm.x86.avx512fp16.maskz.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_maskz", - "llvm.x86.avx512fp16.maskz.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_maskz", - "llvm.x86.avx512fp16.maskz.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_maskz", - "llvm.x86.avx512fp16.maskz.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_maskz", - "llvm.x86.avx512fp16.max.ph.128" => "__builtin_ia32_maxph128", - "llvm.x86.avx512fp16.max.ph.256" => "__builtin_ia32_maxph256", - "llvm.x86.avx512fp16.max.ph.512" => "__builtin_ia32_maxph512", - "llvm.x86.avx512fp16.min.ph.128" => "__builtin_ia32_minph128", - "llvm.x86.avx512fp16.min.ph.256" => "__builtin_ia32_minph256", - "llvm.x86.avx512fp16.min.ph.512" => "__builtin_ia32_minph512", - "llvm.x86.avx512fp16.mul.ph.512" => "__builtin_ia32_mulph512", - "llvm.x86.avx512fp16.sub.ph.512" => "__builtin_ia32_subph512", - "llvm.x86.avx512fp16.vcomi.sh" => "__builtin_ia32_vcomish", - "llvm.x86.avx512fp16.vcvtsh2si32" => "__builtin_ia32_vcvtsh2si32", - "llvm.x86.avx512fp16.vcvtsh2si64" => "__builtin_ia32_vcvtsh2si64", - "llvm.x86.avx512fp16.vcvtsh2usi32" => "__builtin_ia32_vcvtsh2usi32", - "llvm.x86.avx512fp16.vcvtsh2usi64" => "__builtin_ia32_vcvtsh2usi64", - "llvm.x86.avx512fp16.vcvtsi2sh" => "__builtin_ia32_vcvtsi2sh", - "llvm.x86.avx512fp16.vcvtsi642sh" => "__builtin_ia32_vcvtsi642sh", - "llvm.x86.avx512fp16.vcvttsh2si32" => "__builtin_ia32_vcvttsh2si32", - "llvm.x86.avx512fp16.vcvttsh2si64" => "__builtin_ia32_vcvttsh2si64", - "llvm.x86.avx512fp16.vcvttsh2usi32" => "__builtin_ia32_vcvttsh2usi32", - "llvm.x86.avx512fp16.vcvttsh2usi64" => "__builtin_ia32_vcvttsh2usi64", - "llvm.x86.avx512fp16.vcvtusi2sh" => "__builtin_ia32_vcvtusi2sh", - "llvm.x86.avx512fp16.vcvtusi642sh" => "__builtin_ia32_vcvtusi642sh", - "llvm.x86.avx512fp16.vfmaddsub.ph.128" => "__builtin_ia32_vfmaddsubph", - "llvm.x86.avx512fp16.vfmaddsub.ph.256" => "__builtin_ia32_vfmaddsubph256", - "llvm.x86.axor32" => "__builtin_ia32_axor32", - "llvm.x86.axor64" => "__builtin_ia32_axor64", - "llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", - "llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", - "llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", - "llvm.x86.bmi.bzhi.64" => "__builtin_ia32_bzhi_di", - "llvm.x86.bmi.pdep.32" => "__builtin_ia32_pdep_si", - "llvm.x86.bmi.pdep.64" => "__builtin_ia32_pdep_di", - "llvm.x86.bmi.pext.32" => "__builtin_ia32_pext_si", - "llvm.x86.bmi.pext.64" => "__builtin_ia32_pext_di", - "llvm.x86.cldemote" => "__builtin_ia32_cldemote", - "llvm.x86.clflushopt" => "__builtin_ia32_clflushopt", - "llvm.x86.clrssbsy" => "__builtin_ia32_clrssbsy", - "llvm.x86.clui" => "__builtin_ia32_clui", - "llvm.x86.clwb" => "__builtin_ia32_clwb", - "llvm.x86.clzero" => "__builtin_ia32_clzero", - "llvm.x86.cmpccxadd32" => "__builtin_ia32_cmpccxadd32", - "llvm.x86.cmpccxadd64" => "__builtin_ia32_cmpccxadd64", - "llvm.x86.directstore32" => "__builtin_ia32_directstore_u32", - "llvm.x86.directstore64" => "__builtin_ia32_directstore_u64", - "llvm.x86.enqcmd" => "__builtin_ia32_enqcmd", - "llvm.x86.enqcmds" => "__builtin_ia32_enqcmds", - "llvm.x86.flags.read.u32" => "__builtin_ia32_readeflags_u32", - "llvm.x86.flags.read.u64" => "__builtin_ia32_readeflags_u64", - "llvm.x86.flags.write.u32" => "__builtin_ia32_writeeflags_u32", - "llvm.x86.flags.write.u64" => "__builtin_ia32_writeeflags_u64", - "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", - "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", - "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", - "llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", - "llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", - "llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", - "llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", - "llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", - "llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", - "llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", - "llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", - "llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", - "llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", - "llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", - "llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", - "llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", - "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", - "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", - "llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", - "llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", - "llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", - "llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", - "llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", - "llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", - "llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", - "llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", - "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", - "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", - "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", - "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", - "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", - "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", - "llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", - "llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", - "llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", - "llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", - "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", - "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", - "llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", - "llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", - "llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", - "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", - "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", - "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", - "llvm.x86.fxrstor" => "__builtin_ia32_fxrstor", - "llvm.x86.fxrstor64" => "__builtin_ia32_fxrstor64", - "llvm.x86.fxsave" => "__builtin_ia32_fxsave", - "llvm.x86.fxsave64" => "__builtin_ia32_fxsave64", - "llvm.x86.incsspd" => "__builtin_ia32_incsspd", - "llvm.x86.incsspq" => "__builtin_ia32_incsspq", - "llvm.x86.invpcid" => "__builtin_ia32_invpcid", - "llvm.x86.ldtilecfg" => "__builtin_ia32_tile_loadconfig", - "llvm.x86.ldtilecfg.internal" => "__builtin_ia32_tile_loadconfig_internal", - "llvm.x86.llwpcb" => "__builtin_ia32_llwpcb", - "llvm.x86.loadiwkey" => "__builtin_ia32_loadiwkey", - "llvm.x86.lwpins32" => "__builtin_ia32_lwpins32", - "llvm.x86.lwpins64" => "__builtin_ia32_lwpins64", - "llvm.x86.lwpval32" => "__builtin_ia32_lwpval32", - "llvm.x86.lwpval64" => "__builtin_ia32_lwpval64", - "llvm.x86.mmx.emms" => "__builtin_ia32_emms", - "llvm.x86.mmx.femms" => "__builtin_ia32_femms", - "llvm.x86.monitorx" => "__builtin_ia32_monitorx", - "llvm.x86.movdir64b" => "__builtin_ia32_movdir64b", - "llvm.x86.movrsdi" => "__builtin_ia32_movrsdi", - "llvm.x86.movrshi" => "__builtin_ia32_movrshi", - "llvm.x86.movrsqi" => "__builtin_ia32_movrsqi", - "llvm.x86.movrssi" => "__builtin_ia32_movrssi", - "llvm.x86.mwaitx" => "__builtin_ia32_mwaitx", - "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", - "llvm.x86.pclmulqdq.256" => "__builtin_ia32_pclmulqdq256", - "llvm.x86.pclmulqdq.512" => "__builtin_ia32_pclmulqdq512", - "llvm.x86.prefetchrs" => "__builtin_ia32_prefetchrs", - "llvm.x86.ptwrite32" => "__builtin_ia32_ptwrite32", - "llvm.x86.ptwrite64" => "__builtin_ia32_ptwrite64", - "llvm.x86.rdfsbase.32" => "__builtin_ia32_rdfsbase32", - "llvm.x86.rdfsbase.64" => "__builtin_ia32_rdfsbase64", - "llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32", - "llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64", - "llvm.x86.rdpid" => "__builtin_ia32_rdpid", - "llvm.x86.rdpkru" => "__builtin_ia32_rdpkru", - "llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", - "llvm.x86.rdpru" => "__builtin_ia32_rdpru", - "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", - "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", - "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", - "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", - "llvm.x86.rstorssp" => "__builtin_ia32_rstorssp", - "llvm.x86.saveprevssp" => "__builtin_ia32_saveprevssp", - "llvm.x86.senduipi" => "__builtin_ia32_senduipi", - "llvm.x86.serialize" => "__builtin_ia32_serialize", - "llvm.x86.setssbsy" => "__builtin_ia32_setssbsy", - "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", - "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", - "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", - "llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4", - "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", - "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", - "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", - "llvm.x86.slwpcb" => "__builtin_ia32_slwpcb", - "llvm.x86.sse.add.ss" => "__builtin_ia32_addss", - "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", - "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", - "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", - "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", - "llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt", - "llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", - "llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", - "llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", - "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", - "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", - "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", - "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", - "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", - "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", - "llvm.x86.sse.div.ss" => "__builtin_ia32_divss", - "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", - "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", - "llvm.x86.sse.min.ps" => "__builtin_ia32_minps", - "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", - "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", - "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", - "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", - "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", - "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", - "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", - "llvm.x86.sse.sfence" => "__builtin_ia32_sfence", - "llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", - "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", - "llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", - "llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", - "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", - "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", - "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", - "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", - "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", - "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", - "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", - "llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", - "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", - "llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", - "llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", - "llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", - "llvm.x86.sse2.comigt.sd" => "__builtin_ia32_comisdgt", - "llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", - "llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", - "llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", - "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", - "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", - "llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", - "llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", - "llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", - "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", - "llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", - "llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", - "llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", - "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", - "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", - "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", - "llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", - "llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", - "llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", - "llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", - "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", - "llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", - "llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", - "llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", - "llvm.x86.sse2.max.sd" => "__builtin_ia32_maxsd", - "llvm.x86.sse2.mfence" => "__builtin_ia32_mfence", - "llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", - "llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", - "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", - "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", - "llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", - "llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", - "llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", - "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", - "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", - "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", - "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", - "llvm.x86.sse2.pause" => "__builtin_ia32_pause", - "llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", - "llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", - "llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", - "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", - "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", - "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", - "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", - "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", - "llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", - "llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", - "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", - "llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", - "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", - "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", - "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", - "llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", - "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", - "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", - "llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", - "llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", - "llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", - "llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128", - "llvm.x86.sse2.pslli.w" => "__builtin_ia32_psllwi128", - "llvm.x86.sse2.psra.d" => "__builtin_ia32_psrad128", - "llvm.x86.sse2.psra.w" => "__builtin_ia32_psraw128", - "llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", - "llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", - "llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", - "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", - "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", - "llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", - "llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", - "llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", - "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", - "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", - "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", - "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", - "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", - "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", - "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", - "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", - "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", - "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", - "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", - "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", - "llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", - "llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", - "llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", - "llvm.x86.sse2.ucomile.sd" => "__builtin_ia32_ucomisdle", - "llvm.x86.sse2.ucomilt.sd" => "__builtin_ia32_ucomisdlt", - "llvm.x86.sse2.ucomineq.sd" => "__builtin_ia32_ucomisdneq", - "llvm.x86.sse3.addsub.pd" => "__builtin_ia32_addsubpd", - "llvm.x86.sse3.addsub.ps" => "__builtin_ia32_addsubps", - "llvm.x86.sse3.hadd.pd" => "__builtin_ia32_haddpd", - "llvm.x86.sse3.hadd.ps" => "__builtin_ia32_haddps", - "llvm.x86.sse3.hsub.pd" => "__builtin_ia32_hsubpd", - "llvm.x86.sse3.hsub.ps" => "__builtin_ia32_hsubps", - "llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", - "llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", - "llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", - "llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", - "llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", - "llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", - "llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", - "llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", - "llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", - "llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", - "llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", - "llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", - "llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", - "llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", - "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", - "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", - "llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", - "llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", - "llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", - "llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", - "llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", - "llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", - "llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", - "llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", - "llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", - "llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", - "llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", - "llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", - "llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", - "llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", - "llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", - "llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", - "llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", - "llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", - "llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", - "llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", - "llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", - "llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", - "llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", - "llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", - "llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", - "llvm.x86.sse41.round.pd" => "__builtin_ia32_roundpd", - "llvm.x86.sse41.round.ps" => "__builtin_ia32_roundps", - "llvm.x86.sse41.round.sd" => "__builtin_ia32_roundsd", - "llvm.x86.sse41.round.ss" => "__builtin_ia32_roundss", - "llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi", - "llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si", - "llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi", - "llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di", - "llvm.x86.sse42.pcmpestri128" => "__builtin_ia32_pcmpestri128", - "llvm.x86.sse42.pcmpestria128" => "__builtin_ia32_pcmpestria128", - "llvm.x86.sse42.pcmpestric128" => "__builtin_ia32_pcmpestric128", - "llvm.x86.sse42.pcmpestrio128" => "__builtin_ia32_pcmpestrio128", - "llvm.x86.sse42.pcmpestris128" => "__builtin_ia32_pcmpestris128", - "llvm.x86.sse42.pcmpestriz128" => "__builtin_ia32_pcmpestriz128", - "llvm.x86.sse42.pcmpestrm128" => "__builtin_ia32_pcmpestrm128", - "llvm.x86.sse42.pcmpistri128" => "__builtin_ia32_pcmpistri128", - "llvm.x86.sse42.pcmpistria128" => "__builtin_ia32_pcmpistria128", - "llvm.x86.sse42.pcmpistric128" => "__builtin_ia32_pcmpistric128", - "llvm.x86.sse42.pcmpistrio128" => "__builtin_ia32_pcmpistrio128", - "llvm.x86.sse42.pcmpistris128" => "__builtin_ia32_pcmpistris128", - "llvm.x86.sse42.pcmpistriz128" => "__builtin_ia32_pcmpistriz128", - "llvm.x86.sse42.pcmpistrm128" => "__builtin_ia32_pcmpistrm128", - "llvm.x86.sse4a.extrq" => "__builtin_ia32_extrq", - "llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", - "llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", - "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", - "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", - "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", - "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", - "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", - "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", - "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", - "llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", - "llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", - "llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", - "llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", - "llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", - "llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", - "llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", - "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", - "llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", - "llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", - "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", - "llvm.x86.sttilecfg" => "__builtin_ia32_tile_storeconfig", - "llvm.x86.stui" => "__builtin_ia32_stui", - "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", - "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", - "llvm.x86.t2rpntlvwz0" => "__builtin_ia32_t2rpntlvwz0", - "llvm.x86.t2rpntlvwz0rs" => "__builtin_ia32_t2rpntlvwz0rs", - "llvm.x86.t2rpntlvwz0rst1" => "__builtin_ia32_t2rpntlvwz0rst1", - "llvm.x86.t2rpntlvwz0t1" => "__builtin_ia32_t2rpntlvwz0t1", - "llvm.x86.t2rpntlvwz1" => "__builtin_ia32_t2rpntlvwz1", - "llvm.x86.t2rpntlvwz1rs" => "__builtin_ia32_t2rpntlvwz1rs", - "llvm.x86.t2rpntlvwz1rst1" => "__builtin_ia32_t2rpntlvwz1rst1", - "llvm.x86.t2rpntlvwz1t1" => "__builtin_ia32_t2rpntlvwz1t1", - "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", - "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", - "llvm.x86.tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps", - "llvm.x86.tcmmimfp16ps.internal" => "__builtin_ia32_tcmmimfp16ps_internal", - "llvm.x86.tcmmrlfp16ps" => "__builtin_ia32_tcmmrlfp16ps", - "llvm.x86.tcmmrlfp16ps.internal" => "__builtin_ia32_tcmmrlfp16ps_internal", - "llvm.x86.tconjtcmmimfp16ps" => "__builtin_ia32_tconjtcmmimfp16ps", - "llvm.x86.tconjtcmmimfp16ps.internal" => "__builtin_ia32_tconjtcmmimfp16ps_internal", - "llvm.x86.tconjtfp16" => "__builtin_ia32_tconjtfp16", - "llvm.x86.tconjtfp16.internal" => "__builtin_ia32_tconjtfp16_internal", - "llvm.x86.tcvtrowd2ps" => "__builtin_ia32_tcvtrowd2ps", - "llvm.x86.tcvtrowd2ps.internal" => "__builtin_ia32_tcvtrowd2ps_internal", - "llvm.x86.tcvtrowps2bf16h" => "__builtin_ia32_tcvtrowps2bf16h", - "llvm.x86.tcvtrowps2bf16h.internal" => "__builtin_ia32_tcvtrowps2bf16h_internal", - "llvm.x86.tcvtrowps2bf16l" => "__builtin_ia32_tcvtrowps2bf16l", - "llvm.x86.tcvtrowps2bf16l.internal" => "__builtin_ia32_tcvtrowps2bf16l_internal", - "llvm.x86.tcvtrowps2phh" => "__builtin_ia32_tcvtrowps2phh", - "llvm.x86.tcvtrowps2phh.internal" => "__builtin_ia32_tcvtrowps2phh_internal", - "llvm.x86.tcvtrowps2phl" => "__builtin_ia32_tcvtrowps2phl", - "llvm.x86.tcvtrowps2phl.internal" => "__builtin_ia32_tcvtrowps2phl_internal", - "llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps", - "llvm.x86.tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal", - "llvm.x86.tdpbf8ps" => "__builtin_ia32_tdpbf8ps", - "llvm.x86.tdpbf8ps.internal" => "__builtin_ia32_tdpbf8ps_internal", - "llvm.x86.tdpbhf8ps" => "__builtin_ia32_tdpbhf8ps", - "llvm.x86.tdpbhf8ps.internal" => "__builtin_ia32_tdpbhf8ps_internal", - "llvm.x86.tdpbssd" => "__builtin_ia32_tdpbssd", - "llvm.x86.tdpbssd.internal" => "__builtin_ia32_tdpbssd_internal", - "llvm.x86.tdpbsud" => "__builtin_ia32_tdpbsud", - "llvm.x86.tdpbsud.internal" => "__builtin_ia32_tdpbsud_internal", - "llvm.x86.tdpbusd" => "__builtin_ia32_tdpbusd", - "llvm.x86.tdpbusd.internal" => "__builtin_ia32_tdpbusd_internal", - "llvm.x86.tdpbuud" => "__builtin_ia32_tdpbuud", - "llvm.x86.tdpbuud.internal" => "__builtin_ia32_tdpbuud_internal", - "llvm.x86.tdpfp16ps" => "__builtin_ia32_tdpfp16ps", - "llvm.x86.tdpfp16ps.internal" => "__builtin_ia32_tdpfp16ps_internal", - "llvm.x86.tdphbf8ps" => "__builtin_ia32_tdphbf8ps", - "llvm.x86.tdphbf8ps.internal" => "__builtin_ia32_tdphbf8ps_internal", - "llvm.x86.tdphf8ps" => "__builtin_ia32_tdphf8ps", - "llvm.x86.tdphf8ps.internal" => "__builtin_ia32_tdphf8ps_internal", - "llvm.x86.testui" => "__builtin_ia32_testui", - "llvm.x86.tileloadd64" => "__builtin_ia32_tileloadd64", - "llvm.x86.tileloadd64.internal" => "__builtin_ia32_tileloadd64_internal", - "llvm.x86.tileloaddrs64" => "__builtin_ia32_tileloaddrs64", - "llvm.x86.tileloaddrs64.internal" => "__builtin_ia32_tileloaddrs64_internal", - "llvm.x86.tileloaddrst164" => "__builtin_ia32_tileloaddrst164", - "llvm.x86.tileloaddrst164.internal" => "__builtin_ia32_tileloaddrst164_internal", - "llvm.x86.tileloaddt164" => "__builtin_ia32_tileloaddt164", - "llvm.x86.tileloaddt164.internal" => "__builtin_ia32_tileloaddt164_internal", - "llvm.x86.tilemovrow" => "__builtin_ia32_tilemovrow", - "llvm.x86.tilemovrow.internal" => "__builtin_ia32_tilemovrow_internal", - "llvm.x86.tilerelease" => "__builtin_ia32_tilerelease", - "llvm.x86.tilestored64" => "__builtin_ia32_tilestored64", - "llvm.x86.tilestored64.internal" => "__builtin_ia32_tilestored64_internal", - "llvm.x86.tilezero" => "__builtin_ia32_tilezero", - "llvm.x86.tilezero.internal" => "__builtin_ia32_tilezero_internal", - "llvm.x86.tmmultf32ps" => "__builtin_ia32_tmmultf32ps", - "llvm.x86.tmmultf32ps.internal" => "__builtin_ia32_tmmultf32ps_internal", - "llvm.x86.tpause" => "__builtin_ia32_tpause", - "llvm.x86.ttcmmimfp16ps" => "__builtin_ia32_ttcmmimfp16ps", - "llvm.x86.ttcmmimfp16ps.internal" => "__builtin_ia32_ttcmmimfp16ps_internal", - "llvm.x86.ttcmmrlfp16ps" => "__builtin_ia32_ttcmmrlfp16ps", - "llvm.x86.ttcmmrlfp16ps.internal" => "__builtin_ia32_ttcmmrlfp16ps_internal", - "llvm.x86.ttdpbf16ps" => "__builtin_ia32_ttdpbf16ps", - "llvm.x86.ttdpbf16ps.internal" => "__builtin_ia32_ttdpbf16ps_internal", - "llvm.x86.ttdpfp16ps" => "__builtin_ia32_ttdpfp16ps", - "llvm.x86.ttdpfp16ps.internal" => "__builtin_ia32_ttdpfp16ps_internal", - "llvm.x86.ttmmultf32ps" => "__builtin_ia32_ttmmultf32ps", - "llvm.x86.ttmmultf32ps.internal" => "__builtin_ia32_ttmmultf32ps_internal", - "llvm.x86.ttransposed" => "__builtin_ia32_ttransposed", - "llvm.x86.ttransposed.internal" => "__builtin_ia32_ttransposed_internal", - "llvm.x86.umonitor" => "__builtin_ia32_umonitor", - "llvm.x86.umwait" => "__builtin_ia32_umwait", - "llvm.x86.urdmsr" => "__builtin_ia32_urdmsr", - "llvm.x86.uwrmsr" => "__builtin_ia32_uwrmsr", - "llvm.x86.vbcstnebf162ps128" => "__builtin_ia32_vbcstnebf162ps128", - "llvm.x86.vbcstnebf162ps256" => "__builtin_ia32_vbcstnebf162ps256", - "llvm.x86.vbcstnesh2ps128" => "__builtin_ia32_vbcstnesh2ps128", - "llvm.x86.vbcstnesh2ps256" => "__builtin_ia32_vbcstnesh2ps256", - "llvm.x86.vcvtneebf162ps128" => "__builtin_ia32_vcvtneebf162ps128", - "llvm.x86.vcvtneebf162ps256" => "__builtin_ia32_vcvtneebf162ps256", - "llvm.x86.vcvtneeph2ps128" => "__builtin_ia32_vcvtneeph2ps128", - "llvm.x86.vcvtneeph2ps256" => "__builtin_ia32_vcvtneeph2ps256", - "llvm.x86.vcvtneobf162ps128" => "__builtin_ia32_vcvtneobf162ps128", - "llvm.x86.vcvtneobf162ps256" => "__builtin_ia32_vcvtneobf162ps256", - "llvm.x86.vcvtneoph2ps128" => "__builtin_ia32_vcvtneoph2ps128", - "llvm.x86.vcvtneoph2ps256" => "__builtin_ia32_vcvtneoph2ps256", - "llvm.x86.vcvtneps2bf16128" => "__builtin_ia32_vcvtneps2bf16128", - "llvm.x86.vcvtneps2bf16256" => "__builtin_ia32_vcvtneps2bf16256", - "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", - "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", - "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", - "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", - "llvm.x86.vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi", - "llvm.x86.vgf2p8affineinvqb.256" => "__builtin_ia32_vgf2p8affineinvqb_v32qi", - "llvm.x86.vgf2p8affineinvqb.512" => "__builtin_ia32_vgf2p8affineinvqb_v64qi", - "llvm.x86.vgf2p8affineqb.128" => "__builtin_ia32_vgf2p8affineqb_v16qi", - "llvm.x86.vgf2p8affineqb.256" => "__builtin_ia32_vgf2p8affineqb_v32qi", - "llvm.x86.vgf2p8affineqb.512" => "__builtin_ia32_vgf2p8affineqb_v64qi", - "llvm.x86.vgf2p8mulb.128" => "__builtin_ia32_vgf2p8mulb_v16qi", - "llvm.x86.vgf2p8mulb.256" => "__builtin_ia32_vgf2p8mulb_v32qi", - "llvm.x86.vgf2p8mulb.512" => "__builtin_ia32_vgf2p8mulb_v64qi", - "llvm.x86.vsha512msg1" => "__builtin_ia32_vsha512msg1", - "llvm.x86.vsha512msg2" => "__builtin_ia32_vsha512msg2", - "llvm.x86.vsha512rnds2" => "__builtin_ia32_vsha512rnds2", - "llvm.x86.vsm3msg1" => "__builtin_ia32_vsm3msg1", - "llvm.x86.vsm3msg2" => "__builtin_ia32_vsm3msg2", - "llvm.x86.vsm3rnds2" => "__builtin_ia32_vsm3rnds2", - "llvm.x86.vsm4key4128" => "__builtin_ia32_vsm4key4128", - "llvm.x86.vsm4key4256" => "__builtin_ia32_vsm4key4256", - "llvm.x86.vsm4key4512" => "__builtin_ia32_vsm4key4512", - "llvm.x86.vsm4rnds4128" => "__builtin_ia32_vsm4rnds4128", - "llvm.x86.vsm4rnds4256" => "__builtin_ia32_vsm4rnds4256", - "llvm.x86.vsm4rnds4512" => "__builtin_ia32_vsm4rnds4512", - "llvm.x86.wbinvd" => "__builtin_ia32_wbinvd", - "llvm.x86.wbnoinvd" => "__builtin_ia32_wbnoinvd", - "llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32", - "llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64", - "llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32", - "llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64", - "llvm.x86.wrpkru" => "__builtin_ia32_wrpkru", - "llvm.x86.wrssd" => "__builtin_ia32_wrssd", - "llvm.x86.wrssq" => "__builtin_ia32_wrssq", - "llvm.x86.wrussd" => "__builtin_ia32_wrussd", - "llvm.x86.wrussq" => "__builtin_ia32_wrussq", - "llvm.x86.xabort" => "__builtin_ia32_xabort", - "llvm.x86.xbegin" => "__builtin_ia32_xbegin", - "llvm.x86.xend" => "__builtin_ia32_xend", - "llvm.x86.xop.vfrcz.pd" => "__builtin_ia32_vfrczpd", - "llvm.x86.xop.vfrcz.pd.256" => "__builtin_ia32_vfrczpd256", - "llvm.x86.xop.vfrcz.ps" => "__builtin_ia32_vfrczps", - "llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", - "llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", - "llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", - "llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", - "llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", - "llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", - "llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", - "llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", - "llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", - "llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", - "llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", - "llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", - "llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", - "llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", - "llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", - "llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", - "llvm.x86.xop.vpermil2ps.256" => "__builtin_ia32_vpermil2ps256", - "llvm.x86.xop.vphaddbd" => "__builtin_ia32_vphaddbd", - "llvm.x86.xop.vphaddbq" => "__builtin_ia32_vphaddbq", - "llvm.x86.xop.vphaddbw" => "__builtin_ia32_vphaddbw", - "llvm.x86.xop.vphadddq" => "__builtin_ia32_vphadddq", - "llvm.x86.xop.vphaddubd" => "__builtin_ia32_vphaddubd", - "llvm.x86.xop.vphaddubq" => "__builtin_ia32_vphaddubq", - "llvm.x86.xop.vphaddubw" => "__builtin_ia32_vphaddubw", - "llvm.x86.xop.vphaddudq" => "__builtin_ia32_vphaddudq", - "llvm.x86.xop.vphadduwd" => "__builtin_ia32_vphadduwd", - "llvm.x86.xop.vphadduwq" => "__builtin_ia32_vphadduwq", - "llvm.x86.xop.vphaddwd" => "__builtin_ia32_vphaddwd", - "llvm.x86.xop.vphaddwq" => "__builtin_ia32_vphaddwq", - "llvm.x86.xop.vphsubbw" => "__builtin_ia32_vphsubbw", - "llvm.x86.xop.vphsubdq" => "__builtin_ia32_vphsubdq", - "llvm.x86.xop.vphsubwd" => "__builtin_ia32_vphsubwd", - "llvm.x86.xop.vpmacsdd" => "__builtin_ia32_vpmacsdd", - "llvm.x86.xop.vpmacsdqh" => "__builtin_ia32_vpmacsdqh", - "llvm.x86.xop.vpmacsdql" => "__builtin_ia32_vpmacsdql", - "llvm.x86.xop.vpmacssdd" => "__builtin_ia32_vpmacssdd", - "llvm.x86.xop.vpmacssdqh" => "__builtin_ia32_vpmacssdqh", - "llvm.x86.xop.vpmacssdql" => "__builtin_ia32_vpmacssdql", - "llvm.x86.xop.vpmacsswd" => "__builtin_ia32_vpmacsswd", - "llvm.x86.xop.vpmacssww" => "__builtin_ia32_vpmacssww", - "llvm.x86.xop.vpmacswd" => "__builtin_ia32_vpmacswd", - "llvm.x86.xop.vpmacsww" => "__builtin_ia32_vpmacsww", - "llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", - "llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", - "llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", - "llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", - "llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", - "llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", - "llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", - "llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", - "llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", - "llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", - "llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", - "llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", - "llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", - "llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq", - "llvm.x86.xop.vpshaw" => "__builtin_ia32_vpshaw", - "llvm.x86.xop.vpshlb" => "__builtin_ia32_vpshlb", - "llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld", - "llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", - "llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", - "llvm.x86.xresldtrk" => "__builtin_ia32_xresldtrk", - "llvm.x86.xsusldtrk" => "__builtin_ia32_xsusldtrk", - "llvm.x86.xtest" => "__builtin_ia32_xtest", - // xcore - "llvm.xcore.bitrev" => "__builtin_bitrev", - "llvm.xcore.getid" => "__builtin_getid", - "llvm.xcore.getps" => "__builtin_getps", - "llvm.xcore.setps" => "__builtin_setps", - _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), +/// Translate a given LLVM intrinsic name to an equivalent GCC one. +fn map_arch_intrinsic(name: &str) -> &str { + let Some(name) = name.strip_prefix("llvm.") else { + unimplemented!("***** unsupported LLVM intrinsic {}", name) + }; + let Some((arch, name)) = name.split_once('.') else { + unimplemented!("***** unsupported LLVM intrinsic {}", name) + }; + match arch { + "AMDGPU" => { + #[allow(non_snake_case)] + fn AMDGPU(name: &str) -> &str { + match name { + // AMDGPU + "div.fixup.f32" => "__builtin_amdgpu_div_fixup", + "div.fixup.f64" => "__builtin_amdgpu_div_fixup", + "div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", + "div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", + "div.fmas.f32" => "__builtin_amdgpu_div_fmas", + "div.fmas.f64" => "__builtin_amdgpu_div_fmas", + "div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", + "div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", + "ldexp.f32" => "__builtin_amdgpu_ldexp", + "ldexp.f64" => "__builtin_amdgpu_ldexp", + "ldexp.v2f64" => "__builtin_amdgpu_ldexp", + "ldexp.v4f32" => "__builtin_amdgpu_ldexp", + "rcp.f32" => "__builtin_amdgpu_rcp", + "rcp.f64" => "__builtin_amdgpu_rcp", + "rcp.v2f64" => "__builtin_amdgpu_rcp", + "rcp.v4f32" => "__builtin_amdgpu_rcp", + "rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", + "rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", + "rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", + "rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", + "rsq.f32" => "__builtin_amdgpu_rsq", + "rsq.f64" => "__builtin_amdgpu_rsq", + "rsq.v2f64" => "__builtin_amdgpu_rsq", + "rsq.v4f32" => "__builtin_amdgpu_rsq", + "trig.preop.f32" => "__builtin_amdgpu_trig_preop", + "trig.preop.f64" => "__builtin_amdgpu_trig_preop", + "trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", + "trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + AMDGPU(name) + } + "aarch64" => { + #[allow(non_snake_case)] + fn aarch64(name: &str) -> &str { + match name { + // aarch64 + "chkfeat" => "__builtin_arm_chkfeat", + "dmb" => "__builtin_arm_dmb", + "dsb" => "__builtin_arm_dsb", + "gcspopm" => "__builtin_arm_gcspopm", + "gcsss" => "__builtin_arm_gcsss", + "isb" => "__builtin_arm_isb", + "prefetch" => "__builtin_arm_prefetch", + "sme.in.streaming.mode" => "__builtin_arm_in_streaming_mode", + "sve.aesd" => "__builtin_sve_svaesd_u8", + "sve.aese" => "__builtin_sve_svaese_u8", + "sve.aesimc" => "__builtin_sve_svaesimc_u8", + "sve.aesmc" => "__builtin_sve_svaesmc_u8", + "sve.rax1" => "__builtin_sve_svrax1_u64", + "sve.rdffr" => "__builtin_sve_svrdffr", + "sve.rdffr.z" => "__builtin_sve_svrdffr_z", + "sve.setffr" => "__builtin_sve_svsetffr", + "sve.sm4e" => "__builtin_sve_svsm4e_u32", + "sve.sm4ekey" => "__builtin_sve_svsm4ekey_u32", + "sve.wrffr" => "__builtin_sve_svwrffr", + "tcancel" => "__builtin_arm_tcancel", + "tcommit" => "__builtin_arm_tcommit", + "tstart" => "__builtin_arm_tstart", + "ttest" => "__builtin_arm_ttest", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + aarch64(name) + } + "amdgcn" => { + #[allow(non_snake_case)] + fn amdgcn(name: &str) -> &str { + match name { + // amdgcn + "alignbyte" => "__builtin_amdgcn_alignbyte", + "ashr.pk.i8.i32" => "__builtin_amdgcn_ashr_pk_i8_i32", + "ashr.pk.u8.i32" => "__builtin_amdgcn_ashr_pk_u8_i32", + "buffer.wbinvl1" => "__builtin_amdgcn_buffer_wbinvl1", + "buffer.wbinvl1.sc" => "__builtin_amdgcn_buffer_wbinvl1_sc", + "buffer.wbinvl1.vol" => "__builtin_amdgcn_buffer_wbinvl1_vol", + "cubeid" => "__builtin_amdgcn_cubeid", + "cubema" => "__builtin_amdgcn_cubema", + "cubesc" => "__builtin_amdgcn_cubesc", + "cubetc" => "__builtin_amdgcn_cubetc", + "cvt.f32.bf8" => "__builtin_amdgcn_cvt_f32_bf8", + "cvt.f32.fp8" => "__builtin_amdgcn_cvt_f32_fp8", + "cvt.off.f32.i4" => "__builtin_amdgcn_cvt_off_f32_i4", + "cvt.pk.bf8.f32" => "__builtin_amdgcn_cvt_pk_bf8_f32", + "cvt.pk.f32.bf8" => "__builtin_amdgcn_cvt_pk_f32_bf8", + "cvt.pk.f32.fp8" => "__builtin_amdgcn_cvt_pk_f32_fp8", + "cvt.pk.fp8.f32" => "__builtin_amdgcn_cvt_pk_fp8_f32", + "cvt.pk.i16" => "__builtin_amdgcn_cvt_pk_i16", + "cvt.pk.u16" => "__builtin_amdgcn_cvt_pk_u16", + "cvt.pk.u8.f32" => "__builtin_amdgcn_cvt_pk_u8_f32", + "cvt.pknorm.i16" => "__builtin_amdgcn_cvt_pknorm_i16", + "cvt.pknorm.u16" => "__builtin_amdgcn_cvt_pknorm_u16", + "cvt.pkrtz" => "__builtin_amdgcn_cvt_pkrtz", + "cvt.scalef32.2xpk16.bf6.f32" => "__builtin_amdgcn_cvt_scalef32_2xpk16_bf6_f32", + "cvt.scalef32.2xpk16.fp6.f32" => "__builtin_amdgcn_cvt_scalef32_2xpk16_fp6_f32", + "cvt.scalef32.f16.bf8" => "__builtin_amdgcn_cvt_scalef32_f16_bf8", + "cvt.scalef32.f16.fp8" => "__builtin_amdgcn_cvt_scalef32_f16_fp8", + "cvt.scalef32.f32.bf8" => "__builtin_amdgcn_cvt_scalef32_f32_bf8", + "cvt.scalef32.f32.fp8" => "__builtin_amdgcn_cvt_scalef32_f32_fp8", + "cvt.scalef32.pk.bf16.bf8" => "__builtin_amdgcn_cvt_scalef32_pk_bf16_bf8", + "cvt.scalef32.pk.bf16.fp4" => "__builtin_amdgcn_cvt_scalef32_pk_bf16_fp4", + "cvt.scalef32.pk.bf16.fp8" => "__builtin_amdgcn_cvt_scalef32_pk_bf16_fp8", + "cvt.scalef32.pk.bf8.bf16" => "__builtin_amdgcn_cvt_scalef32_pk_bf8_bf16", + "cvt.scalef32.pk.bf8.f16" => "__builtin_amdgcn_cvt_scalef32_pk_bf8_f16", + "cvt.scalef32.pk.bf8.f32" => "__builtin_amdgcn_cvt_scalef32_pk_bf8_f32", + "cvt.scalef32.pk.f16.bf8" => "__builtin_amdgcn_cvt_scalef32_pk_f16_bf8", + "cvt.scalef32.pk.f16.fp4" => "__builtin_amdgcn_cvt_scalef32_pk_f16_fp4", + "cvt.scalef32.pk.f16.fp8" => "__builtin_amdgcn_cvt_scalef32_pk_f16_fp8", + "cvt.scalef32.pk.f32.bf8" => "__builtin_amdgcn_cvt_scalef32_pk_f32_bf8", + "cvt.scalef32.pk.f32.fp4" => "__builtin_amdgcn_cvt_scalef32_pk_f32_fp4", + "cvt.scalef32.pk.f32.fp8" => "__builtin_amdgcn_cvt_scalef32_pk_f32_fp8", + "cvt.scalef32.pk.fp4.bf16" => "__builtin_amdgcn_cvt_scalef32_pk_fp4_bf16", + "cvt.scalef32.pk.fp4.f16" => "__builtin_amdgcn_cvt_scalef32_pk_fp4_f16", + "cvt.scalef32.pk.fp4.f32" => "__builtin_amdgcn_cvt_scalef32_pk_fp4_f32", + "cvt.scalef32.pk.fp8.bf16" => "__builtin_amdgcn_cvt_scalef32_pk_fp8_bf16", + "cvt.scalef32.pk.fp8.f16" => "__builtin_amdgcn_cvt_scalef32_pk_fp8_f16", + "cvt.scalef32.pk.fp8.f32" => "__builtin_amdgcn_cvt_scalef32_pk_fp8_f32", + "cvt.scalef32.pk32.bf16.bf6" => "__builtin_amdgcn_cvt_scalef32_pk32_bf16_bf6", + "cvt.scalef32.pk32.bf16.fp6" => "__builtin_amdgcn_cvt_scalef32_pk32_bf16_fp6", + "cvt.scalef32.pk32.bf6.bf16" => "__builtin_amdgcn_cvt_scalef32_pk32_bf6_bf16", + "cvt.scalef32.pk32.bf6.f16" => "__builtin_amdgcn_cvt_scalef32_pk32_bf6_f16", + "cvt.scalef32.pk32.f16.bf6" => "__builtin_amdgcn_cvt_scalef32_pk32_f16_bf6", + "cvt.scalef32.pk32.f16.fp6" => "__builtin_amdgcn_cvt_scalef32_pk32_f16_fp6", + "cvt.scalef32.pk32.f32.bf6" => "__builtin_amdgcn_cvt_scalef32_pk32_f32_bf6", + "cvt.scalef32.pk32.f32.fp6" => "__builtin_amdgcn_cvt_scalef32_pk32_f32_fp6", + "cvt.scalef32.pk32.fp6.bf16" => "__builtin_amdgcn_cvt_scalef32_pk32_fp6_bf16", + "cvt.scalef32.pk32.fp6.f16" => "__builtin_amdgcn_cvt_scalef32_pk32_fp6_f16", + "cvt.scalef32.sr.bf8.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_bf8_bf16", + "cvt.scalef32.sr.bf8.f16" => "__builtin_amdgcn_cvt_scalef32_sr_bf8_f16", + "cvt.scalef32.sr.bf8.f32" => "__builtin_amdgcn_cvt_scalef32_sr_bf8_f32", + "cvt.scalef32.sr.fp8.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_fp8_bf16", + "cvt.scalef32.sr.fp8.f16" => "__builtin_amdgcn_cvt_scalef32_sr_fp8_f16", + "cvt.scalef32.sr.fp8.f32" => "__builtin_amdgcn_cvt_scalef32_sr_fp8_f32", + "cvt.scalef32.sr.pk.fp4.bf16" => "__builtin_amdgcn_cvt_scalef32_sr_pk_fp4_bf16", + "cvt.scalef32.sr.pk.fp4.f16" => "__builtin_amdgcn_cvt_scalef32_sr_pk_fp4_f16", + "cvt.scalef32.sr.pk.fp4.f32" => "__builtin_amdgcn_cvt_scalef32_sr_pk_fp4_f32", + "cvt.scalef32.sr.pk32.bf6.bf16" => { + "__builtin_amdgcn_cvt_scalef32_sr_pk32_bf6_bf16" + } + "cvt.scalef32.sr.pk32.bf6.f16" => { + "__builtin_amdgcn_cvt_scalef32_sr_pk32_bf6_f16" + } + "cvt.scalef32.sr.pk32.bf6.f32" => { + "__builtin_amdgcn_cvt_scalef32_sr_pk32_bf6_f32" + } + "cvt.scalef32.sr.pk32.fp6.bf16" => { + "__builtin_amdgcn_cvt_scalef32_sr_pk32_fp6_bf16" + } + "cvt.scalef32.sr.pk32.fp6.f16" => { + "__builtin_amdgcn_cvt_scalef32_sr_pk32_fp6_f16" + } + "cvt.scalef32.sr.pk32.fp6.f32" => { + "__builtin_amdgcn_cvt_scalef32_sr_pk32_fp6_f32" + } + "cvt.sr.bf16.f32" => "__builtin_amdgcn_cvt_sr_bf16_f32", + "cvt.sr.bf8.f32" => "__builtin_amdgcn_cvt_sr_bf8_f32", + "cvt.sr.f16.f32" => "__builtin_amdgcn_cvt_sr_f16_f32", + "cvt.sr.fp8.f32" => "__builtin_amdgcn_cvt_sr_fp8_f32", + "dispatch.id" => "__builtin_amdgcn_dispatch_id", + "dot4.f32.bf8.bf8" => "__builtin_amdgcn_dot4_f32_bf8_bf8", + "dot4.f32.bf8.fp8" => "__builtin_amdgcn_dot4_f32_bf8_fp8", + "dot4.f32.fp8.bf8" => "__builtin_amdgcn_dot4_f32_fp8_bf8", + "dot4.f32.fp8.fp8" => "__builtin_amdgcn_dot4_f32_fp8_fp8", + "ds.add.gs.reg.rtn" => "__builtin_amdgcn_ds_add_gs_reg_rtn", + "ds.bpermute" => "__builtin_amdgcn_ds_bpermute", + "ds.bpermute.fi.b32" => "__builtin_amdgcn_ds_bpermute_fi_b32", + "ds.gws.barrier" => "__builtin_amdgcn_ds_gws_barrier", + "ds.gws.init" => "__builtin_amdgcn_ds_gws_init", + "ds.gws.sema.br" => "__builtin_amdgcn_ds_gws_sema_br", + "ds.gws.sema.p" => "__builtin_amdgcn_ds_gws_sema_p", + "ds.gws.sema.release.all" => "__builtin_amdgcn_ds_gws_sema_release_all", + "ds.gws.sema.v" => "__builtin_amdgcn_ds_gws_sema_v", + "ds.permute" => "__builtin_amdgcn_ds_permute", + "ds.sub.gs.reg.rtn" => "__builtin_amdgcn_ds_sub_gs_reg_rtn", + "ds.swizzle" => "__builtin_amdgcn_ds_swizzle", + "endpgm" => "__builtin_amdgcn_endpgm", + "fdot2" => "__builtin_amdgcn_fdot2", + "fdot2.bf16.bf16" => "__builtin_amdgcn_fdot2_bf16_bf16", + "fdot2.f16.f16" => "__builtin_amdgcn_fdot2_f16_f16", + "fdot2.f32.bf16" => "__builtin_amdgcn_fdot2_f32_bf16", + "fdot2c.f32.bf16" => "__builtin_amdgcn_fdot2c_f32_bf16", + "fmul.legacy" => "__builtin_amdgcn_fmul_legacy", + "global.load.lds" => "__builtin_amdgcn_global_load_lds", + "groupstaticsize" => "__builtin_amdgcn_groupstaticsize", + "iglp.opt" => "__builtin_amdgcn_iglp_opt", + "implicit.buffer.ptr" => "__builtin_amdgcn_implicit_buffer_ptr", + "implicitarg.ptr" => "__builtin_amdgcn_implicitarg_ptr", + "interp.mov" => "__builtin_amdgcn_interp_mov", + "interp.p1" => "__builtin_amdgcn_interp_p1", + "interp.p1.f16" => "__builtin_amdgcn_interp_p1_f16", + "interp.p2" => "__builtin_amdgcn_interp_p2", + "interp.p2.f16" => "__builtin_amdgcn_interp_p2_f16", + "is.private" => "__builtin_amdgcn_is_private", + "is.shared" => "__builtin_amdgcn_is_shared", + "kernarg.segment.ptr" => "__builtin_amdgcn_kernarg_segment_ptr", + "lerp" => "__builtin_amdgcn_lerp", + "mbcnt.hi" => "__builtin_amdgcn_mbcnt_hi", + "mbcnt.lo" => "__builtin_amdgcn_mbcnt_lo", + "mfma.f32.16x16x16bf16.1k" => "__builtin_amdgcn_mfma_f32_16x16x16bf16_1k", + "mfma.f32.16x16x16f16" => "__builtin_amdgcn_mfma_f32_16x16x16f16", + "mfma.f32.16x16x1f32" => "__builtin_amdgcn_mfma_f32_16x16x1f32", + "mfma.f32.16x16x2bf16" => "__builtin_amdgcn_mfma_f32_16x16x2bf16", + "mfma.f32.16x16x32.bf16" => "__builtin_amdgcn_mfma_f32_16x16x32_bf16", + "mfma.f32.16x16x32.bf8.bf8" => "__builtin_amdgcn_mfma_f32_16x16x32_bf8_bf8", + "mfma.f32.16x16x32.bf8.fp8" => "__builtin_amdgcn_mfma_f32_16x16x32_bf8_fp8", + "mfma.f32.16x16x32.f16" => "__builtin_amdgcn_mfma_f32_16x16x32_f16", + "mfma.f32.16x16x32.fp8.bf8" => "__builtin_amdgcn_mfma_f32_16x16x32_fp8_bf8", + "mfma.f32.16x16x32.fp8.fp8" => "__builtin_amdgcn_mfma_f32_16x16x32_fp8_fp8", + "mfma.f32.16x16x4bf16.1k" => "__builtin_amdgcn_mfma_f32_16x16x4bf16_1k", + "mfma.f32.16x16x4f16" => "__builtin_amdgcn_mfma_f32_16x16x4f16", + "mfma.f32.16x16x4f32" => "__builtin_amdgcn_mfma_f32_16x16x4f32", + "mfma.f32.16x16x8.xf32" => "__builtin_amdgcn_mfma_f32_16x16x8_xf32", + "mfma.f32.16x16x8bf16" => "__builtin_amdgcn_mfma_f32_16x16x8bf16", + "mfma.f32.32x32x16.bf16" => "__builtin_amdgcn_mfma_f32_32x32x16_bf16", + "mfma.f32.32x32x16.bf8.bf8" => "__builtin_amdgcn_mfma_f32_32x32x16_bf8_bf8", + "mfma.f32.32x32x16.bf8.fp8" => "__builtin_amdgcn_mfma_f32_32x32x16_bf8_fp8", + "mfma.f32.32x32x16.f16" => "__builtin_amdgcn_mfma_f32_32x32x16_f16", + "mfma.f32.32x32x16.fp8.bf8" => "__builtin_amdgcn_mfma_f32_32x32x16_fp8_bf8", + "mfma.f32.32x32x16.fp8.fp8" => "__builtin_amdgcn_mfma_f32_32x32x16_fp8_fp8", + "mfma.f32.32x32x1f32" => "__builtin_amdgcn_mfma_f32_32x32x1f32", + "mfma.f32.32x32x2bf16" => "__builtin_amdgcn_mfma_f32_32x32x2bf16", + "mfma.f32.32x32x2f32" => "__builtin_amdgcn_mfma_f32_32x32x2f32", + "mfma.f32.32x32x4.xf32" => "__builtin_amdgcn_mfma_f32_32x32x4_xf32", + "mfma.f32.32x32x4bf16" => "__builtin_amdgcn_mfma_f32_32x32x4bf16", + "mfma.f32.32x32x4bf16.1k" => "__builtin_amdgcn_mfma_f32_32x32x4bf16_1k", + "mfma.f32.32x32x4f16" => "__builtin_amdgcn_mfma_f32_32x32x4f16", + "mfma.f32.32x32x8bf16.1k" => "__builtin_amdgcn_mfma_f32_32x32x8bf16_1k", + "mfma.f32.32x32x8f16" => "__builtin_amdgcn_mfma_f32_32x32x8f16", + "mfma.f32.4x4x1f32" => "__builtin_amdgcn_mfma_f32_4x4x1f32", + "mfma.f32.4x4x2bf16" => "__builtin_amdgcn_mfma_f32_4x4x2bf16", + "mfma.f32.4x4x4bf16.1k" => "__builtin_amdgcn_mfma_f32_4x4x4bf16_1k", + "mfma.f32.4x4x4f16" => "__builtin_amdgcn_mfma_f32_4x4x4f16", + "mfma.f64.16x16x4f64" => "__builtin_amdgcn_mfma_f64_16x16x4f64", + "mfma.f64.4x4x4f64" => "__builtin_amdgcn_mfma_f64_4x4x4f64", + "mfma.i32.16x16x16i8" => "__builtin_amdgcn_mfma_i32_16x16x16i8", + "mfma.i32.16x16x32.i8" => "__builtin_amdgcn_mfma_i32_16x16x32_i8", + "mfma.i32.16x16x4i8" => "__builtin_amdgcn_mfma_i32_16x16x4i8", + "mfma.i32.16x16x64.i8" => "__builtin_amdgcn_mfma_i32_16x16x64_i8", + "mfma.i32.32x32x16.i8" => "__builtin_amdgcn_mfma_i32_32x32x16_i8", + "mfma.i32.32x32x32.i8" => "__builtin_amdgcn_mfma_i32_32x32x32_i8", + "mfma.i32.32x32x4i8" => "__builtin_amdgcn_mfma_i32_32x32x4i8", + "mfma.i32.32x32x8i8" => "__builtin_amdgcn_mfma_i32_32x32x8i8", + "mfma.i32.4x4x4i8" => "__builtin_amdgcn_mfma_i32_4x4x4i8", + "mqsad.pk.u16.u8" => "__builtin_amdgcn_mqsad_pk_u16_u8", + "mqsad.u32.u8" => "__builtin_amdgcn_mqsad_u32_u8", + "msad.u8" => "__builtin_amdgcn_msad_u8", + "perm" => "__builtin_amdgcn_perm", + "permlane16.var" => "__builtin_amdgcn_permlane16_var", + "permlanex16.var" => "__builtin_amdgcn_permlanex16_var", + "prng.b32" => "__builtin_amdgcn_prng_b32", + "qsad.pk.u16.u8" => "__builtin_amdgcn_qsad_pk_u16_u8", + "queue.ptr" => "__builtin_amdgcn_queue_ptr", + "raw.ptr.buffer.load.lds" => "__builtin_amdgcn_raw_ptr_buffer_load_lds", + "rcp.legacy" => "__builtin_amdgcn_rcp_legacy", + "rsq.legacy" => "__builtin_amdgcn_rsq_legacy", + "s.barrier" => "__builtin_amdgcn_s_barrier", + "s.barrier.signal" => "__builtin_amdgcn_s_barrier_signal", + "s.barrier.signal.isfirst" => "__builtin_amdgcn_s_barrier_signal_isfirst", + "s.barrier.signal.var" => "__builtin_amdgcn_s_barrier_signal_var", + "s.barrier.wait" => "__builtin_amdgcn_s_barrier_wait", + "s.buffer.prefetch.data" => "__builtin_amdgcn_s_buffer_prefetch_data", + "s.dcache.inv" => "__builtin_amdgcn_s_dcache_inv", + "s.dcache.inv.vol" => "__builtin_amdgcn_s_dcache_inv_vol", + "s.dcache.wb" => "__builtin_amdgcn_s_dcache_wb", + "s.dcache.wb.vol" => "__builtin_amdgcn_s_dcache_wb_vol", + "s.decperflevel" => "__builtin_amdgcn_s_decperflevel", + "s.get.barrier.state" => "__builtin_amdgcn_s_get_barrier_state", + "s.get.named.barrier.state" => "__builtin_amdgcn_s_get_named_barrier_state", + "s.get.waveid.in.workgroup" => "__builtin_amdgcn_s_get_waveid_in_workgroup", + "s.getpc" => "__builtin_amdgcn_s_getpc", + "s.getreg" => "__builtin_amdgcn_s_getreg", + "s.incperflevel" => "__builtin_amdgcn_s_incperflevel", + "s.memrealtime" => "__builtin_amdgcn_s_memrealtime", + "s.memtime" => "__builtin_amdgcn_s_memtime", + "s.sendmsg" => "__builtin_amdgcn_s_sendmsg", + "s.sendmsghalt" => "__builtin_amdgcn_s_sendmsghalt", + "s.setprio" => "__builtin_amdgcn_s_setprio", + "s.setreg" => "__builtin_amdgcn_s_setreg", + "s.sleep" => "__builtin_amdgcn_s_sleep", + "s.sleep.var" => "__builtin_amdgcn_s_sleep_var", + "s.ttracedata" => "__builtin_amdgcn_s_ttracedata", + "s.ttracedata.imm" => "__builtin_amdgcn_s_ttracedata_imm", + "s.wait.event.export.ready" => "__builtin_amdgcn_s_wait_event_export_ready", + "s.waitcnt" => "__builtin_amdgcn_s_waitcnt", + "sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", + "sad.u16" => "__builtin_amdgcn_sad_u16", + "sad.u8" => "__builtin_amdgcn_sad_u8", + "sched.barrier" => "__builtin_amdgcn_sched_barrier", + "sched.group.barrier" => "__builtin_amdgcn_sched_group_barrier", + "sdot2" => "__builtin_amdgcn_sdot2", + "sdot4" => "__builtin_amdgcn_sdot4", + "sdot8" => "__builtin_amdgcn_sdot8", + "smfmac.f32.16x16x128.bf8.bf8" => { + "__builtin_amdgcn_smfmac_f32_16x16x128_bf8_bf8" + } + "smfmac.f32.16x16x128.bf8.fp8" => { + "__builtin_amdgcn_smfmac_f32_16x16x128_bf8_fp8" + } + "smfmac.f32.16x16x128.fp8.bf8" => { + "__builtin_amdgcn_smfmac_f32_16x16x128_fp8_bf8" + } + "smfmac.f32.16x16x128.fp8.fp8" => { + "__builtin_amdgcn_smfmac_f32_16x16x128_fp8_fp8" + } + "smfmac.f32.16x16x32.bf16" => "__builtin_amdgcn_smfmac_f32_16x16x32_bf16", + "smfmac.f32.16x16x32.f16" => "__builtin_amdgcn_smfmac_f32_16x16x32_f16", + "smfmac.f32.16x16x64.bf16" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf16", + "smfmac.f32.16x16x64.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf8_bf8", + "smfmac.f32.16x16x64.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x64_bf8_fp8", + "smfmac.f32.16x16x64.f16" => "__builtin_amdgcn_smfmac_f32_16x16x64_f16", + "smfmac.f32.16x16x64.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_16x16x64_fp8_bf8", + "smfmac.f32.16x16x64.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_16x16x64_fp8_fp8", + "smfmac.f32.32x32x16.bf16" => "__builtin_amdgcn_smfmac_f32_32x32x16_bf16", + "smfmac.f32.32x32x16.f16" => "__builtin_amdgcn_smfmac_f32_32x32x16_f16", + "smfmac.f32.32x32x32.bf16" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf16", + "smfmac.f32.32x32x32.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf8_bf8", + "smfmac.f32.32x32x32.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x32_bf8_fp8", + "smfmac.f32.32x32x32.f16" => "__builtin_amdgcn_smfmac_f32_32x32x32_f16", + "smfmac.f32.32x32x32.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x32_fp8_bf8", + "smfmac.f32.32x32x32.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x32_fp8_fp8", + "smfmac.f32.32x32x64.bf8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x64_bf8_bf8", + "smfmac.f32.32x32x64.bf8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x64_bf8_fp8", + "smfmac.f32.32x32x64.fp8.bf8" => "__builtin_amdgcn_smfmac_f32_32x32x64_fp8_bf8", + "smfmac.f32.32x32x64.fp8.fp8" => "__builtin_amdgcn_smfmac_f32_32x32x64_fp8_fp8", + "smfmac.i32.16x16x128.i8" => "__builtin_amdgcn_smfmac_i32_16x16x128_i8", + "smfmac.i32.16x16x64.i8" => "__builtin_amdgcn_smfmac_i32_16x16x64_i8", + "smfmac.i32.32x32x32.i8" => "__builtin_amdgcn_smfmac_i32_32x32x32_i8", + "smfmac.i32.32x32x64.i8" => "__builtin_amdgcn_smfmac_i32_32x32x64_i8", + "sudot4" => "__builtin_amdgcn_sudot4", + "sudot8" => "__builtin_amdgcn_sudot8", + "udot2" => "__builtin_amdgcn_udot2", + "udot4" => "__builtin_amdgcn_udot4", + "udot8" => "__builtin_amdgcn_udot8", + "wave.barrier" => "__builtin_amdgcn_wave_barrier", + "wavefrontsize" => "__builtin_amdgcn_wavefrontsize", + "workgroup.id.x" => "__builtin_amdgcn_workgroup_id_x", + "workgroup.id.y" => "__builtin_amdgcn_workgroup_id_y", + "workgroup.id.z" => "__builtin_amdgcn_workgroup_id_z", + "workitem.id.x" => "__builtin_amdgcn_workitem_id_x", + "workitem.id.y" => "__builtin_amdgcn_workitem_id_y", + "workitem.id.z" => "__builtin_amdgcn_workitem_id_z", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + amdgcn(name) + } + "arm" => { + #[allow(non_snake_case)] + fn arm(name: &str) -> &str { + match name { + // arm + "cdp" => "__builtin_arm_cdp", + "cdp2" => "__builtin_arm_cdp2", + "cmse.tt" => "__builtin_arm_cmse_TT", + "cmse.tta" => "__builtin_arm_cmse_TTA", + "cmse.ttat" => "__builtin_arm_cmse_TTAT", + "cmse.ttt" => "__builtin_arm_cmse_TTT", + "dmb" => "__builtin_arm_dmb", + "dsb" => "__builtin_arm_dsb", + "get.fpscr" => "__builtin_arm_get_fpscr", + "isb" => "__builtin_arm_isb", + "ldc" => "__builtin_arm_ldc", + "ldc2" => "__builtin_arm_ldc2", + "ldc2l" => "__builtin_arm_ldc2l", + "ldcl" => "__builtin_arm_ldcl", + "mcr" => "__builtin_arm_mcr", + "mcr2" => "__builtin_arm_mcr2", + "mcrr" => "__builtin_arm_mcrr", + "mcrr2" => "__builtin_arm_mcrr2", + "mrc" => "__builtin_arm_mrc", + "mrc2" => "__builtin_arm_mrc2", + "qadd" => "__builtin_arm_qadd", + "qadd16" => "__builtin_arm_qadd16", + "qadd8" => "__builtin_arm_qadd8", + "qasx" => "__builtin_arm_qasx", + "qsax" => "__builtin_arm_qsax", + "qsub" => "__builtin_arm_qsub", + "qsub16" => "__builtin_arm_qsub16", + "qsub8" => "__builtin_arm_qsub8", + "sadd16" => "__builtin_arm_sadd16", + "sadd8" => "__builtin_arm_sadd8", + "sasx" => "__builtin_arm_sasx", + "sel" => "__builtin_arm_sel", + "set.fpscr" => "__builtin_arm_set_fpscr", + "shadd16" => "__builtin_arm_shadd16", + "shadd8" => "__builtin_arm_shadd8", + "shasx" => "__builtin_arm_shasx", + "shsax" => "__builtin_arm_shsax", + "shsub16" => "__builtin_arm_shsub16", + "shsub8" => "__builtin_arm_shsub8", + "smlabb" => "__builtin_arm_smlabb", + "smlabt" => "__builtin_arm_smlabt", + "smlad" => "__builtin_arm_smlad", + "smladx" => "__builtin_arm_smladx", + "smlald" => "__builtin_arm_smlald", + "smlaldx" => "__builtin_arm_smlaldx", + "smlatb" => "__builtin_arm_smlatb", + "smlatt" => "__builtin_arm_smlatt", + "smlawb" => "__builtin_arm_smlawb", + "smlawt" => "__builtin_arm_smlawt", + "smlsd" => "__builtin_arm_smlsd", + "smlsdx" => "__builtin_arm_smlsdx", + "smlsld" => "__builtin_arm_smlsld", + "smlsldx" => "__builtin_arm_smlsldx", + "smuad" => "__builtin_arm_smuad", + "smuadx" => "__builtin_arm_smuadx", + "smulbb" => "__builtin_arm_smulbb", + "smulbt" => "__builtin_arm_smulbt", + "smultb" => "__builtin_arm_smultb", + "smultt" => "__builtin_arm_smultt", + "smulwb" => "__builtin_arm_smulwb", + "smulwt" => "__builtin_arm_smulwt", + "smusd" => "__builtin_arm_smusd", + "smusdx" => "__builtin_arm_smusdx", + "ssat" => "__builtin_arm_ssat", + "ssat16" => "__builtin_arm_ssat16", + "ssax" => "__builtin_arm_ssax", + "ssub16" => "__builtin_arm_ssub16", + "ssub8" => "__builtin_arm_ssub8", + "stc" => "__builtin_arm_stc", + "stc2" => "__builtin_arm_stc2", + "stc2l" => "__builtin_arm_stc2l", + "stcl" => "__builtin_arm_stcl", + "sxtab16" => "__builtin_arm_sxtab16", + "sxtb16" => "__builtin_arm_sxtb16", + "thread.pointer" => "__builtin_thread_pointer", + "uadd16" => "__builtin_arm_uadd16", + "uadd8" => "__builtin_arm_uadd8", + "uasx" => "__builtin_arm_uasx", + "uhadd16" => "__builtin_arm_uhadd16", + "uhadd8" => "__builtin_arm_uhadd8", + "uhasx" => "__builtin_arm_uhasx", + "uhsax" => "__builtin_arm_uhsax", + "uhsub16" => "__builtin_arm_uhsub16", + "uhsub8" => "__builtin_arm_uhsub8", + "uqadd16" => "__builtin_arm_uqadd16", + "uqadd8" => "__builtin_arm_uqadd8", + "uqasx" => "__builtin_arm_uqasx", + "uqsax" => "__builtin_arm_uqsax", + "uqsub16" => "__builtin_arm_uqsub16", + "uqsub8" => "__builtin_arm_uqsub8", + "usad8" => "__builtin_arm_usad8", + "usada8" => "__builtin_arm_usada8", + "usat" => "__builtin_arm_usat", + "usat16" => "__builtin_arm_usat16", + "usax" => "__builtin_arm_usax", + "usub16" => "__builtin_arm_usub16", + "usub8" => "__builtin_arm_usub8", + "uxtab16" => "__builtin_arm_uxtab16", + "uxtb16" => "__builtin_arm_uxtb16", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + arm(name) + } + "bpf" => { + #[allow(non_snake_case)] + fn bpf(name: &str) -> &str { + match name { + // bpf + "btf.type.id" => "__builtin_bpf_btf_type_id", + "compare" => "__builtin_bpf_compare", + "getelementptr.and.load" => "__builtin_bpf_getelementptr_and_load", + "getelementptr.and.store" => "__builtin_bpf_getelementptr_and_store", + "load.byte" => "__builtin_bpf_load_byte", + "load.half" => "__builtin_bpf_load_half", + "load.word" => "__builtin_bpf_load_word", + "passthrough" => "__builtin_bpf_passthrough", + "preserve.enum.value" => "__builtin_bpf_preserve_enum_value", + "preserve.field.info" => "__builtin_bpf_preserve_field_info", + "preserve.type.info" => "__builtin_bpf_preserve_type_info", + "pseudo" => "__builtin_bpf_pseudo", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + bpf(name) + } + "cuda" => { + #[allow(non_snake_case)] + fn cuda(name: &str) -> &str { + match name { + // cuda + "syncthreads" => "__syncthreads", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + cuda(name) + } + "hexagon" => { + #[allow(non_snake_case)] + fn hexagon(name: &str) -> &str { + match name { + // hexagon + "A2.abs" => "__builtin_HEXAGON_A2_abs", + "A2.absp" => "__builtin_HEXAGON_A2_absp", + "A2.abssat" => "__builtin_HEXAGON_A2_abssat", + "A2.add" => "__builtin_HEXAGON_A2_add", + "A2.addh.h16.hh" => "__builtin_HEXAGON_A2_addh_h16_hh", + "A2.addh.h16.hl" => "__builtin_HEXAGON_A2_addh_h16_hl", + "A2.addh.h16.lh" => "__builtin_HEXAGON_A2_addh_h16_lh", + "A2.addh.h16.ll" => "__builtin_HEXAGON_A2_addh_h16_ll", + "A2.addh.h16.sat.hh" => "__builtin_HEXAGON_A2_addh_h16_sat_hh", + "A2.addh.h16.sat.hl" => "__builtin_HEXAGON_A2_addh_h16_sat_hl", + "A2.addh.h16.sat.lh" => "__builtin_HEXAGON_A2_addh_h16_sat_lh", + "A2.addh.h16.sat.ll" => "__builtin_HEXAGON_A2_addh_h16_sat_ll", + "A2.addh.l16.hl" => "__builtin_HEXAGON_A2_addh_l16_hl", + "A2.addh.l16.ll" => "__builtin_HEXAGON_A2_addh_l16_ll", + "A2.addh.l16.sat.hl" => "__builtin_HEXAGON_A2_addh_l16_sat_hl", + "A2.addh.l16.sat.ll" => "__builtin_HEXAGON_A2_addh_l16_sat_ll", + "A2.addi" => "__builtin_HEXAGON_A2_addi", + "A2.addp" => "__builtin_HEXAGON_A2_addp", + "A2.addpsat" => "__builtin_HEXAGON_A2_addpsat", + "A2.addsat" => "__builtin_HEXAGON_A2_addsat", + "A2.addsp" => "__builtin_HEXAGON_A2_addsp", + "A2.and" => "__builtin_HEXAGON_A2_and", + "A2.andir" => "__builtin_HEXAGON_A2_andir", + "A2.andp" => "__builtin_HEXAGON_A2_andp", + "A2.aslh" => "__builtin_HEXAGON_A2_aslh", + "A2.asrh" => "__builtin_HEXAGON_A2_asrh", + "A2.combine.hh" => "__builtin_HEXAGON_A2_combine_hh", + "A2.combine.hl" => "__builtin_HEXAGON_A2_combine_hl", + "A2.combine.lh" => "__builtin_HEXAGON_A2_combine_lh", + "A2.combine.ll" => "__builtin_HEXAGON_A2_combine_ll", + "A2.combineii" => "__builtin_HEXAGON_A2_combineii", + "A2.combinew" => "__builtin_HEXAGON_A2_combinew", + "A2.max" => "__builtin_HEXAGON_A2_max", + "A2.maxp" => "__builtin_HEXAGON_A2_maxp", + "A2.maxu" => "__builtin_HEXAGON_A2_maxu", + "A2.maxup" => "__builtin_HEXAGON_A2_maxup", + "A2.min" => "__builtin_HEXAGON_A2_min", + "A2.minp" => "__builtin_HEXAGON_A2_minp", + "A2.minu" => "__builtin_HEXAGON_A2_minu", + "A2.minup" => "__builtin_HEXAGON_A2_minup", + "A2.neg" => "__builtin_HEXAGON_A2_neg", + "A2.negp" => "__builtin_HEXAGON_A2_negp", + "A2.negsat" => "__builtin_HEXAGON_A2_negsat", + "A2.not" => "__builtin_HEXAGON_A2_not", + "A2.notp" => "__builtin_HEXAGON_A2_notp", + "A2.or" => "__builtin_HEXAGON_A2_or", + "A2.orir" => "__builtin_HEXAGON_A2_orir", + "A2.orp" => "__builtin_HEXAGON_A2_orp", + "A2.roundsat" => "__builtin_HEXAGON_A2_roundsat", + "A2.sat" => "__builtin_HEXAGON_A2_sat", + "A2.satb" => "__builtin_HEXAGON_A2_satb", + "A2.sath" => "__builtin_HEXAGON_A2_sath", + "A2.satub" => "__builtin_HEXAGON_A2_satub", + "A2.satuh" => "__builtin_HEXAGON_A2_satuh", + "A2.sub" => "__builtin_HEXAGON_A2_sub", + "A2.subh.h16.hh" => "__builtin_HEXAGON_A2_subh_h16_hh", + "A2.subh.h16.hl" => "__builtin_HEXAGON_A2_subh_h16_hl", + "A2.subh.h16.lh" => "__builtin_HEXAGON_A2_subh_h16_lh", + "A2.subh.h16.ll" => "__builtin_HEXAGON_A2_subh_h16_ll", + "A2.subh.h16.sat.hh" => "__builtin_HEXAGON_A2_subh_h16_sat_hh", + "A2.subh.h16.sat.hl" => "__builtin_HEXAGON_A2_subh_h16_sat_hl", + "A2.subh.h16.sat.lh" => "__builtin_HEXAGON_A2_subh_h16_sat_lh", + "A2.subh.h16.sat.ll" => "__builtin_HEXAGON_A2_subh_h16_sat_ll", + "A2.subh.l16.hl" => "__builtin_HEXAGON_A2_subh_l16_hl", + "A2.subh.l16.ll" => "__builtin_HEXAGON_A2_subh_l16_ll", + "A2.subh.l16.sat.hl" => "__builtin_HEXAGON_A2_subh_l16_sat_hl", + "A2.subh.l16.sat.ll" => "__builtin_HEXAGON_A2_subh_l16_sat_ll", + "A2.subp" => "__builtin_HEXAGON_A2_subp", + "A2.subri" => "__builtin_HEXAGON_A2_subri", + "A2.subsat" => "__builtin_HEXAGON_A2_subsat", + "A2.svaddh" => "__builtin_HEXAGON_A2_svaddh", + "A2.svaddhs" => "__builtin_HEXAGON_A2_svaddhs", + "A2.svadduhs" => "__builtin_HEXAGON_A2_svadduhs", + "A2.svavgh" => "__builtin_HEXAGON_A2_svavgh", + "A2.svavghs" => "__builtin_HEXAGON_A2_svavghs", + "A2.svnavgh" => "__builtin_HEXAGON_A2_svnavgh", + "A2.svsubh" => "__builtin_HEXAGON_A2_svsubh", + "A2.svsubhs" => "__builtin_HEXAGON_A2_svsubhs", + "A2.svsubuhs" => "__builtin_HEXAGON_A2_svsubuhs", + "A2.swiz" => "__builtin_HEXAGON_A2_swiz", + "A2.sxtb" => "__builtin_HEXAGON_A2_sxtb", + "A2.sxth" => "__builtin_HEXAGON_A2_sxth", + "A2.sxtw" => "__builtin_HEXAGON_A2_sxtw", + "A2.tfr" => "__builtin_HEXAGON_A2_tfr", + "A2.tfrih" => "__builtin_HEXAGON_A2_tfrih", + "A2.tfril" => "__builtin_HEXAGON_A2_tfril", + "A2.tfrp" => "__builtin_HEXAGON_A2_tfrp", + "A2.tfrpi" => "__builtin_HEXAGON_A2_tfrpi", + "A2.tfrsi" => "__builtin_HEXAGON_A2_tfrsi", + "A2.vabsh" => "__builtin_HEXAGON_A2_vabsh", + "A2.vabshsat" => "__builtin_HEXAGON_A2_vabshsat", + "A2.vabsw" => "__builtin_HEXAGON_A2_vabsw", + "A2.vabswsat" => "__builtin_HEXAGON_A2_vabswsat", + "A2.vaddb.map" => "__builtin_HEXAGON_A2_vaddb_map", + "A2.vaddh" => "__builtin_HEXAGON_A2_vaddh", + "A2.vaddhs" => "__builtin_HEXAGON_A2_vaddhs", + "A2.vaddub" => "__builtin_HEXAGON_A2_vaddub", + "A2.vaddubs" => "__builtin_HEXAGON_A2_vaddubs", + "A2.vadduhs" => "__builtin_HEXAGON_A2_vadduhs", + "A2.vaddw" => "__builtin_HEXAGON_A2_vaddw", + "A2.vaddws" => "__builtin_HEXAGON_A2_vaddws", + "A2.vavgh" => "__builtin_HEXAGON_A2_vavgh", + "A2.vavghcr" => "__builtin_HEXAGON_A2_vavghcr", + "A2.vavghr" => "__builtin_HEXAGON_A2_vavghr", + "A2.vavgub" => "__builtin_HEXAGON_A2_vavgub", + "A2.vavgubr" => "__builtin_HEXAGON_A2_vavgubr", + "A2.vavguh" => "__builtin_HEXAGON_A2_vavguh", + "A2.vavguhr" => "__builtin_HEXAGON_A2_vavguhr", + "A2.vavguw" => "__builtin_HEXAGON_A2_vavguw", + "A2.vavguwr" => "__builtin_HEXAGON_A2_vavguwr", + "A2.vavgw" => "__builtin_HEXAGON_A2_vavgw", + "A2.vavgwcr" => "__builtin_HEXAGON_A2_vavgwcr", + "A2.vavgwr" => "__builtin_HEXAGON_A2_vavgwr", + "A2.vcmpbeq" => "__builtin_HEXAGON_A2_vcmpbeq", + "A2.vcmpbgtu" => "__builtin_HEXAGON_A2_vcmpbgtu", + "A2.vcmpheq" => "__builtin_HEXAGON_A2_vcmpheq", + "A2.vcmphgt" => "__builtin_HEXAGON_A2_vcmphgt", + "A2.vcmphgtu" => "__builtin_HEXAGON_A2_vcmphgtu", + "A2.vcmpweq" => "__builtin_HEXAGON_A2_vcmpweq", + "A2.vcmpwgt" => "__builtin_HEXAGON_A2_vcmpwgt", + "A2.vcmpwgtu" => "__builtin_HEXAGON_A2_vcmpwgtu", + "A2.vconj" => "__builtin_HEXAGON_A2_vconj", + "A2.vmaxb" => "__builtin_HEXAGON_A2_vmaxb", + "A2.vmaxh" => "__builtin_HEXAGON_A2_vmaxh", + "A2.vmaxub" => "__builtin_HEXAGON_A2_vmaxub", + "A2.vmaxuh" => "__builtin_HEXAGON_A2_vmaxuh", + "A2.vmaxuw" => "__builtin_HEXAGON_A2_vmaxuw", + "A2.vmaxw" => "__builtin_HEXAGON_A2_vmaxw", + "A2.vminb" => "__builtin_HEXAGON_A2_vminb", + "A2.vminh" => "__builtin_HEXAGON_A2_vminh", + "A2.vminub" => "__builtin_HEXAGON_A2_vminub", + "A2.vminuh" => "__builtin_HEXAGON_A2_vminuh", + "A2.vminuw" => "__builtin_HEXAGON_A2_vminuw", + "A2.vminw" => "__builtin_HEXAGON_A2_vminw", + "A2.vnavgh" => "__builtin_HEXAGON_A2_vnavgh", + "A2.vnavghcr" => "__builtin_HEXAGON_A2_vnavghcr", + "A2.vnavghr" => "__builtin_HEXAGON_A2_vnavghr", + "A2.vnavgw" => "__builtin_HEXAGON_A2_vnavgw", + "A2.vnavgwcr" => "__builtin_HEXAGON_A2_vnavgwcr", + "A2.vnavgwr" => "__builtin_HEXAGON_A2_vnavgwr", + "A2.vraddub" => "__builtin_HEXAGON_A2_vraddub", + "A2.vraddub.acc" => "__builtin_HEXAGON_A2_vraddub_acc", + "A2.vrsadub" => "__builtin_HEXAGON_A2_vrsadub", + "A2.vrsadub.acc" => "__builtin_HEXAGON_A2_vrsadub_acc", + "A2.vsubb.map" => "__builtin_HEXAGON_A2_vsubb_map", + "A2.vsubh" => "__builtin_HEXAGON_A2_vsubh", + "A2.vsubhs" => "__builtin_HEXAGON_A2_vsubhs", + "A2.vsubub" => "__builtin_HEXAGON_A2_vsubub", + "A2.vsububs" => "__builtin_HEXAGON_A2_vsububs", + "A2.vsubuhs" => "__builtin_HEXAGON_A2_vsubuhs", + "A2.vsubw" => "__builtin_HEXAGON_A2_vsubw", + "A2.vsubws" => "__builtin_HEXAGON_A2_vsubws", + "A2.xor" => "__builtin_HEXAGON_A2_xor", + "A2.xorp" => "__builtin_HEXAGON_A2_xorp", + "A2.zxtb" => "__builtin_HEXAGON_A2_zxtb", + "A2.zxth" => "__builtin_HEXAGON_A2_zxth", + "A4.andn" => "__builtin_HEXAGON_A4_andn", + "A4.andnp" => "__builtin_HEXAGON_A4_andnp", + "A4.bitsplit" => "__builtin_HEXAGON_A4_bitsplit", + "A4.bitspliti" => "__builtin_HEXAGON_A4_bitspliti", + "A4.boundscheck" => "__builtin_HEXAGON_A4_boundscheck", + "A4.cmpbeq" => "__builtin_HEXAGON_A4_cmpbeq", + "A4.cmpbeqi" => "__builtin_HEXAGON_A4_cmpbeqi", + "A4.cmpbgt" => "__builtin_HEXAGON_A4_cmpbgt", + "A4.cmpbgti" => "__builtin_HEXAGON_A4_cmpbgti", + "A4.cmpbgtu" => "__builtin_HEXAGON_A4_cmpbgtu", + "A4.cmpbgtui" => "__builtin_HEXAGON_A4_cmpbgtui", + "A4.cmpheq" => "__builtin_HEXAGON_A4_cmpheq", + "A4.cmpheqi" => "__builtin_HEXAGON_A4_cmpheqi", + "A4.cmphgt" => "__builtin_HEXAGON_A4_cmphgt", + "A4.cmphgti" => "__builtin_HEXAGON_A4_cmphgti", + "A4.cmphgtu" => "__builtin_HEXAGON_A4_cmphgtu", + "A4.cmphgtui" => "__builtin_HEXAGON_A4_cmphgtui", + "A4.combineir" => "__builtin_HEXAGON_A4_combineir", + "A4.combineri" => "__builtin_HEXAGON_A4_combineri", + "A4.cround.ri" => "__builtin_HEXAGON_A4_cround_ri", + "A4.cround.rr" => "__builtin_HEXAGON_A4_cround_rr", + "A4.modwrapu" => "__builtin_HEXAGON_A4_modwrapu", + "A4.orn" => "__builtin_HEXAGON_A4_orn", + "A4.ornp" => "__builtin_HEXAGON_A4_ornp", + "A4.rcmpeq" => "__builtin_HEXAGON_A4_rcmpeq", + "A4.rcmpeqi" => "__builtin_HEXAGON_A4_rcmpeqi", + "A4.rcmpneq" => "__builtin_HEXAGON_A4_rcmpneq", + "A4.rcmpneqi" => "__builtin_HEXAGON_A4_rcmpneqi", + "A4.round.ri" => "__builtin_HEXAGON_A4_round_ri", + "A4.round.ri.sat" => "__builtin_HEXAGON_A4_round_ri_sat", + "A4.round.rr" => "__builtin_HEXAGON_A4_round_rr", + "A4.round.rr.sat" => "__builtin_HEXAGON_A4_round_rr_sat", + "A4.tlbmatch" => "__builtin_HEXAGON_A4_tlbmatch", + "A4.vcmpbeq.any" => "__builtin_HEXAGON_A4_vcmpbeq_any", + "A4.vcmpbeqi" => "__builtin_HEXAGON_A4_vcmpbeqi", + "A4.vcmpbgt" => "__builtin_HEXAGON_A4_vcmpbgt", + "A4.vcmpbgti" => "__builtin_HEXAGON_A4_vcmpbgti", + "A4.vcmpbgtui" => "__builtin_HEXAGON_A4_vcmpbgtui", + "A4.vcmpheqi" => "__builtin_HEXAGON_A4_vcmpheqi", + "A4.vcmphgti" => "__builtin_HEXAGON_A4_vcmphgti", + "A4.vcmphgtui" => "__builtin_HEXAGON_A4_vcmphgtui", + "A4.vcmpweqi" => "__builtin_HEXAGON_A4_vcmpweqi", + "A4.vcmpwgti" => "__builtin_HEXAGON_A4_vcmpwgti", + "A4.vcmpwgtui" => "__builtin_HEXAGON_A4_vcmpwgtui", + "A4.vrmaxh" => "__builtin_HEXAGON_A4_vrmaxh", + "A4.vrmaxuh" => "__builtin_HEXAGON_A4_vrmaxuh", + "A4.vrmaxuw" => "__builtin_HEXAGON_A4_vrmaxuw", + "A4.vrmaxw" => "__builtin_HEXAGON_A4_vrmaxw", + "A4.vrminh" => "__builtin_HEXAGON_A4_vrminh", + "A4.vrminuh" => "__builtin_HEXAGON_A4_vrminuh", + "A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw", + "A4.vrminw" => "__builtin_HEXAGON_A4_vrminw", + "A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs", + "A6.vcmpbeq.notany" => "__builtin_HEXAGON_A6_vcmpbeq_notany", + "A7.clip" => "__builtin_HEXAGON_A7_clip", + "A7.croundd.ri" => "__builtin_HEXAGON_A7_croundd_ri", + "A7.croundd.rr" => "__builtin_HEXAGON_A7_croundd_rr", + "A7.vclip" => "__builtin_HEXAGON_A7_vclip", + "C2.all8" => "__builtin_HEXAGON_C2_all8", + "C2.and" => "__builtin_HEXAGON_C2_and", + "C2.andn" => "__builtin_HEXAGON_C2_andn", + "C2.any8" => "__builtin_HEXAGON_C2_any8", + "C2.bitsclr" => "__builtin_HEXAGON_C2_bitsclr", + "C2.bitsclri" => "__builtin_HEXAGON_C2_bitsclri", + "C2.bitsset" => "__builtin_HEXAGON_C2_bitsset", + "C2.cmpeq" => "__builtin_HEXAGON_C2_cmpeq", + "C2.cmpeqi" => "__builtin_HEXAGON_C2_cmpeqi", + "C2.cmpeqp" => "__builtin_HEXAGON_C2_cmpeqp", + "C2.cmpgei" => "__builtin_HEXAGON_C2_cmpgei", + "C2.cmpgeui" => "__builtin_HEXAGON_C2_cmpgeui", + "C2.cmpgt" => "__builtin_HEXAGON_C2_cmpgt", + "C2.cmpgti" => "__builtin_HEXAGON_C2_cmpgti", + "C2.cmpgtp" => "__builtin_HEXAGON_C2_cmpgtp", + "C2.cmpgtu" => "__builtin_HEXAGON_C2_cmpgtu", + "C2.cmpgtui" => "__builtin_HEXAGON_C2_cmpgtui", + "C2.cmpgtup" => "__builtin_HEXAGON_C2_cmpgtup", + "C2.cmplt" => "__builtin_HEXAGON_C2_cmplt", + "C2.cmpltu" => "__builtin_HEXAGON_C2_cmpltu", + "C2.mask" => "__builtin_HEXAGON_C2_mask", + "C2.mux" => "__builtin_HEXAGON_C2_mux", + "C2.muxii" => "__builtin_HEXAGON_C2_muxii", + "C2.muxir" => "__builtin_HEXAGON_C2_muxir", + "C2.muxri" => "__builtin_HEXAGON_C2_muxri", + "C2.not" => "__builtin_HEXAGON_C2_not", + "C2.or" => "__builtin_HEXAGON_C2_or", + "C2.orn" => "__builtin_HEXAGON_C2_orn", + "C2.pxfer.map" => "__builtin_HEXAGON_C2_pxfer_map", + "C2.tfrpr" => "__builtin_HEXAGON_C2_tfrpr", + "C2.tfrrp" => "__builtin_HEXAGON_C2_tfrrp", + "C2.vitpack" => "__builtin_HEXAGON_C2_vitpack", + "C2.vmux" => "__builtin_HEXAGON_C2_vmux", + "C2.xor" => "__builtin_HEXAGON_C2_xor", + "C4.and.and" => "__builtin_HEXAGON_C4_and_and", + "C4.and.andn" => "__builtin_HEXAGON_C4_and_andn", + "C4.and.or" => "__builtin_HEXAGON_C4_and_or", + "C4.and.orn" => "__builtin_HEXAGON_C4_and_orn", + "C4.cmplte" => "__builtin_HEXAGON_C4_cmplte", + "C4.cmpltei" => "__builtin_HEXAGON_C4_cmpltei", + "C4.cmplteu" => "__builtin_HEXAGON_C4_cmplteu", + "C4.cmplteui" => "__builtin_HEXAGON_C4_cmplteui", + "C4.cmpneq" => "__builtin_HEXAGON_C4_cmpneq", + "C4.cmpneqi" => "__builtin_HEXAGON_C4_cmpneqi", + "C4.fastcorner9" => "__builtin_HEXAGON_C4_fastcorner9", + "C4.fastcorner9.not" => "__builtin_HEXAGON_C4_fastcorner9_not", + "C4.nbitsclr" => "__builtin_HEXAGON_C4_nbitsclr", + "C4.nbitsclri" => "__builtin_HEXAGON_C4_nbitsclri", + "C4.nbitsset" => "__builtin_HEXAGON_C4_nbitsset", + "C4.or.and" => "__builtin_HEXAGON_C4_or_and", + "C4.or.andn" => "__builtin_HEXAGON_C4_or_andn", + "C4.or.or" => "__builtin_HEXAGON_C4_or_or", + "C4.or.orn" => "__builtin_HEXAGON_C4_or_orn", + "F2.conv.d2df" => "__builtin_HEXAGON_F2_conv_d2df", + "F2.conv.d2sf" => "__builtin_HEXAGON_F2_conv_d2sf", + "F2.conv.df2d" => "__builtin_HEXAGON_F2_conv_df2d", + "F2.conv.df2d.chop" => "__builtin_HEXAGON_F2_conv_df2d_chop", + "F2.conv.df2sf" => "__builtin_HEXAGON_F2_conv_df2sf", + "F2.conv.df2ud" => "__builtin_HEXAGON_F2_conv_df2ud", + "F2.conv.df2ud.chop" => "__builtin_HEXAGON_F2_conv_df2ud_chop", + "F2.conv.df2uw" => "__builtin_HEXAGON_F2_conv_df2uw", + "F2.conv.df2uw.chop" => "__builtin_HEXAGON_F2_conv_df2uw_chop", + "F2.conv.df2w" => "__builtin_HEXAGON_F2_conv_df2w", + "F2.conv.df2w.chop" => "__builtin_HEXAGON_F2_conv_df2w_chop", + "F2.conv.sf2d" => "__builtin_HEXAGON_F2_conv_sf2d", + "F2.conv.sf2d.chop" => "__builtin_HEXAGON_F2_conv_sf2d_chop", + "F2.conv.sf2df" => "__builtin_HEXAGON_F2_conv_sf2df", + "F2.conv.sf2ud" => "__builtin_HEXAGON_F2_conv_sf2ud", + "F2.conv.sf2ud.chop" => "__builtin_HEXAGON_F2_conv_sf2ud_chop", + "F2.conv.sf2uw" => "__builtin_HEXAGON_F2_conv_sf2uw", + "F2.conv.sf2uw.chop" => "__builtin_HEXAGON_F2_conv_sf2uw_chop", + "F2.conv.sf2w" => "__builtin_HEXAGON_F2_conv_sf2w", + "F2.conv.sf2w.chop" => "__builtin_HEXAGON_F2_conv_sf2w_chop", + "F2.conv.ud2df" => "__builtin_HEXAGON_F2_conv_ud2df", + "F2.conv.ud2sf" => "__builtin_HEXAGON_F2_conv_ud2sf", + "F2.conv.uw2df" => "__builtin_HEXAGON_F2_conv_uw2df", + "F2.conv.uw2sf" => "__builtin_HEXAGON_F2_conv_uw2sf", + "F2.conv.w2df" => "__builtin_HEXAGON_F2_conv_w2df", + "F2.conv.w2sf" => "__builtin_HEXAGON_F2_conv_w2sf", + "F2.dfadd" => "__builtin_HEXAGON_F2_dfadd", + "F2.dfclass" => "__builtin_HEXAGON_F2_dfclass", + "F2.dfcmpeq" => "__builtin_HEXAGON_F2_dfcmpeq", + "F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge", + "F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt", + "F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo", + "F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd", + "F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn", + "F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr", + "F2.dffma" => "__builtin_HEXAGON_F2_dffma", + "F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib", + "F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc", + "F2.dffms" => "__builtin_HEXAGON_F2_dffms", + "F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib", + "F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n", + "F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p", + "F2.dfmax" => "__builtin_HEXAGON_F2_dfmax", + "F2.dfmin" => "__builtin_HEXAGON_F2_dfmin", + "F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy", + "F2.dfmpyfix" => "__builtin_HEXAGON_F2_dfmpyfix", + "F2.dfmpyhh" => "__builtin_HEXAGON_F2_dfmpyhh", + "F2.dfmpylh" => "__builtin_HEXAGON_F2_dfmpylh", + "F2.dfmpyll" => "__builtin_HEXAGON_F2_dfmpyll", + "F2.dfsub" => "__builtin_HEXAGON_F2_dfsub", + "F2.sfadd" => "__builtin_HEXAGON_F2_sfadd", + "F2.sfclass" => "__builtin_HEXAGON_F2_sfclass", + "F2.sfcmpeq" => "__builtin_HEXAGON_F2_sfcmpeq", + "F2.sfcmpge" => "__builtin_HEXAGON_F2_sfcmpge", + "F2.sfcmpgt" => "__builtin_HEXAGON_F2_sfcmpgt", + "F2.sfcmpuo" => "__builtin_HEXAGON_F2_sfcmpuo", + "F2.sffixupd" => "__builtin_HEXAGON_F2_sffixupd", + "F2.sffixupn" => "__builtin_HEXAGON_F2_sffixupn", + "F2.sffixupr" => "__builtin_HEXAGON_F2_sffixupr", + "F2.sffma" => "__builtin_HEXAGON_F2_sffma", + "F2.sffma.lib" => "__builtin_HEXAGON_F2_sffma_lib", + "F2.sffma.sc" => "__builtin_HEXAGON_F2_sffma_sc", + "F2.sffms" => "__builtin_HEXAGON_F2_sffms", + "F2.sffms.lib" => "__builtin_HEXAGON_F2_sffms_lib", + "F2.sfimm.n" => "__builtin_HEXAGON_F2_sfimm_n", + "F2.sfimm.p" => "__builtin_HEXAGON_F2_sfimm_p", + "F2.sfmax" => "__builtin_HEXAGON_F2_sfmax", + "F2.sfmin" => "__builtin_HEXAGON_F2_sfmin", + "F2.sfmpy" => "__builtin_HEXAGON_F2_sfmpy", + "F2.sfsub" => "__builtin_HEXAGON_F2_sfsub", + "L2.loadw.locked" => "__builtin_HEXAGON_L2_loadw_locked", + "L4.loadd.locked" => "__builtin__HEXAGON_L4_loadd_locked", + "M2.acci" => "__builtin_HEXAGON_M2_acci", + "M2.accii" => "__builtin_HEXAGON_M2_accii", + "M2.cmaci.s0" => "__builtin_HEXAGON_M2_cmaci_s0", + "M2.cmacr.s0" => "__builtin_HEXAGON_M2_cmacr_s0", + "M2.cmacs.s0" => "__builtin_HEXAGON_M2_cmacs_s0", + "M2.cmacs.s1" => "__builtin_HEXAGON_M2_cmacs_s1", + "M2.cmacsc.s0" => "__builtin_HEXAGON_M2_cmacsc_s0", + "M2.cmacsc.s1" => "__builtin_HEXAGON_M2_cmacsc_s1", + "M2.cmpyi.s0" => "__builtin_HEXAGON_M2_cmpyi_s0", + "M2.cmpyr.s0" => "__builtin_HEXAGON_M2_cmpyr_s0", + "M2.cmpyrs.s0" => "__builtin_HEXAGON_M2_cmpyrs_s0", + "M2.cmpyrs.s1" => "__builtin_HEXAGON_M2_cmpyrs_s1", + "M2.cmpyrsc.s0" => "__builtin_HEXAGON_M2_cmpyrsc_s0", + "M2.cmpyrsc.s1" => "__builtin_HEXAGON_M2_cmpyrsc_s1", + "M2.cmpys.s0" => "__builtin_HEXAGON_M2_cmpys_s0", + "M2.cmpys.s1" => "__builtin_HEXAGON_M2_cmpys_s1", + "M2.cmpysc.s0" => "__builtin_HEXAGON_M2_cmpysc_s0", + "M2.cmpysc.s1" => "__builtin_HEXAGON_M2_cmpysc_s1", + "M2.cnacs.s0" => "__builtin_HEXAGON_M2_cnacs_s0", + "M2.cnacs.s1" => "__builtin_HEXAGON_M2_cnacs_s1", + "M2.cnacsc.s0" => "__builtin_HEXAGON_M2_cnacsc_s0", + "M2.cnacsc.s1" => "__builtin_HEXAGON_M2_cnacsc_s1", + "M2.dpmpyss.acc.s0" => "__builtin_HEXAGON_M2_dpmpyss_acc_s0", + "M2.dpmpyss.nac.s0" => "__builtin_HEXAGON_M2_dpmpyss_nac_s0", + "M2.dpmpyss.rnd.s0" => "__builtin_HEXAGON_M2_dpmpyss_rnd_s0", + "M2.dpmpyss.s0" => "__builtin_HEXAGON_M2_dpmpyss_s0", + "M2.dpmpyuu.acc.s0" => "__builtin_HEXAGON_M2_dpmpyuu_acc_s0", + "M2.dpmpyuu.nac.s0" => "__builtin_HEXAGON_M2_dpmpyuu_nac_s0", + "M2.dpmpyuu.s0" => "__builtin_HEXAGON_M2_dpmpyuu_s0", + "M2.hmmpyh.rs1" => "__builtin_HEXAGON_M2_hmmpyh_rs1", + "M2.hmmpyh.s1" => "__builtin_HEXAGON_M2_hmmpyh_s1", + "M2.hmmpyl.rs1" => "__builtin_HEXAGON_M2_hmmpyl_rs1", + "M2.hmmpyl.s1" => "__builtin_HEXAGON_M2_hmmpyl_s1", + "M2.maci" => "__builtin_HEXAGON_M2_maci", + "M2.macsin" => "__builtin_HEXAGON_M2_macsin", + "M2.macsip" => "__builtin_HEXAGON_M2_macsip", + "M2.mmachs.rs0" => "__builtin_HEXAGON_M2_mmachs_rs0", + "M2.mmachs.rs1" => "__builtin_HEXAGON_M2_mmachs_rs1", + "M2.mmachs.s0" => "__builtin_HEXAGON_M2_mmachs_s0", + "M2.mmachs.s1" => "__builtin_HEXAGON_M2_mmachs_s1", + "M2.mmacls.rs0" => "__builtin_HEXAGON_M2_mmacls_rs0", + "M2.mmacls.rs1" => "__builtin_HEXAGON_M2_mmacls_rs1", + "M2.mmacls.s0" => "__builtin_HEXAGON_M2_mmacls_s0", + "M2.mmacls.s1" => "__builtin_HEXAGON_M2_mmacls_s1", + "M2.mmacuhs.rs0" => "__builtin_HEXAGON_M2_mmacuhs_rs0", + "M2.mmacuhs.rs1" => "__builtin_HEXAGON_M2_mmacuhs_rs1", + "M2.mmacuhs.s0" => "__builtin_HEXAGON_M2_mmacuhs_s0", + "M2.mmacuhs.s1" => "__builtin_HEXAGON_M2_mmacuhs_s1", + "M2.mmaculs.rs0" => "__builtin_HEXAGON_M2_mmaculs_rs0", + "M2.mmaculs.rs1" => "__builtin_HEXAGON_M2_mmaculs_rs1", + "M2.mmaculs.s0" => "__builtin_HEXAGON_M2_mmaculs_s0", + "M2.mmaculs.s1" => "__builtin_HEXAGON_M2_mmaculs_s1", + "M2.mmpyh.rs0" => "__builtin_HEXAGON_M2_mmpyh_rs0", + "M2.mmpyh.rs1" => "__builtin_HEXAGON_M2_mmpyh_rs1", + "M2.mmpyh.s0" => "__builtin_HEXAGON_M2_mmpyh_s0", + "M2.mmpyh.s1" => "__builtin_HEXAGON_M2_mmpyh_s1", + "M2.mmpyl.rs0" => "__builtin_HEXAGON_M2_mmpyl_rs0", + "M2.mmpyl.rs1" => "__builtin_HEXAGON_M2_mmpyl_rs1", + "M2.mmpyl.s0" => "__builtin_HEXAGON_M2_mmpyl_s0", + "M2.mmpyl.s1" => "__builtin_HEXAGON_M2_mmpyl_s1", + "M2.mmpyuh.rs0" => "__builtin_HEXAGON_M2_mmpyuh_rs0", + "M2.mmpyuh.rs1" => "__builtin_HEXAGON_M2_mmpyuh_rs1", + "M2.mmpyuh.s0" => "__builtin_HEXAGON_M2_mmpyuh_s0", + "M2.mmpyuh.s1" => "__builtin_HEXAGON_M2_mmpyuh_s1", + "M2.mmpyul.rs0" => "__builtin_HEXAGON_M2_mmpyul_rs0", + "M2.mmpyul.rs1" => "__builtin_HEXAGON_M2_mmpyul_rs1", + "M2.mmpyul.s0" => "__builtin_HEXAGON_M2_mmpyul_s0", + "M2.mmpyul.s1" => "__builtin_HEXAGON_M2_mmpyul_s1", + "M2.mnaci" => "__builtin_HEXAGON_M2_mnaci", + "M2.mpy.acc.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_hh_s0", + "M2.mpy.acc.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_hh_s1", + "M2.mpy.acc.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_hl_s0", + "M2.mpy.acc.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_hl_s1", + "M2.mpy.acc.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_lh_s0", + "M2.mpy.acc.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_lh_s1", + "M2.mpy.acc.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_ll_s0", + "M2.mpy.acc.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_ll_s1", + "M2.mpy.acc.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0", + "M2.mpy.acc.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1", + "M2.mpy.acc.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0", + "M2.mpy.acc.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1", + "M2.mpy.acc.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0", + "M2.mpy.acc.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1", + "M2.mpy.acc.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0", + "M2.mpy.acc.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1", + "M2.mpy.hh.s0" => "__builtin_HEXAGON_M2_mpy_hh_s0", + "M2.mpy.hh.s1" => "__builtin_HEXAGON_M2_mpy_hh_s1", + "M2.mpy.hl.s0" => "__builtin_HEXAGON_M2_mpy_hl_s0", + "M2.mpy.hl.s1" => "__builtin_HEXAGON_M2_mpy_hl_s1", + "M2.mpy.lh.s0" => "__builtin_HEXAGON_M2_mpy_lh_s0", + "M2.mpy.lh.s1" => "__builtin_HEXAGON_M2_mpy_lh_s1", + "M2.mpy.ll.s0" => "__builtin_HEXAGON_M2_mpy_ll_s0", + "M2.mpy.ll.s1" => "__builtin_HEXAGON_M2_mpy_ll_s1", + "M2.mpy.nac.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_hh_s0", + "M2.mpy.nac.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_hh_s1", + "M2.mpy.nac.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_hl_s0", + "M2.mpy.nac.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_hl_s1", + "M2.mpy.nac.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_lh_s0", + "M2.mpy.nac.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_lh_s1", + "M2.mpy.nac.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_ll_s0", + "M2.mpy.nac.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_ll_s1", + "M2.mpy.nac.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0", + "M2.mpy.nac.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1", + "M2.mpy.nac.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0", + "M2.mpy.nac.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1", + "M2.mpy.nac.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0", + "M2.mpy.nac.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1", + "M2.mpy.nac.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0", + "M2.mpy.nac.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1", + "M2.mpy.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s0", + "M2.mpy.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s1", + "M2.mpy.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s0", + "M2.mpy.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s1", + "M2.mpy.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s0", + "M2.mpy.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s1", + "M2.mpy.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s0", + "M2.mpy.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s1", + "M2.mpy.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_hh_s0", + "M2.mpy.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_hh_s1", + "M2.mpy.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_hl_s0", + "M2.mpy.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_hl_s1", + "M2.mpy.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_lh_s0", + "M2.mpy.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_lh_s1", + "M2.mpy.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_ll_s0", + "M2.mpy.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_ll_s1", + "M2.mpy.sat.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0", + "M2.mpy.sat.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1", + "M2.mpy.sat.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0", + "M2.mpy.sat.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1", + "M2.mpy.sat.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0", + "M2.mpy.sat.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1", + "M2.mpy.sat.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0", + "M2.mpy.sat.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1", + "M2.mpy.up" => "__builtin_HEXAGON_M2_mpy_up", + "M2.mpy.up.s1" => "__builtin_HEXAGON_M2_mpy_up_s1", + "M2.mpy.up.s1.sat" => "__builtin_HEXAGON_M2_mpy_up_s1_sat", + "M2.mpyd.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s0", + "M2.mpyd.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s1", + "M2.mpyd.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s0", + "M2.mpyd.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s1", + "M2.mpyd.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s0", + "M2.mpyd.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s1", + "M2.mpyd.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s0", + "M2.mpyd.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s1", + "M2.mpyd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_hh_s0", + "M2.mpyd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_hh_s1", + "M2.mpyd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_hl_s0", + "M2.mpyd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_hl_s1", + "M2.mpyd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_lh_s0", + "M2.mpyd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_lh_s1", + "M2.mpyd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_ll_s0", + "M2.mpyd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_ll_s1", + "M2.mpyd.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s0", + "M2.mpyd.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s1", + "M2.mpyd.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s0", + "M2.mpyd.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s1", + "M2.mpyd.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s0", + "M2.mpyd.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s1", + "M2.mpyd.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s0", + "M2.mpyd.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s1", + "M2.mpyd.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0", + "M2.mpyd.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1", + "M2.mpyd.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s0", + "M2.mpyd.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s1", + "M2.mpyd.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0", + "M2.mpyd.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1", + "M2.mpyd.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s0", + "M2.mpyd.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s1", + "M2.mpyi" => "__builtin_HEXAGON_M2_mpyi", + "M2.mpysmi" => "__builtin_HEXAGON_M2_mpysmi", + "M2.mpysu.up" => "__builtin_HEXAGON_M2_mpysu_up", + "M2.mpyu.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s0", + "M2.mpyu.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s1", + "M2.mpyu.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s0", + "M2.mpyu.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s1", + "M2.mpyu.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s0", + "M2.mpyu.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s1", + "M2.mpyu.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s0", + "M2.mpyu.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s1", + "M2.mpyu.hh.s0" => "__builtin_HEXAGON_M2_mpyu_hh_s0", + "M2.mpyu.hh.s1" => "__builtin_HEXAGON_M2_mpyu_hh_s1", + "M2.mpyu.hl.s0" => "__builtin_HEXAGON_M2_mpyu_hl_s0", + "M2.mpyu.hl.s1" => "__builtin_HEXAGON_M2_mpyu_hl_s1", + "M2.mpyu.lh.s0" => "__builtin_HEXAGON_M2_mpyu_lh_s0", + "M2.mpyu.lh.s1" => "__builtin_HEXAGON_M2_mpyu_lh_s1", + "M2.mpyu.ll.s0" => "__builtin_HEXAGON_M2_mpyu_ll_s0", + "M2.mpyu.ll.s1" => "__builtin_HEXAGON_M2_mpyu_ll_s1", + "M2.mpyu.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s0", + "M2.mpyu.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s1", + "M2.mpyu.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s0", + "M2.mpyu.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s1", + "M2.mpyu.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s0", + "M2.mpyu.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s1", + "M2.mpyu.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s0", + "M2.mpyu.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s1", + "M2.mpyu.up" => "__builtin_HEXAGON_M2_mpyu_up", + "M2.mpyud.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s0", + "M2.mpyud.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s1", + "M2.mpyud.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s0", + "M2.mpyud.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s1", + "M2.mpyud.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s0", + "M2.mpyud.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s1", + "M2.mpyud.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s0", + "M2.mpyud.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s1", + "M2.mpyud.hh.s0" => "__builtin_HEXAGON_M2_mpyud_hh_s0", + "M2.mpyud.hh.s1" => "__builtin_HEXAGON_M2_mpyud_hh_s1", + "M2.mpyud.hl.s0" => "__builtin_HEXAGON_M2_mpyud_hl_s0", + "M2.mpyud.hl.s1" => "__builtin_HEXAGON_M2_mpyud_hl_s1", + "M2.mpyud.lh.s0" => "__builtin_HEXAGON_M2_mpyud_lh_s0", + "M2.mpyud.lh.s1" => "__builtin_HEXAGON_M2_mpyud_lh_s1", + "M2.mpyud.ll.s0" => "__builtin_HEXAGON_M2_mpyud_ll_s0", + "M2.mpyud.ll.s1" => "__builtin_HEXAGON_M2_mpyud_ll_s1", + "M2.mpyud.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s0", + "M2.mpyud.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s1", + "M2.mpyud.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s0", + "M2.mpyud.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s1", + "M2.mpyud.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s0", + "M2.mpyud.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s1", + "M2.mpyud.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s0", + "M2.mpyud.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s1", + "M2.mpyui" => "__builtin_HEXAGON_M2_mpyui", + "M2.nacci" => "__builtin_HEXAGON_M2_nacci", + "M2.naccii" => "__builtin_HEXAGON_M2_naccii", + "M2.subacc" => "__builtin_HEXAGON_M2_subacc", + "M2.vabsdiffh" => "__builtin_HEXAGON_M2_vabsdiffh", + "M2.vabsdiffw" => "__builtin_HEXAGON_M2_vabsdiffw", + "M2.vcmac.s0.sat.i" => "__builtin_HEXAGON_M2_vcmac_s0_sat_i", + "M2.vcmac.s0.sat.r" => "__builtin_HEXAGON_M2_vcmac_s0_sat_r", + "M2.vcmpy.s0.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_i", + "M2.vcmpy.s0.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_r", + "M2.vcmpy.s1.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_i", + "M2.vcmpy.s1.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_r", + "M2.vdmacs.s0" => "__builtin_HEXAGON_M2_vdmacs_s0", + "M2.vdmacs.s1" => "__builtin_HEXAGON_M2_vdmacs_s1", + "M2.vdmpyrs.s0" => "__builtin_HEXAGON_M2_vdmpyrs_s0", + "M2.vdmpyrs.s1" => "__builtin_HEXAGON_M2_vdmpyrs_s1", + "M2.vdmpys.s0" => "__builtin_HEXAGON_M2_vdmpys_s0", + "M2.vdmpys.s1" => "__builtin_HEXAGON_M2_vdmpys_s1", + "M2.vmac2" => "__builtin_HEXAGON_M2_vmac2", + "M2.vmac2es" => "__builtin_HEXAGON_M2_vmac2es", + "M2.vmac2es.s0" => "__builtin_HEXAGON_M2_vmac2es_s0", + "M2.vmac2es.s1" => "__builtin_HEXAGON_M2_vmac2es_s1", + "M2.vmac2s.s0" => "__builtin_HEXAGON_M2_vmac2s_s0", + "M2.vmac2s.s1" => "__builtin_HEXAGON_M2_vmac2s_s1", + "M2.vmac2su.s0" => "__builtin_HEXAGON_M2_vmac2su_s0", + "M2.vmac2su.s1" => "__builtin_HEXAGON_M2_vmac2su_s1", + "M2.vmpy2es.s0" => "__builtin_HEXAGON_M2_vmpy2es_s0", + "M2.vmpy2es.s1" => "__builtin_HEXAGON_M2_vmpy2es_s1", + "M2.vmpy2s.s0" => "__builtin_HEXAGON_M2_vmpy2s_s0", + "M2.vmpy2s.s0pack" => "__builtin_HEXAGON_M2_vmpy2s_s0pack", + "M2.vmpy2s.s1" => "__builtin_HEXAGON_M2_vmpy2s_s1", + "M2.vmpy2s.s1pack" => "__builtin_HEXAGON_M2_vmpy2s_s1pack", + "M2.vmpy2su.s0" => "__builtin_HEXAGON_M2_vmpy2su_s0", + "M2.vmpy2su.s1" => "__builtin_HEXAGON_M2_vmpy2su_s1", + "M2.vraddh" => "__builtin_HEXAGON_M2_vraddh", + "M2.vradduh" => "__builtin_HEXAGON_M2_vradduh", + "M2.vrcmaci.s0" => "__builtin_HEXAGON_M2_vrcmaci_s0", + "M2.vrcmaci.s0c" => "__builtin_HEXAGON_M2_vrcmaci_s0c", + "M2.vrcmacr.s0" => "__builtin_HEXAGON_M2_vrcmacr_s0", + "M2.vrcmacr.s0c" => "__builtin_HEXAGON_M2_vrcmacr_s0c", + "M2.vrcmpyi.s0" => "__builtin_HEXAGON_M2_vrcmpyi_s0", + "M2.vrcmpyi.s0c" => "__builtin_HEXAGON_M2_vrcmpyi_s0c", + "M2.vrcmpyr.s0" => "__builtin_HEXAGON_M2_vrcmpyr_s0", + "M2.vrcmpyr.s0c" => "__builtin_HEXAGON_M2_vrcmpyr_s0c", + "M2.vrcmpys.acc.s1" => "__builtin_HEXAGON_M2_vrcmpys_acc_s1", + "M2.vrcmpys.s1" => "__builtin_HEXAGON_M2_vrcmpys_s1", + "M2.vrcmpys.s1rp" => "__builtin_HEXAGON_M2_vrcmpys_s1rp", + "M2.vrmac.s0" => "__builtin_HEXAGON_M2_vrmac_s0", + "M2.vrmpy.s0" => "__builtin_HEXAGON_M2_vrmpy_s0", + "M2.xor.xacc" => "__builtin_HEXAGON_M2_xor_xacc", + "M4.and.and" => "__builtin_HEXAGON_M4_and_and", + "M4.and.andn" => "__builtin_HEXAGON_M4_and_andn", + "M4.and.or" => "__builtin_HEXAGON_M4_and_or", + "M4.and.xor" => "__builtin_HEXAGON_M4_and_xor", + "M4.cmpyi.wh" => "__builtin_HEXAGON_M4_cmpyi_wh", + "M4.cmpyi.whc" => "__builtin_HEXAGON_M4_cmpyi_whc", + "M4.cmpyr.wh" => "__builtin_HEXAGON_M4_cmpyr_wh", + "M4.cmpyr.whc" => "__builtin_HEXAGON_M4_cmpyr_whc", + "M4.mac.up.s1.sat" => "__builtin_HEXAGON_M4_mac_up_s1_sat", + "M4.mpyri.addi" => "__builtin_HEXAGON_M4_mpyri_addi", + "M4.mpyri.addr" => "__builtin_HEXAGON_M4_mpyri_addr", + "M4.mpyri.addr.u2" => "__builtin_HEXAGON_M4_mpyri_addr_u2", + "M4.mpyrr.addi" => "__builtin_HEXAGON_M4_mpyrr_addi", + "M4.mpyrr.addr" => "__builtin_HEXAGON_M4_mpyrr_addr", + "M4.nac.up.s1.sat" => "__builtin_HEXAGON_M4_nac_up_s1_sat", + "M4.or.and" => "__builtin_HEXAGON_M4_or_and", + "M4.or.andn" => "__builtin_HEXAGON_M4_or_andn", + "M4.or.or" => "__builtin_HEXAGON_M4_or_or", + "M4.or.xor" => "__builtin_HEXAGON_M4_or_xor", + "M4.pmpyw" => "__builtin_HEXAGON_M4_pmpyw", + "M4.pmpyw.acc" => "__builtin_HEXAGON_M4_pmpyw_acc", + "M4.vpmpyh" => "__builtin_HEXAGON_M4_vpmpyh", + "M4.vpmpyh.acc" => "__builtin_HEXAGON_M4_vpmpyh_acc", + "M4.vrmpyeh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s0", + "M4.vrmpyeh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s1", + "M4.vrmpyeh.s0" => "__builtin_HEXAGON_M4_vrmpyeh_s0", + "M4.vrmpyeh.s1" => "__builtin_HEXAGON_M4_vrmpyeh_s1", + "M4.vrmpyoh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s0", + "M4.vrmpyoh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s1", + "M4.vrmpyoh.s0" => "__builtin_HEXAGON_M4_vrmpyoh_s0", + "M4.vrmpyoh.s1" => "__builtin_HEXAGON_M4_vrmpyoh_s1", + "M4.xor.and" => "__builtin_HEXAGON_M4_xor_and", + "M4.xor.andn" => "__builtin_HEXAGON_M4_xor_andn", + "M4.xor.or" => "__builtin_HEXAGON_M4_xor_or", + "M4.xor.xacc" => "__builtin_HEXAGON_M4_xor_xacc", + "M5.vdmacbsu" => "__builtin_HEXAGON_M5_vdmacbsu", + "M5.vdmpybsu" => "__builtin_HEXAGON_M5_vdmpybsu", + "M5.vmacbsu" => "__builtin_HEXAGON_M5_vmacbsu", + "M5.vmacbuu" => "__builtin_HEXAGON_M5_vmacbuu", + "M5.vmpybsu" => "__builtin_HEXAGON_M5_vmpybsu", + "M5.vmpybuu" => "__builtin_HEXAGON_M5_vmpybuu", + "M5.vrmacbsu" => "__builtin_HEXAGON_M5_vrmacbsu", + "M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu", + "M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu", + "M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", + "M6.vabsdiffb" => "__builtin_HEXAGON_M6_vabsdiffb", + "M6.vabsdiffub" => "__builtin_HEXAGON_M6_vabsdiffub", + "M7.dcmpyiw" => "__builtin_HEXAGON_M7_dcmpyiw", + "M7.dcmpyiw.acc" => "__builtin_HEXAGON_M7_dcmpyiw_acc", + "M7.dcmpyiwc" => "__builtin_HEXAGON_M7_dcmpyiwc", + "M7.dcmpyiwc.acc" => "__builtin_HEXAGON_M7_dcmpyiwc_acc", + "M7.dcmpyrw" => "__builtin_HEXAGON_M7_dcmpyrw", + "M7.dcmpyrw.acc" => "__builtin_HEXAGON_M7_dcmpyrw_acc", + "M7.dcmpyrwc" => "__builtin_HEXAGON_M7_dcmpyrwc", + "M7.dcmpyrwc.acc" => "__builtin_HEXAGON_M7_dcmpyrwc_acc", + "M7.vdmpy" => "__builtin_HEXAGON_M7_vdmpy", + "M7.vdmpy.acc" => "__builtin_HEXAGON_M7_vdmpy_acc", + "M7.wcmpyiw" => "__builtin_HEXAGON_M7_wcmpyiw", + "M7.wcmpyiw.rnd" => "__builtin_HEXAGON_M7_wcmpyiw_rnd", + "M7.wcmpyiwc" => "__builtin_HEXAGON_M7_wcmpyiwc", + "M7.wcmpyiwc.rnd" => "__builtin_HEXAGON_M7_wcmpyiwc_rnd", + "M7.wcmpyrw" => "__builtin_HEXAGON_M7_wcmpyrw", + "M7.wcmpyrw.rnd" => "__builtin_HEXAGON_M7_wcmpyrw_rnd", + "M7.wcmpyrwc" => "__builtin_HEXAGON_M7_wcmpyrwc", + "M7.wcmpyrwc.rnd" => "__builtin_HEXAGON_M7_wcmpyrwc_rnd", + "S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri", + "S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p", + "S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc", + "S2.asl.i.p.and" => "__builtin_HEXAGON_S2_asl_i_p_and", + "S2.asl.i.p.nac" => "__builtin_HEXAGON_S2_asl_i_p_nac", + "S2.asl.i.p.or" => "__builtin_HEXAGON_S2_asl_i_p_or", + "S2.asl.i.p.xacc" => "__builtin_HEXAGON_S2_asl_i_p_xacc", + "S2.asl.i.r" => "__builtin_HEXAGON_S2_asl_i_r", + "S2.asl.i.r.acc" => "__builtin_HEXAGON_S2_asl_i_r_acc", + "S2.asl.i.r.and" => "__builtin_HEXAGON_S2_asl_i_r_and", + "S2.asl.i.r.nac" => "__builtin_HEXAGON_S2_asl_i_r_nac", + "S2.asl.i.r.or" => "__builtin_HEXAGON_S2_asl_i_r_or", + "S2.asl.i.r.sat" => "__builtin_HEXAGON_S2_asl_i_r_sat", + "S2.asl.i.r.xacc" => "__builtin_HEXAGON_S2_asl_i_r_xacc", + "S2.asl.i.vh" => "__builtin_HEXAGON_S2_asl_i_vh", + "S2.asl.i.vw" => "__builtin_HEXAGON_S2_asl_i_vw", + "S2.asl.r.p" => "__builtin_HEXAGON_S2_asl_r_p", + "S2.asl.r.p.acc" => "__builtin_HEXAGON_S2_asl_r_p_acc", + "S2.asl.r.p.and" => "__builtin_HEXAGON_S2_asl_r_p_and", + "S2.asl.r.p.nac" => "__builtin_HEXAGON_S2_asl_r_p_nac", + "S2.asl.r.p.or" => "__builtin_HEXAGON_S2_asl_r_p_or", + "S2.asl.r.p.xor" => "__builtin_HEXAGON_S2_asl_r_p_xor", + "S2.asl.r.r" => "__builtin_HEXAGON_S2_asl_r_r", + "S2.asl.r.r.acc" => "__builtin_HEXAGON_S2_asl_r_r_acc", + "S2.asl.r.r.and" => "__builtin_HEXAGON_S2_asl_r_r_and", + "S2.asl.r.r.nac" => "__builtin_HEXAGON_S2_asl_r_r_nac", + "S2.asl.r.r.or" => "__builtin_HEXAGON_S2_asl_r_r_or", + "S2.asl.r.r.sat" => "__builtin_HEXAGON_S2_asl_r_r_sat", + "S2.asl.r.vh" => "__builtin_HEXAGON_S2_asl_r_vh", + "S2.asl.r.vw" => "__builtin_HEXAGON_S2_asl_r_vw", + "S2.asr.i.p" => "__builtin_HEXAGON_S2_asr_i_p", + "S2.asr.i.p.acc" => "__builtin_HEXAGON_S2_asr_i_p_acc", + "S2.asr.i.p.and" => "__builtin_HEXAGON_S2_asr_i_p_and", + "S2.asr.i.p.nac" => "__builtin_HEXAGON_S2_asr_i_p_nac", + "S2.asr.i.p.or" => "__builtin_HEXAGON_S2_asr_i_p_or", + "S2.asr.i.p.rnd" => "__builtin_HEXAGON_S2_asr_i_p_rnd", + "S2.asr.i.p.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax", + "S2.asr.i.r" => "__builtin_HEXAGON_S2_asr_i_r", + "S2.asr.i.r.acc" => "__builtin_HEXAGON_S2_asr_i_r_acc", + "S2.asr.i.r.and" => "__builtin_HEXAGON_S2_asr_i_r_and", + "S2.asr.i.r.nac" => "__builtin_HEXAGON_S2_asr_i_r_nac", + "S2.asr.i.r.or" => "__builtin_HEXAGON_S2_asr_i_r_or", + "S2.asr.i.r.rnd" => "__builtin_HEXAGON_S2_asr_i_r_rnd", + "S2.asr.i.r.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax", + "S2.asr.i.svw.trun" => "__builtin_HEXAGON_S2_asr_i_svw_trun", + "S2.asr.i.vh" => "__builtin_HEXAGON_S2_asr_i_vh", + "S2.asr.i.vw" => "__builtin_HEXAGON_S2_asr_i_vw", + "S2.asr.r.p" => "__builtin_HEXAGON_S2_asr_r_p", + "S2.asr.r.p.acc" => "__builtin_HEXAGON_S2_asr_r_p_acc", + "S2.asr.r.p.and" => "__builtin_HEXAGON_S2_asr_r_p_and", + "S2.asr.r.p.nac" => "__builtin_HEXAGON_S2_asr_r_p_nac", + "S2.asr.r.p.or" => "__builtin_HEXAGON_S2_asr_r_p_or", + "S2.asr.r.p.xor" => "__builtin_HEXAGON_S2_asr_r_p_xor", + "S2.asr.r.r" => "__builtin_HEXAGON_S2_asr_r_r", + "S2.asr.r.r.acc" => "__builtin_HEXAGON_S2_asr_r_r_acc", + "S2.asr.r.r.and" => "__builtin_HEXAGON_S2_asr_r_r_and", + "S2.asr.r.r.nac" => "__builtin_HEXAGON_S2_asr_r_r_nac", + "S2.asr.r.r.or" => "__builtin_HEXAGON_S2_asr_r_r_or", + "S2.asr.r.r.sat" => "__builtin_HEXAGON_S2_asr_r_r_sat", + "S2.asr.r.svw.trun" => "__builtin_HEXAGON_S2_asr_r_svw_trun", + "S2.asr.r.vh" => "__builtin_HEXAGON_S2_asr_r_vh", + "S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw", + "S2.brev" => "__builtin_HEXAGON_S2_brev", + "S2.brevp" => "__builtin_HEXAGON_S2_brevp", + "S2.cabacencbin" => "__builtin_HEXAGON_S2_cabacencbin", + "S2.cl0" => "__builtin_HEXAGON_S2_cl0", + "S2.cl0p" => "__builtin_HEXAGON_S2_cl0p", + "S2.cl1" => "__builtin_HEXAGON_S2_cl1", + "S2.cl1p" => "__builtin_HEXAGON_S2_cl1p", + "S2.clb" => "__builtin_HEXAGON_S2_clb", + "S2.clbnorm" => "__builtin_HEXAGON_S2_clbnorm", + "S2.clbp" => "__builtin_HEXAGON_S2_clbp", + "S2.clrbit.i" => "__builtin_HEXAGON_S2_clrbit_i", + "S2.clrbit.r" => "__builtin_HEXAGON_S2_clrbit_r", + "S2.ct0" => "__builtin_HEXAGON_S2_ct0", + "S2.ct0p" => "__builtin_HEXAGON_S2_ct0p", + "S2.ct1" => "__builtin_HEXAGON_S2_ct1", + "S2.ct1p" => "__builtin_HEXAGON_S2_ct1p", + "S2.deinterleave" => "__builtin_HEXAGON_S2_deinterleave", + "S2.extractu" => "__builtin_HEXAGON_S2_extractu", + "S2.extractu.rp" => "__builtin_HEXAGON_S2_extractu_rp", + "S2.extractup" => "__builtin_HEXAGON_S2_extractup", + "S2.extractup.rp" => "__builtin_HEXAGON_S2_extractup_rp", + "S2.insert" => "__builtin_HEXAGON_S2_insert", + "S2.insert.rp" => "__builtin_HEXAGON_S2_insert_rp", + "S2.insertp" => "__builtin_HEXAGON_S2_insertp", + "S2.insertp.rp" => "__builtin_HEXAGON_S2_insertp_rp", + "S2.interleave" => "__builtin_HEXAGON_S2_interleave", + "S2.lfsp" => "__builtin_HEXAGON_S2_lfsp", + "S2.lsl.r.p" => "__builtin_HEXAGON_S2_lsl_r_p", + "S2.lsl.r.p.acc" => "__builtin_HEXAGON_S2_lsl_r_p_acc", + "S2.lsl.r.p.and" => "__builtin_HEXAGON_S2_lsl_r_p_and", + "S2.lsl.r.p.nac" => "__builtin_HEXAGON_S2_lsl_r_p_nac", + "S2.lsl.r.p.or" => "__builtin_HEXAGON_S2_lsl_r_p_or", + "S2.lsl.r.p.xor" => "__builtin_HEXAGON_S2_lsl_r_p_xor", + "S2.lsl.r.r" => "__builtin_HEXAGON_S2_lsl_r_r", + "S2.lsl.r.r.acc" => "__builtin_HEXAGON_S2_lsl_r_r_acc", + "S2.lsl.r.r.and" => "__builtin_HEXAGON_S2_lsl_r_r_and", + "S2.lsl.r.r.nac" => "__builtin_HEXAGON_S2_lsl_r_r_nac", + "S2.lsl.r.r.or" => "__builtin_HEXAGON_S2_lsl_r_r_or", + "S2.lsl.r.vh" => "__builtin_HEXAGON_S2_lsl_r_vh", + "S2.lsl.r.vw" => "__builtin_HEXAGON_S2_lsl_r_vw", + "S2.lsr.i.p" => "__builtin_HEXAGON_S2_lsr_i_p", + "S2.lsr.i.p.acc" => "__builtin_HEXAGON_S2_lsr_i_p_acc", + "S2.lsr.i.p.and" => "__builtin_HEXAGON_S2_lsr_i_p_and", + "S2.lsr.i.p.nac" => "__builtin_HEXAGON_S2_lsr_i_p_nac", + "S2.lsr.i.p.or" => "__builtin_HEXAGON_S2_lsr_i_p_or", + "S2.lsr.i.p.xacc" => "__builtin_HEXAGON_S2_lsr_i_p_xacc", + "S2.lsr.i.r" => "__builtin_HEXAGON_S2_lsr_i_r", + "S2.lsr.i.r.acc" => "__builtin_HEXAGON_S2_lsr_i_r_acc", + "S2.lsr.i.r.and" => "__builtin_HEXAGON_S2_lsr_i_r_and", + "S2.lsr.i.r.nac" => "__builtin_HEXAGON_S2_lsr_i_r_nac", + "S2.lsr.i.r.or" => "__builtin_HEXAGON_S2_lsr_i_r_or", + "S2.lsr.i.r.xacc" => "__builtin_HEXAGON_S2_lsr_i_r_xacc", + "S2.lsr.i.vh" => "__builtin_HEXAGON_S2_lsr_i_vh", + "S2.lsr.i.vw" => "__builtin_HEXAGON_S2_lsr_i_vw", + "S2.lsr.r.p" => "__builtin_HEXAGON_S2_lsr_r_p", + "S2.lsr.r.p.acc" => "__builtin_HEXAGON_S2_lsr_r_p_acc", + "S2.lsr.r.p.and" => "__builtin_HEXAGON_S2_lsr_r_p_and", + "S2.lsr.r.p.nac" => "__builtin_HEXAGON_S2_lsr_r_p_nac", + "S2.lsr.r.p.or" => "__builtin_HEXAGON_S2_lsr_r_p_or", + "S2.lsr.r.p.xor" => "__builtin_HEXAGON_S2_lsr_r_p_xor", + "S2.lsr.r.r" => "__builtin_HEXAGON_S2_lsr_r_r", + "S2.lsr.r.r.acc" => "__builtin_HEXAGON_S2_lsr_r_r_acc", + "S2.lsr.r.r.and" => "__builtin_HEXAGON_S2_lsr_r_r_and", + "S2.lsr.r.r.nac" => "__builtin_HEXAGON_S2_lsr_r_r_nac", + "S2.lsr.r.r.or" => "__builtin_HEXAGON_S2_lsr_r_r_or", + "S2.lsr.r.vh" => "__builtin_HEXAGON_S2_lsr_r_vh", + "S2.lsr.r.vw" => "__builtin_HEXAGON_S2_lsr_r_vw", + "S2.mask" => "__builtin_HEXAGON_S2_mask", + "S2.packhl" => "__builtin_HEXAGON_S2_packhl", + "S2.parityp" => "__builtin_HEXAGON_S2_parityp", + "S2.setbit.i" => "__builtin_HEXAGON_S2_setbit_i", + "S2.setbit.r" => "__builtin_HEXAGON_S2_setbit_r", + "S2.shuffeb" => "__builtin_HEXAGON_S2_shuffeb", + "S2.shuffeh" => "__builtin_HEXAGON_S2_shuffeh", + "S2.shuffob" => "__builtin_HEXAGON_S2_shuffob", + "S2.shuffoh" => "__builtin_HEXAGON_S2_shuffoh", + "S2.storerb.pbr" => "__builtin_brev_stb", + "S2.storerd.pbr" => "__builtin_brev_std", + "S2.storerf.pbr" => "__builtin_brev_sthhi", + "S2.storerh.pbr" => "__builtin_brev_sth", + "S2.storeri.pbr" => "__builtin_brev_stw", + "S2.storew.locked" => "__builtin_HEXAGON_S2_storew_locked", + "S2.svsathb" => "__builtin_HEXAGON_S2_svsathb", + "S2.svsathub" => "__builtin_HEXAGON_S2_svsathub", + "S2.tableidxb.goodsyntax" => "__builtin_HEXAGON_S2_tableidxb_goodsyntax", + "S2.tableidxd.goodsyntax" => "__builtin_HEXAGON_S2_tableidxd_goodsyntax", + "S2.tableidxh.goodsyntax" => "__builtin_HEXAGON_S2_tableidxh_goodsyntax", + "S2.tableidxw.goodsyntax" => "__builtin_HEXAGON_S2_tableidxw_goodsyntax", + "S2.togglebit.i" => "__builtin_HEXAGON_S2_togglebit_i", + "S2.togglebit.r" => "__builtin_HEXAGON_S2_togglebit_r", + "S2.tstbit.i" => "__builtin_HEXAGON_S2_tstbit_i", + "S2.tstbit.r" => "__builtin_HEXAGON_S2_tstbit_r", + "S2.valignib" => "__builtin_HEXAGON_S2_valignib", + "S2.valignrb" => "__builtin_HEXAGON_S2_valignrb", + "S2.vcnegh" => "__builtin_HEXAGON_S2_vcnegh", + "S2.vcrotate" => "__builtin_HEXAGON_S2_vcrotate", + "S2.vrcnegh" => "__builtin_HEXAGON_S2_vrcnegh", + "S2.vrndpackwh" => "__builtin_HEXAGON_S2_vrndpackwh", + "S2.vrndpackwhs" => "__builtin_HEXAGON_S2_vrndpackwhs", + "S2.vsathb" => "__builtin_HEXAGON_S2_vsathb", + "S2.vsathb.nopack" => "__builtin_HEXAGON_S2_vsathb_nopack", + "S2.vsathub" => "__builtin_HEXAGON_S2_vsathub", + "S2.vsathub.nopack" => "__builtin_HEXAGON_S2_vsathub_nopack", + "S2.vsatwh" => "__builtin_HEXAGON_S2_vsatwh", + "S2.vsatwh.nopack" => "__builtin_HEXAGON_S2_vsatwh_nopack", + "S2.vsatwuh" => "__builtin_HEXAGON_S2_vsatwuh", + "S2.vsatwuh.nopack" => "__builtin_HEXAGON_S2_vsatwuh_nopack", + "S2.vsplatrb" => "__builtin_HEXAGON_S2_vsplatrb", + "S2.vsplatrh" => "__builtin_HEXAGON_S2_vsplatrh", + "S2.vspliceib" => "__builtin_HEXAGON_S2_vspliceib", + "S2.vsplicerb" => "__builtin_HEXAGON_S2_vsplicerb", + "S2.vsxtbh" => "__builtin_HEXAGON_S2_vsxtbh", + "S2.vsxthw" => "__builtin_HEXAGON_S2_vsxthw", + "S2.vtrunehb" => "__builtin_HEXAGON_S2_vtrunehb", + "S2.vtrunewh" => "__builtin_HEXAGON_S2_vtrunewh", + "S2.vtrunohb" => "__builtin_HEXAGON_S2_vtrunohb", + "S2.vtrunowh" => "__builtin_HEXAGON_S2_vtrunowh", + "S2.vzxtbh" => "__builtin_HEXAGON_S2_vzxtbh", + "S2.vzxthw" => "__builtin_HEXAGON_S2_vzxthw", + "S4.addaddi" => "__builtin_HEXAGON_S4_addaddi", + "S4.addi.asl.ri" => "__builtin_HEXAGON_S4_addi_asl_ri", + "S4.addi.lsr.ri" => "__builtin_HEXAGON_S4_addi_lsr_ri", + "S4.andi.asl.ri" => "__builtin_HEXAGON_S4_andi_asl_ri", + "S4.andi.lsr.ri" => "__builtin_HEXAGON_S4_andi_lsr_ri", + "S4.clbaddi" => "__builtin_HEXAGON_S4_clbaddi", + "S4.clbpaddi" => "__builtin_HEXAGON_S4_clbpaddi", + "S4.clbpnorm" => "__builtin_HEXAGON_S4_clbpnorm", + "S4.extract" => "__builtin_HEXAGON_S4_extract", + "S4.extract.rp" => "__builtin_HEXAGON_S4_extract_rp", + "S4.extractp" => "__builtin_HEXAGON_S4_extractp", + "S4.extractp.rp" => "__builtin_HEXAGON_S4_extractp_rp", + "S4.lsli" => "__builtin_HEXAGON_S4_lsli", + "S4.ntstbit.i" => "__builtin_HEXAGON_S4_ntstbit_i", + "S4.ntstbit.r" => "__builtin_HEXAGON_S4_ntstbit_r", + "S4.or.andi" => "__builtin_HEXAGON_S4_or_andi", + "S4.or.andix" => "__builtin_HEXAGON_S4_or_andix", + "S4.or.ori" => "__builtin_HEXAGON_S4_or_ori", + "S4.ori.asl.ri" => "__builtin_HEXAGON_S4_ori_asl_ri", + "S4.ori.lsr.ri" => "__builtin_HEXAGON_S4_ori_lsr_ri", + "S4.parity" => "__builtin_HEXAGON_S4_parity", + "S4.stored.locked" => "__builtin_HEXAGON_S4_stored_locked", + "S4.subaddi" => "__builtin_HEXAGON_S4_subaddi", + "S4.subi.asl.ri" => "__builtin_HEXAGON_S4_subi_asl_ri", + "S4.subi.lsr.ri" => "__builtin_HEXAGON_S4_subi_lsr_ri", + "S4.vrcrotate" => "__builtin_HEXAGON_S4_vrcrotate", + "S4.vrcrotate.acc" => "__builtin_HEXAGON_S4_vrcrotate_acc", + "S4.vxaddsubh" => "__builtin_HEXAGON_S4_vxaddsubh", + "S4.vxaddsubhr" => "__builtin_HEXAGON_S4_vxaddsubhr", + "S4.vxaddsubw" => "__builtin_HEXAGON_S4_vxaddsubw", + "S4.vxsubaddh" => "__builtin_HEXAGON_S4_vxsubaddh", + "S4.vxsubaddhr" => "__builtin_HEXAGON_S4_vxsubaddhr", + "S4.vxsubaddw" => "__builtin_HEXAGON_S4_vxsubaddw", + "S5.asrhub.rnd.sat.goodsyntax" => { + "__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax" + } + "S5.asrhub.sat" => "__builtin_HEXAGON_S5_asrhub_sat", + "S5.popcountp" => "__builtin_HEXAGON_S5_popcountp", + "S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax", + "S6.rol.i.p" => "__builtin_HEXAGON_S6_rol_i_p", + "S6.rol.i.p.acc" => "__builtin_HEXAGON_S6_rol_i_p_acc", + "S6.rol.i.p.and" => "__builtin_HEXAGON_S6_rol_i_p_and", + "S6.rol.i.p.nac" => "__builtin_HEXAGON_S6_rol_i_p_nac", + "S6.rol.i.p.or" => "__builtin_HEXAGON_S6_rol_i_p_or", + "S6.rol.i.p.xacc" => "__builtin_HEXAGON_S6_rol_i_p_xacc", + "S6.rol.i.r" => "__builtin_HEXAGON_S6_rol_i_r", + "S6.rol.i.r.acc" => "__builtin_HEXAGON_S6_rol_i_r_acc", + "S6.rol.i.r.and" => "__builtin_HEXAGON_S6_rol_i_r_and", + "S6.rol.i.r.nac" => "__builtin_HEXAGON_S6_rol_i_r_nac", + "S6.rol.i.r.or" => "__builtin_HEXAGON_S6_rol_i_r_or", + "S6.rol.i.r.xacc" => "__builtin_HEXAGON_S6_rol_i_r_xacc", + "S6.vsplatrbp" => "__builtin_HEXAGON_S6_vsplatrbp", + "S6.vtrunehb.ppp" => "__builtin_HEXAGON_S6_vtrunehb_ppp", + "S6.vtrunohb.ppp" => "__builtin_HEXAGON_S6_vtrunohb_ppp", + "SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", + "V6.extractw" => "__builtin_HEXAGON_V6_extractw", + "V6.extractw.128B" => "__builtin_HEXAGON_V6_extractw_128B", + "V6.get.qfext" => "__builtin_HEXAGON_V6_get_qfext", + "V6.get.qfext.128B" => "__builtin_HEXAGON_V6_get_qfext_128B", + "V6.get.qfext.oracc" => "__builtin_HEXAGON_V6_get_qfext_oracc", + "V6.get.qfext.oracc.128B" => "__builtin_HEXAGON_V6_get_qfext_oracc_128B", + "V6.hi" => "__builtin_HEXAGON_V6_hi", + "V6.hi.128B" => "__builtin_HEXAGON_V6_hi_128B", + "V6.lo" => "__builtin_HEXAGON_V6_lo", + "V6.lo.128B" => "__builtin_HEXAGON_V6_lo_128B", + "V6.lvsplatb" => "__builtin_HEXAGON_V6_lvsplatb", + "V6.lvsplatb.128B" => "__builtin_HEXAGON_V6_lvsplatb_128B", + "V6.lvsplath" => "__builtin_HEXAGON_V6_lvsplath", + "V6.lvsplath.128B" => "__builtin_HEXAGON_V6_lvsplath_128B", + "V6.lvsplatw" => "__builtin_HEXAGON_V6_lvsplatw", + "V6.lvsplatw.128B" => "__builtin_HEXAGON_V6_lvsplatw_128B", + "V6.pred.and" => "__builtin_HEXAGON_V6_pred_and", + "V6.pred.and.128B" => "__builtin_HEXAGON_V6_pred_and_128B", + "V6.pred.and.n" => "__builtin_HEXAGON_V6_pred_and_n", + "V6.pred.and.n.128B" => "__builtin_HEXAGON_V6_pred_and_n_128B", + "V6.pred.not" => "__builtin_HEXAGON_V6_pred_not", + "V6.pred.not.128B" => "__builtin_HEXAGON_V6_pred_not_128B", + "V6.pred.or" => "__builtin_HEXAGON_V6_pred_or", + "V6.pred.or.128B" => "__builtin_HEXAGON_V6_pred_or_128B", + "V6.pred.or.n" => "__builtin_HEXAGON_V6_pred_or_n", + "V6.pred.or.n.128B" => "__builtin_HEXAGON_V6_pred_or_n_128B", + "V6.pred.scalar2" => "__builtin_HEXAGON_V6_pred_scalar2", + "V6.pred.scalar2.128B" => "__builtin_HEXAGON_V6_pred_scalar2_128B", + "V6.pred.scalar2v2" => "__builtin_HEXAGON_V6_pred_scalar2v2", + "V6.pred.scalar2v2.128B" => "__builtin_HEXAGON_V6_pred_scalar2v2_128B", + "V6.pred.xor" => "__builtin_HEXAGON_V6_pred_xor", + "V6.pred.xor.128B" => "__builtin_HEXAGON_V6_pred_xor_128B", + "V6.set.qfext" => "__builtin_HEXAGON_V6_set_qfext", + "V6.set.qfext.128B" => "__builtin_HEXAGON_V6_set_qfext_128B", + "V6.shuffeqh" => "__builtin_HEXAGON_V6_shuffeqh", + "V6.shuffeqh.128B" => "__builtin_HEXAGON_V6_shuffeqh_128B", + "V6.shuffeqw" => "__builtin_HEXAGON_V6_shuffeqw", + "V6.shuffeqw.128B" => "__builtin_HEXAGON_V6_shuffeqw_128B", + "V6.v6mpyhubs10" => "__builtin_HEXAGON_V6_v6mpyhubs10", + "V6.v6mpyhubs10.128B" => "__builtin_HEXAGON_V6_v6mpyhubs10_128B", + "V6.v6mpyhubs10.vxx" => "__builtin_HEXAGON_V6_v6mpyhubs10_vxx", + "V6.v6mpyhubs10.vxx.128B" => "__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B", + "V6.v6mpyvubs10" => "__builtin_HEXAGON_V6_v6mpyvubs10", + "V6.v6mpyvubs10.128B" => "__builtin_HEXAGON_V6_v6mpyvubs10_128B", + "V6.v6mpyvubs10.vxx" => "__builtin_HEXAGON_V6_v6mpyvubs10_vxx", + "V6.v6mpyvubs10.vxx.128B" => "__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B", + "V6.vS32b.nqpred.ai" => "__builtin_HEXAGON_V6_vS32b_nqpred_ai", + "V6.vS32b.nqpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_nqpred_ai_128B", + "V6.vS32b.nt.nqpred.ai" => "__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai", + "V6.vS32b.nt.nqpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai_128B", + "V6.vS32b.nt.qpred.ai" => "__builtin_HEXAGON_V6_vS32b_nt_qpred_ai", + "V6.vS32b.nt.qpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_nt_qpred_ai_128B", + "V6.vS32b.qpred.ai" => "__builtin_HEXAGON_V6_vS32b_qpred_ai", + "V6.vS32b.qpred.ai.128B" => "__builtin_HEXAGON_V6_vS32b_qpred_ai_128B", + "V6.vabs.f8" => "__builtin_HEXAGON_V6_vabs_f8", + "V6.vabs.f8.128B" => "__builtin_HEXAGON_V6_vabs_f8_128B", + "V6.vabs.hf" => "__builtin_HEXAGON_V6_vabs_hf", + "V6.vabs.hf.128B" => "__builtin_HEXAGON_V6_vabs_hf_128B", + "V6.vabs.sf" => "__builtin_HEXAGON_V6_vabs_sf", + "V6.vabs.sf.128B" => "__builtin_HEXAGON_V6_vabs_sf_128B", + "V6.vabsb" => "__builtin_HEXAGON_V6_vabsb", + "V6.vabsb.128B" => "__builtin_HEXAGON_V6_vabsb_128B", + "V6.vabsb.sat" => "__builtin_HEXAGON_V6_vabsb_sat", + "V6.vabsb.sat.128B" => "__builtin_HEXAGON_V6_vabsb_sat_128B", + "V6.vabsdiffh" => "__builtin_HEXAGON_V6_vabsdiffh", + "V6.vabsdiffh.128B" => "__builtin_HEXAGON_V6_vabsdiffh_128B", + "V6.vabsdiffub" => "__builtin_HEXAGON_V6_vabsdiffub", + "V6.vabsdiffub.128B" => "__builtin_HEXAGON_V6_vabsdiffub_128B", + "V6.vabsdiffuh" => "__builtin_HEXAGON_V6_vabsdiffuh", + "V6.vabsdiffuh.128B" => "__builtin_HEXAGON_V6_vabsdiffuh_128B", + "V6.vabsdiffw" => "__builtin_HEXAGON_V6_vabsdiffw", + "V6.vabsdiffw.128B" => "__builtin_HEXAGON_V6_vabsdiffw_128B", + "V6.vabsh" => "__builtin_HEXAGON_V6_vabsh", + "V6.vabsh.128B" => "__builtin_HEXAGON_V6_vabsh_128B", + "V6.vabsh.sat" => "__builtin_HEXAGON_V6_vabsh_sat", + "V6.vabsh.sat.128B" => "__builtin_HEXAGON_V6_vabsh_sat_128B", + "V6.vabsw" => "__builtin_HEXAGON_V6_vabsw", + "V6.vabsw.128B" => "__builtin_HEXAGON_V6_vabsw_128B", + "V6.vabsw.sat" => "__builtin_HEXAGON_V6_vabsw_sat", + "V6.vabsw.sat.128B" => "__builtin_HEXAGON_V6_vabsw_sat_128B", + "V6.vadd.hf" => "__builtin_HEXAGON_V6_vadd_hf", + "V6.vadd.hf.128B" => "__builtin_HEXAGON_V6_vadd_hf_128B", + "V6.vadd.hf.f8" => "__builtin_HEXAGON_V6_vadd_hf_f8", + "V6.vadd.hf.f8.128B" => "__builtin_HEXAGON_V6_vadd_hf_f8_128B", + "V6.vadd.hf.hf" => "__builtin_HEXAGON_V6_vadd_hf_hf", + "V6.vadd.hf.hf.128B" => "__builtin_HEXAGON_V6_vadd_hf_hf_128B", + "V6.vadd.qf16" => "__builtin_HEXAGON_V6_vadd_qf16", + "V6.vadd.qf16.128B" => "__builtin_HEXAGON_V6_vadd_qf16_128B", + "V6.vadd.qf16.mix" => "__builtin_HEXAGON_V6_vadd_qf16_mix", + "V6.vadd.qf16.mix.128B" => "__builtin_HEXAGON_V6_vadd_qf16_mix_128B", + "V6.vadd.qf32" => "__builtin_HEXAGON_V6_vadd_qf32", + "V6.vadd.qf32.128B" => "__builtin_HEXAGON_V6_vadd_qf32_128B", + "V6.vadd.qf32.mix" => "__builtin_HEXAGON_V6_vadd_qf32_mix", + "V6.vadd.qf32.mix.128B" => "__builtin_HEXAGON_V6_vadd_qf32_mix_128B", + "V6.vadd.sf" => "__builtin_HEXAGON_V6_vadd_sf", + "V6.vadd.sf.128B" => "__builtin_HEXAGON_V6_vadd_sf_128B", + "V6.vadd.sf.bf" => "__builtin_HEXAGON_V6_vadd_sf_bf", + "V6.vadd.sf.bf.128B" => "__builtin_HEXAGON_V6_vadd_sf_bf_128B", + "V6.vadd.sf.hf" => "__builtin_HEXAGON_V6_vadd_sf_hf", + "V6.vadd.sf.hf.128B" => "__builtin_HEXAGON_V6_vadd_sf_hf_128B", + "V6.vadd.sf.sf" => "__builtin_HEXAGON_V6_vadd_sf_sf", + "V6.vadd.sf.sf.128B" => "__builtin_HEXAGON_V6_vadd_sf_sf_128B", + "V6.vaddb" => "__builtin_HEXAGON_V6_vaddb", + "V6.vaddb.128B" => "__builtin_HEXAGON_V6_vaddb_128B", + "V6.vaddb.dv" => "__builtin_HEXAGON_V6_vaddb_dv", + "V6.vaddb.dv.128B" => "__builtin_HEXAGON_V6_vaddb_dv_128B", + "V6.vaddbnq" => "__builtin_HEXAGON_V6_vaddbnq", + "V6.vaddbnq.128B" => "__builtin_HEXAGON_V6_vaddbnq_128B", + "V6.vaddbq" => "__builtin_HEXAGON_V6_vaddbq", + "V6.vaddbq.128B" => "__builtin_HEXAGON_V6_vaddbq_128B", + "V6.vaddbsat" => "__builtin_HEXAGON_V6_vaddbsat", + "V6.vaddbsat.128B" => "__builtin_HEXAGON_V6_vaddbsat_128B", + "V6.vaddbsat.dv" => "__builtin_HEXAGON_V6_vaddbsat_dv", + "V6.vaddbsat.dv.128B" => "__builtin_HEXAGON_V6_vaddbsat_dv_128B", + "V6.vaddcarrysat" => "__builtin_HEXAGON_V6_vaddcarrysat", + "V6.vaddcarrysat.128B" => "__builtin_HEXAGON_V6_vaddcarrysat_128B", + "V6.vaddclbh" => "__builtin_HEXAGON_V6_vaddclbh", + "V6.vaddclbh.128B" => "__builtin_HEXAGON_V6_vaddclbh_128B", + "V6.vaddclbw" => "__builtin_HEXAGON_V6_vaddclbw", + "V6.vaddclbw.128B" => "__builtin_HEXAGON_V6_vaddclbw_128B", + "V6.vaddh" => "__builtin_HEXAGON_V6_vaddh", + "V6.vaddh.128B" => "__builtin_HEXAGON_V6_vaddh_128B", + "V6.vaddh.dv" => "__builtin_HEXAGON_V6_vaddh_dv", + "V6.vaddh.dv.128B" => "__builtin_HEXAGON_V6_vaddh_dv_128B", + "V6.vaddhnq" => "__builtin_HEXAGON_V6_vaddhnq", + "V6.vaddhnq.128B" => "__builtin_HEXAGON_V6_vaddhnq_128B", + "V6.vaddhq" => "__builtin_HEXAGON_V6_vaddhq", + "V6.vaddhq.128B" => "__builtin_HEXAGON_V6_vaddhq_128B", + "V6.vaddhsat" => "__builtin_HEXAGON_V6_vaddhsat", + "V6.vaddhsat.128B" => "__builtin_HEXAGON_V6_vaddhsat_128B", + "V6.vaddhsat.dv" => "__builtin_HEXAGON_V6_vaddhsat_dv", + "V6.vaddhsat.dv.128B" => "__builtin_HEXAGON_V6_vaddhsat_dv_128B", + "V6.vaddhw" => "__builtin_HEXAGON_V6_vaddhw", + "V6.vaddhw.128B" => "__builtin_HEXAGON_V6_vaddhw_128B", + "V6.vaddhw.acc" => "__builtin_HEXAGON_V6_vaddhw_acc", + "V6.vaddhw.acc.128B" => "__builtin_HEXAGON_V6_vaddhw_acc_128B", + "V6.vaddubh" => "__builtin_HEXAGON_V6_vaddubh", + "V6.vaddubh.128B" => "__builtin_HEXAGON_V6_vaddubh_128B", + "V6.vaddubh.acc" => "__builtin_HEXAGON_V6_vaddubh_acc", + "V6.vaddubh.acc.128B" => "__builtin_HEXAGON_V6_vaddubh_acc_128B", + "V6.vaddubsat" => "__builtin_HEXAGON_V6_vaddubsat", + "V6.vaddubsat.128B" => "__builtin_HEXAGON_V6_vaddubsat_128B", + "V6.vaddubsat.dv" => "__builtin_HEXAGON_V6_vaddubsat_dv", + "V6.vaddubsat.dv.128B" => "__builtin_HEXAGON_V6_vaddubsat_dv_128B", + "V6.vaddububb.sat" => "__builtin_HEXAGON_V6_vaddububb_sat", + "V6.vaddububb.sat.128B" => "__builtin_HEXAGON_V6_vaddububb_sat_128B", + "V6.vadduhsat" => "__builtin_HEXAGON_V6_vadduhsat", + "V6.vadduhsat.128B" => "__builtin_HEXAGON_V6_vadduhsat_128B", + "V6.vadduhsat.dv" => "__builtin_HEXAGON_V6_vadduhsat_dv", + "V6.vadduhsat.dv.128B" => "__builtin_HEXAGON_V6_vadduhsat_dv_128B", + "V6.vadduhw" => "__builtin_HEXAGON_V6_vadduhw", + "V6.vadduhw.128B" => "__builtin_HEXAGON_V6_vadduhw_128B", + "V6.vadduhw.acc" => "__builtin_HEXAGON_V6_vadduhw_acc", + "V6.vadduhw.acc.128B" => "__builtin_HEXAGON_V6_vadduhw_acc_128B", + "V6.vadduwsat" => "__builtin_HEXAGON_V6_vadduwsat", + "V6.vadduwsat.128B" => "__builtin_HEXAGON_V6_vadduwsat_128B", + "V6.vadduwsat.dv" => "__builtin_HEXAGON_V6_vadduwsat_dv", + "V6.vadduwsat.dv.128B" => "__builtin_HEXAGON_V6_vadduwsat_dv_128B", + "V6.vaddw" => "__builtin_HEXAGON_V6_vaddw", + "V6.vaddw.128B" => "__builtin_HEXAGON_V6_vaddw_128B", + "V6.vaddw.dv" => "__builtin_HEXAGON_V6_vaddw_dv", + "V6.vaddw.dv.128B" => "__builtin_HEXAGON_V6_vaddw_dv_128B", + "V6.vaddwnq" => "__builtin_HEXAGON_V6_vaddwnq", + "V6.vaddwnq.128B" => "__builtin_HEXAGON_V6_vaddwnq_128B", + "V6.vaddwq" => "__builtin_HEXAGON_V6_vaddwq", + "V6.vaddwq.128B" => "__builtin_HEXAGON_V6_vaddwq_128B", + "V6.vaddwsat" => "__builtin_HEXAGON_V6_vaddwsat", + "V6.vaddwsat.128B" => "__builtin_HEXAGON_V6_vaddwsat_128B", + "V6.vaddwsat.dv" => "__builtin_HEXAGON_V6_vaddwsat_dv", + "V6.vaddwsat.dv.128B" => "__builtin_HEXAGON_V6_vaddwsat_dv_128B", + "V6.valignb" => "__builtin_HEXAGON_V6_valignb", + "V6.valignb.128B" => "__builtin_HEXAGON_V6_valignb_128B", + "V6.valignbi" => "__builtin_HEXAGON_V6_valignbi", + "V6.valignbi.128B" => "__builtin_HEXAGON_V6_valignbi_128B", + "V6.vand" => "__builtin_HEXAGON_V6_vand", + "V6.vand.128B" => "__builtin_HEXAGON_V6_vand_128B", + "V6.vandnqrt" => "__builtin_HEXAGON_V6_vandnqrt", + "V6.vandnqrt.128B" => "__builtin_HEXAGON_V6_vandnqrt_128B", + "V6.vandnqrt.acc" => "__builtin_HEXAGON_V6_vandnqrt_acc", + "V6.vandnqrt.acc.128B" => "__builtin_HEXAGON_V6_vandnqrt_acc_128B", + "V6.vandqrt" => "__builtin_HEXAGON_V6_vandqrt", + "V6.vandqrt.128B" => "__builtin_HEXAGON_V6_vandqrt_128B", + "V6.vandqrt.acc" => "__builtin_HEXAGON_V6_vandqrt_acc", + "V6.vandqrt.acc.128B" => "__builtin_HEXAGON_V6_vandqrt_acc_128B", + "V6.vandvnqv" => "__builtin_HEXAGON_V6_vandvnqv", + "V6.vandvnqv.128B" => "__builtin_HEXAGON_V6_vandvnqv_128B", + "V6.vandvqv" => "__builtin_HEXAGON_V6_vandvqv", + "V6.vandvqv.128B" => "__builtin_HEXAGON_V6_vandvqv_128B", + "V6.vandvrt" => "__builtin_HEXAGON_V6_vandvrt", + "V6.vandvrt.128B" => "__builtin_HEXAGON_V6_vandvrt_128B", + "V6.vandvrt.acc" => "__builtin_HEXAGON_V6_vandvrt_acc", + "V6.vandvrt.acc.128B" => "__builtin_HEXAGON_V6_vandvrt_acc_128B", + "V6.vaslh" => "__builtin_HEXAGON_V6_vaslh", + "V6.vaslh.128B" => "__builtin_HEXAGON_V6_vaslh_128B", + "V6.vaslh.acc" => "__builtin_HEXAGON_V6_vaslh_acc", + "V6.vaslh.acc.128B" => "__builtin_HEXAGON_V6_vaslh_acc_128B", + "V6.vaslhv" => "__builtin_HEXAGON_V6_vaslhv", + "V6.vaslhv.128B" => "__builtin_HEXAGON_V6_vaslhv_128B", + "V6.vaslw" => "__builtin_HEXAGON_V6_vaslw", + "V6.vaslw.128B" => "__builtin_HEXAGON_V6_vaslw_128B", + "V6.vaslw.acc" => "__builtin_HEXAGON_V6_vaslw_acc", + "V6.vaslw.acc.128B" => "__builtin_HEXAGON_V6_vaslw_acc_128B", + "V6.vaslwv" => "__builtin_HEXAGON_V6_vaslwv", + "V6.vaslwv.128B" => "__builtin_HEXAGON_V6_vaslwv_128B", + "V6.vasr.into" => "__builtin_HEXAGON_V6_vasr_into", + "V6.vasr.into.128B" => "__builtin_HEXAGON_V6_vasr_into_128B", + "V6.vasrh" => "__builtin_HEXAGON_V6_vasrh", + "V6.vasrh.128B" => "__builtin_HEXAGON_V6_vasrh_128B", + "V6.vasrh.acc" => "__builtin_HEXAGON_V6_vasrh_acc", + "V6.vasrh.acc.128B" => "__builtin_HEXAGON_V6_vasrh_acc_128B", + "V6.vasrhbrndsat" => "__builtin_HEXAGON_V6_vasrhbrndsat", + "V6.vasrhbrndsat.128B" => "__builtin_HEXAGON_V6_vasrhbrndsat_128B", + "V6.vasrhbsat" => "__builtin_HEXAGON_V6_vasrhbsat", + "V6.vasrhbsat.128B" => "__builtin_HEXAGON_V6_vasrhbsat_128B", + "V6.vasrhubrndsat" => "__builtin_HEXAGON_V6_vasrhubrndsat", + "V6.vasrhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrhubrndsat_128B", + "V6.vasrhubsat" => "__builtin_HEXAGON_V6_vasrhubsat", + "V6.vasrhubsat.128B" => "__builtin_HEXAGON_V6_vasrhubsat_128B", + "V6.vasrhv" => "__builtin_HEXAGON_V6_vasrhv", + "V6.vasrhv.128B" => "__builtin_HEXAGON_V6_vasrhv_128B", + "V6.vasruhubrndsat" => "__builtin_HEXAGON_V6_vasruhubrndsat", + "V6.vasruhubrndsat.128B" => "__builtin_HEXAGON_V6_vasruhubrndsat_128B", + "V6.vasruhubsat" => "__builtin_HEXAGON_V6_vasruhubsat", + "V6.vasruhubsat.128B" => "__builtin_HEXAGON_V6_vasruhubsat_128B", + "V6.vasruwuhrndsat" => "__builtin_HEXAGON_V6_vasruwuhrndsat", + "V6.vasruwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasruwuhrndsat_128B", + "V6.vasruwuhsat" => "__builtin_HEXAGON_V6_vasruwuhsat", + "V6.vasruwuhsat.128B" => "__builtin_HEXAGON_V6_vasruwuhsat_128B", + "V6.vasrvuhubrndsat" => "__builtin_HEXAGON_V6_vasrvuhubrndsat", + "V6.vasrvuhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrvuhubrndsat_128B", + "V6.vasrvuhubsat" => "__builtin_HEXAGON_V6_vasrvuhubsat", + "V6.vasrvuhubsat.128B" => "__builtin_HEXAGON_V6_vasrvuhubsat_128B", + "V6.vasrvwuhrndsat" => "__builtin_HEXAGON_V6_vasrvwuhrndsat", + "V6.vasrvwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasrvwuhrndsat_128B", + "V6.vasrvwuhsat" => "__builtin_HEXAGON_V6_vasrvwuhsat", + "V6.vasrvwuhsat.128B" => "__builtin_HEXAGON_V6_vasrvwuhsat_128B", + "V6.vasrw" => "__builtin_HEXAGON_V6_vasrw", + "V6.vasrw.128B" => "__builtin_HEXAGON_V6_vasrw_128B", + "V6.vasrw.acc" => "__builtin_HEXAGON_V6_vasrw_acc", + "V6.vasrw.acc.128B" => "__builtin_HEXAGON_V6_vasrw_acc_128B", + "V6.vasrwh" => "__builtin_HEXAGON_V6_vasrwh", + "V6.vasrwh.128B" => "__builtin_HEXAGON_V6_vasrwh_128B", + "V6.vasrwhrndsat" => "__builtin_HEXAGON_V6_vasrwhrndsat", + "V6.vasrwhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwhrndsat_128B", + "V6.vasrwhsat" => "__builtin_HEXAGON_V6_vasrwhsat", + "V6.vasrwhsat.128B" => "__builtin_HEXAGON_V6_vasrwhsat_128B", + "V6.vasrwuhrndsat" => "__builtin_HEXAGON_V6_vasrwuhrndsat", + "V6.vasrwuhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwuhrndsat_128B", + "V6.vasrwuhsat" => "__builtin_HEXAGON_V6_vasrwuhsat", + "V6.vasrwuhsat.128B" => "__builtin_HEXAGON_V6_vasrwuhsat_128B", + "V6.vasrwv" => "__builtin_HEXAGON_V6_vasrwv", + "V6.vasrwv.128B" => "__builtin_HEXAGON_V6_vasrwv_128B", + "V6.vassign" => "__builtin_HEXAGON_V6_vassign", + "V6.vassign.128B" => "__builtin_HEXAGON_V6_vassign_128B", + "V6.vassign.fp" => "__builtin_HEXAGON_V6_vassign_fp", + "V6.vassign.fp.128B" => "__builtin_HEXAGON_V6_vassign_fp_128B", + "V6.vassignp" => "__builtin_HEXAGON_V6_vassignp", + "V6.vassignp.128B" => "__builtin_HEXAGON_V6_vassignp_128B", + "V6.vavgb" => "__builtin_HEXAGON_V6_vavgb", + "V6.vavgb.128B" => "__builtin_HEXAGON_V6_vavgb_128B", + "V6.vavgbrnd" => "__builtin_HEXAGON_V6_vavgbrnd", + "V6.vavgbrnd.128B" => "__builtin_HEXAGON_V6_vavgbrnd_128B", + "V6.vavgh" => "__builtin_HEXAGON_V6_vavgh", + "V6.vavgh.128B" => "__builtin_HEXAGON_V6_vavgh_128B", + "V6.vavghrnd" => "__builtin_HEXAGON_V6_vavghrnd", + "V6.vavghrnd.128B" => "__builtin_HEXAGON_V6_vavghrnd_128B", + "V6.vavgub" => "__builtin_HEXAGON_V6_vavgub", + "V6.vavgub.128B" => "__builtin_HEXAGON_V6_vavgub_128B", + "V6.vavgubrnd" => "__builtin_HEXAGON_V6_vavgubrnd", + "V6.vavgubrnd.128B" => "__builtin_HEXAGON_V6_vavgubrnd_128B", + "V6.vavguh" => "__builtin_HEXAGON_V6_vavguh", + "V6.vavguh.128B" => "__builtin_HEXAGON_V6_vavguh_128B", + "V6.vavguhrnd" => "__builtin_HEXAGON_V6_vavguhrnd", + "V6.vavguhrnd.128B" => "__builtin_HEXAGON_V6_vavguhrnd_128B", + "V6.vavguw" => "__builtin_HEXAGON_V6_vavguw", + "V6.vavguw.128B" => "__builtin_HEXAGON_V6_vavguw_128B", + "V6.vavguwrnd" => "__builtin_HEXAGON_V6_vavguwrnd", + "V6.vavguwrnd.128B" => "__builtin_HEXAGON_V6_vavguwrnd_128B", + "V6.vavgw" => "__builtin_HEXAGON_V6_vavgw", + "V6.vavgw.128B" => "__builtin_HEXAGON_V6_vavgw_128B", + "V6.vavgwrnd" => "__builtin_HEXAGON_V6_vavgwrnd", + "V6.vavgwrnd.128B" => "__builtin_HEXAGON_V6_vavgwrnd_128B", + "V6.vcl0h" => "__builtin_HEXAGON_V6_vcl0h", + "V6.vcl0h.128B" => "__builtin_HEXAGON_V6_vcl0h_128B", + "V6.vcl0w" => "__builtin_HEXAGON_V6_vcl0w", + "V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B", + "V6.vcombine" => "__builtin_HEXAGON_V6_vcombine", + "V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B", + "V6.vconv.h.hf" => "__builtin_HEXAGON_V6_vconv_h_hf", + "V6.vconv.h.hf.128B" => "__builtin_HEXAGON_V6_vconv_h_hf_128B", + "V6.vconv.hf.h" => "__builtin_HEXAGON_V6_vconv_hf_h", + "V6.vconv.hf.h.128B" => "__builtin_HEXAGON_V6_vconv_hf_h_128B", + "V6.vconv.hf.qf16" => "__builtin_HEXAGON_V6_vconv_hf_qf16", + "V6.vconv.hf.qf16.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf16_128B", + "V6.vconv.hf.qf32" => "__builtin_HEXAGON_V6_vconv_hf_qf32", + "V6.vconv.hf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf32_128B", + "V6.vconv.sf.qf32" => "__builtin_HEXAGON_V6_vconv_sf_qf32", + "V6.vconv.sf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_sf_qf32_128B", + "V6.vconv.sf.w" => "__builtin_HEXAGON_V6_vconv_sf_w", + "V6.vconv.sf.w.128B" => "__builtin_HEXAGON_V6_vconv_sf_w_128B", + "V6.vconv.w.sf" => "__builtin_HEXAGON_V6_vconv_w_sf", + "V6.vconv.w.sf.128B" => "__builtin_HEXAGON_V6_vconv_w_sf_128B", + "V6.vcvt.b.hf" => "__builtin_HEXAGON_V6_vcvt_b_hf", + "V6.vcvt.b.hf.128B" => "__builtin_HEXAGON_V6_vcvt_b_hf_128B", + "V6.vcvt.bf.sf" => "__builtin_HEXAGON_V6_vcvt_bf_sf", + "V6.vcvt.bf.sf.128B" => "__builtin_HEXAGON_V6_vcvt_bf_sf_128B", + "V6.vcvt.f8.hf" => "__builtin_HEXAGON_V6_vcvt_f8_hf", + "V6.vcvt.f8.hf.128B" => "__builtin_HEXAGON_V6_vcvt_f8_hf_128B", + "V6.vcvt.h.hf" => "__builtin_HEXAGON_V6_vcvt_h_hf", + "V6.vcvt.h.hf.128B" => "__builtin_HEXAGON_V6_vcvt_h_hf_128B", + "V6.vcvt.hf.b" => "__builtin_HEXAGON_V6_vcvt_hf_b", + "V6.vcvt.hf.b.128B" => "__builtin_HEXAGON_V6_vcvt_hf_b_128B", + "V6.vcvt.hf.f8" => "__builtin_HEXAGON_V6_vcvt_hf_f8", + "V6.vcvt.hf.f8.128B" => "__builtin_HEXAGON_V6_vcvt_hf_f8_128B", + "V6.vcvt.hf.h" => "__builtin_HEXAGON_V6_vcvt_hf_h", + "V6.vcvt.hf.h.128B" => "__builtin_HEXAGON_V6_vcvt_hf_h_128B", + "V6.vcvt.hf.sf" => "__builtin_HEXAGON_V6_vcvt_hf_sf", + "V6.vcvt.hf.sf.128B" => "__builtin_HEXAGON_V6_vcvt_hf_sf_128B", + "V6.vcvt.hf.ub" => "__builtin_HEXAGON_V6_vcvt_hf_ub", + "V6.vcvt.hf.ub.128B" => "__builtin_HEXAGON_V6_vcvt_hf_ub_128B", + "V6.vcvt.hf.uh" => "__builtin_HEXAGON_V6_vcvt_hf_uh", + "V6.vcvt.hf.uh.128B" => "__builtin_HEXAGON_V6_vcvt_hf_uh_128B", + "V6.vcvt.sf.hf" => "__builtin_HEXAGON_V6_vcvt_sf_hf", + "V6.vcvt.sf.hf.128B" => "__builtin_HEXAGON_V6_vcvt_sf_hf_128B", + "V6.vcvt.ub.hf" => "__builtin_HEXAGON_V6_vcvt_ub_hf", + "V6.vcvt.ub.hf.128B" => "__builtin_HEXAGON_V6_vcvt_ub_hf_128B", + "V6.vcvt.uh.hf" => "__builtin_HEXAGON_V6_vcvt_uh_hf", + "V6.vcvt.uh.hf.128B" => "__builtin_HEXAGON_V6_vcvt_uh_hf_128B", + "V6.vcvt2.b.hf" => "__builtin_HEXAGON_V6_vcvt2_b_hf", + "V6.vcvt2.b.hf.128B" => "__builtin_HEXAGON_V6_vcvt2_b_hf_128B", + "V6.vcvt2.hf.b" => "__builtin_HEXAGON_V6_vcvt2_hf_b", + "V6.vcvt2.hf.b.128B" => "__builtin_HEXAGON_V6_vcvt2_hf_b_128B", + "V6.vcvt2.hf.ub" => "__builtin_HEXAGON_V6_vcvt2_hf_ub", + "V6.vcvt2.hf.ub.128B" => "__builtin_HEXAGON_V6_vcvt2_hf_ub_128B", + "V6.vcvt2.ub.hf" => "__builtin_HEXAGON_V6_vcvt2_ub_hf", + "V6.vcvt2.ub.hf.128B" => "__builtin_HEXAGON_V6_vcvt2_ub_hf_128B", + "V6.vd0" => "__builtin_HEXAGON_V6_vd0", + "V6.vd0.128B" => "__builtin_HEXAGON_V6_vd0_128B", + "V6.vdd0" => "__builtin_HEXAGON_V6_vdd0", + "V6.vdd0.128B" => "__builtin_HEXAGON_V6_vdd0_128B", + "V6.vdealb" => "__builtin_HEXAGON_V6_vdealb", + "V6.vdealb.128B" => "__builtin_HEXAGON_V6_vdealb_128B", + "V6.vdealb4w" => "__builtin_HEXAGON_V6_vdealb4w", + "V6.vdealb4w.128B" => "__builtin_HEXAGON_V6_vdealb4w_128B", + "V6.vdealh" => "__builtin_HEXAGON_V6_vdealh", + "V6.vdealh.128B" => "__builtin_HEXAGON_V6_vdealh_128B", + "V6.vdealvdd" => "__builtin_HEXAGON_V6_vdealvdd", + "V6.vdealvdd.128B" => "__builtin_HEXAGON_V6_vdealvdd_128B", + "V6.vdelta" => "__builtin_HEXAGON_V6_vdelta", + "V6.vdelta.128B" => "__builtin_HEXAGON_V6_vdelta_128B", + "V6.vdmpy.sf.hf" => "__builtin_HEXAGON_V6_vdmpy_sf_hf", + "V6.vdmpy.sf.hf.128B" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_128B", + "V6.vdmpy.sf.hf.acc" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_acc", + "V6.vdmpy.sf.hf.acc.128B" => "__builtin_HEXAGON_V6_vdmpy_sf_hf_acc_128B", + "V6.vdmpybus" => "__builtin_HEXAGON_V6_vdmpybus", + "V6.vdmpybus.128B" => "__builtin_HEXAGON_V6_vdmpybus_128B", + "V6.vdmpybus.acc" => "__builtin_HEXAGON_V6_vdmpybus_acc", + "V6.vdmpybus.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_acc_128B", + "V6.vdmpybus.dv" => "__builtin_HEXAGON_V6_vdmpybus_dv", + "V6.vdmpybus.dv.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_128B", + "V6.vdmpybus.dv.acc" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc", + "V6.vdmpybus.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc_128B", + "V6.vdmpyhb" => "__builtin_HEXAGON_V6_vdmpyhb", + "V6.vdmpyhb.128B" => "__builtin_HEXAGON_V6_vdmpyhb_128B", + "V6.vdmpyhb.acc" => "__builtin_HEXAGON_V6_vdmpyhb_acc", + "V6.vdmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_acc_128B", + "V6.vdmpyhb.dv" => "__builtin_HEXAGON_V6_vdmpyhb_dv", + "V6.vdmpyhb.dv.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_128B", + "V6.vdmpyhb.dv.acc" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc", + "V6.vdmpyhb.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc_128B", + "V6.vdmpyhisat" => "__builtin_HEXAGON_V6_vdmpyhisat", + "V6.vdmpyhisat.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_128B", + "V6.vdmpyhisat.acc" => "__builtin_HEXAGON_V6_vdmpyhisat_acc", + "V6.vdmpyhisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_acc_128B", + "V6.vdmpyhsat" => "__builtin_HEXAGON_V6_vdmpyhsat", + "V6.vdmpyhsat.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_128B", + "V6.vdmpyhsat.acc" => "__builtin_HEXAGON_V6_vdmpyhsat_acc", + "V6.vdmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_acc_128B", + "V6.vdmpyhsuisat" => "__builtin_HEXAGON_V6_vdmpyhsuisat", + "V6.vdmpyhsuisat.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_128B", + "V6.vdmpyhsuisat.acc" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc", + "V6.vdmpyhsuisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc_128B", + "V6.vdmpyhsusat" => "__builtin_HEXAGON_V6_vdmpyhsusat", + "V6.vdmpyhsusat.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_128B", + "V6.vdmpyhsusat.acc" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc", + "V6.vdmpyhsusat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc_128B", + "V6.vdmpyhvsat" => "__builtin_HEXAGON_V6_vdmpyhvsat", + "V6.vdmpyhvsat.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_128B", + "V6.vdmpyhvsat.acc" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc", + "V6.vdmpyhvsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc_128B", + "V6.vdsaduh" => "__builtin_HEXAGON_V6_vdsaduh", + "V6.vdsaduh.128B" => "__builtin_HEXAGON_V6_vdsaduh_128B", + "V6.vdsaduh.acc" => "__builtin_HEXAGON_V6_vdsaduh_acc", + "V6.vdsaduh.acc.128B" => "__builtin_HEXAGON_V6_vdsaduh_acc_128B", + "V6.veqb" => "__builtin_HEXAGON_V6_veqb", + "V6.veqb.128B" => "__builtin_HEXAGON_V6_veqb_128B", + "V6.veqb.and" => "__builtin_HEXAGON_V6_veqb_and", + "V6.veqb.and.128B" => "__builtin_HEXAGON_V6_veqb_and_128B", + "V6.veqb.or" => "__builtin_HEXAGON_V6_veqb_or", + "V6.veqb.or.128B" => "__builtin_HEXAGON_V6_veqb_or_128B", + "V6.veqb.xor" => "__builtin_HEXAGON_V6_veqb_xor", + "V6.veqb.xor.128B" => "__builtin_HEXAGON_V6_veqb_xor_128B", + "V6.veqh" => "__builtin_HEXAGON_V6_veqh", + "V6.veqh.128B" => "__builtin_HEXAGON_V6_veqh_128B", + "V6.veqh.and" => "__builtin_HEXAGON_V6_veqh_and", + "V6.veqh.and.128B" => "__builtin_HEXAGON_V6_veqh_and_128B", + "V6.veqh.or" => "__builtin_HEXAGON_V6_veqh_or", + "V6.veqh.or.128B" => "__builtin_HEXAGON_V6_veqh_or_128B", + "V6.veqh.xor" => "__builtin_HEXAGON_V6_veqh_xor", + "V6.veqh.xor.128B" => "__builtin_HEXAGON_V6_veqh_xor_128B", + "V6.veqw" => "__builtin_HEXAGON_V6_veqw", + "V6.veqw.128B" => "__builtin_HEXAGON_V6_veqw_128B", + "V6.veqw.and" => "__builtin_HEXAGON_V6_veqw_and", + "V6.veqw.and.128B" => "__builtin_HEXAGON_V6_veqw_and_128B", + "V6.veqw.or" => "__builtin_HEXAGON_V6_veqw_or", + "V6.veqw.or.128B" => "__builtin_HEXAGON_V6_veqw_or_128B", + "V6.veqw.xor" => "__builtin_HEXAGON_V6_veqw_xor", + "V6.veqw.xor.128B" => "__builtin_HEXAGON_V6_veqw_xor_128B", + "V6.vfmax.f8" => "__builtin_HEXAGON_V6_vfmax_f8", + "V6.vfmax.f8.128B" => "__builtin_HEXAGON_V6_vfmax_f8_128B", + "V6.vfmax.hf" => "__builtin_HEXAGON_V6_vfmax_hf", + "V6.vfmax.hf.128B" => "__builtin_HEXAGON_V6_vfmax_hf_128B", + "V6.vfmax.sf" => "__builtin_HEXAGON_V6_vfmax_sf", + "V6.vfmax.sf.128B" => "__builtin_HEXAGON_V6_vfmax_sf_128B", + "V6.vfmin.f8" => "__builtin_HEXAGON_V6_vfmin_f8", + "V6.vfmin.f8.128B" => "__builtin_HEXAGON_V6_vfmin_f8_128B", + "V6.vfmin.hf" => "__builtin_HEXAGON_V6_vfmin_hf", + "V6.vfmin.hf.128B" => "__builtin_HEXAGON_V6_vfmin_hf_128B", + "V6.vfmin.sf" => "__builtin_HEXAGON_V6_vfmin_sf", + "V6.vfmin.sf.128B" => "__builtin_HEXAGON_V6_vfmin_sf_128B", + "V6.vfneg.f8" => "__builtin_HEXAGON_V6_vfneg_f8", + "V6.vfneg.f8.128B" => "__builtin_HEXAGON_V6_vfneg_f8_128B", + "V6.vfneg.hf" => "__builtin_HEXAGON_V6_vfneg_hf", + "V6.vfneg.hf.128B" => "__builtin_HEXAGON_V6_vfneg_hf_128B", + "V6.vfneg.sf" => "__builtin_HEXAGON_V6_vfneg_sf", + "V6.vfneg.sf.128B" => "__builtin_HEXAGON_V6_vfneg_sf_128B", + "V6.vgathermh" => "__builtin_HEXAGON_V6_vgathermh", + "V6.vgathermh.128B" => "__builtin_HEXAGON_V6_vgathermh_128B", + "V6.vgathermhq" => "__builtin_HEXAGON_V6_vgathermhq", + "V6.vgathermhq.128B" => "__builtin_HEXAGON_V6_vgathermhq_128B", + "V6.vgathermhw" => "__builtin_HEXAGON_V6_vgathermhw", + "V6.vgathermhw.128B" => "__builtin_HEXAGON_V6_vgathermhw_128B", + "V6.vgathermhwq" => "__builtin_HEXAGON_V6_vgathermhwq", + "V6.vgathermhwq.128B" => "__builtin_HEXAGON_V6_vgathermhwq_128B", + "V6.vgathermw" => "__builtin_HEXAGON_V6_vgathermw", + "V6.vgathermw.128B" => "__builtin_HEXAGON_V6_vgathermw_128B", + "V6.vgathermwq" => "__builtin_HEXAGON_V6_vgathermwq", + "V6.vgathermwq.128B" => "__builtin_HEXAGON_V6_vgathermwq_128B", + "V6.vgtb" => "__builtin_HEXAGON_V6_vgtb", + "V6.vgtb.128B" => "__builtin_HEXAGON_V6_vgtb_128B", + "V6.vgtb.and" => "__builtin_HEXAGON_V6_vgtb_and", + "V6.vgtb.and.128B" => "__builtin_HEXAGON_V6_vgtb_and_128B", + "V6.vgtb.or" => "__builtin_HEXAGON_V6_vgtb_or", + "V6.vgtb.or.128B" => "__builtin_HEXAGON_V6_vgtb_or_128B", + "V6.vgtb.xor" => "__builtin_HEXAGON_V6_vgtb_xor", + "V6.vgtb.xor.128B" => "__builtin_HEXAGON_V6_vgtb_xor_128B", + "V6.vgtbf" => "__builtin_HEXAGON_V6_vgtbf", + "V6.vgtbf.128B" => "__builtin_HEXAGON_V6_vgtbf_128B", + "V6.vgtbf.and" => "__builtin_HEXAGON_V6_vgtbf_and", + "V6.vgtbf.and.128B" => "__builtin_HEXAGON_V6_vgtbf_and_128B", + "V6.vgtbf.or" => "__builtin_HEXAGON_V6_vgtbf_or", + "V6.vgtbf.or.128B" => "__builtin_HEXAGON_V6_vgtbf_or_128B", + "V6.vgtbf.xor" => "__builtin_HEXAGON_V6_vgtbf_xor", + "V6.vgtbf.xor.128B" => "__builtin_HEXAGON_V6_vgtbf_xor_128B", + "V6.vgth" => "__builtin_HEXAGON_V6_vgth", + "V6.vgth.128B" => "__builtin_HEXAGON_V6_vgth_128B", + "V6.vgth.and" => "__builtin_HEXAGON_V6_vgth_and", + "V6.vgth.and.128B" => "__builtin_HEXAGON_V6_vgth_and_128B", + "V6.vgth.or" => "__builtin_HEXAGON_V6_vgth_or", + "V6.vgth.or.128B" => "__builtin_HEXAGON_V6_vgth_or_128B", + "V6.vgth.xor" => "__builtin_HEXAGON_V6_vgth_xor", + "V6.vgth.xor.128B" => "__builtin_HEXAGON_V6_vgth_xor_128B", + "V6.vgthf" => "__builtin_HEXAGON_V6_vgthf", + "V6.vgthf.128B" => "__builtin_HEXAGON_V6_vgthf_128B", + "V6.vgthf.and" => "__builtin_HEXAGON_V6_vgthf_and", + "V6.vgthf.and.128B" => "__builtin_HEXAGON_V6_vgthf_and_128B", + "V6.vgthf.or" => "__builtin_HEXAGON_V6_vgthf_or", + "V6.vgthf.or.128B" => "__builtin_HEXAGON_V6_vgthf_or_128B", + "V6.vgthf.xor" => "__builtin_HEXAGON_V6_vgthf_xor", + "V6.vgthf.xor.128B" => "__builtin_HEXAGON_V6_vgthf_xor_128B", + "V6.vgtsf" => "__builtin_HEXAGON_V6_vgtsf", + "V6.vgtsf.128B" => "__builtin_HEXAGON_V6_vgtsf_128B", + "V6.vgtsf.and" => "__builtin_HEXAGON_V6_vgtsf_and", + "V6.vgtsf.and.128B" => "__builtin_HEXAGON_V6_vgtsf_and_128B", + "V6.vgtsf.or" => "__builtin_HEXAGON_V6_vgtsf_or", + "V6.vgtsf.or.128B" => "__builtin_HEXAGON_V6_vgtsf_or_128B", + "V6.vgtsf.xor" => "__builtin_HEXAGON_V6_vgtsf_xor", + "V6.vgtsf.xor.128B" => "__builtin_HEXAGON_V6_vgtsf_xor_128B", + "V6.vgtub" => "__builtin_HEXAGON_V6_vgtub", + "V6.vgtub.128B" => "__builtin_HEXAGON_V6_vgtub_128B", + "V6.vgtub.and" => "__builtin_HEXAGON_V6_vgtub_and", + "V6.vgtub.and.128B" => "__builtin_HEXAGON_V6_vgtub_and_128B", + "V6.vgtub.or" => "__builtin_HEXAGON_V6_vgtub_or", + "V6.vgtub.or.128B" => "__builtin_HEXAGON_V6_vgtub_or_128B", + "V6.vgtub.xor" => "__builtin_HEXAGON_V6_vgtub_xor", + "V6.vgtub.xor.128B" => "__builtin_HEXAGON_V6_vgtub_xor_128B", + "V6.vgtuh" => "__builtin_HEXAGON_V6_vgtuh", + "V6.vgtuh.128B" => "__builtin_HEXAGON_V6_vgtuh_128B", + "V6.vgtuh.and" => "__builtin_HEXAGON_V6_vgtuh_and", + "V6.vgtuh.and.128B" => "__builtin_HEXAGON_V6_vgtuh_and_128B", + "V6.vgtuh.or" => "__builtin_HEXAGON_V6_vgtuh_or", + "V6.vgtuh.or.128B" => "__builtin_HEXAGON_V6_vgtuh_or_128B", + "V6.vgtuh.xor" => "__builtin_HEXAGON_V6_vgtuh_xor", + "V6.vgtuh.xor.128B" => "__builtin_HEXAGON_V6_vgtuh_xor_128B", + "V6.vgtuw" => "__builtin_HEXAGON_V6_vgtuw", + "V6.vgtuw.128B" => "__builtin_HEXAGON_V6_vgtuw_128B", + "V6.vgtuw.and" => "__builtin_HEXAGON_V6_vgtuw_and", + "V6.vgtuw.and.128B" => "__builtin_HEXAGON_V6_vgtuw_and_128B", + "V6.vgtuw.or" => "__builtin_HEXAGON_V6_vgtuw_or", + "V6.vgtuw.or.128B" => "__builtin_HEXAGON_V6_vgtuw_or_128B", + "V6.vgtuw.xor" => "__builtin_HEXAGON_V6_vgtuw_xor", + "V6.vgtuw.xor.128B" => "__builtin_HEXAGON_V6_vgtuw_xor_128B", + "V6.vgtw" => "__builtin_HEXAGON_V6_vgtw", + "V6.vgtw.128B" => "__builtin_HEXAGON_V6_vgtw_128B", + "V6.vgtw.and" => "__builtin_HEXAGON_V6_vgtw_and", + "V6.vgtw.and.128B" => "__builtin_HEXAGON_V6_vgtw_and_128B", + "V6.vgtw.or" => "__builtin_HEXAGON_V6_vgtw_or", + "V6.vgtw.or.128B" => "__builtin_HEXAGON_V6_vgtw_or_128B", + "V6.vgtw.xor" => "__builtin_HEXAGON_V6_vgtw_xor", + "V6.vgtw.xor.128B" => "__builtin_HEXAGON_V6_vgtw_xor_128B", + "V6.vinsertwr" => "__builtin_HEXAGON_V6_vinsertwr", + "V6.vinsertwr.128B" => "__builtin_HEXAGON_V6_vinsertwr_128B", + "V6.vlalignb" => "__builtin_HEXAGON_V6_vlalignb", + "V6.vlalignb.128B" => "__builtin_HEXAGON_V6_vlalignb_128B", + "V6.vlalignbi" => "__builtin_HEXAGON_V6_vlalignbi", + "V6.vlalignbi.128B" => "__builtin_HEXAGON_V6_vlalignbi_128B", + "V6.vlsrb" => "__builtin_HEXAGON_V6_vlsrb", + "V6.vlsrb.128B" => "__builtin_HEXAGON_V6_vlsrb_128B", + "V6.vlsrh" => "__builtin_HEXAGON_V6_vlsrh", + "V6.vlsrh.128B" => "__builtin_HEXAGON_V6_vlsrh_128B", + "V6.vlsrhv" => "__builtin_HEXAGON_V6_vlsrhv", + "V6.vlsrhv.128B" => "__builtin_HEXAGON_V6_vlsrhv_128B", + "V6.vlsrw" => "__builtin_HEXAGON_V6_vlsrw", + "V6.vlsrw.128B" => "__builtin_HEXAGON_V6_vlsrw_128B", + "V6.vlsrwv" => "__builtin_HEXAGON_V6_vlsrwv", + "V6.vlsrwv.128B" => "__builtin_HEXAGON_V6_vlsrwv_128B", + "V6.vlut4" => "__builtin_HEXAGON_V6_vlut4", + "V6.vlut4.128B" => "__builtin_HEXAGON_V6_vlut4_128B", + "V6.vlutb" => "__builtin_HEXAGON_V6_vlutb", + "V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B", + "V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc", + "V6.vlutb.acc.128B" => "__builtin_HEXAGON_V6_vlutb_acc_128B", + "V6.vlutb.dv" => "__builtin_HEXAGON_V6_vlutb_dv", + "V6.vlutb.dv.128B" => "__builtin_HEXAGON_V6_vlutb_dv_128B", + "V6.vlutb.dv.acc" => "__builtin_HEXAGON_V6_vlutb_dv_acc", + "V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B", + "V6.vlutvvb" => "__builtin_HEXAGON_V6_vlutvvb", + "V6.vlutvvb.128B" => "__builtin_HEXAGON_V6_vlutvvb_128B", + "V6.vlutvvb.nm" => "__builtin_HEXAGON_V6_vlutvvb_nm", + "V6.vlutvvb.nm.128B" => "__builtin_HEXAGON_V6_vlutvvb_nm_128B", + "V6.vlutvvb.oracc" => "__builtin_HEXAGON_V6_vlutvvb_oracc", + "V6.vlutvvb.oracc.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracc_128B", + "V6.vlutvvb.oracci" => "__builtin_HEXAGON_V6_vlutvvb_oracci", + "V6.vlutvvb.oracci.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracci_128B", + "V6.vlutvvbi" => "__builtin_HEXAGON_V6_vlutvvbi", + "V6.vlutvvbi.128B" => "__builtin_HEXAGON_V6_vlutvvbi_128B", + "V6.vlutvwh" => "__builtin_HEXAGON_V6_vlutvwh", + "V6.vlutvwh.128B" => "__builtin_HEXAGON_V6_vlutvwh_128B", + "V6.vlutvwh.nm" => "__builtin_HEXAGON_V6_vlutvwh_nm", + "V6.vlutvwh.nm.128B" => "__builtin_HEXAGON_V6_vlutvwh_nm_128B", + "V6.vlutvwh.oracc" => "__builtin_HEXAGON_V6_vlutvwh_oracc", + "V6.vlutvwh.oracc.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracc_128B", + "V6.vlutvwh.oracci" => "__builtin_HEXAGON_V6_vlutvwh_oracci", + "V6.vlutvwh.oracci.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracci_128B", + "V6.vlutvwhi" => "__builtin_HEXAGON_V6_vlutvwhi", + "V6.vlutvwhi.128B" => "__builtin_HEXAGON_V6_vlutvwhi_128B", + "V6.vmax.bf" => "__builtin_HEXAGON_V6_vmax_bf", + "V6.vmax.bf.128B" => "__builtin_HEXAGON_V6_vmax_bf_128B", + "V6.vmax.hf" => "__builtin_HEXAGON_V6_vmax_hf", + "V6.vmax.hf.128B" => "__builtin_HEXAGON_V6_vmax_hf_128B", + "V6.vmax.sf" => "__builtin_HEXAGON_V6_vmax_sf", + "V6.vmax.sf.128B" => "__builtin_HEXAGON_V6_vmax_sf_128B", + "V6.vmaxb" => "__builtin_HEXAGON_V6_vmaxb", + "V6.vmaxb.128B" => "__builtin_HEXAGON_V6_vmaxb_128B", + "V6.vmaxh" => "__builtin_HEXAGON_V6_vmaxh", + "V6.vmaxh.128B" => "__builtin_HEXAGON_V6_vmaxh_128B", + "V6.vmaxub" => "__builtin_HEXAGON_V6_vmaxub", + "V6.vmaxub.128B" => "__builtin_HEXAGON_V6_vmaxub_128B", + "V6.vmaxuh" => "__builtin_HEXAGON_V6_vmaxuh", + "V6.vmaxuh.128B" => "__builtin_HEXAGON_V6_vmaxuh_128B", + "V6.vmaxw" => "__builtin_HEXAGON_V6_vmaxw", + "V6.vmaxw.128B" => "__builtin_HEXAGON_V6_vmaxw_128B", + "V6.vmerge.qf" => "__builtin_HEXAGON_V6_vmerge_qf", + "V6.vmerge.qf.128B" => "__builtin_HEXAGON_V6_vmerge_qf_128B", + "V6.vmin.bf" => "__builtin_HEXAGON_V6_vmin_bf", + "V6.vmin.bf.128B" => "__builtin_HEXAGON_V6_vmin_bf_128B", + "V6.vmin.hf" => "__builtin_HEXAGON_V6_vmin_hf", + "V6.vmin.hf.128B" => "__builtin_HEXAGON_V6_vmin_hf_128B", + "V6.vmin.sf" => "__builtin_HEXAGON_V6_vmin_sf", + "V6.vmin.sf.128B" => "__builtin_HEXAGON_V6_vmin_sf_128B", + "V6.vminb" => "__builtin_HEXAGON_V6_vminb", + "V6.vminb.128B" => "__builtin_HEXAGON_V6_vminb_128B", + "V6.vminh" => "__builtin_HEXAGON_V6_vminh", + "V6.vminh.128B" => "__builtin_HEXAGON_V6_vminh_128B", + "V6.vminub" => "__builtin_HEXAGON_V6_vminub", + "V6.vminub.128B" => "__builtin_HEXAGON_V6_vminub_128B", + "V6.vminuh" => "__builtin_HEXAGON_V6_vminuh", + "V6.vminuh.128B" => "__builtin_HEXAGON_V6_vminuh_128B", + "V6.vminw" => "__builtin_HEXAGON_V6_vminw", + "V6.vminw.128B" => "__builtin_HEXAGON_V6_vminw_128B", + "V6.vmpabus" => "__builtin_HEXAGON_V6_vmpabus", + "V6.vmpabus.128B" => "__builtin_HEXAGON_V6_vmpabus_128B", + "V6.vmpabus.acc" => "__builtin_HEXAGON_V6_vmpabus_acc", + "V6.vmpabus.acc.128B" => "__builtin_HEXAGON_V6_vmpabus_acc_128B", + "V6.vmpabusv" => "__builtin_HEXAGON_V6_vmpabusv", + "V6.vmpabusv.128B" => "__builtin_HEXAGON_V6_vmpabusv_128B", + "V6.vmpabuu" => "__builtin_HEXAGON_V6_vmpabuu", + "V6.vmpabuu.128B" => "__builtin_HEXAGON_V6_vmpabuu_128B", + "V6.vmpabuu.acc" => "__builtin_HEXAGON_V6_vmpabuu_acc", + "V6.vmpabuu.acc.128B" => "__builtin_HEXAGON_V6_vmpabuu_acc_128B", + "V6.vmpabuuv" => "__builtin_HEXAGON_V6_vmpabuuv", + "V6.vmpabuuv.128B" => "__builtin_HEXAGON_V6_vmpabuuv_128B", + "V6.vmpahb" => "__builtin_HEXAGON_V6_vmpahb", + "V6.vmpahb.128B" => "__builtin_HEXAGON_V6_vmpahb_128B", + "V6.vmpahb.acc" => "__builtin_HEXAGON_V6_vmpahb_acc", + "V6.vmpahb.acc.128B" => "__builtin_HEXAGON_V6_vmpahb_acc_128B", + "V6.vmpahhsat" => "__builtin_HEXAGON_V6_vmpahhsat", + "V6.vmpahhsat.128B" => "__builtin_HEXAGON_V6_vmpahhsat_128B", + "V6.vmpauhb" => "__builtin_HEXAGON_V6_vmpauhb", + "V6.vmpauhb.128B" => "__builtin_HEXAGON_V6_vmpauhb_128B", + "V6.vmpauhb.acc" => "__builtin_HEXAGON_V6_vmpauhb_acc", + "V6.vmpauhb.acc.128B" => "__builtin_HEXAGON_V6_vmpauhb_acc_128B", + "V6.vmpauhuhsat" => "__builtin_HEXAGON_V6_vmpauhuhsat", + "V6.vmpauhuhsat.128B" => "__builtin_HEXAGON_V6_vmpauhuhsat_128B", + "V6.vmpsuhuhsat" => "__builtin_HEXAGON_V6_vmpsuhuhsat", + "V6.vmpsuhuhsat.128B" => "__builtin_HEXAGON_V6_vmpsuhuhsat_128B", + "V6.vmpy.hf.f8" => "__builtin_HEXAGON_V6_vmpy_hf_f8", + "V6.vmpy.hf.f8.128B" => "__builtin_HEXAGON_V6_vmpy_hf_f8_128B", + "V6.vmpy.hf.f8.acc" => "__builtin_HEXAGON_V6_vmpy_hf_f8_acc", + "V6.vmpy.hf.f8.acc.128B" => "__builtin_HEXAGON_V6_vmpy_hf_f8_acc_128B", + "V6.vmpy.hf.hf" => "__builtin_HEXAGON_V6_vmpy_hf_hf", + "V6.vmpy.hf.hf.128B" => "__builtin_HEXAGON_V6_vmpy_hf_hf_128B", + "V6.vmpy.hf.hf.acc" => "__builtin_HEXAGON_V6_vmpy_hf_hf_acc", + "V6.vmpy.hf.hf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_hf_hf_acc_128B", + "V6.vmpy.qf16" => "__builtin_HEXAGON_V6_vmpy_qf16", + "V6.vmpy.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_128B", + "V6.vmpy.qf16.hf" => "__builtin_HEXAGON_V6_vmpy_qf16_hf", + "V6.vmpy.qf16.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_hf_128B", + "V6.vmpy.qf16.mix.hf" => "__builtin_HEXAGON_V6_vmpy_qf16_mix_hf", + "V6.vmpy.qf16.mix.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf16_mix_hf_128B", + "V6.vmpy.qf32" => "__builtin_HEXAGON_V6_vmpy_qf32", + "V6.vmpy.qf32.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_128B", + "V6.vmpy.qf32.hf" => "__builtin_HEXAGON_V6_vmpy_qf32_hf", + "V6.vmpy.qf32.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_hf_128B", + "V6.vmpy.qf32.mix.hf" => "__builtin_HEXAGON_V6_vmpy_qf32_mix_hf", + "V6.vmpy.qf32.mix.hf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_mix_hf_128B", + "V6.vmpy.qf32.qf16" => "__builtin_HEXAGON_V6_vmpy_qf32_qf16", + "V6.vmpy.qf32.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_qf16_128B", + "V6.vmpy.qf32.sf" => "__builtin_HEXAGON_V6_vmpy_qf32_sf", + "V6.vmpy.qf32.sf.128B" => "__builtin_HEXAGON_V6_vmpy_qf32_sf_128B", + "V6.vmpy.rt.hf" => "__builtin_HEXAGON_V6_vmpy_rt_hf", + "V6.vmpy.rt.hf.128B" => "__builtin_HEXAGON_V6_vmpy_rt_hf_128B", + "V6.vmpy.rt.qf16" => "__builtin_HEXAGON_V6_vmpy_rt_qf16", + "V6.vmpy.rt.qf16.128B" => "__builtin_HEXAGON_V6_vmpy_rt_qf16_128B", + "V6.vmpy.rt.sf" => "__builtin_HEXAGON_V6_vmpy_rt_sf", + "V6.vmpy.rt.sf.128B" => "__builtin_HEXAGON_V6_vmpy_rt_sf_128B", + "V6.vmpy.sf.bf" => "__builtin_HEXAGON_V6_vmpy_sf_bf", + "V6.vmpy.sf.bf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_bf_128B", + "V6.vmpy.sf.bf.acc" => "__builtin_HEXAGON_V6_vmpy_sf_bf_acc", + "V6.vmpy.sf.bf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_sf_bf_acc_128B", + "V6.vmpy.sf.hf" => "__builtin_HEXAGON_V6_vmpy_sf_hf", + "V6.vmpy.sf.hf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_hf_128B", + "V6.vmpy.sf.hf.acc" => "__builtin_HEXAGON_V6_vmpy_sf_hf_acc", + "V6.vmpy.sf.hf.acc.128B" => "__builtin_HEXAGON_V6_vmpy_sf_hf_acc_128B", + "V6.vmpy.sf.sf" => "__builtin_HEXAGON_V6_vmpy_sf_sf", + "V6.vmpy.sf.sf.128B" => "__builtin_HEXAGON_V6_vmpy_sf_sf_128B", + "V6.vmpybus" => "__builtin_HEXAGON_V6_vmpybus", + "V6.vmpybus.128B" => "__builtin_HEXAGON_V6_vmpybus_128B", + "V6.vmpybus.acc" => "__builtin_HEXAGON_V6_vmpybus_acc", + "V6.vmpybus.acc.128B" => "__builtin_HEXAGON_V6_vmpybus_acc_128B", + "V6.vmpybusv" => "__builtin_HEXAGON_V6_vmpybusv", + "V6.vmpybusv.128B" => "__builtin_HEXAGON_V6_vmpybusv_128B", + "V6.vmpybusv.acc" => "__builtin_HEXAGON_V6_vmpybusv_acc", + "V6.vmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vmpybusv_acc_128B", + "V6.vmpybv" => "__builtin_HEXAGON_V6_vmpybv", + "V6.vmpybv.128B" => "__builtin_HEXAGON_V6_vmpybv_128B", + "V6.vmpybv.acc" => "__builtin_HEXAGON_V6_vmpybv_acc", + "V6.vmpybv.acc.128B" => "__builtin_HEXAGON_V6_vmpybv_acc_128B", + "V6.vmpyewuh" => "__builtin_HEXAGON_V6_vmpyewuh", + "V6.vmpyewuh.128B" => "__builtin_HEXAGON_V6_vmpyewuh_128B", + "V6.vmpyewuh.64" => "__builtin_HEXAGON_V6_vmpyewuh_64", + "V6.vmpyewuh.64.128B" => "__builtin_HEXAGON_V6_vmpyewuh_64_128B", + "V6.vmpyh" => "__builtin_HEXAGON_V6_vmpyh", + "V6.vmpyh.128B" => "__builtin_HEXAGON_V6_vmpyh_128B", + "V6.vmpyh.acc" => "__builtin_HEXAGON_V6_vmpyh_acc", + "V6.vmpyh.acc.128B" => "__builtin_HEXAGON_V6_vmpyh_acc_128B", + "V6.vmpyhsat.acc" => "__builtin_HEXAGON_V6_vmpyhsat_acc", + "V6.vmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vmpyhsat_acc_128B", + "V6.vmpyhsrs" => "__builtin_HEXAGON_V6_vmpyhsrs", + "V6.vmpyhsrs.128B" => "__builtin_HEXAGON_V6_vmpyhsrs_128B", + "V6.vmpyhss" => "__builtin_HEXAGON_V6_vmpyhss", + "V6.vmpyhss.128B" => "__builtin_HEXAGON_V6_vmpyhss_128B", + "V6.vmpyhus" => "__builtin_HEXAGON_V6_vmpyhus", + "V6.vmpyhus.128B" => "__builtin_HEXAGON_V6_vmpyhus_128B", + "V6.vmpyhus.acc" => "__builtin_HEXAGON_V6_vmpyhus_acc", + "V6.vmpyhus.acc.128B" => "__builtin_HEXAGON_V6_vmpyhus_acc_128B", + "V6.vmpyhv" => "__builtin_HEXAGON_V6_vmpyhv", + "V6.vmpyhv.128B" => "__builtin_HEXAGON_V6_vmpyhv_128B", + "V6.vmpyhv.acc" => "__builtin_HEXAGON_V6_vmpyhv_acc", + "V6.vmpyhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyhv_acc_128B", + "V6.vmpyhvsrs" => "__builtin_HEXAGON_V6_vmpyhvsrs", + "V6.vmpyhvsrs.128B" => "__builtin_HEXAGON_V6_vmpyhvsrs_128B", + "V6.vmpyieoh" => "__builtin_HEXAGON_V6_vmpyieoh", + "V6.vmpyieoh.128B" => "__builtin_HEXAGON_V6_vmpyieoh_128B", + "V6.vmpyiewh.acc" => "__builtin_HEXAGON_V6_vmpyiewh_acc", + "V6.vmpyiewh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewh_acc_128B", + "V6.vmpyiewuh" => "__builtin_HEXAGON_V6_vmpyiewuh", + "V6.vmpyiewuh.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_128B", + "V6.vmpyiewuh.acc" => "__builtin_HEXAGON_V6_vmpyiewuh_acc", + "V6.vmpyiewuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_acc_128B", + "V6.vmpyih" => "__builtin_HEXAGON_V6_vmpyih", + "V6.vmpyih.128B" => "__builtin_HEXAGON_V6_vmpyih_128B", + "V6.vmpyih.acc" => "__builtin_HEXAGON_V6_vmpyih_acc", + "V6.vmpyih.acc.128B" => "__builtin_HEXAGON_V6_vmpyih_acc_128B", + "V6.vmpyihb" => "__builtin_HEXAGON_V6_vmpyihb", + "V6.vmpyihb.128B" => "__builtin_HEXAGON_V6_vmpyihb_128B", + "V6.vmpyihb.acc" => "__builtin_HEXAGON_V6_vmpyihb_acc", + "V6.vmpyihb.acc.128B" => "__builtin_HEXAGON_V6_vmpyihb_acc_128B", + "V6.vmpyiowh" => "__builtin_HEXAGON_V6_vmpyiowh", + "V6.vmpyiowh.128B" => "__builtin_HEXAGON_V6_vmpyiowh_128B", + "V6.vmpyiwb" => "__builtin_HEXAGON_V6_vmpyiwb", + "V6.vmpyiwb.128B" => "__builtin_HEXAGON_V6_vmpyiwb_128B", + "V6.vmpyiwb.acc" => "__builtin_HEXAGON_V6_vmpyiwb_acc", + "V6.vmpyiwb.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwb_acc_128B", + "V6.vmpyiwh" => "__builtin_HEXAGON_V6_vmpyiwh", + "V6.vmpyiwh.128B" => "__builtin_HEXAGON_V6_vmpyiwh_128B", + "V6.vmpyiwh.acc" => "__builtin_HEXAGON_V6_vmpyiwh_acc", + "V6.vmpyiwh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwh_acc_128B", + "V6.vmpyiwub" => "__builtin_HEXAGON_V6_vmpyiwub", + "V6.vmpyiwub.128B" => "__builtin_HEXAGON_V6_vmpyiwub_128B", + "V6.vmpyiwub.acc" => "__builtin_HEXAGON_V6_vmpyiwub_acc", + "V6.vmpyiwub.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwub_acc_128B", + "V6.vmpyowh" => "__builtin_HEXAGON_V6_vmpyowh", + "V6.vmpyowh.128B" => "__builtin_HEXAGON_V6_vmpyowh_128B", + "V6.vmpyowh.64.acc" => "__builtin_HEXAGON_V6_vmpyowh_64_acc", + "V6.vmpyowh.64.acc.128B" => "__builtin_HEXAGON_V6_vmpyowh_64_acc_128B", + "V6.vmpyowh.rnd" => "__builtin_HEXAGON_V6_vmpyowh_rnd", + "V6.vmpyowh.rnd.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_128B", + "V6.vmpyowh.rnd.sacc" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc", + "V6.vmpyowh.rnd.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc_128B", + "V6.vmpyowh.sacc" => "__builtin_HEXAGON_V6_vmpyowh_sacc", + "V6.vmpyowh.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_sacc_128B", + "V6.vmpyub" => "__builtin_HEXAGON_V6_vmpyub", + "V6.vmpyub.128B" => "__builtin_HEXAGON_V6_vmpyub_128B", + "V6.vmpyub.acc" => "__builtin_HEXAGON_V6_vmpyub_acc", + "V6.vmpyub.acc.128B" => "__builtin_HEXAGON_V6_vmpyub_acc_128B", + "V6.vmpyubv" => "__builtin_HEXAGON_V6_vmpyubv", + "V6.vmpyubv.128B" => "__builtin_HEXAGON_V6_vmpyubv_128B", + "V6.vmpyubv.acc" => "__builtin_HEXAGON_V6_vmpyubv_acc", + "V6.vmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vmpyubv_acc_128B", + "V6.vmpyuh" => "__builtin_HEXAGON_V6_vmpyuh", + "V6.vmpyuh.128B" => "__builtin_HEXAGON_V6_vmpyuh_128B", + "V6.vmpyuh.acc" => "__builtin_HEXAGON_V6_vmpyuh_acc", + "V6.vmpyuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyuh_acc_128B", + "V6.vmpyuhe" => "__builtin_HEXAGON_V6_vmpyuhe", + "V6.vmpyuhe.128B" => "__builtin_HEXAGON_V6_vmpyuhe_128B", + "V6.vmpyuhe.acc" => "__builtin_HEXAGON_V6_vmpyuhe_acc", + "V6.vmpyuhe.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhe_acc_128B", + "V6.vmpyuhv" => "__builtin_HEXAGON_V6_vmpyuhv", + "V6.vmpyuhv.128B" => "__builtin_HEXAGON_V6_vmpyuhv_128B", + "V6.vmpyuhv.acc" => "__builtin_HEXAGON_V6_vmpyuhv_acc", + "V6.vmpyuhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhv_acc_128B", + "V6.vmpyuhvs" => "__builtin_HEXAGON_V6_vmpyuhvs", + "V6.vmpyuhvs.128B" => "__builtin_HEXAGON_V6_vmpyuhvs_128B", + "V6.vmux" => "__builtin_HEXAGON_V6_vmux", + "V6.vmux.128B" => "__builtin_HEXAGON_V6_vmux_128B", + "V6.vnavgb" => "__builtin_HEXAGON_V6_vnavgb", + "V6.vnavgb.128B" => "__builtin_HEXAGON_V6_vnavgb_128B", + "V6.vnavgh" => "__builtin_HEXAGON_V6_vnavgh", + "V6.vnavgh.128B" => "__builtin_HEXAGON_V6_vnavgh_128B", + "V6.vnavgub" => "__builtin_HEXAGON_V6_vnavgub", + "V6.vnavgub.128B" => "__builtin_HEXAGON_V6_vnavgub_128B", + "V6.vnavgw" => "__builtin_HEXAGON_V6_vnavgw", + "V6.vnavgw.128B" => "__builtin_HEXAGON_V6_vnavgw_128B", + "V6.vnormamth" => "__builtin_HEXAGON_V6_vnormamth", + "V6.vnormamth.128B" => "__builtin_HEXAGON_V6_vnormamth_128B", + "V6.vnormamtw" => "__builtin_HEXAGON_V6_vnormamtw", + "V6.vnormamtw.128B" => "__builtin_HEXAGON_V6_vnormamtw_128B", + "V6.vnot" => "__builtin_HEXAGON_V6_vnot", + "V6.vnot.128B" => "__builtin_HEXAGON_V6_vnot_128B", + "V6.vor" => "__builtin_HEXAGON_V6_vor", + "V6.vor.128B" => "__builtin_HEXAGON_V6_vor_128B", + "V6.vpackeb" => "__builtin_HEXAGON_V6_vpackeb", + "V6.vpackeb.128B" => "__builtin_HEXAGON_V6_vpackeb_128B", + "V6.vpackeh" => "__builtin_HEXAGON_V6_vpackeh", + "V6.vpackeh.128B" => "__builtin_HEXAGON_V6_vpackeh_128B", + "V6.vpackhb.sat" => "__builtin_HEXAGON_V6_vpackhb_sat", + "V6.vpackhb.sat.128B" => "__builtin_HEXAGON_V6_vpackhb_sat_128B", + "V6.vpackhub.sat" => "__builtin_HEXAGON_V6_vpackhub_sat", + "V6.vpackhub.sat.128B" => "__builtin_HEXAGON_V6_vpackhub_sat_128B", + "V6.vpackob" => "__builtin_HEXAGON_V6_vpackob", + "V6.vpackob.128B" => "__builtin_HEXAGON_V6_vpackob_128B", + "V6.vpackoh" => "__builtin_HEXAGON_V6_vpackoh", + "V6.vpackoh.128B" => "__builtin_HEXAGON_V6_vpackoh_128B", + "V6.vpackwh.sat" => "__builtin_HEXAGON_V6_vpackwh_sat", + "V6.vpackwh.sat.128B" => "__builtin_HEXAGON_V6_vpackwh_sat_128B", + "V6.vpackwuh.sat" => "__builtin_HEXAGON_V6_vpackwuh_sat", + "V6.vpackwuh.sat.128B" => "__builtin_HEXAGON_V6_vpackwuh_sat_128B", + "V6.vpopcounth" => "__builtin_HEXAGON_V6_vpopcounth", + "V6.vpopcounth.128B" => "__builtin_HEXAGON_V6_vpopcounth_128B", + "V6.vprefixqb" => "__builtin_HEXAGON_V6_vprefixqb", + "V6.vprefixqb.128B" => "__builtin_HEXAGON_V6_vprefixqb_128B", + "V6.vprefixqh" => "__builtin_HEXAGON_V6_vprefixqh", + "V6.vprefixqh.128B" => "__builtin_HEXAGON_V6_vprefixqh_128B", + "V6.vprefixqw" => "__builtin_HEXAGON_V6_vprefixqw", + "V6.vprefixqw.128B" => "__builtin_HEXAGON_V6_vprefixqw_128B", + "V6.vrdelta" => "__builtin_HEXAGON_V6_vrdelta", + "V6.vrdelta.128B" => "__builtin_HEXAGON_V6_vrdelta_128B", + "V6.vrmpybub.rtt" => "__builtin_HEXAGON_V6_vrmpybub_rtt", + "V6.vrmpybub.rtt.128B" => "__builtin_HEXAGON_V6_vrmpybub_rtt_128B", + "V6.vrmpybub.rtt.acc" => "__builtin_HEXAGON_V6_vrmpybub_rtt_acc", + "V6.vrmpybub.rtt.acc.128B" => "__builtin_HEXAGON_V6_vrmpybub_rtt_acc_128B", + "V6.vrmpybus" => "__builtin_HEXAGON_V6_vrmpybus", + "V6.vrmpybus.128B" => "__builtin_HEXAGON_V6_vrmpybus_128B", + "V6.vrmpybus.acc" => "__builtin_HEXAGON_V6_vrmpybus_acc", + "V6.vrmpybus.acc.128B" => "__builtin_HEXAGON_V6_vrmpybus_acc_128B", + "V6.vrmpybusi" => "__builtin_HEXAGON_V6_vrmpybusi", + "V6.vrmpybusi.128B" => "__builtin_HEXAGON_V6_vrmpybusi_128B", + "V6.vrmpybusi.acc" => "__builtin_HEXAGON_V6_vrmpybusi_acc", + "V6.vrmpybusi.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusi_acc_128B", + "V6.vrmpybusv" => "__builtin_HEXAGON_V6_vrmpybusv", + "V6.vrmpybusv.128B" => "__builtin_HEXAGON_V6_vrmpybusv_128B", + "V6.vrmpybusv.acc" => "__builtin_HEXAGON_V6_vrmpybusv_acc", + "V6.vrmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusv_acc_128B", + "V6.vrmpybv" => "__builtin_HEXAGON_V6_vrmpybv", + "V6.vrmpybv.128B" => "__builtin_HEXAGON_V6_vrmpybv_128B", + "V6.vrmpybv.acc" => "__builtin_HEXAGON_V6_vrmpybv_acc", + "V6.vrmpybv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybv_acc_128B", + "V6.vrmpyub" => "__builtin_HEXAGON_V6_vrmpyub", + "V6.vrmpyub.128B" => "__builtin_HEXAGON_V6_vrmpyub_128B", + "V6.vrmpyub.acc" => "__builtin_HEXAGON_V6_vrmpyub_acc", + "V6.vrmpyub.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_acc_128B", + "V6.vrmpyub.rtt" => "__builtin_HEXAGON_V6_vrmpyub_rtt", + "V6.vrmpyub.rtt.128B" => "__builtin_HEXAGON_V6_vrmpyub_rtt_128B", + "V6.vrmpyub.rtt.acc" => "__builtin_HEXAGON_V6_vrmpyub_rtt_acc", + "V6.vrmpyub.rtt.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B", + "V6.vrmpyubi" => "__builtin_HEXAGON_V6_vrmpyubi", + "V6.vrmpyubi.128B" => "__builtin_HEXAGON_V6_vrmpyubi_128B", + "V6.vrmpyubi.acc" => "__builtin_HEXAGON_V6_vrmpyubi_acc", + "V6.vrmpyubi.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubi_acc_128B", + "V6.vrmpyubv" => "__builtin_HEXAGON_V6_vrmpyubv", + "V6.vrmpyubv.128B" => "__builtin_HEXAGON_V6_vrmpyubv_128B", + "V6.vrmpyubv.acc" => "__builtin_HEXAGON_V6_vrmpyubv_acc", + "V6.vrmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubv_acc_128B", + "V6.vror" => "__builtin_HEXAGON_V6_vror", + "V6.vror.128B" => "__builtin_HEXAGON_V6_vror_128B", + "V6.vrotr" => "__builtin_HEXAGON_V6_vrotr", + "V6.vrotr.128B" => "__builtin_HEXAGON_V6_vrotr_128B", + "V6.vroundhb" => "__builtin_HEXAGON_V6_vroundhb", + "V6.vroundhb.128B" => "__builtin_HEXAGON_V6_vroundhb_128B", + "V6.vroundhub" => "__builtin_HEXAGON_V6_vroundhub", + "V6.vroundhub.128B" => "__builtin_HEXAGON_V6_vroundhub_128B", + "V6.vrounduhub" => "__builtin_HEXAGON_V6_vrounduhub", + "V6.vrounduhub.128B" => "__builtin_HEXAGON_V6_vrounduhub_128B", + "V6.vrounduwuh" => "__builtin_HEXAGON_V6_vrounduwuh", + "V6.vrounduwuh.128B" => "__builtin_HEXAGON_V6_vrounduwuh_128B", + "V6.vroundwh" => "__builtin_HEXAGON_V6_vroundwh", + "V6.vroundwh.128B" => "__builtin_HEXAGON_V6_vroundwh_128B", + "V6.vroundwuh" => "__builtin_HEXAGON_V6_vroundwuh", + "V6.vroundwuh.128B" => "__builtin_HEXAGON_V6_vroundwuh_128B", + "V6.vrsadubi" => "__builtin_HEXAGON_V6_vrsadubi", + "V6.vrsadubi.128B" => "__builtin_HEXAGON_V6_vrsadubi_128B", + "V6.vrsadubi.acc" => "__builtin_HEXAGON_V6_vrsadubi_acc", + "V6.vrsadubi.acc.128B" => "__builtin_HEXAGON_V6_vrsadubi_acc_128B", + "V6.vsatdw" => "__builtin_HEXAGON_V6_vsatdw", + "V6.vsatdw.128B" => "__builtin_HEXAGON_V6_vsatdw_128B", + "V6.vsathub" => "__builtin_HEXAGON_V6_vsathub", + "V6.vsathub.128B" => "__builtin_HEXAGON_V6_vsathub_128B", + "V6.vsatuwuh" => "__builtin_HEXAGON_V6_vsatuwuh", + "V6.vsatuwuh.128B" => "__builtin_HEXAGON_V6_vsatuwuh_128B", + "V6.vsatwh" => "__builtin_HEXAGON_V6_vsatwh", + "V6.vsatwh.128B" => "__builtin_HEXAGON_V6_vsatwh_128B", + "V6.vsb" => "__builtin_HEXAGON_V6_vsb", + "V6.vsb.128B" => "__builtin_HEXAGON_V6_vsb_128B", + "V6.vscattermh" => "__builtin_HEXAGON_V6_vscattermh", + "V6.vscattermh.128B" => "__builtin_HEXAGON_V6_vscattermh_128B", + "V6.vscattermh.add" => "__builtin_HEXAGON_V6_vscattermh_add", + "V6.vscattermh.add.128B" => "__builtin_HEXAGON_V6_vscattermh_add_128B", + "V6.vscattermhq" => "__builtin_HEXAGON_V6_vscattermhq", + "V6.vscattermhq.128B" => "__builtin_HEXAGON_V6_vscattermhq_128B", + "V6.vscattermhw" => "__builtin_HEXAGON_V6_vscattermhw", + "V6.vscattermhw.128B" => "__builtin_HEXAGON_V6_vscattermhw_128B", + "V6.vscattermhw.add" => "__builtin_HEXAGON_V6_vscattermhw_add", + "V6.vscattermhw.add.128B" => "__builtin_HEXAGON_V6_vscattermhw_add_128B", + "V6.vscattermhwq" => "__builtin_HEXAGON_V6_vscattermhwq", + "V6.vscattermhwq.128B" => "__builtin_HEXAGON_V6_vscattermhwq_128B", + "V6.vscattermw" => "__builtin_HEXAGON_V6_vscattermw", + "V6.vscattermw.128B" => "__builtin_HEXAGON_V6_vscattermw_128B", + "V6.vscattermw.add" => "__builtin_HEXAGON_V6_vscattermw_add", + "V6.vscattermw.add.128B" => "__builtin_HEXAGON_V6_vscattermw_add_128B", + "V6.vscattermwq" => "__builtin_HEXAGON_V6_vscattermwq", + "V6.vscattermwq.128B" => "__builtin_HEXAGON_V6_vscattermwq_128B", + "V6.vsh" => "__builtin_HEXAGON_V6_vsh", + "V6.vsh.128B" => "__builtin_HEXAGON_V6_vsh_128B", + "V6.vshufeh" => "__builtin_HEXAGON_V6_vshufeh", + "V6.vshufeh.128B" => "__builtin_HEXAGON_V6_vshufeh_128B", + "V6.vshuffb" => "__builtin_HEXAGON_V6_vshuffb", + "V6.vshuffb.128B" => "__builtin_HEXAGON_V6_vshuffb_128B", + "V6.vshuffeb" => "__builtin_HEXAGON_V6_vshuffeb", + "V6.vshuffeb.128B" => "__builtin_HEXAGON_V6_vshuffeb_128B", + "V6.vshuffh" => "__builtin_HEXAGON_V6_vshuffh", + "V6.vshuffh.128B" => "__builtin_HEXAGON_V6_vshuffh_128B", + "V6.vshuffob" => "__builtin_HEXAGON_V6_vshuffob", + "V6.vshuffob.128B" => "__builtin_HEXAGON_V6_vshuffob_128B", + "V6.vshuffvdd" => "__builtin_HEXAGON_V6_vshuffvdd", + "V6.vshuffvdd.128B" => "__builtin_HEXAGON_V6_vshuffvdd_128B", + "V6.vshufoeb" => "__builtin_HEXAGON_V6_vshufoeb", + "V6.vshufoeb.128B" => "__builtin_HEXAGON_V6_vshufoeb_128B", + "V6.vshufoeh" => "__builtin_HEXAGON_V6_vshufoeh", + "V6.vshufoeh.128B" => "__builtin_HEXAGON_V6_vshufoeh_128B", + "V6.vshufoh" => "__builtin_HEXAGON_V6_vshufoh", + "V6.vshufoh.128B" => "__builtin_HEXAGON_V6_vshufoh_128B", + "V6.vsub.hf" => "__builtin_HEXAGON_V6_vsub_hf", + "V6.vsub.hf.128B" => "__builtin_HEXAGON_V6_vsub_hf_128B", + "V6.vsub.hf.f8" => "__builtin_HEXAGON_V6_vsub_hf_f8", + "V6.vsub.hf.f8.128B" => "__builtin_HEXAGON_V6_vsub_hf_f8_128B", + "V6.vsub.hf.hf" => "__builtin_HEXAGON_V6_vsub_hf_hf", + "V6.vsub.hf.hf.128B" => "__builtin_HEXAGON_V6_vsub_hf_hf_128B", + "V6.vsub.qf16" => "__builtin_HEXAGON_V6_vsub_qf16", + "V6.vsub.qf16.128B" => "__builtin_HEXAGON_V6_vsub_qf16_128B", + "V6.vsub.qf16.mix" => "__builtin_HEXAGON_V6_vsub_qf16_mix", + "V6.vsub.qf16.mix.128B" => "__builtin_HEXAGON_V6_vsub_qf16_mix_128B", + "V6.vsub.qf32" => "__builtin_HEXAGON_V6_vsub_qf32", + "V6.vsub.qf32.128B" => "__builtin_HEXAGON_V6_vsub_qf32_128B", + "V6.vsub.qf32.mix" => "__builtin_HEXAGON_V6_vsub_qf32_mix", + "V6.vsub.qf32.mix.128B" => "__builtin_HEXAGON_V6_vsub_qf32_mix_128B", + "V6.vsub.sf" => "__builtin_HEXAGON_V6_vsub_sf", + "V6.vsub.sf.128B" => "__builtin_HEXAGON_V6_vsub_sf_128B", + "V6.vsub.sf.bf" => "__builtin_HEXAGON_V6_vsub_sf_bf", + "V6.vsub.sf.bf.128B" => "__builtin_HEXAGON_V6_vsub_sf_bf_128B", + "V6.vsub.sf.hf" => "__builtin_HEXAGON_V6_vsub_sf_hf", + "V6.vsub.sf.hf.128B" => "__builtin_HEXAGON_V6_vsub_sf_hf_128B", + "V6.vsub.sf.sf" => "__builtin_HEXAGON_V6_vsub_sf_sf", + "V6.vsub.sf.sf.128B" => "__builtin_HEXAGON_V6_vsub_sf_sf_128B", + "V6.vsubb" => "__builtin_HEXAGON_V6_vsubb", + "V6.vsubb.128B" => "__builtin_HEXAGON_V6_vsubb_128B", + "V6.vsubb.dv" => "__builtin_HEXAGON_V6_vsubb_dv", + "V6.vsubb.dv.128B" => "__builtin_HEXAGON_V6_vsubb_dv_128B", + "V6.vsubbnq" => "__builtin_HEXAGON_V6_vsubbnq", + "V6.vsubbnq.128B" => "__builtin_HEXAGON_V6_vsubbnq_128B", + "V6.vsubbq" => "__builtin_HEXAGON_V6_vsubbq", + "V6.vsubbq.128B" => "__builtin_HEXAGON_V6_vsubbq_128B", + "V6.vsubbsat" => "__builtin_HEXAGON_V6_vsubbsat", + "V6.vsubbsat.128B" => "__builtin_HEXAGON_V6_vsubbsat_128B", + "V6.vsubbsat.dv" => "__builtin_HEXAGON_V6_vsubbsat_dv", + "V6.vsubbsat.dv.128B" => "__builtin_HEXAGON_V6_vsubbsat_dv_128B", + "V6.vsubh" => "__builtin_HEXAGON_V6_vsubh", + "V6.vsubh.128B" => "__builtin_HEXAGON_V6_vsubh_128B", + "V6.vsubh.dv" => "__builtin_HEXAGON_V6_vsubh_dv", + "V6.vsubh.dv.128B" => "__builtin_HEXAGON_V6_vsubh_dv_128B", + "V6.vsubhnq" => "__builtin_HEXAGON_V6_vsubhnq", + "V6.vsubhnq.128B" => "__builtin_HEXAGON_V6_vsubhnq_128B", + "V6.vsubhq" => "__builtin_HEXAGON_V6_vsubhq", + "V6.vsubhq.128B" => "__builtin_HEXAGON_V6_vsubhq_128B", + "V6.vsubhsat" => "__builtin_HEXAGON_V6_vsubhsat", + "V6.vsubhsat.128B" => "__builtin_HEXAGON_V6_vsubhsat_128B", + "V6.vsubhsat.dv" => "__builtin_HEXAGON_V6_vsubhsat_dv", + "V6.vsubhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubhsat_dv_128B", + "V6.vsubhw" => "__builtin_HEXAGON_V6_vsubhw", + "V6.vsubhw.128B" => "__builtin_HEXAGON_V6_vsubhw_128B", + "V6.vsububh" => "__builtin_HEXAGON_V6_vsububh", + "V6.vsububh.128B" => "__builtin_HEXAGON_V6_vsububh_128B", + "V6.vsububsat" => "__builtin_HEXAGON_V6_vsububsat", + "V6.vsububsat.128B" => "__builtin_HEXAGON_V6_vsububsat_128B", + "V6.vsububsat.dv" => "__builtin_HEXAGON_V6_vsububsat_dv", + "V6.vsububsat.dv.128B" => "__builtin_HEXAGON_V6_vsububsat_dv_128B", + "V6.vsubububb.sat" => "__builtin_HEXAGON_V6_vsubububb_sat", + "V6.vsubububb.sat.128B" => "__builtin_HEXAGON_V6_vsubububb_sat_128B", + "V6.vsubuhsat" => "__builtin_HEXAGON_V6_vsubuhsat", + "V6.vsubuhsat.128B" => "__builtin_HEXAGON_V6_vsubuhsat_128B", + "V6.vsubuhsat.dv" => "__builtin_HEXAGON_V6_vsubuhsat_dv", + "V6.vsubuhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuhsat_dv_128B", + "V6.vsubuhw" => "__builtin_HEXAGON_V6_vsubuhw", + "V6.vsubuhw.128B" => "__builtin_HEXAGON_V6_vsubuhw_128B", + "V6.vsubuwsat" => "__builtin_HEXAGON_V6_vsubuwsat", + "V6.vsubuwsat.128B" => "__builtin_HEXAGON_V6_vsubuwsat_128B", + "V6.vsubuwsat.dv" => "__builtin_HEXAGON_V6_vsubuwsat_dv", + "V6.vsubuwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuwsat_dv_128B", + "V6.vsubw" => "__builtin_HEXAGON_V6_vsubw", + "V6.vsubw.128B" => "__builtin_HEXAGON_V6_vsubw_128B", + "V6.vsubw.dv" => "__builtin_HEXAGON_V6_vsubw_dv", + "V6.vsubw.dv.128B" => "__builtin_HEXAGON_V6_vsubw_dv_128B", + "V6.vsubwnq" => "__builtin_HEXAGON_V6_vsubwnq", + "V6.vsubwnq.128B" => "__builtin_HEXAGON_V6_vsubwnq_128B", + "V6.vsubwq" => "__builtin_HEXAGON_V6_vsubwq", + "V6.vsubwq.128B" => "__builtin_HEXAGON_V6_vsubwq_128B", + "V6.vsubwsat" => "__builtin_HEXAGON_V6_vsubwsat", + "V6.vsubwsat.128B" => "__builtin_HEXAGON_V6_vsubwsat_128B", + "V6.vsubwsat.dv" => "__builtin_HEXAGON_V6_vsubwsat_dv", + "V6.vsubwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubwsat_dv_128B", + "V6.vswap" => "__builtin_HEXAGON_V6_vswap", + "V6.vswap.128B" => "__builtin_HEXAGON_V6_vswap_128B", + "V6.vtmpyb" => "__builtin_HEXAGON_V6_vtmpyb", + "V6.vtmpyb.128B" => "__builtin_HEXAGON_V6_vtmpyb_128B", + "V6.vtmpyb.acc" => "__builtin_HEXAGON_V6_vtmpyb_acc", + "V6.vtmpyb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyb_acc_128B", + "V6.vtmpybus" => "__builtin_HEXAGON_V6_vtmpybus", + "V6.vtmpybus.128B" => "__builtin_HEXAGON_V6_vtmpybus_128B", + "V6.vtmpybus.acc" => "__builtin_HEXAGON_V6_vtmpybus_acc", + "V6.vtmpybus.acc.128B" => "__builtin_HEXAGON_V6_vtmpybus_acc_128B", + "V6.vtmpyhb" => "__builtin_HEXAGON_V6_vtmpyhb", + "V6.vtmpyhb.128B" => "__builtin_HEXAGON_V6_vtmpyhb_128B", + "V6.vtmpyhb.acc" => "__builtin_HEXAGON_V6_vtmpyhb_acc", + "V6.vtmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyhb_acc_128B", + "V6.vunpackb" => "__builtin_HEXAGON_V6_vunpackb", + "V6.vunpackb.128B" => "__builtin_HEXAGON_V6_vunpackb_128B", + "V6.vunpackh" => "__builtin_HEXAGON_V6_vunpackh", + "V6.vunpackh.128B" => "__builtin_HEXAGON_V6_vunpackh_128B", + "V6.vunpackob" => "__builtin_HEXAGON_V6_vunpackob", + "V6.vunpackob.128B" => "__builtin_HEXAGON_V6_vunpackob_128B", + "V6.vunpackoh" => "__builtin_HEXAGON_V6_vunpackoh", + "V6.vunpackoh.128B" => "__builtin_HEXAGON_V6_vunpackoh_128B", + "V6.vunpackub" => "__builtin_HEXAGON_V6_vunpackub", + "V6.vunpackub.128B" => "__builtin_HEXAGON_V6_vunpackub_128B", + "V6.vunpackuh" => "__builtin_HEXAGON_V6_vunpackuh", + "V6.vunpackuh.128B" => "__builtin_HEXAGON_V6_vunpackuh_128B", + "V6.vxor" => "__builtin_HEXAGON_V6_vxor", + "V6.vxor.128B" => "__builtin_HEXAGON_V6_vxor_128B", + "V6.vzb" => "__builtin_HEXAGON_V6_vzb", + "V6.vzb.128B" => "__builtin_HEXAGON_V6_vzb_128B", + "V6.vzh" => "__builtin_HEXAGON_V6_vzh", + "V6.vzh.128B" => "__builtin_HEXAGON_V6_vzh_128B", + "Y2.dccleana" => "__builtin_HEXAGON_Y2_dccleana", + "Y2.dccleaninva" => "__builtin_HEXAGON_Y2_dccleaninva", + "Y2.dcfetch" => "__builtin_HEXAGON_Y2_dcfetch", + "Y2.dcinva" => "__builtin_HEXAGON_Y2_dcinva", + "Y2.dczeroa" => "__builtin_HEXAGON_Y2_dczeroa", + "Y4.l2fetch" => "__builtin_HEXAGON_Y4_l2fetch", + "Y5.l2fetch" => "__builtin_HEXAGON_Y5_l2fetch", + "Y6.dmlink" => "__builtin_HEXAGON_Y6_dmlink", + "Y6.dmpause" => "__builtin_HEXAGON_Y6_dmpause", + "Y6.dmpoll" => "__builtin_HEXAGON_Y6_dmpoll", + "Y6.dmresume" => "__builtin_HEXAGON_Y6_dmresume", + "Y6.dmstart" => "__builtin_HEXAGON_Y6_dmstart", + "Y6.dmwait" => "__builtin_HEXAGON_Y6_dmwait", + "brev.ldb" => "__builtin_brev_ldb", + "brev.ldd" => "__builtin_brev_ldd", + "brev.ldh" => "__builtin_brev_ldh", + "brev.ldub" => "__builtin_brev_ldub", + "brev.lduh" => "__builtin_brev_lduh", + "brev.ldw" => "__builtin_brev_ldw", + "brev.stb" => "__builtin_brev_stb", + "brev.std" => "__builtin_brev_std", + "brev.sth" => "__builtin_brev_sth", + "brev.sthhi" => "__builtin_brev_sthhi", + "brev.stw" => "__builtin_brev_stw", + "circ.ldb" => "__builtin_circ_ldb", + "circ.ldd" => "__builtin_circ_ldd", + "circ.ldh" => "__builtin_circ_ldh", + "circ.ldub" => "__builtin_circ_ldub", + "circ.lduh" => "__builtin_circ_lduh", + "circ.ldw" => "__builtin_circ_ldw", + "circ.stb" => "__builtin_circ_stb", + "circ.std" => "__builtin_circ_std", + "circ.sth" => "__builtin_circ_sth", + "circ.sthhi" => "__builtin_circ_sthhi", + "circ.stw" => "__builtin_circ_stw", + "mm256i.vaddw" => "__builtin__mm256i_vaddw", + "prefetch" => "__builtin_HEXAGON_prefetch", + "vmemcpy" => "__builtin_hexagon_vmemcpy", + "vmemset" => "__builtin_hexagon_vmemset", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + hexagon(name) + } + "loongarch" => { + #[allow(non_snake_case)] + fn loongarch(name: &str) -> &str { + match name { + // loongarch + "asrtgt.d" => "__builtin_loongarch_asrtgt_d", + "asrtle.d" => "__builtin_loongarch_asrtle_d", + "break" => "__builtin_loongarch_break", + "cacop.d" => "__builtin_loongarch_cacop_d", + "cacop.w" => "__builtin_loongarch_cacop_w", + "cpucfg" => "__builtin_loongarch_cpucfg", + "crc.w.b.w" => "__builtin_loongarch_crc_w_b_w", + "crc.w.d.w" => "__builtin_loongarch_crc_w_d_w", + "crc.w.h.w" => "__builtin_loongarch_crc_w_h_w", + "crc.w.w.w" => "__builtin_loongarch_crc_w_w_w", + "crcc.w.b.w" => "__builtin_loongarch_crcc_w_b_w", + "crcc.w.d.w" => "__builtin_loongarch_crcc_w_d_w", + "crcc.w.h.w" => "__builtin_loongarch_crcc_w_h_w", + "crcc.w.w.w" => "__builtin_loongarch_crcc_w_w_w", + "csrrd.d" => "__builtin_loongarch_csrrd_d", + "csrrd.w" => "__builtin_loongarch_csrrd_w", + "csrwr.d" => "__builtin_loongarch_csrwr_d", + "csrwr.w" => "__builtin_loongarch_csrwr_w", + "csrxchg.d" => "__builtin_loongarch_csrxchg_d", + "csrxchg.w" => "__builtin_loongarch_csrxchg_w", + "dbar" => "__builtin_loongarch_dbar", + "frecipe.d" => "__builtin_loongarch_frecipe_d", + "frecipe.s" => "__builtin_loongarch_frecipe_s", + "frsqrte.d" => "__builtin_loongarch_frsqrte_d", + "frsqrte.s" => "__builtin_loongarch_frsqrte_s", + "ibar" => "__builtin_loongarch_ibar", + "iocsrrd.b" => "__builtin_loongarch_iocsrrd_b", + "iocsrrd.d" => "__builtin_loongarch_iocsrrd_d", + "iocsrrd.h" => "__builtin_loongarch_iocsrrd_h", + "iocsrrd.w" => "__builtin_loongarch_iocsrrd_w", + "iocsrwr.b" => "__builtin_loongarch_iocsrwr_b", + "iocsrwr.d" => "__builtin_loongarch_iocsrwr_d", + "iocsrwr.h" => "__builtin_loongarch_iocsrwr_h", + "iocsrwr.w" => "__builtin_loongarch_iocsrwr_w", + "lasx.vext2xv.d.b" => "__builtin_lasx_vext2xv_d_b", + "lasx.vext2xv.d.h" => "__builtin_lasx_vext2xv_d_h", + "lasx.vext2xv.d.w" => "__builtin_lasx_vext2xv_d_w", + "lasx.vext2xv.du.bu" => "__builtin_lasx_vext2xv_du_bu", + "lasx.vext2xv.du.hu" => "__builtin_lasx_vext2xv_du_hu", + "lasx.vext2xv.du.wu" => "__builtin_lasx_vext2xv_du_wu", + "lasx.vext2xv.h.b" => "__builtin_lasx_vext2xv_h_b", + "lasx.vext2xv.hu.bu" => "__builtin_lasx_vext2xv_hu_bu", + "lasx.vext2xv.w.b" => "__builtin_lasx_vext2xv_w_b", + "lasx.vext2xv.w.h" => "__builtin_lasx_vext2xv_w_h", + "lasx.vext2xv.wu.bu" => "__builtin_lasx_vext2xv_wu_bu", + "lasx.vext2xv.wu.hu" => "__builtin_lasx_vext2xv_wu_hu", + "lasx.xbnz.b" => "__builtin_lasx_xbnz_b", + "lasx.xbnz.d" => "__builtin_lasx_xbnz_d", + "lasx.xbnz.h" => "__builtin_lasx_xbnz_h", + "lasx.xbnz.v" => "__builtin_lasx_xbnz_v", + "lasx.xbnz.w" => "__builtin_lasx_xbnz_w", + "lasx.xbz.b" => "__builtin_lasx_xbz_b", + "lasx.xbz.d" => "__builtin_lasx_xbz_d", + "lasx.xbz.h" => "__builtin_lasx_xbz_h", + "lasx.xbz.v" => "__builtin_lasx_xbz_v", + "lasx.xbz.w" => "__builtin_lasx_xbz_w", + "lasx.xvabsd.b" => "__builtin_lasx_xvabsd_b", + "lasx.xvabsd.bu" => "__builtin_lasx_xvabsd_bu", + "lasx.xvabsd.d" => "__builtin_lasx_xvabsd_d", + "lasx.xvabsd.du" => "__builtin_lasx_xvabsd_du", + "lasx.xvabsd.h" => "__builtin_lasx_xvabsd_h", + "lasx.xvabsd.hu" => "__builtin_lasx_xvabsd_hu", + "lasx.xvabsd.w" => "__builtin_lasx_xvabsd_w", + "lasx.xvabsd.wu" => "__builtin_lasx_xvabsd_wu", + "lasx.xvadd.b" => "__builtin_lasx_xvadd_b", + "lasx.xvadd.d" => "__builtin_lasx_xvadd_d", + "lasx.xvadd.h" => "__builtin_lasx_xvadd_h", + "lasx.xvadd.q" => "__builtin_lasx_xvadd_q", + "lasx.xvadd.w" => "__builtin_lasx_xvadd_w", + "lasx.xvadda.b" => "__builtin_lasx_xvadda_b", + "lasx.xvadda.d" => "__builtin_lasx_xvadda_d", + "lasx.xvadda.h" => "__builtin_lasx_xvadda_h", + "lasx.xvadda.w" => "__builtin_lasx_xvadda_w", + "lasx.xvaddi.bu" => "__builtin_lasx_xvaddi_bu", + "lasx.xvaddi.du" => "__builtin_lasx_xvaddi_du", + "lasx.xvaddi.hu" => "__builtin_lasx_xvaddi_hu", + "lasx.xvaddi.wu" => "__builtin_lasx_xvaddi_wu", + "lasx.xvaddwev.d.w" => "__builtin_lasx_xvaddwev_d_w", + "lasx.xvaddwev.d.wu" => "__builtin_lasx_xvaddwev_d_wu", + "lasx.xvaddwev.d.wu.w" => "__builtin_lasx_xvaddwev_d_wu_w", + "lasx.xvaddwev.h.b" => "__builtin_lasx_xvaddwev_h_b", + "lasx.xvaddwev.h.bu" => "__builtin_lasx_xvaddwev_h_bu", + "lasx.xvaddwev.h.bu.b" => "__builtin_lasx_xvaddwev_h_bu_b", + "lasx.xvaddwev.q.d" => "__builtin_lasx_xvaddwev_q_d", + "lasx.xvaddwev.q.du" => "__builtin_lasx_xvaddwev_q_du", + "lasx.xvaddwev.q.du.d" => "__builtin_lasx_xvaddwev_q_du_d", + "lasx.xvaddwev.w.h" => "__builtin_lasx_xvaddwev_w_h", + "lasx.xvaddwev.w.hu" => "__builtin_lasx_xvaddwev_w_hu", + "lasx.xvaddwev.w.hu.h" => "__builtin_lasx_xvaddwev_w_hu_h", + "lasx.xvaddwod.d.w" => "__builtin_lasx_xvaddwod_d_w", + "lasx.xvaddwod.d.wu" => "__builtin_lasx_xvaddwod_d_wu", + "lasx.xvaddwod.d.wu.w" => "__builtin_lasx_xvaddwod_d_wu_w", + "lasx.xvaddwod.h.b" => "__builtin_lasx_xvaddwod_h_b", + "lasx.xvaddwod.h.bu" => "__builtin_lasx_xvaddwod_h_bu", + "lasx.xvaddwod.h.bu.b" => "__builtin_lasx_xvaddwod_h_bu_b", + "lasx.xvaddwod.q.d" => "__builtin_lasx_xvaddwod_q_d", + "lasx.xvaddwod.q.du" => "__builtin_lasx_xvaddwod_q_du", + "lasx.xvaddwod.q.du.d" => "__builtin_lasx_xvaddwod_q_du_d", + "lasx.xvaddwod.w.h" => "__builtin_lasx_xvaddwod_w_h", + "lasx.xvaddwod.w.hu" => "__builtin_lasx_xvaddwod_w_hu", + "lasx.xvaddwod.w.hu.h" => "__builtin_lasx_xvaddwod_w_hu_h", + "lasx.xvand.v" => "__builtin_lasx_xvand_v", + "lasx.xvandi.b" => "__builtin_lasx_xvandi_b", + "lasx.xvandn.v" => "__builtin_lasx_xvandn_v", + "lasx.xvavg.b" => "__builtin_lasx_xvavg_b", + "lasx.xvavg.bu" => "__builtin_lasx_xvavg_bu", + "lasx.xvavg.d" => "__builtin_lasx_xvavg_d", + "lasx.xvavg.du" => "__builtin_lasx_xvavg_du", + "lasx.xvavg.h" => "__builtin_lasx_xvavg_h", + "lasx.xvavg.hu" => "__builtin_lasx_xvavg_hu", + "lasx.xvavg.w" => "__builtin_lasx_xvavg_w", + "lasx.xvavg.wu" => "__builtin_lasx_xvavg_wu", + "lasx.xvavgr.b" => "__builtin_lasx_xvavgr_b", + "lasx.xvavgr.bu" => "__builtin_lasx_xvavgr_bu", + "lasx.xvavgr.d" => "__builtin_lasx_xvavgr_d", + "lasx.xvavgr.du" => "__builtin_lasx_xvavgr_du", + "lasx.xvavgr.h" => "__builtin_lasx_xvavgr_h", + "lasx.xvavgr.hu" => "__builtin_lasx_xvavgr_hu", + "lasx.xvavgr.w" => "__builtin_lasx_xvavgr_w", + "lasx.xvavgr.wu" => "__builtin_lasx_xvavgr_wu", + "lasx.xvbitclr.b" => "__builtin_lasx_xvbitclr_b", + "lasx.xvbitclr.d" => "__builtin_lasx_xvbitclr_d", + "lasx.xvbitclr.h" => "__builtin_lasx_xvbitclr_h", + "lasx.xvbitclr.w" => "__builtin_lasx_xvbitclr_w", + "lasx.xvbitclri.b" => "__builtin_lasx_xvbitclri_b", + "lasx.xvbitclri.d" => "__builtin_lasx_xvbitclri_d", + "lasx.xvbitclri.h" => "__builtin_lasx_xvbitclri_h", + "lasx.xvbitclri.w" => "__builtin_lasx_xvbitclri_w", + "lasx.xvbitrev.b" => "__builtin_lasx_xvbitrev_b", + "lasx.xvbitrev.d" => "__builtin_lasx_xvbitrev_d", + "lasx.xvbitrev.h" => "__builtin_lasx_xvbitrev_h", + "lasx.xvbitrev.w" => "__builtin_lasx_xvbitrev_w", + "lasx.xvbitrevi.b" => "__builtin_lasx_xvbitrevi_b", + "lasx.xvbitrevi.d" => "__builtin_lasx_xvbitrevi_d", + "lasx.xvbitrevi.h" => "__builtin_lasx_xvbitrevi_h", + "lasx.xvbitrevi.w" => "__builtin_lasx_xvbitrevi_w", + "lasx.xvbitsel.v" => "__builtin_lasx_xvbitsel_v", + "lasx.xvbitseli.b" => "__builtin_lasx_xvbitseli_b", + "lasx.xvbitset.b" => "__builtin_lasx_xvbitset_b", + "lasx.xvbitset.d" => "__builtin_lasx_xvbitset_d", + "lasx.xvbitset.h" => "__builtin_lasx_xvbitset_h", + "lasx.xvbitset.w" => "__builtin_lasx_xvbitset_w", + "lasx.xvbitseti.b" => "__builtin_lasx_xvbitseti_b", + "lasx.xvbitseti.d" => "__builtin_lasx_xvbitseti_d", + "lasx.xvbitseti.h" => "__builtin_lasx_xvbitseti_h", + "lasx.xvbitseti.w" => "__builtin_lasx_xvbitseti_w", + "lasx.xvbsll.v" => "__builtin_lasx_xvbsll_v", + "lasx.xvbsrl.v" => "__builtin_lasx_xvbsrl_v", + "lasx.xvclo.b" => "__builtin_lasx_xvclo_b", + "lasx.xvclo.d" => "__builtin_lasx_xvclo_d", + "lasx.xvclo.h" => "__builtin_lasx_xvclo_h", + "lasx.xvclo.w" => "__builtin_lasx_xvclo_w", + "lasx.xvclz.b" => "__builtin_lasx_xvclz_b", + "lasx.xvclz.d" => "__builtin_lasx_xvclz_d", + "lasx.xvclz.h" => "__builtin_lasx_xvclz_h", + "lasx.xvclz.w" => "__builtin_lasx_xvclz_w", + "lasx.xvdiv.b" => "__builtin_lasx_xvdiv_b", + "lasx.xvdiv.bu" => "__builtin_lasx_xvdiv_bu", + "lasx.xvdiv.d" => "__builtin_lasx_xvdiv_d", + "lasx.xvdiv.du" => "__builtin_lasx_xvdiv_du", + "lasx.xvdiv.h" => "__builtin_lasx_xvdiv_h", + "lasx.xvdiv.hu" => "__builtin_lasx_xvdiv_hu", + "lasx.xvdiv.w" => "__builtin_lasx_xvdiv_w", + "lasx.xvdiv.wu" => "__builtin_lasx_xvdiv_wu", + "lasx.xvexth.d.w" => "__builtin_lasx_xvexth_d_w", + "lasx.xvexth.du.wu" => "__builtin_lasx_xvexth_du_wu", + "lasx.xvexth.h.b" => "__builtin_lasx_xvexth_h_b", + "lasx.xvexth.hu.bu" => "__builtin_lasx_xvexth_hu_bu", + "lasx.xvexth.q.d" => "__builtin_lasx_xvexth_q_d", + "lasx.xvexth.qu.du" => "__builtin_lasx_xvexth_qu_du", + "lasx.xvexth.w.h" => "__builtin_lasx_xvexth_w_h", + "lasx.xvexth.wu.hu" => "__builtin_lasx_xvexth_wu_hu", + "lasx.xvextl.q.d" => "__builtin_lasx_xvextl_q_d", + "lasx.xvextl.qu.du" => "__builtin_lasx_xvextl_qu_du", + "lasx.xvextrins.b" => "__builtin_lasx_xvextrins_b", + "lasx.xvextrins.d" => "__builtin_lasx_xvextrins_d", + "lasx.xvextrins.h" => "__builtin_lasx_xvextrins_h", + "lasx.xvextrins.w" => "__builtin_lasx_xvextrins_w", + "lasx.xvfadd.d" => "__builtin_lasx_xvfadd_d", + "lasx.xvfadd.s" => "__builtin_lasx_xvfadd_s", + "lasx.xvfclass.d" => "__builtin_lasx_xvfclass_d", + "lasx.xvfclass.s" => "__builtin_lasx_xvfclass_s", + "lasx.xvfcmp.caf.d" => "__builtin_lasx_xvfcmp_caf_d", + "lasx.xvfcmp.caf.s" => "__builtin_lasx_xvfcmp_caf_s", + "lasx.xvfcmp.ceq.d" => "__builtin_lasx_xvfcmp_ceq_d", + "lasx.xvfcmp.ceq.s" => "__builtin_lasx_xvfcmp_ceq_s", + "lasx.xvfcmp.cle.d" => "__builtin_lasx_xvfcmp_cle_d", + "lasx.xvfcmp.cle.s" => "__builtin_lasx_xvfcmp_cle_s", + "lasx.xvfcmp.clt.d" => "__builtin_lasx_xvfcmp_clt_d", + "lasx.xvfcmp.clt.s" => "__builtin_lasx_xvfcmp_clt_s", + "lasx.xvfcmp.cne.d" => "__builtin_lasx_xvfcmp_cne_d", + "lasx.xvfcmp.cne.s" => "__builtin_lasx_xvfcmp_cne_s", + "lasx.xvfcmp.cor.d" => "__builtin_lasx_xvfcmp_cor_d", + "lasx.xvfcmp.cor.s" => "__builtin_lasx_xvfcmp_cor_s", + "lasx.xvfcmp.cueq.d" => "__builtin_lasx_xvfcmp_cueq_d", + "lasx.xvfcmp.cueq.s" => "__builtin_lasx_xvfcmp_cueq_s", + "lasx.xvfcmp.cule.d" => "__builtin_lasx_xvfcmp_cule_d", + "lasx.xvfcmp.cule.s" => "__builtin_lasx_xvfcmp_cule_s", + "lasx.xvfcmp.cult.d" => "__builtin_lasx_xvfcmp_cult_d", + "lasx.xvfcmp.cult.s" => "__builtin_lasx_xvfcmp_cult_s", + "lasx.xvfcmp.cun.d" => "__builtin_lasx_xvfcmp_cun_d", + "lasx.xvfcmp.cun.s" => "__builtin_lasx_xvfcmp_cun_s", + "lasx.xvfcmp.cune.d" => "__builtin_lasx_xvfcmp_cune_d", + "lasx.xvfcmp.cune.s" => "__builtin_lasx_xvfcmp_cune_s", + "lasx.xvfcmp.saf.d" => "__builtin_lasx_xvfcmp_saf_d", + "lasx.xvfcmp.saf.s" => "__builtin_lasx_xvfcmp_saf_s", + "lasx.xvfcmp.seq.d" => "__builtin_lasx_xvfcmp_seq_d", + "lasx.xvfcmp.seq.s" => "__builtin_lasx_xvfcmp_seq_s", + "lasx.xvfcmp.sle.d" => "__builtin_lasx_xvfcmp_sle_d", + "lasx.xvfcmp.sle.s" => "__builtin_lasx_xvfcmp_sle_s", + "lasx.xvfcmp.slt.d" => "__builtin_lasx_xvfcmp_slt_d", + "lasx.xvfcmp.slt.s" => "__builtin_lasx_xvfcmp_slt_s", + "lasx.xvfcmp.sne.d" => "__builtin_lasx_xvfcmp_sne_d", + "lasx.xvfcmp.sne.s" => "__builtin_lasx_xvfcmp_sne_s", + "lasx.xvfcmp.sor.d" => "__builtin_lasx_xvfcmp_sor_d", + "lasx.xvfcmp.sor.s" => "__builtin_lasx_xvfcmp_sor_s", + "lasx.xvfcmp.sueq.d" => "__builtin_lasx_xvfcmp_sueq_d", + "lasx.xvfcmp.sueq.s" => "__builtin_lasx_xvfcmp_sueq_s", + "lasx.xvfcmp.sule.d" => "__builtin_lasx_xvfcmp_sule_d", + "lasx.xvfcmp.sule.s" => "__builtin_lasx_xvfcmp_sule_s", + "lasx.xvfcmp.sult.d" => "__builtin_lasx_xvfcmp_sult_d", + "lasx.xvfcmp.sult.s" => "__builtin_lasx_xvfcmp_sult_s", + "lasx.xvfcmp.sun.d" => "__builtin_lasx_xvfcmp_sun_d", + "lasx.xvfcmp.sun.s" => "__builtin_lasx_xvfcmp_sun_s", + "lasx.xvfcmp.sune.d" => "__builtin_lasx_xvfcmp_sune_d", + "lasx.xvfcmp.sune.s" => "__builtin_lasx_xvfcmp_sune_s", + "lasx.xvfcvt.h.s" => "__builtin_lasx_xvfcvt_h_s", + "lasx.xvfcvt.s.d" => "__builtin_lasx_xvfcvt_s_d", + "lasx.xvfcvth.d.s" => "__builtin_lasx_xvfcvth_d_s", + "lasx.xvfcvth.s.h" => "__builtin_lasx_xvfcvth_s_h", + "lasx.xvfcvtl.d.s" => "__builtin_lasx_xvfcvtl_d_s", + "lasx.xvfcvtl.s.h" => "__builtin_lasx_xvfcvtl_s_h", + "lasx.xvfdiv.d" => "__builtin_lasx_xvfdiv_d", + "lasx.xvfdiv.s" => "__builtin_lasx_xvfdiv_s", + "lasx.xvffint.d.l" => "__builtin_lasx_xvffint_d_l", + "lasx.xvffint.d.lu" => "__builtin_lasx_xvffint_d_lu", + "lasx.xvffint.s.l" => "__builtin_lasx_xvffint_s_l", + "lasx.xvffint.s.w" => "__builtin_lasx_xvffint_s_w", + "lasx.xvffint.s.wu" => "__builtin_lasx_xvffint_s_wu", + "lasx.xvffinth.d.w" => "__builtin_lasx_xvffinth_d_w", + "lasx.xvffintl.d.w" => "__builtin_lasx_xvffintl_d_w", + "lasx.xvflogb.d" => "__builtin_lasx_xvflogb_d", + "lasx.xvflogb.s" => "__builtin_lasx_xvflogb_s", + "lasx.xvfmadd.d" => "__builtin_lasx_xvfmadd_d", + "lasx.xvfmadd.s" => "__builtin_lasx_xvfmadd_s", + "lasx.xvfmax.d" => "__builtin_lasx_xvfmax_d", + "lasx.xvfmax.s" => "__builtin_lasx_xvfmax_s", + "lasx.xvfmaxa.d" => "__builtin_lasx_xvfmaxa_d", + "lasx.xvfmaxa.s" => "__builtin_lasx_xvfmaxa_s", + "lasx.xvfmin.d" => "__builtin_lasx_xvfmin_d", + "lasx.xvfmin.s" => "__builtin_lasx_xvfmin_s", + "lasx.xvfmina.d" => "__builtin_lasx_xvfmina_d", + "lasx.xvfmina.s" => "__builtin_lasx_xvfmina_s", + "lasx.xvfmsub.d" => "__builtin_lasx_xvfmsub_d", + "lasx.xvfmsub.s" => "__builtin_lasx_xvfmsub_s", + "lasx.xvfmul.d" => "__builtin_lasx_xvfmul_d", + "lasx.xvfmul.s" => "__builtin_lasx_xvfmul_s", + "lasx.xvfnmadd.d" => "__builtin_lasx_xvfnmadd_d", + "lasx.xvfnmadd.s" => "__builtin_lasx_xvfnmadd_s", + "lasx.xvfnmsub.d" => "__builtin_lasx_xvfnmsub_d", + "lasx.xvfnmsub.s" => "__builtin_lasx_xvfnmsub_s", + "lasx.xvfrecip.d" => "__builtin_lasx_xvfrecip_d", + "lasx.xvfrecip.s" => "__builtin_lasx_xvfrecip_s", + "lasx.xvfrecipe.d" => "__builtin_lasx_xvfrecipe_d", + "lasx.xvfrecipe.s" => "__builtin_lasx_xvfrecipe_s", + "lasx.xvfrint.d" => "__builtin_lasx_xvfrint_d", + "lasx.xvfrint.s" => "__builtin_lasx_xvfrint_s", + "lasx.xvfrintrm.d" => "__builtin_lasx_xvfrintrm_d", + "lasx.xvfrintrm.s" => "__builtin_lasx_xvfrintrm_s", + "lasx.xvfrintrne.d" => "__builtin_lasx_xvfrintrne_d", + "lasx.xvfrintrne.s" => "__builtin_lasx_xvfrintrne_s", + "lasx.xvfrintrp.d" => "__builtin_lasx_xvfrintrp_d", + "lasx.xvfrintrp.s" => "__builtin_lasx_xvfrintrp_s", + "lasx.xvfrintrz.d" => "__builtin_lasx_xvfrintrz_d", + "lasx.xvfrintrz.s" => "__builtin_lasx_xvfrintrz_s", + "lasx.xvfrsqrt.d" => "__builtin_lasx_xvfrsqrt_d", + "lasx.xvfrsqrt.s" => "__builtin_lasx_xvfrsqrt_s", + "lasx.xvfrsqrte.d" => "__builtin_lasx_xvfrsqrte_d", + "lasx.xvfrsqrte.s" => "__builtin_lasx_xvfrsqrte_s", + "lasx.xvfrstp.b" => "__builtin_lasx_xvfrstp_b", + "lasx.xvfrstp.h" => "__builtin_lasx_xvfrstp_h", + "lasx.xvfrstpi.b" => "__builtin_lasx_xvfrstpi_b", + "lasx.xvfrstpi.h" => "__builtin_lasx_xvfrstpi_h", + "lasx.xvfsqrt.d" => "__builtin_lasx_xvfsqrt_d", + "lasx.xvfsqrt.s" => "__builtin_lasx_xvfsqrt_s", + "lasx.xvfsub.d" => "__builtin_lasx_xvfsub_d", + "lasx.xvfsub.s" => "__builtin_lasx_xvfsub_s", + "lasx.xvftint.l.d" => "__builtin_lasx_xvftint_l_d", + "lasx.xvftint.lu.d" => "__builtin_lasx_xvftint_lu_d", + "lasx.xvftint.w.d" => "__builtin_lasx_xvftint_w_d", + "lasx.xvftint.w.s" => "__builtin_lasx_xvftint_w_s", + "lasx.xvftint.wu.s" => "__builtin_lasx_xvftint_wu_s", + "lasx.xvftinth.l.s" => "__builtin_lasx_xvftinth_l_s", + "lasx.xvftintl.l.s" => "__builtin_lasx_xvftintl_l_s", + "lasx.xvftintrm.l.d" => "__builtin_lasx_xvftintrm_l_d", + "lasx.xvftintrm.w.d" => "__builtin_lasx_xvftintrm_w_d", + "lasx.xvftintrm.w.s" => "__builtin_lasx_xvftintrm_w_s", + "lasx.xvftintrmh.l.s" => "__builtin_lasx_xvftintrmh_l_s", + "lasx.xvftintrml.l.s" => "__builtin_lasx_xvftintrml_l_s", + "lasx.xvftintrne.l.d" => "__builtin_lasx_xvftintrne_l_d", + "lasx.xvftintrne.w.d" => "__builtin_lasx_xvftintrne_w_d", + "lasx.xvftintrne.w.s" => "__builtin_lasx_xvftintrne_w_s", + "lasx.xvftintrneh.l.s" => "__builtin_lasx_xvftintrneh_l_s", + "lasx.xvftintrnel.l.s" => "__builtin_lasx_xvftintrnel_l_s", + "lasx.xvftintrp.l.d" => "__builtin_lasx_xvftintrp_l_d", + "lasx.xvftintrp.w.d" => "__builtin_lasx_xvftintrp_w_d", + "lasx.xvftintrp.w.s" => "__builtin_lasx_xvftintrp_w_s", + "lasx.xvftintrph.l.s" => "__builtin_lasx_xvftintrph_l_s", + "lasx.xvftintrpl.l.s" => "__builtin_lasx_xvftintrpl_l_s", + "lasx.xvftintrz.l.d" => "__builtin_lasx_xvftintrz_l_d", + "lasx.xvftintrz.lu.d" => "__builtin_lasx_xvftintrz_lu_d", + "lasx.xvftintrz.w.d" => "__builtin_lasx_xvftintrz_w_d", + "lasx.xvftintrz.w.s" => "__builtin_lasx_xvftintrz_w_s", + "lasx.xvftintrz.wu.s" => "__builtin_lasx_xvftintrz_wu_s", + "lasx.xvftintrzh.l.s" => "__builtin_lasx_xvftintrzh_l_s", + "lasx.xvftintrzl.l.s" => "__builtin_lasx_xvftintrzl_l_s", + "lasx.xvhaddw.d.w" => "__builtin_lasx_xvhaddw_d_w", + "lasx.xvhaddw.du.wu" => "__builtin_lasx_xvhaddw_du_wu", + "lasx.xvhaddw.h.b" => "__builtin_lasx_xvhaddw_h_b", + "lasx.xvhaddw.hu.bu" => "__builtin_lasx_xvhaddw_hu_bu", + "lasx.xvhaddw.q.d" => "__builtin_lasx_xvhaddw_q_d", + "lasx.xvhaddw.qu.du" => "__builtin_lasx_xvhaddw_qu_du", + "lasx.xvhaddw.w.h" => "__builtin_lasx_xvhaddw_w_h", + "lasx.xvhaddw.wu.hu" => "__builtin_lasx_xvhaddw_wu_hu", + "lasx.xvhsubw.d.w" => "__builtin_lasx_xvhsubw_d_w", + "lasx.xvhsubw.du.wu" => "__builtin_lasx_xvhsubw_du_wu", + "lasx.xvhsubw.h.b" => "__builtin_lasx_xvhsubw_h_b", + "lasx.xvhsubw.hu.bu" => "__builtin_lasx_xvhsubw_hu_bu", + "lasx.xvhsubw.q.d" => "__builtin_lasx_xvhsubw_q_d", + "lasx.xvhsubw.qu.du" => "__builtin_lasx_xvhsubw_qu_du", + "lasx.xvhsubw.w.h" => "__builtin_lasx_xvhsubw_w_h", + "lasx.xvhsubw.wu.hu" => "__builtin_lasx_xvhsubw_wu_hu", + "lasx.xvilvh.b" => "__builtin_lasx_xvilvh_b", + "lasx.xvilvh.d" => "__builtin_lasx_xvilvh_d", + "lasx.xvilvh.h" => "__builtin_lasx_xvilvh_h", + "lasx.xvilvh.w" => "__builtin_lasx_xvilvh_w", + "lasx.xvilvl.b" => "__builtin_lasx_xvilvl_b", + "lasx.xvilvl.d" => "__builtin_lasx_xvilvl_d", + "lasx.xvilvl.h" => "__builtin_lasx_xvilvl_h", + "lasx.xvilvl.w" => "__builtin_lasx_xvilvl_w", + "lasx.xvinsgr2vr.d" => "__builtin_lasx_xvinsgr2vr_d", + "lasx.xvinsgr2vr.w" => "__builtin_lasx_xvinsgr2vr_w", + "lasx.xvinsve0.d" => "__builtin_lasx_xvinsve0_d", + "lasx.xvinsve0.w" => "__builtin_lasx_xvinsve0_w", + "lasx.xvld" => "__builtin_lasx_xvld", + "lasx.xvldi" => "__builtin_lasx_xvldi", + "lasx.xvldrepl.b" => "__builtin_lasx_xvldrepl_b", + "lasx.xvldrepl.d" => "__builtin_lasx_xvldrepl_d", + "lasx.xvldrepl.h" => "__builtin_lasx_xvldrepl_h", + "lasx.xvldrepl.w" => "__builtin_lasx_xvldrepl_w", + "lasx.xvldx" => "__builtin_lasx_xvldx", + "lasx.xvmadd.b" => "__builtin_lasx_xvmadd_b", + "lasx.xvmadd.d" => "__builtin_lasx_xvmadd_d", + "lasx.xvmadd.h" => "__builtin_lasx_xvmadd_h", + "lasx.xvmadd.w" => "__builtin_lasx_xvmadd_w", + "lasx.xvmaddwev.d.w" => "__builtin_lasx_xvmaddwev_d_w", + "lasx.xvmaddwev.d.wu" => "__builtin_lasx_xvmaddwev_d_wu", + "lasx.xvmaddwev.d.wu.w" => "__builtin_lasx_xvmaddwev_d_wu_w", + "lasx.xvmaddwev.h.b" => "__builtin_lasx_xvmaddwev_h_b", + "lasx.xvmaddwev.h.bu" => "__builtin_lasx_xvmaddwev_h_bu", + "lasx.xvmaddwev.h.bu.b" => "__builtin_lasx_xvmaddwev_h_bu_b", + "lasx.xvmaddwev.q.d" => "__builtin_lasx_xvmaddwev_q_d", + "lasx.xvmaddwev.q.du" => "__builtin_lasx_xvmaddwev_q_du", + "lasx.xvmaddwev.q.du.d" => "__builtin_lasx_xvmaddwev_q_du_d", + "lasx.xvmaddwev.w.h" => "__builtin_lasx_xvmaddwev_w_h", + "lasx.xvmaddwev.w.hu" => "__builtin_lasx_xvmaddwev_w_hu", + "lasx.xvmaddwev.w.hu.h" => "__builtin_lasx_xvmaddwev_w_hu_h", + "lasx.xvmaddwod.d.w" => "__builtin_lasx_xvmaddwod_d_w", + "lasx.xvmaddwod.d.wu" => "__builtin_lasx_xvmaddwod_d_wu", + "lasx.xvmaddwod.d.wu.w" => "__builtin_lasx_xvmaddwod_d_wu_w", + "lasx.xvmaddwod.h.b" => "__builtin_lasx_xvmaddwod_h_b", + "lasx.xvmaddwod.h.bu" => "__builtin_lasx_xvmaddwod_h_bu", + "lasx.xvmaddwod.h.bu.b" => "__builtin_lasx_xvmaddwod_h_bu_b", + "lasx.xvmaddwod.q.d" => "__builtin_lasx_xvmaddwod_q_d", + "lasx.xvmaddwod.q.du" => "__builtin_lasx_xvmaddwod_q_du", + "lasx.xvmaddwod.q.du.d" => "__builtin_lasx_xvmaddwod_q_du_d", + "lasx.xvmaddwod.w.h" => "__builtin_lasx_xvmaddwod_w_h", + "lasx.xvmaddwod.w.hu" => "__builtin_lasx_xvmaddwod_w_hu", + "lasx.xvmaddwod.w.hu.h" => "__builtin_lasx_xvmaddwod_w_hu_h", + "lasx.xvmax.b" => "__builtin_lasx_xvmax_b", + "lasx.xvmax.bu" => "__builtin_lasx_xvmax_bu", + "lasx.xvmax.d" => "__builtin_lasx_xvmax_d", + "lasx.xvmax.du" => "__builtin_lasx_xvmax_du", + "lasx.xvmax.h" => "__builtin_lasx_xvmax_h", + "lasx.xvmax.hu" => "__builtin_lasx_xvmax_hu", + "lasx.xvmax.w" => "__builtin_lasx_xvmax_w", + "lasx.xvmax.wu" => "__builtin_lasx_xvmax_wu", + "lasx.xvmaxi.b" => "__builtin_lasx_xvmaxi_b", + "lasx.xvmaxi.bu" => "__builtin_lasx_xvmaxi_bu", + "lasx.xvmaxi.d" => "__builtin_lasx_xvmaxi_d", + "lasx.xvmaxi.du" => "__builtin_lasx_xvmaxi_du", + "lasx.xvmaxi.h" => "__builtin_lasx_xvmaxi_h", + "lasx.xvmaxi.hu" => "__builtin_lasx_xvmaxi_hu", + "lasx.xvmaxi.w" => "__builtin_lasx_xvmaxi_w", + "lasx.xvmaxi.wu" => "__builtin_lasx_xvmaxi_wu", + "lasx.xvmin.b" => "__builtin_lasx_xvmin_b", + "lasx.xvmin.bu" => "__builtin_lasx_xvmin_bu", + "lasx.xvmin.d" => "__builtin_lasx_xvmin_d", + "lasx.xvmin.du" => "__builtin_lasx_xvmin_du", + "lasx.xvmin.h" => "__builtin_lasx_xvmin_h", + "lasx.xvmin.hu" => "__builtin_lasx_xvmin_hu", + "lasx.xvmin.w" => "__builtin_lasx_xvmin_w", + "lasx.xvmin.wu" => "__builtin_lasx_xvmin_wu", + "lasx.xvmini.b" => "__builtin_lasx_xvmini_b", + "lasx.xvmini.bu" => "__builtin_lasx_xvmini_bu", + "lasx.xvmini.d" => "__builtin_lasx_xvmini_d", + "lasx.xvmini.du" => "__builtin_lasx_xvmini_du", + "lasx.xvmini.h" => "__builtin_lasx_xvmini_h", + "lasx.xvmini.hu" => "__builtin_lasx_xvmini_hu", + "lasx.xvmini.w" => "__builtin_lasx_xvmini_w", + "lasx.xvmini.wu" => "__builtin_lasx_xvmini_wu", + "lasx.xvmod.b" => "__builtin_lasx_xvmod_b", + "lasx.xvmod.bu" => "__builtin_lasx_xvmod_bu", + "lasx.xvmod.d" => "__builtin_lasx_xvmod_d", + "lasx.xvmod.du" => "__builtin_lasx_xvmod_du", + "lasx.xvmod.h" => "__builtin_lasx_xvmod_h", + "lasx.xvmod.hu" => "__builtin_lasx_xvmod_hu", + "lasx.xvmod.w" => "__builtin_lasx_xvmod_w", + "lasx.xvmod.wu" => "__builtin_lasx_xvmod_wu", + "lasx.xvmskgez.b" => "__builtin_lasx_xvmskgez_b", + "lasx.xvmskltz.b" => "__builtin_lasx_xvmskltz_b", + "lasx.xvmskltz.d" => "__builtin_lasx_xvmskltz_d", + "lasx.xvmskltz.h" => "__builtin_lasx_xvmskltz_h", + "lasx.xvmskltz.w" => "__builtin_lasx_xvmskltz_w", + "lasx.xvmsknz.b" => "__builtin_lasx_xvmsknz_b", + "lasx.xvmsub.b" => "__builtin_lasx_xvmsub_b", + "lasx.xvmsub.d" => "__builtin_lasx_xvmsub_d", + "lasx.xvmsub.h" => "__builtin_lasx_xvmsub_h", + "lasx.xvmsub.w" => "__builtin_lasx_xvmsub_w", + "lasx.xvmuh.b" => "__builtin_lasx_xvmuh_b", + "lasx.xvmuh.bu" => "__builtin_lasx_xvmuh_bu", + "lasx.xvmuh.d" => "__builtin_lasx_xvmuh_d", + "lasx.xvmuh.du" => "__builtin_lasx_xvmuh_du", + "lasx.xvmuh.h" => "__builtin_lasx_xvmuh_h", + "lasx.xvmuh.hu" => "__builtin_lasx_xvmuh_hu", + "lasx.xvmuh.w" => "__builtin_lasx_xvmuh_w", + "lasx.xvmuh.wu" => "__builtin_lasx_xvmuh_wu", + "lasx.xvmul.b" => "__builtin_lasx_xvmul_b", + "lasx.xvmul.d" => "__builtin_lasx_xvmul_d", + "lasx.xvmul.h" => "__builtin_lasx_xvmul_h", + "lasx.xvmul.w" => "__builtin_lasx_xvmul_w", + "lasx.xvmulwev.d.w" => "__builtin_lasx_xvmulwev_d_w", + "lasx.xvmulwev.d.wu" => "__builtin_lasx_xvmulwev_d_wu", + "lasx.xvmulwev.d.wu.w" => "__builtin_lasx_xvmulwev_d_wu_w", + "lasx.xvmulwev.h.b" => "__builtin_lasx_xvmulwev_h_b", + "lasx.xvmulwev.h.bu" => "__builtin_lasx_xvmulwev_h_bu", + "lasx.xvmulwev.h.bu.b" => "__builtin_lasx_xvmulwev_h_bu_b", + "lasx.xvmulwev.q.d" => "__builtin_lasx_xvmulwev_q_d", + "lasx.xvmulwev.q.du" => "__builtin_lasx_xvmulwev_q_du", + "lasx.xvmulwev.q.du.d" => "__builtin_lasx_xvmulwev_q_du_d", + "lasx.xvmulwev.w.h" => "__builtin_lasx_xvmulwev_w_h", + "lasx.xvmulwev.w.hu" => "__builtin_lasx_xvmulwev_w_hu", + "lasx.xvmulwev.w.hu.h" => "__builtin_lasx_xvmulwev_w_hu_h", + "lasx.xvmulwod.d.w" => "__builtin_lasx_xvmulwod_d_w", + "lasx.xvmulwod.d.wu" => "__builtin_lasx_xvmulwod_d_wu", + "lasx.xvmulwod.d.wu.w" => "__builtin_lasx_xvmulwod_d_wu_w", + "lasx.xvmulwod.h.b" => "__builtin_lasx_xvmulwod_h_b", + "lasx.xvmulwod.h.bu" => "__builtin_lasx_xvmulwod_h_bu", + "lasx.xvmulwod.h.bu.b" => "__builtin_lasx_xvmulwod_h_bu_b", + "lasx.xvmulwod.q.d" => "__builtin_lasx_xvmulwod_q_d", + "lasx.xvmulwod.q.du" => "__builtin_lasx_xvmulwod_q_du", + "lasx.xvmulwod.q.du.d" => "__builtin_lasx_xvmulwod_q_du_d", + "lasx.xvmulwod.w.h" => "__builtin_lasx_xvmulwod_w_h", + "lasx.xvmulwod.w.hu" => "__builtin_lasx_xvmulwod_w_hu", + "lasx.xvmulwod.w.hu.h" => "__builtin_lasx_xvmulwod_w_hu_h", + "lasx.xvneg.b" => "__builtin_lasx_xvneg_b", + "lasx.xvneg.d" => "__builtin_lasx_xvneg_d", + "lasx.xvneg.h" => "__builtin_lasx_xvneg_h", + "lasx.xvneg.w" => "__builtin_lasx_xvneg_w", + "lasx.xvnor.v" => "__builtin_lasx_xvnor_v", + "lasx.xvnori.b" => "__builtin_lasx_xvnori_b", + "lasx.xvor.v" => "__builtin_lasx_xvor_v", + "lasx.xvori.b" => "__builtin_lasx_xvori_b", + "lasx.xvorn.v" => "__builtin_lasx_xvorn_v", + "lasx.xvpackev.b" => "__builtin_lasx_xvpackev_b", + "lasx.xvpackev.d" => "__builtin_lasx_xvpackev_d", + "lasx.xvpackev.h" => "__builtin_lasx_xvpackev_h", + "lasx.xvpackev.w" => "__builtin_lasx_xvpackev_w", + "lasx.xvpackod.b" => "__builtin_lasx_xvpackod_b", + "lasx.xvpackod.d" => "__builtin_lasx_xvpackod_d", + "lasx.xvpackod.h" => "__builtin_lasx_xvpackod_h", + "lasx.xvpackod.w" => "__builtin_lasx_xvpackod_w", + "lasx.xvpcnt.b" => "__builtin_lasx_xvpcnt_b", + "lasx.xvpcnt.d" => "__builtin_lasx_xvpcnt_d", + "lasx.xvpcnt.h" => "__builtin_lasx_xvpcnt_h", + "lasx.xvpcnt.w" => "__builtin_lasx_xvpcnt_w", + "lasx.xvperm.w" => "__builtin_lasx_xvperm_w", + "lasx.xvpermi.d" => "__builtin_lasx_xvpermi_d", + "lasx.xvpermi.q" => "__builtin_lasx_xvpermi_q", + "lasx.xvpermi.w" => "__builtin_lasx_xvpermi_w", + "lasx.xvpickev.b" => "__builtin_lasx_xvpickev_b", + "lasx.xvpickev.d" => "__builtin_lasx_xvpickev_d", + "lasx.xvpickev.h" => "__builtin_lasx_xvpickev_h", + "lasx.xvpickev.w" => "__builtin_lasx_xvpickev_w", + "lasx.xvpickod.b" => "__builtin_lasx_xvpickod_b", + "lasx.xvpickod.d" => "__builtin_lasx_xvpickod_d", + "lasx.xvpickod.h" => "__builtin_lasx_xvpickod_h", + "lasx.xvpickod.w" => "__builtin_lasx_xvpickod_w", + "lasx.xvpickve.d" => "__builtin_lasx_xvpickve_d", + "lasx.xvpickve.d.f" => "__builtin_lasx_xvpickve_d_f", + "lasx.xvpickve.w" => "__builtin_lasx_xvpickve_w", + "lasx.xvpickve.w.f" => "__builtin_lasx_xvpickve_w_f", + "lasx.xvpickve2gr.d" => "__builtin_lasx_xvpickve2gr_d", + "lasx.xvpickve2gr.du" => "__builtin_lasx_xvpickve2gr_du", + "lasx.xvpickve2gr.w" => "__builtin_lasx_xvpickve2gr_w", + "lasx.xvpickve2gr.wu" => "__builtin_lasx_xvpickve2gr_wu", + "lasx.xvrepl128vei.b" => "__builtin_lasx_xvrepl128vei_b", + "lasx.xvrepl128vei.d" => "__builtin_lasx_xvrepl128vei_d", + "lasx.xvrepl128vei.h" => "__builtin_lasx_xvrepl128vei_h", + "lasx.xvrepl128vei.w" => "__builtin_lasx_xvrepl128vei_w", + "lasx.xvreplgr2vr.b" => "__builtin_lasx_xvreplgr2vr_b", + "lasx.xvreplgr2vr.d" => "__builtin_lasx_xvreplgr2vr_d", + "lasx.xvreplgr2vr.h" => "__builtin_lasx_xvreplgr2vr_h", + "lasx.xvreplgr2vr.w" => "__builtin_lasx_xvreplgr2vr_w", + "lasx.xvrepli.b" => "__builtin_lasx_xvrepli_b", + "lasx.xvrepli.d" => "__builtin_lasx_xvrepli_d", + "lasx.xvrepli.h" => "__builtin_lasx_xvrepli_h", + "lasx.xvrepli.w" => "__builtin_lasx_xvrepli_w", + "lasx.xvreplve.b" => "__builtin_lasx_xvreplve_b", + "lasx.xvreplve.d" => "__builtin_lasx_xvreplve_d", + "lasx.xvreplve.h" => "__builtin_lasx_xvreplve_h", + "lasx.xvreplve.w" => "__builtin_lasx_xvreplve_w", + "lasx.xvreplve0.b" => "__builtin_lasx_xvreplve0_b", + "lasx.xvreplve0.d" => "__builtin_lasx_xvreplve0_d", + "lasx.xvreplve0.h" => "__builtin_lasx_xvreplve0_h", + "lasx.xvreplve0.q" => "__builtin_lasx_xvreplve0_q", + "lasx.xvreplve0.w" => "__builtin_lasx_xvreplve0_w", + "lasx.xvrotr.b" => "__builtin_lasx_xvrotr_b", + "lasx.xvrotr.d" => "__builtin_lasx_xvrotr_d", + "lasx.xvrotr.h" => "__builtin_lasx_xvrotr_h", + "lasx.xvrotr.w" => "__builtin_lasx_xvrotr_w", + "lasx.xvrotri.b" => "__builtin_lasx_xvrotri_b", + "lasx.xvrotri.d" => "__builtin_lasx_xvrotri_d", + "lasx.xvrotri.h" => "__builtin_lasx_xvrotri_h", + "lasx.xvrotri.w" => "__builtin_lasx_xvrotri_w", + "lasx.xvsadd.b" => "__builtin_lasx_xvsadd_b", + "lasx.xvsadd.bu" => "__builtin_lasx_xvsadd_bu", + "lasx.xvsadd.d" => "__builtin_lasx_xvsadd_d", + "lasx.xvsadd.du" => "__builtin_lasx_xvsadd_du", + "lasx.xvsadd.h" => "__builtin_lasx_xvsadd_h", + "lasx.xvsadd.hu" => "__builtin_lasx_xvsadd_hu", + "lasx.xvsadd.w" => "__builtin_lasx_xvsadd_w", + "lasx.xvsadd.wu" => "__builtin_lasx_xvsadd_wu", + "lasx.xvsat.b" => "__builtin_lasx_xvsat_b", + "lasx.xvsat.bu" => "__builtin_lasx_xvsat_bu", + "lasx.xvsat.d" => "__builtin_lasx_xvsat_d", + "lasx.xvsat.du" => "__builtin_lasx_xvsat_du", + "lasx.xvsat.h" => "__builtin_lasx_xvsat_h", + "lasx.xvsat.hu" => "__builtin_lasx_xvsat_hu", + "lasx.xvsat.w" => "__builtin_lasx_xvsat_w", + "lasx.xvsat.wu" => "__builtin_lasx_xvsat_wu", + "lasx.xvseq.b" => "__builtin_lasx_xvseq_b", + "lasx.xvseq.d" => "__builtin_lasx_xvseq_d", + "lasx.xvseq.h" => "__builtin_lasx_xvseq_h", + "lasx.xvseq.w" => "__builtin_lasx_xvseq_w", + "lasx.xvseqi.b" => "__builtin_lasx_xvseqi_b", + "lasx.xvseqi.d" => "__builtin_lasx_xvseqi_d", + "lasx.xvseqi.h" => "__builtin_lasx_xvseqi_h", + "lasx.xvseqi.w" => "__builtin_lasx_xvseqi_w", + "lasx.xvshuf.b" => "__builtin_lasx_xvshuf_b", + "lasx.xvshuf.d" => "__builtin_lasx_xvshuf_d", + "lasx.xvshuf.h" => "__builtin_lasx_xvshuf_h", + "lasx.xvshuf.w" => "__builtin_lasx_xvshuf_w", + "lasx.xvshuf4i.b" => "__builtin_lasx_xvshuf4i_b", + "lasx.xvshuf4i.d" => "__builtin_lasx_xvshuf4i_d", + "lasx.xvshuf4i.h" => "__builtin_lasx_xvshuf4i_h", + "lasx.xvshuf4i.w" => "__builtin_lasx_xvshuf4i_w", + "lasx.xvsigncov.b" => "__builtin_lasx_xvsigncov_b", + "lasx.xvsigncov.d" => "__builtin_lasx_xvsigncov_d", + "lasx.xvsigncov.h" => "__builtin_lasx_xvsigncov_h", + "lasx.xvsigncov.w" => "__builtin_lasx_xvsigncov_w", + "lasx.xvsle.b" => "__builtin_lasx_xvsle_b", + "lasx.xvsle.bu" => "__builtin_lasx_xvsle_bu", + "lasx.xvsle.d" => "__builtin_lasx_xvsle_d", + "lasx.xvsle.du" => "__builtin_lasx_xvsle_du", + "lasx.xvsle.h" => "__builtin_lasx_xvsle_h", + "lasx.xvsle.hu" => "__builtin_lasx_xvsle_hu", + "lasx.xvsle.w" => "__builtin_lasx_xvsle_w", + "lasx.xvsle.wu" => "__builtin_lasx_xvsle_wu", + "lasx.xvslei.b" => "__builtin_lasx_xvslei_b", + "lasx.xvslei.bu" => "__builtin_lasx_xvslei_bu", + "lasx.xvslei.d" => "__builtin_lasx_xvslei_d", + "lasx.xvslei.du" => "__builtin_lasx_xvslei_du", + "lasx.xvslei.h" => "__builtin_lasx_xvslei_h", + "lasx.xvslei.hu" => "__builtin_lasx_xvslei_hu", + "lasx.xvslei.w" => "__builtin_lasx_xvslei_w", + "lasx.xvslei.wu" => "__builtin_lasx_xvslei_wu", + "lasx.xvsll.b" => "__builtin_lasx_xvsll_b", + "lasx.xvsll.d" => "__builtin_lasx_xvsll_d", + "lasx.xvsll.h" => "__builtin_lasx_xvsll_h", + "lasx.xvsll.w" => "__builtin_lasx_xvsll_w", + "lasx.xvslli.b" => "__builtin_lasx_xvslli_b", + "lasx.xvslli.d" => "__builtin_lasx_xvslli_d", + "lasx.xvslli.h" => "__builtin_lasx_xvslli_h", + "lasx.xvslli.w" => "__builtin_lasx_xvslli_w", + "lasx.xvsllwil.d.w" => "__builtin_lasx_xvsllwil_d_w", + "lasx.xvsllwil.du.wu" => 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"lasx.xvslti.wu" => "__builtin_lasx_xvslti_wu", + "lasx.xvsra.b" => "__builtin_lasx_xvsra_b", + "lasx.xvsra.d" => "__builtin_lasx_xvsra_d", + "lasx.xvsra.h" => "__builtin_lasx_xvsra_h", + "lasx.xvsra.w" => "__builtin_lasx_xvsra_w", + "lasx.xvsrai.b" => "__builtin_lasx_xvsrai_b", + "lasx.xvsrai.d" => "__builtin_lasx_xvsrai_d", + "lasx.xvsrai.h" => "__builtin_lasx_xvsrai_h", + "lasx.xvsrai.w" => "__builtin_lasx_xvsrai_w", + "lasx.xvsran.b.h" => "__builtin_lasx_xvsran_b_h", + "lasx.xvsran.h.w" => "__builtin_lasx_xvsran_h_w", + "lasx.xvsran.w.d" => "__builtin_lasx_xvsran_w_d", + "lasx.xvsrani.b.h" => "__builtin_lasx_xvsrani_b_h", + "lasx.xvsrani.d.q" => "__builtin_lasx_xvsrani_d_q", + "lasx.xvsrani.h.w" => "__builtin_lasx_xvsrani_h_w", + "lasx.xvsrani.w.d" => "__builtin_lasx_xvsrani_w_d", + "lasx.xvsrar.b" => "__builtin_lasx_xvsrar_b", + "lasx.xvsrar.d" => "__builtin_lasx_xvsrar_d", + "lasx.xvsrar.h" => "__builtin_lasx_xvsrar_h", + "lasx.xvsrar.w" => "__builtin_lasx_xvsrar_w", + "lasx.xvsrari.b" => "__builtin_lasx_xvsrari_b", + "lasx.xvsrari.d" => "__builtin_lasx_xvsrari_d", + "lasx.xvsrari.h" => "__builtin_lasx_xvsrari_h", + "lasx.xvsrari.w" => "__builtin_lasx_xvsrari_w", + "lasx.xvsrarn.b.h" => "__builtin_lasx_xvsrarn_b_h", + "lasx.xvsrarn.h.w" => "__builtin_lasx_xvsrarn_h_w", + "lasx.xvsrarn.w.d" => "__builtin_lasx_xvsrarn_w_d", + "lasx.xvsrarni.b.h" => "__builtin_lasx_xvsrarni_b_h", + "lasx.xvsrarni.d.q" => "__builtin_lasx_xvsrarni_d_q", + "lasx.xvsrarni.h.w" => "__builtin_lasx_xvsrarni_h_w", + "lasx.xvsrarni.w.d" => "__builtin_lasx_xvsrarni_w_d", + "lasx.xvsrl.b" => "__builtin_lasx_xvsrl_b", + "lasx.xvsrl.d" => "__builtin_lasx_xvsrl_d", + "lasx.xvsrl.h" => "__builtin_lasx_xvsrl_h", + "lasx.xvsrl.w" => "__builtin_lasx_xvsrl_w", + "lasx.xvsrli.b" => "__builtin_lasx_xvsrli_b", + "lasx.xvsrli.d" => "__builtin_lasx_xvsrli_d", + "lasx.xvsrli.h" => "__builtin_lasx_xvsrli_h", + "lasx.xvsrli.w" => "__builtin_lasx_xvsrli_w", + "lasx.xvsrln.b.h" => "__builtin_lasx_xvsrln_b_h", + "lasx.xvsrln.h.w" => "__builtin_lasx_xvsrln_h_w", + "lasx.xvsrln.w.d" => "__builtin_lasx_xvsrln_w_d", + "lasx.xvsrlni.b.h" => "__builtin_lasx_xvsrlni_b_h", + "lasx.xvsrlni.d.q" => "__builtin_lasx_xvsrlni_d_q", + "lasx.xvsrlni.h.w" => "__builtin_lasx_xvsrlni_h_w", + "lasx.xvsrlni.w.d" => "__builtin_lasx_xvsrlni_w_d", + "lasx.xvsrlr.b" => "__builtin_lasx_xvsrlr_b", + "lasx.xvsrlr.d" => "__builtin_lasx_xvsrlr_d", + "lasx.xvsrlr.h" => "__builtin_lasx_xvsrlr_h", + "lasx.xvsrlr.w" => "__builtin_lasx_xvsrlr_w", + "lasx.xvsrlri.b" => "__builtin_lasx_xvsrlri_b", + "lasx.xvsrlri.d" => "__builtin_lasx_xvsrlri_d", + "lasx.xvsrlri.h" => "__builtin_lasx_xvsrlri_h", + "lasx.xvsrlri.w" => "__builtin_lasx_xvsrlri_w", + "lasx.xvsrlrn.b.h" => "__builtin_lasx_xvsrlrn_b_h", + "lasx.xvsrlrn.h.w" => "__builtin_lasx_xvsrlrn_h_w", + "lasx.xvsrlrn.w.d" => "__builtin_lasx_xvsrlrn_w_d", + "lasx.xvsrlrni.b.h" => "__builtin_lasx_xvsrlrni_b_h", + "lasx.xvsrlrni.d.q" => "__builtin_lasx_xvsrlrni_d_q", + "lasx.xvsrlrni.h.w" => "__builtin_lasx_xvsrlrni_h_w", + "lasx.xvsrlrni.w.d" => "__builtin_lasx_xvsrlrni_w_d", + "lasx.xvssran.b.h" => "__builtin_lasx_xvssran_b_h", + "lasx.xvssran.bu.h" => "__builtin_lasx_xvssran_bu_h", + "lasx.xvssran.h.w" => "__builtin_lasx_xvssran_h_w", + "lasx.xvssran.hu.w" => "__builtin_lasx_xvssran_hu_w", + "lasx.xvssran.w.d" => "__builtin_lasx_xvssran_w_d", + "lasx.xvssran.wu.d" => "__builtin_lasx_xvssran_wu_d", + "lasx.xvssrani.b.h" => "__builtin_lasx_xvssrani_b_h", + "lasx.xvssrani.bu.h" => "__builtin_lasx_xvssrani_bu_h", + "lasx.xvssrani.d.q" => "__builtin_lasx_xvssrani_d_q", + "lasx.xvssrani.du.q" => "__builtin_lasx_xvssrani_du_q", + "lasx.xvssrani.h.w" => "__builtin_lasx_xvssrani_h_w", + "lasx.xvssrani.hu.w" => "__builtin_lasx_xvssrani_hu_w", + "lasx.xvssrani.w.d" => "__builtin_lasx_xvssrani_w_d", + "lasx.xvssrani.wu.d" => "__builtin_lasx_xvssrani_wu_d", + "lasx.xvssrarn.b.h" => "__builtin_lasx_xvssrarn_b_h", + "lasx.xvssrarn.bu.h" => "__builtin_lasx_xvssrarn_bu_h", + "lasx.xvssrarn.h.w" => "__builtin_lasx_xvssrarn_h_w", + "lasx.xvssrarn.hu.w" => "__builtin_lasx_xvssrarn_hu_w", + "lasx.xvssrarn.w.d" => "__builtin_lasx_xvssrarn_w_d", + "lasx.xvssrarn.wu.d" => "__builtin_lasx_xvssrarn_wu_d", + "lasx.xvssrarni.b.h" => "__builtin_lasx_xvssrarni_b_h", + "lasx.xvssrarni.bu.h" => "__builtin_lasx_xvssrarni_bu_h", + "lasx.xvssrarni.d.q" => "__builtin_lasx_xvssrarni_d_q", + "lasx.xvssrarni.du.q" => "__builtin_lasx_xvssrarni_du_q", + "lasx.xvssrarni.h.w" => "__builtin_lasx_xvssrarni_h_w", + "lasx.xvssrarni.hu.w" => "__builtin_lasx_xvssrarni_hu_w", + "lasx.xvssrarni.w.d" => "__builtin_lasx_xvssrarni_w_d", + "lasx.xvssrarni.wu.d" => "__builtin_lasx_xvssrarni_wu_d", + "lasx.xvssrln.b.h" => "__builtin_lasx_xvssrln_b_h", + "lasx.xvssrln.bu.h" => "__builtin_lasx_xvssrln_bu_h", + "lasx.xvssrln.h.w" => "__builtin_lasx_xvssrln_h_w", + "lasx.xvssrln.hu.w" => "__builtin_lasx_xvssrln_hu_w", + "lasx.xvssrln.w.d" => "__builtin_lasx_xvssrln_w_d", + "lasx.xvssrln.wu.d" => "__builtin_lasx_xvssrln_wu_d", + "lasx.xvssrlni.b.h" => "__builtin_lasx_xvssrlni_b_h", + "lasx.xvssrlni.bu.h" => "__builtin_lasx_xvssrlni_bu_h", + "lasx.xvssrlni.d.q" => "__builtin_lasx_xvssrlni_d_q", + "lasx.xvssrlni.du.q" => "__builtin_lasx_xvssrlni_du_q", + "lasx.xvssrlni.h.w" => "__builtin_lasx_xvssrlni_h_w", + "lasx.xvssrlni.hu.w" => "__builtin_lasx_xvssrlni_hu_w", + "lasx.xvssrlni.w.d" => "__builtin_lasx_xvssrlni_w_d", + "lasx.xvssrlni.wu.d" => "__builtin_lasx_xvssrlni_wu_d", + "lasx.xvssrlrn.b.h" => "__builtin_lasx_xvssrlrn_b_h", + "lasx.xvssrlrn.bu.h" => "__builtin_lasx_xvssrlrn_bu_h", + "lasx.xvssrlrn.h.w" => "__builtin_lasx_xvssrlrn_h_w", + "lasx.xvssrlrn.hu.w" => "__builtin_lasx_xvssrlrn_hu_w", + "lasx.xvssrlrn.w.d" => "__builtin_lasx_xvssrlrn_w_d", + "lasx.xvssrlrn.wu.d" => "__builtin_lasx_xvssrlrn_wu_d", + "lasx.xvssrlrni.b.h" => "__builtin_lasx_xvssrlrni_b_h", + "lasx.xvssrlrni.bu.h" => "__builtin_lasx_xvssrlrni_bu_h", + "lasx.xvssrlrni.d.q" => "__builtin_lasx_xvssrlrni_d_q", + "lasx.xvssrlrni.du.q" => "__builtin_lasx_xvssrlrni_du_q", + "lasx.xvssrlrni.h.w" => "__builtin_lasx_xvssrlrni_h_w", + "lasx.xvssrlrni.hu.w" => "__builtin_lasx_xvssrlrni_hu_w", + "lasx.xvssrlrni.w.d" => "__builtin_lasx_xvssrlrni_w_d", + "lasx.xvssrlrni.wu.d" => "__builtin_lasx_xvssrlrni_wu_d", + "lasx.xvssub.b" => "__builtin_lasx_xvssub_b", + "lasx.xvssub.bu" => "__builtin_lasx_xvssub_bu", + "lasx.xvssub.d" => "__builtin_lasx_xvssub_d", + "lasx.xvssub.du" => "__builtin_lasx_xvssub_du", + "lasx.xvssub.h" => "__builtin_lasx_xvssub_h", + "lasx.xvssub.hu" => "__builtin_lasx_xvssub_hu", + "lasx.xvssub.w" => "__builtin_lasx_xvssub_w", + "lasx.xvssub.wu" => "__builtin_lasx_xvssub_wu", + "lasx.xvst" => "__builtin_lasx_xvst", + "lasx.xvstelm.b" => "__builtin_lasx_xvstelm_b", + "lasx.xvstelm.d" => "__builtin_lasx_xvstelm_d", + "lasx.xvstelm.h" => "__builtin_lasx_xvstelm_h", + "lasx.xvstelm.w" => "__builtin_lasx_xvstelm_w", + "lasx.xvstx" => "__builtin_lasx_xvstx", + "lasx.xvsub.b" => "__builtin_lasx_xvsub_b", + "lasx.xvsub.d" => "__builtin_lasx_xvsub_d", + "lasx.xvsub.h" => "__builtin_lasx_xvsub_h", + "lasx.xvsub.q" => "__builtin_lasx_xvsub_q", + "lasx.xvsub.w" => "__builtin_lasx_xvsub_w", + "lasx.xvsubi.bu" => "__builtin_lasx_xvsubi_bu", + "lasx.xvsubi.du" => "__builtin_lasx_xvsubi_du", + "lasx.xvsubi.hu" => "__builtin_lasx_xvsubi_hu", + "lasx.xvsubi.wu" => "__builtin_lasx_xvsubi_wu", + "lasx.xvsubwev.d.w" => "__builtin_lasx_xvsubwev_d_w", + "lasx.xvsubwev.d.wu" => "__builtin_lasx_xvsubwev_d_wu", + "lasx.xvsubwev.h.b" => "__builtin_lasx_xvsubwev_h_b", + "lasx.xvsubwev.h.bu" => "__builtin_lasx_xvsubwev_h_bu", + "lasx.xvsubwev.q.d" => "__builtin_lasx_xvsubwev_q_d", + "lasx.xvsubwev.q.du" => "__builtin_lasx_xvsubwev_q_du", + "lasx.xvsubwev.w.h" => "__builtin_lasx_xvsubwev_w_h", + "lasx.xvsubwev.w.hu" => "__builtin_lasx_xvsubwev_w_hu", + "lasx.xvsubwod.d.w" => "__builtin_lasx_xvsubwod_d_w", + "lasx.xvsubwod.d.wu" => "__builtin_lasx_xvsubwod_d_wu", + "lasx.xvsubwod.h.b" => "__builtin_lasx_xvsubwod_h_b", + "lasx.xvsubwod.h.bu" => "__builtin_lasx_xvsubwod_h_bu", + "lasx.xvsubwod.q.d" => "__builtin_lasx_xvsubwod_q_d", + "lasx.xvsubwod.q.du" => "__builtin_lasx_xvsubwod_q_du", + "lasx.xvsubwod.w.h" => "__builtin_lasx_xvsubwod_w_h", + "lasx.xvsubwod.w.hu" => "__builtin_lasx_xvsubwod_w_hu", + "lasx.xvxor.v" => "__builtin_lasx_xvxor_v", + "lasx.xvxori.b" => "__builtin_lasx_xvxori_b", + "lddir.d" => "__builtin_loongarch_lddir_d", + "ldpte.d" => "__builtin_loongarch_ldpte_d", + "lsx.bnz.b" => "__builtin_lsx_bnz_b", + "lsx.bnz.d" => "__builtin_lsx_bnz_d", + "lsx.bnz.h" => "__builtin_lsx_bnz_h", + "lsx.bnz.v" => "__builtin_lsx_bnz_v", + "lsx.bnz.w" => "__builtin_lsx_bnz_w", + "lsx.bz.b" => "__builtin_lsx_bz_b", + "lsx.bz.d" => "__builtin_lsx_bz_d", + "lsx.bz.h" => "__builtin_lsx_bz_h", + "lsx.bz.v" => "__builtin_lsx_bz_v", + "lsx.bz.w" => "__builtin_lsx_bz_w", + "lsx.vabsd.b" => "__builtin_lsx_vabsd_b", + "lsx.vabsd.bu" => "__builtin_lsx_vabsd_bu", + "lsx.vabsd.d" => "__builtin_lsx_vabsd_d", + "lsx.vabsd.du" => "__builtin_lsx_vabsd_du", + "lsx.vabsd.h" => "__builtin_lsx_vabsd_h", + "lsx.vabsd.hu" => "__builtin_lsx_vabsd_hu", + "lsx.vabsd.w" => "__builtin_lsx_vabsd_w", + "lsx.vabsd.wu" => "__builtin_lsx_vabsd_wu", + "lsx.vadd.b" => "__builtin_lsx_vadd_b", + "lsx.vadd.d" => "__builtin_lsx_vadd_d", + "lsx.vadd.h" => "__builtin_lsx_vadd_h", + "lsx.vadd.q" => "__builtin_lsx_vadd_q", + "lsx.vadd.w" => "__builtin_lsx_vadd_w", + "lsx.vadda.b" => "__builtin_lsx_vadda_b", + "lsx.vadda.d" => "__builtin_lsx_vadda_d", + "lsx.vadda.h" => "__builtin_lsx_vadda_h", + "lsx.vadda.w" => "__builtin_lsx_vadda_w", + "lsx.vaddi.bu" => "__builtin_lsx_vaddi_bu", + "lsx.vaddi.du" => "__builtin_lsx_vaddi_du", + "lsx.vaddi.hu" => "__builtin_lsx_vaddi_hu", + "lsx.vaddi.wu" => "__builtin_lsx_vaddi_wu", + "lsx.vaddwev.d.w" => "__builtin_lsx_vaddwev_d_w", + "lsx.vaddwev.d.wu" => "__builtin_lsx_vaddwev_d_wu", + "lsx.vaddwev.d.wu.w" => "__builtin_lsx_vaddwev_d_wu_w", + "lsx.vaddwev.h.b" => "__builtin_lsx_vaddwev_h_b", + "lsx.vaddwev.h.bu" => "__builtin_lsx_vaddwev_h_bu", + "lsx.vaddwev.h.bu.b" => "__builtin_lsx_vaddwev_h_bu_b", + "lsx.vaddwev.q.d" => "__builtin_lsx_vaddwev_q_d", + "lsx.vaddwev.q.du" => "__builtin_lsx_vaddwev_q_du", + "lsx.vaddwev.q.du.d" => "__builtin_lsx_vaddwev_q_du_d", + "lsx.vaddwev.w.h" => "__builtin_lsx_vaddwev_w_h", + "lsx.vaddwev.w.hu" => "__builtin_lsx_vaddwev_w_hu", + "lsx.vaddwev.w.hu.h" => "__builtin_lsx_vaddwev_w_hu_h", + "lsx.vaddwod.d.w" => "__builtin_lsx_vaddwod_d_w", + "lsx.vaddwod.d.wu" => "__builtin_lsx_vaddwod_d_wu", + "lsx.vaddwod.d.wu.w" => "__builtin_lsx_vaddwod_d_wu_w", + "lsx.vaddwod.h.b" => "__builtin_lsx_vaddwod_h_b", + "lsx.vaddwod.h.bu" => "__builtin_lsx_vaddwod_h_bu", + "lsx.vaddwod.h.bu.b" => "__builtin_lsx_vaddwod_h_bu_b", + "lsx.vaddwod.q.d" => "__builtin_lsx_vaddwod_q_d", + "lsx.vaddwod.q.du" => "__builtin_lsx_vaddwod_q_du", + "lsx.vaddwod.q.du.d" => "__builtin_lsx_vaddwod_q_du_d", + "lsx.vaddwod.w.h" => "__builtin_lsx_vaddwod_w_h", + "lsx.vaddwod.w.hu" => "__builtin_lsx_vaddwod_w_hu", + "lsx.vaddwod.w.hu.h" => "__builtin_lsx_vaddwod_w_hu_h", + "lsx.vand.v" => "__builtin_lsx_vand_v", + "lsx.vandi.b" => "__builtin_lsx_vandi_b", + "lsx.vandn.v" => "__builtin_lsx_vandn_v", + "lsx.vavg.b" => "__builtin_lsx_vavg_b", + "lsx.vavg.bu" => "__builtin_lsx_vavg_bu", + "lsx.vavg.d" => "__builtin_lsx_vavg_d", + "lsx.vavg.du" => "__builtin_lsx_vavg_du", + "lsx.vavg.h" => "__builtin_lsx_vavg_h", + "lsx.vavg.hu" => "__builtin_lsx_vavg_hu", + "lsx.vavg.w" => "__builtin_lsx_vavg_w", + "lsx.vavg.wu" => "__builtin_lsx_vavg_wu", + "lsx.vavgr.b" => "__builtin_lsx_vavgr_b", + "lsx.vavgr.bu" => "__builtin_lsx_vavgr_bu", + "lsx.vavgr.d" => "__builtin_lsx_vavgr_d", + "lsx.vavgr.du" => "__builtin_lsx_vavgr_du", + "lsx.vavgr.h" => "__builtin_lsx_vavgr_h", + "lsx.vavgr.hu" => "__builtin_lsx_vavgr_hu", + "lsx.vavgr.w" => "__builtin_lsx_vavgr_w", + "lsx.vavgr.wu" => "__builtin_lsx_vavgr_wu", + "lsx.vbitclr.b" => "__builtin_lsx_vbitclr_b", + "lsx.vbitclr.d" => "__builtin_lsx_vbitclr_d", + "lsx.vbitclr.h" => "__builtin_lsx_vbitclr_h", + "lsx.vbitclr.w" => "__builtin_lsx_vbitclr_w", + "lsx.vbitclri.b" => "__builtin_lsx_vbitclri_b", + "lsx.vbitclri.d" => "__builtin_lsx_vbitclri_d", + "lsx.vbitclri.h" => "__builtin_lsx_vbitclri_h", + "lsx.vbitclri.w" => "__builtin_lsx_vbitclri_w", + "lsx.vbitrev.b" => "__builtin_lsx_vbitrev_b", + "lsx.vbitrev.d" => "__builtin_lsx_vbitrev_d", + "lsx.vbitrev.h" => "__builtin_lsx_vbitrev_h", + "lsx.vbitrev.w" => "__builtin_lsx_vbitrev_w", + "lsx.vbitrevi.b" => "__builtin_lsx_vbitrevi_b", + "lsx.vbitrevi.d" => "__builtin_lsx_vbitrevi_d", + "lsx.vbitrevi.h" => "__builtin_lsx_vbitrevi_h", + "lsx.vbitrevi.w" => "__builtin_lsx_vbitrevi_w", + "lsx.vbitsel.v" => "__builtin_lsx_vbitsel_v", + "lsx.vbitseli.b" => "__builtin_lsx_vbitseli_b", + "lsx.vbitset.b" => "__builtin_lsx_vbitset_b", + "lsx.vbitset.d" => "__builtin_lsx_vbitset_d", + "lsx.vbitset.h" => "__builtin_lsx_vbitset_h", + "lsx.vbitset.w" => "__builtin_lsx_vbitset_w", + "lsx.vbitseti.b" => "__builtin_lsx_vbitseti_b", + "lsx.vbitseti.d" => "__builtin_lsx_vbitseti_d", + "lsx.vbitseti.h" => "__builtin_lsx_vbitseti_h", + "lsx.vbitseti.w" => "__builtin_lsx_vbitseti_w", + "lsx.vbsll.v" => "__builtin_lsx_vbsll_v", + "lsx.vbsrl.v" => "__builtin_lsx_vbsrl_v", + "lsx.vclo.b" => "__builtin_lsx_vclo_b", + "lsx.vclo.d" => "__builtin_lsx_vclo_d", + "lsx.vclo.h" => "__builtin_lsx_vclo_h", + "lsx.vclo.w" => "__builtin_lsx_vclo_w", + "lsx.vclz.b" => "__builtin_lsx_vclz_b", + "lsx.vclz.d" => "__builtin_lsx_vclz_d", + "lsx.vclz.h" => "__builtin_lsx_vclz_h", + "lsx.vclz.w" => "__builtin_lsx_vclz_w", + "lsx.vdiv.b" => "__builtin_lsx_vdiv_b", + "lsx.vdiv.bu" => "__builtin_lsx_vdiv_bu", + "lsx.vdiv.d" => "__builtin_lsx_vdiv_d", + "lsx.vdiv.du" => "__builtin_lsx_vdiv_du", + "lsx.vdiv.h" => "__builtin_lsx_vdiv_h", + "lsx.vdiv.hu" => "__builtin_lsx_vdiv_hu", + "lsx.vdiv.w" => "__builtin_lsx_vdiv_w", + "lsx.vdiv.wu" => "__builtin_lsx_vdiv_wu", + "lsx.vexth.d.w" => "__builtin_lsx_vexth_d_w", + "lsx.vexth.du.wu" => "__builtin_lsx_vexth_du_wu", + "lsx.vexth.h.b" => "__builtin_lsx_vexth_h_b", + "lsx.vexth.hu.bu" => "__builtin_lsx_vexth_hu_bu", + "lsx.vexth.q.d" => "__builtin_lsx_vexth_q_d", + "lsx.vexth.qu.du" => "__builtin_lsx_vexth_qu_du", + "lsx.vexth.w.h" => "__builtin_lsx_vexth_w_h", + "lsx.vexth.wu.hu" => "__builtin_lsx_vexth_wu_hu", + "lsx.vextl.q.d" => "__builtin_lsx_vextl_q_d", + "lsx.vextl.qu.du" => "__builtin_lsx_vextl_qu_du", + "lsx.vextrins.b" => "__builtin_lsx_vextrins_b", + "lsx.vextrins.d" => "__builtin_lsx_vextrins_d", + "lsx.vextrins.h" => "__builtin_lsx_vextrins_h", + "lsx.vextrins.w" => "__builtin_lsx_vextrins_w", + "lsx.vfadd.d" => "__builtin_lsx_vfadd_d", + "lsx.vfadd.s" => "__builtin_lsx_vfadd_s", + "lsx.vfclass.d" => "__builtin_lsx_vfclass_d", + "lsx.vfclass.s" => "__builtin_lsx_vfclass_s", + "lsx.vfcmp.caf.d" => "__builtin_lsx_vfcmp_caf_d", + "lsx.vfcmp.caf.s" => "__builtin_lsx_vfcmp_caf_s", + "lsx.vfcmp.ceq.d" => "__builtin_lsx_vfcmp_ceq_d", + "lsx.vfcmp.ceq.s" => "__builtin_lsx_vfcmp_ceq_s", + "lsx.vfcmp.cle.d" => "__builtin_lsx_vfcmp_cle_d", + "lsx.vfcmp.cle.s" => "__builtin_lsx_vfcmp_cle_s", + "lsx.vfcmp.clt.d" => "__builtin_lsx_vfcmp_clt_d", + "lsx.vfcmp.clt.s" => "__builtin_lsx_vfcmp_clt_s", + "lsx.vfcmp.cne.d" => "__builtin_lsx_vfcmp_cne_d", + "lsx.vfcmp.cne.s" => "__builtin_lsx_vfcmp_cne_s", + "lsx.vfcmp.cor.d" => "__builtin_lsx_vfcmp_cor_d", + "lsx.vfcmp.cor.s" => "__builtin_lsx_vfcmp_cor_s", + "lsx.vfcmp.cueq.d" => "__builtin_lsx_vfcmp_cueq_d", + "lsx.vfcmp.cueq.s" => "__builtin_lsx_vfcmp_cueq_s", + "lsx.vfcmp.cule.d" => "__builtin_lsx_vfcmp_cule_d", + "lsx.vfcmp.cule.s" => "__builtin_lsx_vfcmp_cule_s", + "lsx.vfcmp.cult.d" => "__builtin_lsx_vfcmp_cult_d", + "lsx.vfcmp.cult.s" => "__builtin_lsx_vfcmp_cult_s", + "lsx.vfcmp.cun.d" => "__builtin_lsx_vfcmp_cun_d", + "lsx.vfcmp.cun.s" => "__builtin_lsx_vfcmp_cun_s", + "lsx.vfcmp.cune.d" => "__builtin_lsx_vfcmp_cune_d", + "lsx.vfcmp.cune.s" => "__builtin_lsx_vfcmp_cune_s", + "lsx.vfcmp.saf.d" => "__builtin_lsx_vfcmp_saf_d", + "lsx.vfcmp.saf.s" => "__builtin_lsx_vfcmp_saf_s", + "lsx.vfcmp.seq.d" => "__builtin_lsx_vfcmp_seq_d", + "lsx.vfcmp.seq.s" => "__builtin_lsx_vfcmp_seq_s", + "lsx.vfcmp.sle.d" => "__builtin_lsx_vfcmp_sle_d", + "lsx.vfcmp.sle.s" => "__builtin_lsx_vfcmp_sle_s", + "lsx.vfcmp.slt.d" => "__builtin_lsx_vfcmp_slt_d", + "lsx.vfcmp.slt.s" => "__builtin_lsx_vfcmp_slt_s", + "lsx.vfcmp.sne.d" => "__builtin_lsx_vfcmp_sne_d", + "lsx.vfcmp.sne.s" => "__builtin_lsx_vfcmp_sne_s", + "lsx.vfcmp.sor.d" => "__builtin_lsx_vfcmp_sor_d", + "lsx.vfcmp.sor.s" => "__builtin_lsx_vfcmp_sor_s", + "lsx.vfcmp.sueq.d" => "__builtin_lsx_vfcmp_sueq_d", + "lsx.vfcmp.sueq.s" => "__builtin_lsx_vfcmp_sueq_s", + "lsx.vfcmp.sule.d" => "__builtin_lsx_vfcmp_sule_d", + "lsx.vfcmp.sule.s" => "__builtin_lsx_vfcmp_sule_s", + "lsx.vfcmp.sult.d" => "__builtin_lsx_vfcmp_sult_d", + "lsx.vfcmp.sult.s" => "__builtin_lsx_vfcmp_sult_s", + "lsx.vfcmp.sun.d" => "__builtin_lsx_vfcmp_sun_d", + "lsx.vfcmp.sun.s" => "__builtin_lsx_vfcmp_sun_s", + "lsx.vfcmp.sune.d" => "__builtin_lsx_vfcmp_sune_d", + "lsx.vfcmp.sune.s" => "__builtin_lsx_vfcmp_sune_s", + "lsx.vfcvt.h.s" => "__builtin_lsx_vfcvt_h_s", + "lsx.vfcvt.s.d" => "__builtin_lsx_vfcvt_s_d", + "lsx.vfcvth.d.s" => "__builtin_lsx_vfcvth_d_s", + "lsx.vfcvth.s.h" => "__builtin_lsx_vfcvth_s_h", + "lsx.vfcvtl.d.s" => "__builtin_lsx_vfcvtl_d_s", + "lsx.vfcvtl.s.h" => "__builtin_lsx_vfcvtl_s_h", + "lsx.vfdiv.d" => "__builtin_lsx_vfdiv_d", + "lsx.vfdiv.s" => "__builtin_lsx_vfdiv_s", + "lsx.vffint.d.l" => "__builtin_lsx_vffint_d_l", + "lsx.vffint.d.lu" => "__builtin_lsx_vffint_d_lu", + "lsx.vffint.s.l" => "__builtin_lsx_vffint_s_l", + "lsx.vffint.s.w" => "__builtin_lsx_vffint_s_w", + "lsx.vffint.s.wu" => "__builtin_lsx_vffint_s_wu", + "lsx.vffinth.d.w" => "__builtin_lsx_vffinth_d_w", + "lsx.vffintl.d.w" => "__builtin_lsx_vffintl_d_w", + "lsx.vflogb.d" => "__builtin_lsx_vflogb_d", + "lsx.vflogb.s" => "__builtin_lsx_vflogb_s", + "lsx.vfmadd.d" => "__builtin_lsx_vfmadd_d", + "lsx.vfmadd.s" => "__builtin_lsx_vfmadd_s", + "lsx.vfmax.d" => "__builtin_lsx_vfmax_d", + "lsx.vfmax.s" => "__builtin_lsx_vfmax_s", + "lsx.vfmaxa.d" => "__builtin_lsx_vfmaxa_d", + "lsx.vfmaxa.s" => "__builtin_lsx_vfmaxa_s", + "lsx.vfmin.d" => "__builtin_lsx_vfmin_d", + "lsx.vfmin.s" => "__builtin_lsx_vfmin_s", + "lsx.vfmina.d" => "__builtin_lsx_vfmina_d", + "lsx.vfmina.s" => "__builtin_lsx_vfmina_s", + "lsx.vfmsub.d" => "__builtin_lsx_vfmsub_d", + "lsx.vfmsub.s" => "__builtin_lsx_vfmsub_s", + "lsx.vfmul.d" => "__builtin_lsx_vfmul_d", + "lsx.vfmul.s" => "__builtin_lsx_vfmul_s", + "lsx.vfnmadd.d" => "__builtin_lsx_vfnmadd_d", + "lsx.vfnmadd.s" => "__builtin_lsx_vfnmadd_s", + "lsx.vfnmsub.d" => "__builtin_lsx_vfnmsub_d", + "lsx.vfnmsub.s" => "__builtin_lsx_vfnmsub_s", + "lsx.vfrecip.d" => "__builtin_lsx_vfrecip_d", + "lsx.vfrecip.s" => "__builtin_lsx_vfrecip_s", + "lsx.vfrecipe.d" => "__builtin_lsx_vfrecipe_d", + "lsx.vfrecipe.s" => "__builtin_lsx_vfrecipe_s", + "lsx.vfrint.d" => "__builtin_lsx_vfrint_d", + "lsx.vfrint.s" => "__builtin_lsx_vfrint_s", + "lsx.vfrintrm.d" => "__builtin_lsx_vfrintrm_d", + "lsx.vfrintrm.s" => "__builtin_lsx_vfrintrm_s", + "lsx.vfrintrne.d" => "__builtin_lsx_vfrintrne_d", + "lsx.vfrintrne.s" => "__builtin_lsx_vfrintrne_s", + "lsx.vfrintrp.d" => "__builtin_lsx_vfrintrp_d", + "lsx.vfrintrp.s" => "__builtin_lsx_vfrintrp_s", + "lsx.vfrintrz.d" => "__builtin_lsx_vfrintrz_d", + "lsx.vfrintrz.s" => "__builtin_lsx_vfrintrz_s", + "lsx.vfrsqrt.d" => "__builtin_lsx_vfrsqrt_d", + "lsx.vfrsqrt.s" => "__builtin_lsx_vfrsqrt_s", + "lsx.vfrsqrte.d" => "__builtin_lsx_vfrsqrte_d", + "lsx.vfrsqrte.s" => "__builtin_lsx_vfrsqrte_s", + "lsx.vfrstp.b" => "__builtin_lsx_vfrstp_b", + "lsx.vfrstp.h" => "__builtin_lsx_vfrstp_h", + "lsx.vfrstpi.b" => "__builtin_lsx_vfrstpi_b", + "lsx.vfrstpi.h" => "__builtin_lsx_vfrstpi_h", + "lsx.vfsqrt.d" => "__builtin_lsx_vfsqrt_d", + "lsx.vfsqrt.s" => "__builtin_lsx_vfsqrt_s", + "lsx.vfsub.d" => "__builtin_lsx_vfsub_d", + "lsx.vfsub.s" => "__builtin_lsx_vfsub_s", + "lsx.vftint.l.d" => "__builtin_lsx_vftint_l_d", + "lsx.vftint.lu.d" => "__builtin_lsx_vftint_lu_d", + "lsx.vftint.w.d" => "__builtin_lsx_vftint_w_d", + "lsx.vftint.w.s" => "__builtin_lsx_vftint_w_s", + "lsx.vftint.wu.s" => "__builtin_lsx_vftint_wu_s", + "lsx.vftinth.l.s" => "__builtin_lsx_vftinth_l_s", + "lsx.vftintl.l.s" => "__builtin_lsx_vftintl_l_s", + "lsx.vftintrm.l.d" => "__builtin_lsx_vftintrm_l_d", + "lsx.vftintrm.w.d" => "__builtin_lsx_vftintrm_w_d", + "lsx.vftintrm.w.s" => "__builtin_lsx_vftintrm_w_s", + "lsx.vftintrmh.l.s" => "__builtin_lsx_vftintrmh_l_s", + "lsx.vftintrml.l.s" => "__builtin_lsx_vftintrml_l_s", + "lsx.vftintrne.l.d" => "__builtin_lsx_vftintrne_l_d", + "lsx.vftintrne.w.d" => "__builtin_lsx_vftintrne_w_d", + "lsx.vftintrne.w.s" => "__builtin_lsx_vftintrne_w_s", + "lsx.vftintrneh.l.s" => "__builtin_lsx_vftintrneh_l_s", + "lsx.vftintrnel.l.s" => "__builtin_lsx_vftintrnel_l_s", + "lsx.vftintrp.l.d" => "__builtin_lsx_vftintrp_l_d", + "lsx.vftintrp.w.d" => "__builtin_lsx_vftintrp_w_d", + "lsx.vftintrp.w.s" => "__builtin_lsx_vftintrp_w_s", + "lsx.vftintrph.l.s" => "__builtin_lsx_vftintrph_l_s", + "lsx.vftintrpl.l.s" => "__builtin_lsx_vftintrpl_l_s", + "lsx.vftintrz.l.d" => "__builtin_lsx_vftintrz_l_d", + "lsx.vftintrz.lu.d" => "__builtin_lsx_vftintrz_lu_d", + "lsx.vftintrz.w.d" => "__builtin_lsx_vftintrz_w_d", + "lsx.vftintrz.w.s" => "__builtin_lsx_vftintrz_w_s", + "lsx.vftintrz.wu.s" => "__builtin_lsx_vftintrz_wu_s", + "lsx.vftintrzh.l.s" => "__builtin_lsx_vftintrzh_l_s", + "lsx.vftintrzl.l.s" => "__builtin_lsx_vftintrzl_l_s", + "lsx.vhaddw.d.w" => "__builtin_lsx_vhaddw_d_w", + "lsx.vhaddw.du.wu" => "__builtin_lsx_vhaddw_du_wu", + "lsx.vhaddw.h.b" => "__builtin_lsx_vhaddw_h_b", + "lsx.vhaddw.hu.bu" => "__builtin_lsx_vhaddw_hu_bu", + "lsx.vhaddw.q.d" => "__builtin_lsx_vhaddw_q_d", + "lsx.vhaddw.qu.du" => "__builtin_lsx_vhaddw_qu_du", + "lsx.vhaddw.w.h" => "__builtin_lsx_vhaddw_w_h", + "lsx.vhaddw.wu.hu" => "__builtin_lsx_vhaddw_wu_hu", + "lsx.vhsubw.d.w" => "__builtin_lsx_vhsubw_d_w", + "lsx.vhsubw.du.wu" => "__builtin_lsx_vhsubw_du_wu", + "lsx.vhsubw.h.b" => "__builtin_lsx_vhsubw_h_b", + "lsx.vhsubw.hu.bu" => "__builtin_lsx_vhsubw_hu_bu", + "lsx.vhsubw.q.d" => "__builtin_lsx_vhsubw_q_d", + "lsx.vhsubw.qu.du" => "__builtin_lsx_vhsubw_qu_du", + "lsx.vhsubw.w.h" => "__builtin_lsx_vhsubw_w_h", + "lsx.vhsubw.wu.hu" => "__builtin_lsx_vhsubw_wu_hu", + "lsx.vilvh.b" => "__builtin_lsx_vilvh_b", + "lsx.vilvh.d" => "__builtin_lsx_vilvh_d", + "lsx.vilvh.h" => "__builtin_lsx_vilvh_h", + "lsx.vilvh.w" => "__builtin_lsx_vilvh_w", + "lsx.vilvl.b" => "__builtin_lsx_vilvl_b", + "lsx.vilvl.d" => "__builtin_lsx_vilvl_d", + "lsx.vilvl.h" => "__builtin_lsx_vilvl_h", + "lsx.vilvl.w" => "__builtin_lsx_vilvl_w", + "lsx.vinsgr2vr.b" => "__builtin_lsx_vinsgr2vr_b", + "lsx.vinsgr2vr.d" => "__builtin_lsx_vinsgr2vr_d", + "lsx.vinsgr2vr.h" => "__builtin_lsx_vinsgr2vr_h", + "lsx.vinsgr2vr.w" => "__builtin_lsx_vinsgr2vr_w", + "lsx.vld" => "__builtin_lsx_vld", + "lsx.vldi" => "__builtin_lsx_vldi", + "lsx.vldrepl.b" => "__builtin_lsx_vldrepl_b", + "lsx.vldrepl.d" => "__builtin_lsx_vldrepl_d", + "lsx.vldrepl.h" => "__builtin_lsx_vldrepl_h", + "lsx.vldrepl.w" => "__builtin_lsx_vldrepl_w", + "lsx.vldx" => "__builtin_lsx_vldx", + "lsx.vmadd.b" => "__builtin_lsx_vmadd_b", + "lsx.vmadd.d" => "__builtin_lsx_vmadd_d", + "lsx.vmadd.h" => "__builtin_lsx_vmadd_h", + "lsx.vmadd.w" => "__builtin_lsx_vmadd_w", + "lsx.vmaddwev.d.w" => "__builtin_lsx_vmaddwev_d_w", + "lsx.vmaddwev.d.wu" => "__builtin_lsx_vmaddwev_d_wu", + "lsx.vmaddwev.d.wu.w" => "__builtin_lsx_vmaddwev_d_wu_w", + "lsx.vmaddwev.h.b" => "__builtin_lsx_vmaddwev_h_b", + "lsx.vmaddwev.h.bu" => "__builtin_lsx_vmaddwev_h_bu", + "lsx.vmaddwev.h.bu.b" => "__builtin_lsx_vmaddwev_h_bu_b", + "lsx.vmaddwev.q.d" => "__builtin_lsx_vmaddwev_q_d", + "lsx.vmaddwev.q.du" => "__builtin_lsx_vmaddwev_q_du", + "lsx.vmaddwev.q.du.d" => "__builtin_lsx_vmaddwev_q_du_d", + "lsx.vmaddwev.w.h" => "__builtin_lsx_vmaddwev_w_h", + "lsx.vmaddwev.w.hu" => "__builtin_lsx_vmaddwev_w_hu", + "lsx.vmaddwev.w.hu.h" => "__builtin_lsx_vmaddwev_w_hu_h", + "lsx.vmaddwod.d.w" => "__builtin_lsx_vmaddwod_d_w", + "lsx.vmaddwod.d.wu" => "__builtin_lsx_vmaddwod_d_wu", + "lsx.vmaddwod.d.wu.w" => "__builtin_lsx_vmaddwod_d_wu_w", + "lsx.vmaddwod.h.b" => "__builtin_lsx_vmaddwod_h_b", + "lsx.vmaddwod.h.bu" => "__builtin_lsx_vmaddwod_h_bu", + "lsx.vmaddwod.h.bu.b" => "__builtin_lsx_vmaddwod_h_bu_b", + "lsx.vmaddwod.q.d" => "__builtin_lsx_vmaddwod_q_d", + "lsx.vmaddwod.q.du" => "__builtin_lsx_vmaddwod_q_du", + "lsx.vmaddwod.q.du.d" => "__builtin_lsx_vmaddwod_q_du_d", + "lsx.vmaddwod.w.h" => "__builtin_lsx_vmaddwod_w_h", + "lsx.vmaddwod.w.hu" => "__builtin_lsx_vmaddwod_w_hu", + "lsx.vmaddwod.w.hu.h" => "__builtin_lsx_vmaddwod_w_hu_h", + "lsx.vmax.b" => "__builtin_lsx_vmax_b", + "lsx.vmax.bu" => "__builtin_lsx_vmax_bu", + "lsx.vmax.d" => "__builtin_lsx_vmax_d", + "lsx.vmax.du" => "__builtin_lsx_vmax_du", + "lsx.vmax.h" => "__builtin_lsx_vmax_h", + "lsx.vmax.hu" => "__builtin_lsx_vmax_hu", + "lsx.vmax.w" => "__builtin_lsx_vmax_w", + "lsx.vmax.wu" => "__builtin_lsx_vmax_wu", + "lsx.vmaxi.b" => "__builtin_lsx_vmaxi_b", + "lsx.vmaxi.bu" => "__builtin_lsx_vmaxi_bu", + "lsx.vmaxi.d" => "__builtin_lsx_vmaxi_d", + "lsx.vmaxi.du" => "__builtin_lsx_vmaxi_du", + "lsx.vmaxi.h" => "__builtin_lsx_vmaxi_h", + "lsx.vmaxi.hu" => "__builtin_lsx_vmaxi_hu", + "lsx.vmaxi.w" => "__builtin_lsx_vmaxi_w", + "lsx.vmaxi.wu" => "__builtin_lsx_vmaxi_wu", + "lsx.vmin.b" => "__builtin_lsx_vmin_b", + "lsx.vmin.bu" => "__builtin_lsx_vmin_bu", + "lsx.vmin.d" => "__builtin_lsx_vmin_d", + "lsx.vmin.du" => "__builtin_lsx_vmin_du", + "lsx.vmin.h" => "__builtin_lsx_vmin_h", + "lsx.vmin.hu" => "__builtin_lsx_vmin_hu", + "lsx.vmin.w" => "__builtin_lsx_vmin_w", + "lsx.vmin.wu" => "__builtin_lsx_vmin_wu", + "lsx.vmini.b" => "__builtin_lsx_vmini_b", + "lsx.vmini.bu" => "__builtin_lsx_vmini_bu", + "lsx.vmini.d" => "__builtin_lsx_vmini_d", + "lsx.vmini.du" => "__builtin_lsx_vmini_du", + "lsx.vmini.h" => "__builtin_lsx_vmini_h", + "lsx.vmini.hu" => "__builtin_lsx_vmini_hu", + "lsx.vmini.w" => "__builtin_lsx_vmini_w", + "lsx.vmini.wu" => "__builtin_lsx_vmini_wu", + "lsx.vmod.b" => "__builtin_lsx_vmod_b", + "lsx.vmod.bu" => "__builtin_lsx_vmod_bu", + "lsx.vmod.d" => "__builtin_lsx_vmod_d", + "lsx.vmod.du" => "__builtin_lsx_vmod_du", + "lsx.vmod.h" => "__builtin_lsx_vmod_h", + "lsx.vmod.hu" => "__builtin_lsx_vmod_hu", + "lsx.vmod.w" => "__builtin_lsx_vmod_w", + "lsx.vmod.wu" => "__builtin_lsx_vmod_wu", + "lsx.vmskgez.b" => "__builtin_lsx_vmskgez_b", + "lsx.vmskltz.b" => "__builtin_lsx_vmskltz_b", + "lsx.vmskltz.d" => "__builtin_lsx_vmskltz_d", + "lsx.vmskltz.h" => "__builtin_lsx_vmskltz_h", + "lsx.vmskltz.w" => "__builtin_lsx_vmskltz_w", + "lsx.vmsknz.b" => "__builtin_lsx_vmsknz_b", + "lsx.vmsub.b" => "__builtin_lsx_vmsub_b", + "lsx.vmsub.d" => "__builtin_lsx_vmsub_d", + "lsx.vmsub.h" => "__builtin_lsx_vmsub_h", + "lsx.vmsub.w" => "__builtin_lsx_vmsub_w", + "lsx.vmuh.b" => "__builtin_lsx_vmuh_b", + "lsx.vmuh.bu" => "__builtin_lsx_vmuh_bu", + "lsx.vmuh.d" => "__builtin_lsx_vmuh_d", + "lsx.vmuh.du" => "__builtin_lsx_vmuh_du", + "lsx.vmuh.h" => "__builtin_lsx_vmuh_h", + "lsx.vmuh.hu" => "__builtin_lsx_vmuh_hu", + "lsx.vmuh.w" => "__builtin_lsx_vmuh_w", + "lsx.vmuh.wu" => "__builtin_lsx_vmuh_wu", + "lsx.vmul.b" => "__builtin_lsx_vmul_b", + "lsx.vmul.d" => "__builtin_lsx_vmul_d", + "lsx.vmul.h" => "__builtin_lsx_vmul_h", + "lsx.vmul.w" => "__builtin_lsx_vmul_w", + "lsx.vmulwev.d.w" => "__builtin_lsx_vmulwev_d_w", + "lsx.vmulwev.d.wu" => "__builtin_lsx_vmulwev_d_wu", + "lsx.vmulwev.d.wu.w" => "__builtin_lsx_vmulwev_d_wu_w", + "lsx.vmulwev.h.b" => "__builtin_lsx_vmulwev_h_b", + "lsx.vmulwev.h.bu" => "__builtin_lsx_vmulwev_h_bu", + "lsx.vmulwev.h.bu.b" => "__builtin_lsx_vmulwev_h_bu_b", + "lsx.vmulwev.q.d" => "__builtin_lsx_vmulwev_q_d", + "lsx.vmulwev.q.du" => "__builtin_lsx_vmulwev_q_du", + "lsx.vmulwev.q.du.d" => "__builtin_lsx_vmulwev_q_du_d", + "lsx.vmulwev.w.h" => "__builtin_lsx_vmulwev_w_h", + "lsx.vmulwev.w.hu" => "__builtin_lsx_vmulwev_w_hu", + "lsx.vmulwev.w.hu.h" => "__builtin_lsx_vmulwev_w_hu_h", + "lsx.vmulwod.d.w" => "__builtin_lsx_vmulwod_d_w", + "lsx.vmulwod.d.wu" => "__builtin_lsx_vmulwod_d_wu", + "lsx.vmulwod.d.wu.w" => "__builtin_lsx_vmulwod_d_wu_w", + "lsx.vmulwod.h.b" => "__builtin_lsx_vmulwod_h_b", + "lsx.vmulwod.h.bu" => "__builtin_lsx_vmulwod_h_bu", + "lsx.vmulwod.h.bu.b" => "__builtin_lsx_vmulwod_h_bu_b", + "lsx.vmulwod.q.d" => "__builtin_lsx_vmulwod_q_d", + "lsx.vmulwod.q.du" => "__builtin_lsx_vmulwod_q_du", + "lsx.vmulwod.q.du.d" => "__builtin_lsx_vmulwod_q_du_d", + "lsx.vmulwod.w.h" => "__builtin_lsx_vmulwod_w_h", + "lsx.vmulwod.w.hu" => "__builtin_lsx_vmulwod_w_hu", + "lsx.vmulwod.w.hu.h" => "__builtin_lsx_vmulwod_w_hu_h", + "lsx.vneg.b" => "__builtin_lsx_vneg_b", + "lsx.vneg.d" => "__builtin_lsx_vneg_d", + "lsx.vneg.h" => "__builtin_lsx_vneg_h", + "lsx.vneg.w" => "__builtin_lsx_vneg_w", + "lsx.vnor.v" => "__builtin_lsx_vnor_v", + "lsx.vnori.b" => "__builtin_lsx_vnori_b", + "lsx.vor.v" => "__builtin_lsx_vor_v", + "lsx.vori.b" => "__builtin_lsx_vori_b", + "lsx.vorn.v" => "__builtin_lsx_vorn_v", + "lsx.vpackev.b" => "__builtin_lsx_vpackev_b", + "lsx.vpackev.d" => "__builtin_lsx_vpackev_d", + "lsx.vpackev.h" => "__builtin_lsx_vpackev_h", + "lsx.vpackev.w" => "__builtin_lsx_vpackev_w", + "lsx.vpackod.b" => "__builtin_lsx_vpackod_b", + "lsx.vpackod.d" => "__builtin_lsx_vpackod_d", + "lsx.vpackod.h" => "__builtin_lsx_vpackod_h", + "lsx.vpackod.w" => "__builtin_lsx_vpackod_w", + "lsx.vpcnt.b" => "__builtin_lsx_vpcnt_b", + "lsx.vpcnt.d" => "__builtin_lsx_vpcnt_d", + "lsx.vpcnt.h" => "__builtin_lsx_vpcnt_h", + "lsx.vpcnt.w" => "__builtin_lsx_vpcnt_w", + "lsx.vpermi.w" => "__builtin_lsx_vpermi_w", + "lsx.vpickev.b" => "__builtin_lsx_vpickev_b", + "lsx.vpickev.d" => "__builtin_lsx_vpickev_d", + "lsx.vpickev.h" => "__builtin_lsx_vpickev_h", + "lsx.vpickev.w" => "__builtin_lsx_vpickev_w", + "lsx.vpickod.b" => "__builtin_lsx_vpickod_b", + "lsx.vpickod.d" => "__builtin_lsx_vpickod_d", + "lsx.vpickod.h" => "__builtin_lsx_vpickod_h", + "lsx.vpickod.w" => "__builtin_lsx_vpickod_w", + "lsx.vpickve2gr.b" => "__builtin_lsx_vpickve2gr_b", + "lsx.vpickve2gr.bu" => "__builtin_lsx_vpickve2gr_bu", + "lsx.vpickve2gr.d" => "__builtin_lsx_vpickve2gr_d", + "lsx.vpickve2gr.du" => "__builtin_lsx_vpickve2gr_du", + "lsx.vpickve2gr.h" => "__builtin_lsx_vpickve2gr_h", + "lsx.vpickve2gr.hu" => "__builtin_lsx_vpickve2gr_hu", + "lsx.vpickve2gr.w" => "__builtin_lsx_vpickve2gr_w", + "lsx.vpickve2gr.wu" => "__builtin_lsx_vpickve2gr_wu", + "lsx.vreplgr2vr.b" => "__builtin_lsx_vreplgr2vr_b", + "lsx.vreplgr2vr.d" => "__builtin_lsx_vreplgr2vr_d", + "lsx.vreplgr2vr.h" => "__builtin_lsx_vreplgr2vr_h", + "lsx.vreplgr2vr.w" => "__builtin_lsx_vreplgr2vr_w", + "lsx.vrepli.b" => "__builtin_lsx_vrepli_b", + "lsx.vrepli.d" => "__builtin_lsx_vrepli_d", + "lsx.vrepli.h" => "__builtin_lsx_vrepli_h", + "lsx.vrepli.w" => "__builtin_lsx_vrepli_w", + "lsx.vreplve.b" => "__builtin_lsx_vreplve_b", + "lsx.vreplve.d" => "__builtin_lsx_vreplve_d", + "lsx.vreplve.h" => "__builtin_lsx_vreplve_h", + "lsx.vreplve.w" => "__builtin_lsx_vreplve_w", + "lsx.vreplvei.b" => "__builtin_lsx_vreplvei_b", + "lsx.vreplvei.d" => "__builtin_lsx_vreplvei_d", + "lsx.vreplvei.h" => "__builtin_lsx_vreplvei_h", + "lsx.vreplvei.w" => "__builtin_lsx_vreplvei_w", + "lsx.vrotr.b" => "__builtin_lsx_vrotr_b", + "lsx.vrotr.d" => "__builtin_lsx_vrotr_d", + "lsx.vrotr.h" => "__builtin_lsx_vrotr_h", + "lsx.vrotr.w" => "__builtin_lsx_vrotr_w", + "lsx.vrotri.b" => "__builtin_lsx_vrotri_b", + "lsx.vrotri.d" => "__builtin_lsx_vrotri_d", + "lsx.vrotri.h" => "__builtin_lsx_vrotri_h", + "lsx.vrotri.w" => "__builtin_lsx_vrotri_w", + "lsx.vsadd.b" => "__builtin_lsx_vsadd_b", + "lsx.vsadd.bu" => "__builtin_lsx_vsadd_bu", + "lsx.vsadd.d" => "__builtin_lsx_vsadd_d", + "lsx.vsadd.du" => "__builtin_lsx_vsadd_du", + "lsx.vsadd.h" => "__builtin_lsx_vsadd_h", + "lsx.vsadd.hu" => "__builtin_lsx_vsadd_hu", + "lsx.vsadd.w" => "__builtin_lsx_vsadd_w", + "lsx.vsadd.wu" => "__builtin_lsx_vsadd_wu", + "lsx.vsat.b" => "__builtin_lsx_vsat_b", + "lsx.vsat.bu" => "__builtin_lsx_vsat_bu", + "lsx.vsat.d" => "__builtin_lsx_vsat_d", + "lsx.vsat.du" => "__builtin_lsx_vsat_du", + "lsx.vsat.h" => "__builtin_lsx_vsat_h", + "lsx.vsat.hu" => "__builtin_lsx_vsat_hu", + "lsx.vsat.w" => "__builtin_lsx_vsat_w", + "lsx.vsat.wu" => "__builtin_lsx_vsat_wu", + "lsx.vseq.b" => "__builtin_lsx_vseq_b", + "lsx.vseq.d" => "__builtin_lsx_vseq_d", + "lsx.vseq.h" => "__builtin_lsx_vseq_h", + "lsx.vseq.w" => "__builtin_lsx_vseq_w", + "lsx.vseqi.b" => "__builtin_lsx_vseqi_b", + "lsx.vseqi.d" => "__builtin_lsx_vseqi_d", + "lsx.vseqi.h" => "__builtin_lsx_vseqi_h", + "lsx.vseqi.w" => "__builtin_lsx_vseqi_w", + "lsx.vshuf.b" => "__builtin_lsx_vshuf_b", + "lsx.vshuf.d" => "__builtin_lsx_vshuf_d", + "lsx.vshuf.h" => "__builtin_lsx_vshuf_h", + "lsx.vshuf.w" => "__builtin_lsx_vshuf_w", + "lsx.vshuf4i.b" => "__builtin_lsx_vshuf4i_b", + "lsx.vshuf4i.d" => "__builtin_lsx_vshuf4i_d", + "lsx.vshuf4i.h" => "__builtin_lsx_vshuf4i_h", + "lsx.vshuf4i.w" => "__builtin_lsx_vshuf4i_w", + "lsx.vsigncov.b" => "__builtin_lsx_vsigncov_b", + "lsx.vsigncov.d" => "__builtin_lsx_vsigncov_d", + "lsx.vsigncov.h" => "__builtin_lsx_vsigncov_h", + "lsx.vsigncov.w" => "__builtin_lsx_vsigncov_w", + "lsx.vsle.b" => "__builtin_lsx_vsle_b", + "lsx.vsle.bu" => "__builtin_lsx_vsle_bu", + "lsx.vsle.d" => "__builtin_lsx_vsle_d", + "lsx.vsle.du" => "__builtin_lsx_vsle_du", + "lsx.vsle.h" => "__builtin_lsx_vsle_h", + "lsx.vsle.hu" => "__builtin_lsx_vsle_hu", + "lsx.vsle.w" => "__builtin_lsx_vsle_w", + "lsx.vsle.wu" => "__builtin_lsx_vsle_wu", + "lsx.vslei.b" => "__builtin_lsx_vslei_b", + "lsx.vslei.bu" => "__builtin_lsx_vslei_bu", + "lsx.vslei.d" => "__builtin_lsx_vslei_d", + "lsx.vslei.du" => "__builtin_lsx_vslei_du", + "lsx.vslei.h" => "__builtin_lsx_vslei_h", + "lsx.vslei.hu" => "__builtin_lsx_vslei_hu", + "lsx.vslei.w" => "__builtin_lsx_vslei_w", + "lsx.vslei.wu" => "__builtin_lsx_vslei_wu", + "lsx.vsll.b" => "__builtin_lsx_vsll_b", + "lsx.vsll.d" => "__builtin_lsx_vsll_d", + "lsx.vsll.h" => "__builtin_lsx_vsll_h", + "lsx.vsll.w" => "__builtin_lsx_vsll_w", + "lsx.vslli.b" => "__builtin_lsx_vslli_b", + "lsx.vslli.d" => "__builtin_lsx_vslli_d", + "lsx.vslli.h" => "__builtin_lsx_vslli_h", + "lsx.vslli.w" => "__builtin_lsx_vslli_w", + "lsx.vsllwil.d.w" => "__builtin_lsx_vsllwil_d_w", + "lsx.vsllwil.du.wu" => "__builtin_lsx_vsllwil_du_wu", + "lsx.vsllwil.h.b" => "__builtin_lsx_vsllwil_h_b", + "lsx.vsllwil.hu.bu" => "__builtin_lsx_vsllwil_hu_bu", + "lsx.vsllwil.w.h" => "__builtin_lsx_vsllwil_w_h", + "lsx.vsllwil.wu.hu" => "__builtin_lsx_vsllwil_wu_hu", + "lsx.vslt.b" => "__builtin_lsx_vslt_b", + "lsx.vslt.bu" => "__builtin_lsx_vslt_bu", + "lsx.vslt.d" => "__builtin_lsx_vslt_d", + "lsx.vslt.du" => "__builtin_lsx_vslt_du", + "lsx.vslt.h" => "__builtin_lsx_vslt_h", + "lsx.vslt.hu" => "__builtin_lsx_vslt_hu", + "lsx.vslt.w" => "__builtin_lsx_vslt_w", + "lsx.vslt.wu" => "__builtin_lsx_vslt_wu", + "lsx.vslti.b" => "__builtin_lsx_vslti_b", + "lsx.vslti.bu" => "__builtin_lsx_vslti_bu", + "lsx.vslti.d" => "__builtin_lsx_vslti_d", + "lsx.vslti.du" => "__builtin_lsx_vslti_du", + "lsx.vslti.h" => "__builtin_lsx_vslti_h", + "lsx.vslti.hu" => "__builtin_lsx_vslti_hu", + "lsx.vslti.w" => "__builtin_lsx_vslti_w", + "lsx.vslti.wu" => "__builtin_lsx_vslti_wu", + "lsx.vsra.b" => "__builtin_lsx_vsra_b", + "lsx.vsra.d" => "__builtin_lsx_vsra_d", + "lsx.vsra.h" => "__builtin_lsx_vsra_h", + "lsx.vsra.w" => "__builtin_lsx_vsra_w", + "lsx.vsrai.b" => "__builtin_lsx_vsrai_b", + "lsx.vsrai.d" => "__builtin_lsx_vsrai_d", + "lsx.vsrai.h" => "__builtin_lsx_vsrai_h", + "lsx.vsrai.w" => "__builtin_lsx_vsrai_w", + "lsx.vsran.b.h" => "__builtin_lsx_vsran_b_h", + "lsx.vsran.h.w" => "__builtin_lsx_vsran_h_w", + "lsx.vsran.w.d" => "__builtin_lsx_vsran_w_d", + "lsx.vsrani.b.h" => "__builtin_lsx_vsrani_b_h", + "lsx.vsrani.d.q" => "__builtin_lsx_vsrani_d_q", + "lsx.vsrani.h.w" => "__builtin_lsx_vsrani_h_w", + "lsx.vsrani.w.d" => "__builtin_lsx_vsrani_w_d", + "lsx.vsrar.b" => "__builtin_lsx_vsrar_b", + "lsx.vsrar.d" => "__builtin_lsx_vsrar_d", + "lsx.vsrar.h" => "__builtin_lsx_vsrar_h", + "lsx.vsrar.w" => "__builtin_lsx_vsrar_w", + "lsx.vsrari.b" => "__builtin_lsx_vsrari_b", + "lsx.vsrari.d" => "__builtin_lsx_vsrari_d", + "lsx.vsrari.h" => "__builtin_lsx_vsrari_h", + "lsx.vsrari.w" => "__builtin_lsx_vsrari_w", + "lsx.vsrarn.b.h" => "__builtin_lsx_vsrarn_b_h", + "lsx.vsrarn.h.w" => "__builtin_lsx_vsrarn_h_w", + "lsx.vsrarn.w.d" => "__builtin_lsx_vsrarn_w_d", + "lsx.vsrarni.b.h" => "__builtin_lsx_vsrarni_b_h", + "lsx.vsrarni.d.q" => "__builtin_lsx_vsrarni_d_q", + "lsx.vsrarni.h.w" => "__builtin_lsx_vsrarni_h_w", + "lsx.vsrarni.w.d" => "__builtin_lsx_vsrarni_w_d", + "lsx.vsrl.b" => "__builtin_lsx_vsrl_b", + "lsx.vsrl.d" => "__builtin_lsx_vsrl_d", + "lsx.vsrl.h" => "__builtin_lsx_vsrl_h", + "lsx.vsrl.w" => "__builtin_lsx_vsrl_w", + "lsx.vsrli.b" => "__builtin_lsx_vsrli_b", + "lsx.vsrli.d" => "__builtin_lsx_vsrli_d", + "lsx.vsrli.h" => "__builtin_lsx_vsrli_h", + "lsx.vsrli.w" => "__builtin_lsx_vsrli_w", + "lsx.vsrln.b.h" => "__builtin_lsx_vsrln_b_h", + "lsx.vsrln.h.w" => "__builtin_lsx_vsrln_h_w", + "lsx.vsrln.w.d" => "__builtin_lsx_vsrln_w_d", + "lsx.vsrlni.b.h" => "__builtin_lsx_vsrlni_b_h", + "lsx.vsrlni.d.q" => "__builtin_lsx_vsrlni_d_q", + "lsx.vsrlni.h.w" => "__builtin_lsx_vsrlni_h_w", + "lsx.vsrlni.w.d" => "__builtin_lsx_vsrlni_w_d", + "lsx.vsrlr.b" => "__builtin_lsx_vsrlr_b", + "lsx.vsrlr.d" => "__builtin_lsx_vsrlr_d", + "lsx.vsrlr.h" => "__builtin_lsx_vsrlr_h", + "lsx.vsrlr.w" => "__builtin_lsx_vsrlr_w", + "lsx.vsrlri.b" => "__builtin_lsx_vsrlri_b", + "lsx.vsrlri.d" => "__builtin_lsx_vsrlri_d", + "lsx.vsrlri.h" => "__builtin_lsx_vsrlri_h", + "lsx.vsrlri.w" => "__builtin_lsx_vsrlri_w", + "lsx.vsrlrn.b.h" => "__builtin_lsx_vsrlrn_b_h", + "lsx.vsrlrn.h.w" => "__builtin_lsx_vsrlrn_h_w", + "lsx.vsrlrn.w.d" => "__builtin_lsx_vsrlrn_w_d", + "lsx.vsrlrni.b.h" => "__builtin_lsx_vsrlrni_b_h", + "lsx.vsrlrni.d.q" => "__builtin_lsx_vsrlrni_d_q", + "lsx.vsrlrni.h.w" => "__builtin_lsx_vsrlrni_h_w", + "lsx.vsrlrni.w.d" => "__builtin_lsx_vsrlrni_w_d", + "lsx.vssran.b.h" => "__builtin_lsx_vssran_b_h", + "lsx.vssran.bu.h" => "__builtin_lsx_vssran_bu_h", + "lsx.vssran.h.w" => "__builtin_lsx_vssran_h_w", + "lsx.vssran.hu.w" => "__builtin_lsx_vssran_hu_w", + "lsx.vssran.w.d" => "__builtin_lsx_vssran_w_d", + "lsx.vssran.wu.d" => "__builtin_lsx_vssran_wu_d", + "lsx.vssrani.b.h" => "__builtin_lsx_vssrani_b_h", + "lsx.vssrani.bu.h" => "__builtin_lsx_vssrani_bu_h", + "lsx.vssrani.d.q" => "__builtin_lsx_vssrani_d_q", + "lsx.vssrani.du.q" => "__builtin_lsx_vssrani_du_q", + "lsx.vssrani.h.w" => "__builtin_lsx_vssrani_h_w", + "lsx.vssrani.hu.w" => "__builtin_lsx_vssrani_hu_w", + "lsx.vssrani.w.d" => "__builtin_lsx_vssrani_w_d", + "lsx.vssrani.wu.d" => "__builtin_lsx_vssrani_wu_d", + "lsx.vssrarn.b.h" => "__builtin_lsx_vssrarn_b_h", + "lsx.vssrarn.bu.h" => "__builtin_lsx_vssrarn_bu_h", + "lsx.vssrarn.h.w" => "__builtin_lsx_vssrarn_h_w", + "lsx.vssrarn.hu.w" => "__builtin_lsx_vssrarn_hu_w", + "lsx.vssrarn.w.d" => "__builtin_lsx_vssrarn_w_d", + "lsx.vssrarn.wu.d" => "__builtin_lsx_vssrarn_wu_d", + "lsx.vssrarni.b.h" => "__builtin_lsx_vssrarni_b_h", + "lsx.vssrarni.bu.h" => "__builtin_lsx_vssrarni_bu_h", + "lsx.vssrarni.d.q" => "__builtin_lsx_vssrarni_d_q", + "lsx.vssrarni.du.q" => "__builtin_lsx_vssrarni_du_q", + "lsx.vssrarni.h.w" => "__builtin_lsx_vssrarni_h_w", + "lsx.vssrarni.hu.w" => "__builtin_lsx_vssrarni_hu_w", + "lsx.vssrarni.w.d" => "__builtin_lsx_vssrarni_w_d", + "lsx.vssrarni.wu.d" => "__builtin_lsx_vssrarni_wu_d", + "lsx.vssrln.b.h" => "__builtin_lsx_vssrln_b_h", + "lsx.vssrln.bu.h" => "__builtin_lsx_vssrln_bu_h", + "lsx.vssrln.h.w" => "__builtin_lsx_vssrln_h_w", + "lsx.vssrln.hu.w" => "__builtin_lsx_vssrln_hu_w", + "lsx.vssrln.w.d" => "__builtin_lsx_vssrln_w_d", + "lsx.vssrln.wu.d" => "__builtin_lsx_vssrln_wu_d", + "lsx.vssrlni.b.h" => "__builtin_lsx_vssrlni_b_h", + "lsx.vssrlni.bu.h" => "__builtin_lsx_vssrlni_bu_h", + "lsx.vssrlni.d.q" => "__builtin_lsx_vssrlni_d_q", + "lsx.vssrlni.du.q" => "__builtin_lsx_vssrlni_du_q", + "lsx.vssrlni.h.w" => "__builtin_lsx_vssrlni_h_w", + "lsx.vssrlni.hu.w" => "__builtin_lsx_vssrlni_hu_w", + "lsx.vssrlni.w.d" => "__builtin_lsx_vssrlni_w_d", + "lsx.vssrlni.wu.d" => "__builtin_lsx_vssrlni_wu_d", + "lsx.vssrlrn.b.h" => "__builtin_lsx_vssrlrn_b_h", + "lsx.vssrlrn.bu.h" => "__builtin_lsx_vssrlrn_bu_h", + "lsx.vssrlrn.h.w" => "__builtin_lsx_vssrlrn_h_w", + "lsx.vssrlrn.hu.w" => "__builtin_lsx_vssrlrn_hu_w", + "lsx.vssrlrn.w.d" => "__builtin_lsx_vssrlrn_w_d", + "lsx.vssrlrn.wu.d" => "__builtin_lsx_vssrlrn_wu_d", + "lsx.vssrlrni.b.h" => "__builtin_lsx_vssrlrni_b_h", + "lsx.vssrlrni.bu.h" => "__builtin_lsx_vssrlrni_bu_h", + "lsx.vssrlrni.d.q" => "__builtin_lsx_vssrlrni_d_q", + "lsx.vssrlrni.du.q" => "__builtin_lsx_vssrlrni_du_q", + "lsx.vssrlrni.h.w" => "__builtin_lsx_vssrlrni_h_w", + "lsx.vssrlrni.hu.w" => "__builtin_lsx_vssrlrni_hu_w", + "lsx.vssrlrni.w.d" => "__builtin_lsx_vssrlrni_w_d", + "lsx.vssrlrni.wu.d" => "__builtin_lsx_vssrlrni_wu_d", + "lsx.vssub.b" => "__builtin_lsx_vssub_b", + "lsx.vssub.bu" => "__builtin_lsx_vssub_bu", + "lsx.vssub.d" => "__builtin_lsx_vssub_d", + "lsx.vssub.du" => "__builtin_lsx_vssub_du", + "lsx.vssub.h" => "__builtin_lsx_vssub_h", + "lsx.vssub.hu" => "__builtin_lsx_vssub_hu", + "lsx.vssub.w" => "__builtin_lsx_vssub_w", + "lsx.vssub.wu" => "__builtin_lsx_vssub_wu", + "lsx.vst" => "__builtin_lsx_vst", + "lsx.vstelm.b" => "__builtin_lsx_vstelm_b", + "lsx.vstelm.d" => "__builtin_lsx_vstelm_d", + "lsx.vstelm.h" => "__builtin_lsx_vstelm_h", + "lsx.vstelm.w" => "__builtin_lsx_vstelm_w", + "lsx.vstx" => "__builtin_lsx_vstx", + "lsx.vsub.b" => "__builtin_lsx_vsub_b", + "lsx.vsub.d" => "__builtin_lsx_vsub_d", + "lsx.vsub.h" => "__builtin_lsx_vsub_h", + "lsx.vsub.q" => "__builtin_lsx_vsub_q", + "lsx.vsub.w" => "__builtin_lsx_vsub_w", + "lsx.vsubi.bu" => "__builtin_lsx_vsubi_bu", + "lsx.vsubi.du" => "__builtin_lsx_vsubi_du", + "lsx.vsubi.hu" => "__builtin_lsx_vsubi_hu", + "lsx.vsubi.wu" => "__builtin_lsx_vsubi_wu", + "lsx.vsubwev.d.w" => "__builtin_lsx_vsubwev_d_w", + "lsx.vsubwev.d.wu" => "__builtin_lsx_vsubwev_d_wu", + "lsx.vsubwev.h.b" => "__builtin_lsx_vsubwev_h_b", + "lsx.vsubwev.h.bu" => "__builtin_lsx_vsubwev_h_bu", + "lsx.vsubwev.q.d" => "__builtin_lsx_vsubwev_q_d", + "lsx.vsubwev.q.du" => "__builtin_lsx_vsubwev_q_du", + "lsx.vsubwev.w.h" => "__builtin_lsx_vsubwev_w_h", + "lsx.vsubwev.w.hu" => "__builtin_lsx_vsubwev_w_hu", + "lsx.vsubwod.d.w" => "__builtin_lsx_vsubwod_d_w", + "lsx.vsubwod.d.wu" => "__builtin_lsx_vsubwod_d_wu", + "lsx.vsubwod.h.b" => "__builtin_lsx_vsubwod_h_b", + "lsx.vsubwod.h.bu" => "__builtin_lsx_vsubwod_h_bu", + "lsx.vsubwod.q.d" => "__builtin_lsx_vsubwod_q_d", + "lsx.vsubwod.q.du" => "__builtin_lsx_vsubwod_q_du", + "lsx.vsubwod.w.h" => "__builtin_lsx_vsubwod_w_h", + "lsx.vsubwod.w.hu" => "__builtin_lsx_vsubwod_w_hu", + "lsx.vxor.v" => "__builtin_lsx_vxor_v", + "lsx.vxori.b" => "__builtin_lsx_vxori_b", + "movfcsr2gr" => "__builtin_loongarch_movfcsr2gr", + "movgr2fcsr" => "__builtin_loongarch_movgr2fcsr", + "syscall" => "__builtin_loongarch_syscall", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + loongarch(name) + } + "mips" => { + #[allow(non_snake_case)] + fn mips(name: &str) -> &str { + match name { + // mips + "absq.s.ph" => "__builtin_mips_absq_s_ph", + "absq.s.qb" => "__builtin_mips_absq_s_qb", + "absq.s.w" => "__builtin_mips_absq_s_w", + "add.a.b" => "__builtin_msa_add_a_b", + "add.a.d" => "__builtin_msa_add_a_d", + "add.a.h" => "__builtin_msa_add_a_h", + "add.a.w" => "__builtin_msa_add_a_w", + "addq.ph" => "__builtin_mips_addq_ph", + "addq.s.ph" => "__builtin_mips_addq_s_ph", + "addq.s.w" => "__builtin_mips_addq_s_w", + "addqh.ph" => "__builtin_mips_addqh_ph", + "addqh.r.ph" => "__builtin_mips_addqh_r_ph", + "addqh.r.w" => "__builtin_mips_addqh_r_w", + "addqh.w" => "__builtin_mips_addqh_w", + "adds.a.b" => "__builtin_msa_adds_a_b", + "adds.a.d" => "__builtin_msa_adds_a_d", + "adds.a.h" => "__builtin_msa_adds_a_h", + "adds.a.w" => "__builtin_msa_adds_a_w", + "adds.s.b" => "__builtin_msa_adds_s_b", + "adds.s.d" => "__builtin_msa_adds_s_d", + "adds.s.h" => "__builtin_msa_adds_s_h", + "adds.s.w" => "__builtin_msa_adds_s_w", + "adds.u.b" => "__builtin_msa_adds_u_b", + "adds.u.d" => "__builtin_msa_adds_u_d", + "adds.u.h" => "__builtin_msa_adds_u_h", + "adds.u.w" => "__builtin_msa_adds_u_w", + "addsc" => "__builtin_mips_addsc", + "addu.ph" => "__builtin_mips_addu_ph", + "addu.qb" => "__builtin_mips_addu_qb", + "addu.s.ph" => "__builtin_mips_addu_s_ph", + "addu.s.qb" => "__builtin_mips_addu_s_qb", + "adduh.qb" => "__builtin_mips_adduh_qb", + "adduh.r.qb" => "__builtin_mips_adduh_r_qb", + "addv.b" => "__builtin_msa_addv_b", + "addv.d" => "__builtin_msa_addv_d", + "addv.h" => "__builtin_msa_addv_h", + "addv.w" => "__builtin_msa_addv_w", + "addvi.b" => "__builtin_msa_addvi_b", + "addvi.d" => "__builtin_msa_addvi_d", + "addvi.h" => "__builtin_msa_addvi_h", + "addvi.w" => "__builtin_msa_addvi_w", + "addwc" => "__builtin_mips_addwc", + "and.v" => "__builtin_msa_and_v", + "andi.b" => "__builtin_msa_andi_b", + "append" => "__builtin_mips_append", + "asub.s.b" => "__builtin_msa_asub_s_b", + "asub.s.d" => "__builtin_msa_asub_s_d", + "asub.s.h" => "__builtin_msa_asub_s_h", + "asub.s.w" => "__builtin_msa_asub_s_w", + "asub.u.b" => "__builtin_msa_asub_u_b", + "asub.u.d" => "__builtin_msa_asub_u_d", + "asub.u.h" => "__builtin_msa_asub_u_h", + "asub.u.w" => "__builtin_msa_asub_u_w", + "ave.s.b" => "__builtin_msa_ave_s_b", + "ave.s.d" => "__builtin_msa_ave_s_d", + "ave.s.h" => "__builtin_msa_ave_s_h", + "ave.s.w" => "__builtin_msa_ave_s_w", + "ave.u.b" => "__builtin_msa_ave_u_b", + "ave.u.d" => "__builtin_msa_ave_u_d", + "ave.u.h" => "__builtin_msa_ave_u_h", + "ave.u.w" => "__builtin_msa_ave_u_w", + "aver.s.b" => "__builtin_msa_aver_s_b", + "aver.s.d" => "__builtin_msa_aver_s_d", + "aver.s.h" => "__builtin_msa_aver_s_h", + "aver.s.w" => "__builtin_msa_aver_s_w", + "aver.u.b" => "__builtin_msa_aver_u_b", + "aver.u.d" => "__builtin_msa_aver_u_d", + "aver.u.h" => "__builtin_msa_aver_u_h", + "aver.u.w" => "__builtin_msa_aver_u_w", + "balign" => "__builtin_mips_balign", + "bclr.b" => "__builtin_msa_bclr_b", + "bclr.d" => "__builtin_msa_bclr_d", + "bclr.h" => "__builtin_msa_bclr_h", + "bclr.w" => "__builtin_msa_bclr_w", + "bclri.b" => "__builtin_msa_bclri_b", + "bclri.d" => "__builtin_msa_bclri_d", + "bclri.h" => "__builtin_msa_bclri_h", + "bclri.w" => "__builtin_msa_bclri_w", + "binsl.b" => "__builtin_msa_binsl_b", + "binsl.d" => "__builtin_msa_binsl_d", + "binsl.h" => "__builtin_msa_binsl_h", + "binsl.w" => "__builtin_msa_binsl_w", + "binsli.b" => "__builtin_msa_binsli_b", + "binsli.d" => "__builtin_msa_binsli_d", + "binsli.h" => "__builtin_msa_binsli_h", + "binsli.w" => "__builtin_msa_binsli_w", + "binsr.b" => "__builtin_msa_binsr_b", + "binsr.d" => "__builtin_msa_binsr_d", + "binsr.h" => "__builtin_msa_binsr_h", + "binsr.w" => "__builtin_msa_binsr_w", + "binsri.b" => "__builtin_msa_binsri_b", + "binsri.d" => "__builtin_msa_binsri_d", + "binsri.h" => "__builtin_msa_binsri_h", + "binsri.w" => "__builtin_msa_binsri_w", + "bitrev" => "__builtin_mips_bitrev", + "bmnz.v" => "__builtin_msa_bmnz_v", + "bmnzi.b" => "__builtin_msa_bmnzi_b", + "bmz.v" => "__builtin_msa_bmz_v", + "bmzi.b" => "__builtin_msa_bmzi_b", + "bneg.b" => "__builtin_msa_bneg_b", + "bneg.d" => "__builtin_msa_bneg_d", + "bneg.h" => "__builtin_msa_bneg_h", + "bneg.w" => "__builtin_msa_bneg_w", + "bnegi.b" => "__builtin_msa_bnegi_b", + "bnegi.d" => "__builtin_msa_bnegi_d", + "bnegi.h" => "__builtin_msa_bnegi_h", + "bnegi.w" => "__builtin_msa_bnegi_w", + "bnz.b" => "__builtin_msa_bnz_b", + "bnz.d" => "__builtin_msa_bnz_d", + "bnz.h" => "__builtin_msa_bnz_h", + "bnz.v" => "__builtin_msa_bnz_v", + "bnz.w" => "__builtin_msa_bnz_w", + "bposge32" => "__builtin_mips_bposge32", + "bsel.v" => "__builtin_msa_bsel_v", + "bseli.b" => "__builtin_msa_bseli_b", + "bset.b" => "__builtin_msa_bset_b", + "bset.d" => "__builtin_msa_bset_d", + "bset.h" => "__builtin_msa_bset_h", + "bset.w" => "__builtin_msa_bset_w", + "bseti.b" => "__builtin_msa_bseti_b", + "bseti.d" => "__builtin_msa_bseti_d", + "bseti.h" => "__builtin_msa_bseti_h", + "bseti.w" => "__builtin_msa_bseti_w", + "bz.b" => "__builtin_msa_bz_b", + "bz.d" => "__builtin_msa_bz_d", + "bz.h" => "__builtin_msa_bz_h", + "bz.v" => "__builtin_msa_bz_v", + "bz.w" => "__builtin_msa_bz_w", + "ceq.b" => "__builtin_msa_ceq_b", + "ceq.d" => "__builtin_msa_ceq_d", + "ceq.h" => "__builtin_msa_ceq_h", + "ceq.w" => "__builtin_msa_ceq_w", + "ceqi.b" => "__builtin_msa_ceqi_b", + "ceqi.d" => "__builtin_msa_ceqi_d", + "ceqi.h" => "__builtin_msa_ceqi_h", + "ceqi.w" => "__builtin_msa_ceqi_w", + "cfcmsa" => "__builtin_msa_cfcmsa", + "cle.s.b" => "__builtin_msa_cle_s_b", + "cle.s.d" => "__builtin_msa_cle_s_d", + "cle.s.h" => "__builtin_msa_cle_s_h", + "cle.s.w" => "__builtin_msa_cle_s_w", + "cle.u.b" => "__builtin_msa_cle_u_b", + "cle.u.d" => "__builtin_msa_cle_u_d", + "cle.u.h" => "__builtin_msa_cle_u_h", + "cle.u.w" => "__builtin_msa_cle_u_w", + "clei.s.b" => "__builtin_msa_clei_s_b", + "clei.s.d" => "__builtin_msa_clei_s_d", + "clei.s.h" => "__builtin_msa_clei_s_h", + "clei.s.w" => "__builtin_msa_clei_s_w", + "clei.u.b" => "__builtin_msa_clei_u_b", + "clei.u.d" => "__builtin_msa_clei_u_d", + "clei.u.h" => "__builtin_msa_clei_u_h", + "clei.u.w" => "__builtin_msa_clei_u_w", + "clt.s.b" => "__builtin_msa_clt_s_b", + "clt.s.d" => "__builtin_msa_clt_s_d", + "clt.s.h" => "__builtin_msa_clt_s_h", + "clt.s.w" => "__builtin_msa_clt_s_w", + "clt.u.b" => "__builtin_msa_clt_u_b", + "clt.u.d" => "__builtin_msa_clt_u_d", + "clt.u.h" => "__builtin_msa_clt_u_h", + "clt.u.w" => "__builtin_msa_clt_u_w", + "clti.s.b" => "__builtin_msa_clti_s_b", + "clti.s.d" => "__builtin_msa_clti_s_d", + "clti.s.h" => "__builtin_msa_clti_s_h", + "clti.s.w" => "__builtin_msa_clti_s_w", + "clti.u.b" => "__builtin_msa_clti_u_b", + "clti.u.d" => "__builtin_msa_clti_u_d", + "clti.u.h" => "__builtin_msa_clti_u_h", + "clti.u.w" => "__builtin_msa_clti_u_w", + "cmp.eq.ph" => "__builtin_mips_cmp_eq_ph", + "cmp.le.ph" => "__builtin_mips_cmp_le_ph", + "cmp.lt.ph" => "__builtin_mips_cmp_lt_ph", + "cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb", + "cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb", + "cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb", + "cmpgu.eq.qb" => "__builtin_mips_cmpgu_eq_qb", + "cmpgu.le.qb" => "__builtin_mips_cmpgu_le_qb", + "cmpgu.lt.qb" => "__builtin_mips_cmpgu_lt_qb", + "cmpu.eq.qb" => "__builtin_mips_cmpu_eq_qb", + "cmpu.le.qb" => "__builtin_mips_cmpu_le_qb", + "cmpu.lt.qb" => "__builtin_mips_cmpu_lt_qb", + "copy.s.b" => "__builtin_msa_copy_s_b", + "copy.s.d" => "__builtin_msa_copy_s_d", + "copy.s.h" => "__builtin_msa_copy_s_h", + "copy.s.w" => "__builtin_msa_copy_s_w", + "copy.u.b" => "__builtin_msa_copy_u_b", + "copy.u.d" => "__builtin_msa_copy_u_d", + "copy.u.h" => "__builtin_msa_copy_u_h", + "copy.u.w" => "__builtin_msa_copy_u_w", + "ctcmsa" => "__builtin_msa_ctcmsa", + "div.s.b" => "__builtin_msa_div_s_b", + "div.s.d" => "__builtin_msa_div_s_d", + "div.s.h" => "__builtin_msa_div_s_h", + "div.s.w" => "__builtin_msa_div_s_w", + "div.u.b" => "__builtin_msa_div_u_b", + "div.u.d" => "__builtin_msa_div_u_d", + "div.u.h" => "__builtin_msa_div_u_h", + "div.u.w" => "__builtin_msa_div_u_w", + "dlsa" => "__builtin_mips_dlsa", + "dotp.s.d" => "__builtin_msa_dotp_s_d", + "dotp.s.h" => "__builtin_msa_dotp_s_h", + "dotp.s.w" => "__builtin_msa_dotp_s_w", + "dotp.u.d" => "__builtin_msa_dotp_u_d", + "dotp.u.h" => "__builtin_msa_dotp_u_h", + "dotp.u.w" => "__builtin_msa_dotp_u_w", + "dpa.w.ph" => "__builtin_mips_dpa_w_ph", + "dpadd.s.d" => "__builtin_msa_dpadd_s_d", + "dpadd.s.h" => "__builtin_msa_dpadd_s_h", + "dpadd.s.w" => "__builtin_msa_dpadd_s_w", + "dpadd.u.d" => "__builtin_msa_dpadd_u_d", + "dpadd.u.h" => "__builtin_msa_dpadd_u_h", + "dpadd.u.w" => "__builtin_msa_dpadd_u_w", + "dpaq.s.w.ph" => "__builtin_mips_dpaq_s_w_ph", + "dpaq.sa.l.w" => "__builtin_mips_dpaq_sa_l_w", + "dpaqx.s.w.ph" => "__builtin_mips_dpaqx_s_w_ph", + "dpaqx.sa.w.ph" => "__builtin_mips_dpaqx_sa_w_ph", + "dpau.h.qbl" => "__builtin_mips_dpau_h_qbl", + "dpau.h.qbr" => "__builtin_mips_dpau_h_qbr", + "dpax.w.ph" => "__builtin_mips_dpax_w_ph", + "dps.w.ph" => "__builtin_mips_dps_w_ph", + "dpsq.s.w.ph" => "__builtin_mips_dpsq_s_w_ph", + "dpsq.sa.l.w" => "__builtin_mips_dpsq_sa_l_w", + "dpsqx.s.w.ph" => "__builtin_mips_dpsqx_s_w_ph", + "dpsqx.sa.w.ph" => "__builtin_mips_dpsqx_sa_w_ph", + "dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl", + "dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr", + "dpsub.s.d" => "__builtin_msa_dpsub_s_d", + "dpsub.s.h" => "__builtin_msa_dpsub_s_h", + "dpsub.s.w" => "__builtin_msa_dpsub_s_w", + "dpsub.u.d" => "__builtin_msa_dpsub_u_d", + "dpsub.u.h" => "__builtin_msa_dpsub_u_h", + "dpsub.u.w" => "__builtin_msa_dpsub_u_w", + "dpsx.w.ph" => "__builtin_mips_dpsx_w_ph", + "extp" => "__builtin_mips_extp", + "extpdp" => "__builtin_mips_extpdp", + "extr.r.w" => "__builtin_mips_extr_r_w", + "extr.rs.w" => "__builtin_mips_extr_rs_w", + "extr.s.h" => "__builtin_mips_extr_s_h", + "extr.w" => "__builtin_mips_extr_w", + "fadd.d" => "__builtin_msa_fadd_d", + "fadd.w" => "__builtin_msa_fadd_w", + "fcaf.d" => "__builtin_msa_fcaf_d", + "fcaf.w" => "__builtin_msa_fcaf_w", + "fceq.d" => "__builtin_msa_fceq_d", + "fceq.w" => "__builtin_msa_fceq_w", + "fclass.d" => "__builtin_msa_fclass_d", + "fclass.w" => "__builtin_msa_fclass_w", + "fcle.d" => "__builtin_msa_fcle_d", + "fcle.w" => "__builtin_msa_fcle_w", + "fclt.d" => "__builtin_msa_fclt_d", + "fclt.w" => "__builtin_msa_fclt_w", + "fcne.d" => "__builtin_msa_fcne_d", + "fcne.w" => "__builtin_msa_fcne_w", + "fcor.d" => "__builtin_msa_fcor_d", + "fcor.w" => "__builtin_msa_fcor_w", + "fcueq.d" => "__builtin_msa_fcueq_d", + "fcueq.w" => "__builtin_msa_fcueq_w", + "fcule.d" => "__builtin_msa_fcule_d", + "fcule.w" => "__builtin_msa_fcule_w", + "fcult.d" => "__builtin_msa_fcult_d", + "fcult.w" => "__builtin_msa_fcult_w", + "fcun.d" => "__builtin_msa_fcun_d", + "fcun.w" => "__builtin_msa_fcun_w", + "fcune.d" => "__builtin_msa_fcune_d", + "fcune.w" => "__builtin_msa_fcune_w", + "fdiv.d" => "__builtin_msa_fdiv_d", + "fdiv.w" => "__builtin_msa_fdiv_w", + "fexdo.h" => "__builtin_msa_fexdo_h", + "fexdo.w" => "__builtin_msa_fexdo_w", + "fexp2.d" => "__builtin_msa_fexp2_d", + "fexp2.w" => "__builtin_msa_fexp2_w", + "fexupl.d" => "__builtin_msa_fexupl_d", + "fexupl.w" => "__builtin_msa_fexupl_w", + "fexupr.d" => "__builtin_msa_fexupr_d", + "fexupr.w" => "__builtin_msa_fexupr_w", + "ffint.s.d" => "__builtin_msa_ffint_s_d", + "ffint.s.w" => "__builtin_msa_ffint_s_w", + "ffint.u.d" => "__builtin_msa_ffint_u_d", + "ffint.u.w" => "__builtin_msa_ffint_u_w", + "ffql.d" => "__builtin_msa_ffql_d", + "ffql.w" => "__builtin_msa_ffql_w", + "ffqr.d" => "__builtin_msa_ffqr_d", + "ffqr.w" => "__builtin_msa_ffqr_w", + "fill.b" => "__builtin_msa_fill_b", + "fill.d" => "__builtin_msa_fill_d", + "fill.h" => "__builtin_msa_fill_h", + "fill.w" => "__builtin_msa_fill_w", + "flog2.d" => "__builtin_msa_flog2_d", + "flog2.w" => "__builtin_msa_flog2_w", + "fmadd.d" => "__builtin_msa_fmadd_d", + "fmadd.w" => "__builtin_msa_fmadd_w", + "fmax.a.d" => "__builtin_msa_fmax_a_d", + "fmax.a.w" => "__builtin_msa_fmax_a_w", + "fmax.d" => "__builtin_msa_fmax_d", + "fmax.w" => "__builtin_msa_fmax_w", + "fmin.a.d" => "__builtin_msa_fmin_a_d", + "fmin.a.w" => "__builtin_msa_fmin_a_w", + "fmin.d" => "__builtin_msa_fmin_d", + "fmin.w" => "__builtin_msa_fmin_w", + "fmsub.d" => "__builtin_msa_fmsub_d", + "fmsub.w" => "__builtin_msa_fmsub_w", + "fmul.d" => "__builtin_msa_fmul_d", + "fmul.w" => "__builtin_msa_fmul_w", + "frcp.d" => "__builtin_msa_frcp_d", + "frcp.w" => "__builtin_msa_frcp_w", + "frint.d" => "__builtin_msa_frint_d", + "frint.w" => "__builtin_msa_frint_w", + "frsqrt.d" => "__builtin_msa_frsqrt_d", + "frsqrt.w" => "__builtin_msa_frsqrt_w", + "fsaf.d" => "__builtin_msa_fsaf_d", + "fsaf.w" => "__builtin_msa_fsaf_w", + "fseq.d" => "__builtin_msa_fseq_d", + "fseq.w" => "__builtin_msa_fseq_w", + "fsle.d" => "__builtin_msa_fsle_d", + "fsle.w" => "__builtin_msa_fsle_w", + "fslt.d" => "__builtin_msa_fslt_d", + "fslt.w" => "__builtin_msa_fslt_w", + "fsne.d" => "__builtin_msa_fsne_d", + "fsne.w" => "__builtin_msa_fsne_w", + "fsor.d" => "__builtin_msa_fsor_d", + "fsor.w" => "__builtin_msa_fsor_w", + "fsqrt.d" => "__builtin_msa_fsqrt_d", + "fsqrt.w" => "__builtin_msa_fsqrt_w", + "fsub.d" => "__builtin_msa_fsub_d", + "fsub.w" => "__builtin_msa_fsub_w", + "fsueq.d" => "__builtin_msa_fsueq_d", + "fsueq.w" => "__builtin_msa_fsueq_w", + "fsule.d" => "__builtin_msa_fsule_d", + "fsule.w" => "__builtin_msa_fsule_w", + "fsult.d" => "__builtin_msa_fsult_d", + "fsult.w" => "__builtin_msa_fsult_w", + "fsun.d" => "__builtin_msa_fsun_d", + "fsun.w" => "__builtin_msa_fsun_w", + "fsune.d" => "__builtin_msa_fsune_d", + "fsune.w" => "__builtin_msa_fsune_w", + "ftint.s.d" => "__builtin_msa_ftint_s_d", + "ftint.s.w" => "__builtin_msa_ftint_s_w", + "ftint.u.d" => "__builtin_msa_ftint_u_d", + "ftint.u.w" => "__builtin_msa_ftint_u_w", + "ftq.h" => "__builtin_msa_ftq_h", + "ftq.w" => "__builtin_msa_ftq_w", + "ftrunc.s.d" => "__builtin_msa_ftrunc_s_d", + "ftrunc.s.w" => "__builtin_msa_ftrunc_s_w", + "ftrunc.u.d" => "__builtin_msa_ftrunc_u_d", + "ftrunc.u.w" => "__builtin_msa_ftrunc_u_w", + "hadd.s.d" => "__builtin_msa_hadd_s_d", + "hadd.s.h" => "__builtin_msa_hadd_s_h", + "hadd.s.w" => "__builtin_msa_hadd_s_w", + "hadd.u.d" => "__builtin_msa_hadd_u_d", + "hadd.u.h" => "__builtin_msa_hadd_u_h", + "hadd.u.w" => "__builtin_msa_hadd_u_w", + "hsub.s.d" => "__builtin_msa_hsub_s_d", + "hsub.s.h" => "__builtin_msa_hsub_s_h", + "hsub.s.w" => "__builtin_msa_hsub_s_w", + "hsub.u.d" => "__builtin_msa_hsub_u_d", + "hsub.u.h" => "__builtin_msa_hsub_u_h", + "hsub.u.w" => "__builtin_msa_hsub_u_w", + "ilvev.b" => "__builtin_msa_ilvev_b", + "ilvev.d" => "__builtin_msa_ilvev_d", + "ilvev.h" => "__builtin_msa_ilvev_h", + "ilvev.w" => "__builtin_msa_ilvev_w", + "ilvl.b" => "__builtin_msa_ilvl_b", + "ilvl.d" => "__builtin_msa_ilvl_d", + "ilvl.h" => "__builtin_msa_ilvl_h", + "ilvl.w" => "__builtin_msa_ilvl_w", + "ilvod.b" => "__builtin_msa_ilvod_b", + "ilvod.d" => "__builtin_msa_ilvod_d", + "ilvod.h" => "__builtin_msa_ilvod_h", + "ilvod.w" => "__builtin_msa_ilvod_w", + "ilvr.b" => "__builtin_msa_ilvr_b", + "ilvr.d" => "__builtin_msa_ilvr_d", + "ilvr.h" => "__builtin_msa_ilvr_h", + "ilvr.w" => "__builtin_msa_ilvr_w", + "insert.b" => "__builtin_msa_insert_b", + "insert.d" => "__builtin_msa_insert_d", + "insert.h" => "__builtin_msa_insert_h", + "insert.w" => "__builtin_msa_insert_w", + "insv" => "__builtin_mips_insv", + "insve.b" => "__builtin_msa_insve_b", + "insve.d" => "__builtin_msa_insve_d", + "insve.h" => "__builtin_msa_insve_h", + "insve.w" => "__builtin_msa_insve_w", + "lbux" => "__builtin_mips_lbux", + "ld.b" => "__builtin_msa_ld_b", + "ld.d" => "__builtin_msa_ld_d", + "ld.h" => "__builtin_msa_ld_h", + "ld.w" => "__builtin_msa_ld_w", + "ldi.b" => "__builtin_msa_ldi_b", + "ldi.d" => "__builtin_msa_ldi_d", + "ldi.h" => "__builtin_msa_ldi_h", + "ldi.w" => "__builtin_msa_ldi_w", + "ldr.d" => "__builtin_msa_ldr_d", + "ldr.w" => "__builtin_msa_ldr_w", + "lhx" => "__builtin_mips_lhx", + "lsa" => "__builtin_mips_lsa", + "lwx" => "__builtin_mips_lwx", + "madd" => "__builtin_mips_madd", + "madd.q.h" => "__builtin_msa_madd_q_h", + "madd.q.w" => "__builtin_msa_madd_q_w", + "maddr.q.h" => "__builtin_msa_maddr_q_h", + "maddr.q.w" => "__builtin_msa_maddr_q_w", + "maddu" => "__builtin_mips_maddu", + "maddv.b" => "__builtin_msa_maddv_b", + "maddv.d" => "__builtin_msa_maddv_d", + "maddv.h" => "__builtin_msa_maddv_h", + "maddv.w" => "__builtin_msa_maddv_w", + "maq.s.w.phl" => "__builtin_mips_maq_s_w_phl", + "maq.s.w.phr" => "__builtin_mips_maq_s_w_phr", + "maq.sa.w.phl" => "__builtin_mips_maq_sa_w_phl", + "maq.sa.w.phr" => "__builtin_mips_maq_sa_w_phr", + "max.a.b" => "__builtin_msa_max_a_b", + "max.a.d" => "__builtin_msa_max_a_d", + "max.a.h" => "__builtin_msa_max_a_h", + "max.a.w" => "__builtin_msa_max_a_w", + "max.s.b" => "__builtin_msa_max_s_b", + "max.s.d" => "__builtin_msa_max_s_d", + "max.s.h" => "__builtin_msa_max_s_h", + "max.s.w" => "__builtin_msa_max_s_w", + "max.u.b" => "__builtin_msa_max_u_b", + "max.u.d" => "__builtin_msa_max_u_d", + "max.u.h" => "__builtin_msa_max_u_h", + "max.u.w" => "__builtin_msa_max_u_w", + "maxi.s.b" => "__builtin_msa_maxi_s_b", + "maxi.s.d" => "__builtin_msa_maxi_s_d", + "maxi.s.h" => "__builtin_msa_maxi_s_h", + "maxi.s.w" => "__builtin_msa_maxi_s_w", + "maxi.u.b" => "__builtin_msa_maxi_u_b", + "maxi.u.d" => "__builtin_msa_maxi_u_d", + "maxi.u.h" => "__builtin_msa_maxi_u_h", + "maxi.u.w" => "__builtin_msa_maxi_u_w", + "min.a.b" => "__builtin_msa_min_a_b", + "min.a.d" => "__builtin_msa_min_a_d", + "min.a.h" => "__builtin_msa_min_a_h", + "min.a.w" => "__builtin_msa_min_a_w", + "min.s.b" => "__builtin_msa_min_s_b", + "min.s.d" => "__builtin_msa_min_s_d", + "min.s.h" => "__builtin_msa_min_s_h", + "min.s.w" => "__builtin_msa_min_s_w", + "min.u.b" => "__builtin_msa_min_u_b", + "min.u.d" => "__builtin_msa_min_u_d", + "min.u.h" => "__builtin_msa_min_u_h", + "min.u.w" => "__builtin_msa_min_u_w", + "mini.s.b" => "__builtin_msa_mini_s_b", + "mini.s.d" => "__builtin_msa_mini_s_d", + "mini.s.h" => "__builtin_msa_mini_s_h", + "mini.s.w" => "__builtin_msa_mini_s_w", + "mini.u.b" => "__builtin_msa_mini_u_b", + "mini.u.d" => "__builtin_msa_mini_u_d", + "mini.u.h" => "__builtin_msa_mini_u_h", + "mini.u.w" => "__builtin_msa_mini_u_w", + "mod.s.b" => "__builtin_msa_mod_s_b", + "mod.s.d" => "__builtin_msa_mod_s_d", + "mod.s.h" => "__builtin_msa_mod_s_h", + "mod.s.w" => "__builtin_msa_mod_s_w", + "mod.u.b" => "__builtin_msa_mod_u_b", + "mod.u.d" => "__builtin_msa_mod_u_d", + "mod.u.h" => "__builtin_msa_mod_u_h", + "mod.u.w" => "__builtin_msa_mod_u_w", + "modsub" => "__builtin_mips_modsub", + "move.v" => "__builtin_msa_move_v", + "msub" => "__builtin_mips_msub", + "msub.q.h" => "__builtin_msa_msub_q_h", + "msub.q.w" => "__builtin_msa_msub_q_w", + "msubr.q.h" => "__builtin_msa_msubr_q_h", + "msubr.q.w" => "__builtin_msa_msubr_q_w", + "msubu" => "__builtin_mips_msubu", + "msubv.b" => "__builtin_msa_msubv_b", + "msubv.d" => "__builtin_msa_msubv_d", + "msubv.h" => "__builtin_msa_msubv_h", + "msubv.w" => "__builtin_msa_msubv_w", + "mthlip" => "__builtin_mips_mthlip", + "mul.ph" => "__builtin_mips_mul_ph", + "mul.q.h" => "__builtin_msa_mul_q_h", + "mul.q.w" => "__builtin_msa_mul_q_w", + "mul.s.ph" => "__builtin_mips_mul_s_ph", + "muleq.s.w.phl" => "__builtin_mips_muleq_s_w_phl", + "muleq.s.w.phr" => "__builtin_mips_muleq_s_w_phr", + "muleu.s.ph.qbl" => "__builtin_mips_muleu_s_ph_qbl", + "muleu.s.ph.qbr" => "__builtin_mips_muleu_s_ph_qbr", + "mulq.rs.ph" => "__builtin_mips_mulq_rs_ph", + "mulq.rs.w" => "__builtin_mips_mulq_rs_w", + "mulq.s.ph" => "__builtin_mips_mulq_s_ph", + "mulq.s.w" => "__builtin_mips_mulq_s_w", + "mulr.q.h" => "__builtin_msa_mulr_q_h", + "mulr.q.w" => "__builtin_msa_mulr_q_w", + "mulsa.w.ph" => "__builtin_mips_mulsa_w_ph", + "mulsaq.s.w.ph" => "__builtin_mips_mulsaq_s_w_ph", + "mult" => "__builtin_mips_mult", + "multu" => "__builtin_mips_multu", + "mulv.b" => "__builtin_msa_mulv_b", + "mulv.d" => "__builtin_msa_mulv_d", + "mulv.h" => "__builtin_msa_mulv_h", + "mulv.w" => "__builtin_msa_mulv_w", + "nloc.b" => "__builtin_msa_nloc_b", + "nloc.d" => "__builtin_msa_nloc_d", + "nloc.h" => "__builtin_msa_nloc_h", + "nloc.w" => "__builtin_msa_nloc_w", + "nlzc.b" => "__builtin_msa_nlzc_b", + "nlzc.d" => "__builtin_msa_nlzc_d", + "nlzc.h" => "__builtin_msa_nlzc_h", + "nlzc.w" => "__builtin_msa_nlzc_w", + "nor.v" => "__builtin_msa_nor_v", + "nori.b" => "__builtin_msa_nori_b", + "or.v" => "__builtin_msa_or_v", + "ori.b" => "__builtin_msa_ori_b", + "packrl.ph" => "__builtin_mips_packrl_ph", + "pckev.b" => "__builtin_msa_pckev_b", + "pckev.d" => "__builtin_msa_pckev_d", + "pckev.h" => "__builtin_msa_pckev_h", + "pckev.w" => "__builtin_msa_pckev_w", + "pckod.b" => "__builtin_msa_pckod_b", + "pckod.d" => "__builtin_msa_pckod_d", + "pckod.h" => "__builtin_msa_pckod_h", + "pckod.w" => "__builtin_msa_pckod_w", + "pcnt.b" => "__builtin_msa_pcnt_b", + "pcnt.d" => "__builtin_msa_pcnt_d", + "pcnt.h" => "__builtin_msa_pcnt_h", + "pcnt.w" => "__builtin_msa_pcnt_w", + "pick.ph" => "__builtin_mips_pick_ph", + "pick.qb" => "__builtin_mips_pick_qb", + "preceq.w.phl" => "__builtin_mips_preceq_w_phl", + "preceq.w.phr" => "__builtin_mips_preceq_w_phr", + "precequ.ph.qbl" => "__builtin_mips_precequ_ph_qbl", + "precequ.ph.qbla" => "__builtin_mips_precequ_ph_qbla", + "precequ.ph.qbr" => "__builtin_mips_precequ_ph_qbr", + "precequ.ph.qbra" => "__builtin_mips_precequ_ph_qbra", + "preceu.ph.qbl" => "__builtin_mips_preceu_ph_qbl", + "preceu.ph.qbla" => "__builtin_mips_preceu_ph_qbla", + "preceu.ph.qbr" => "__builtin_mips_preceu_ph_qbr", + "preceu.ph.qbra" => "__builtin_mips_preceu_ph_qbra", + "precr.qb.ph" => "__builtin_mips_precr_qb_ph", + "precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w", + "precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w", + "precrq.ph.w" => "__builtin_mips_precrq_ph_w", + "precrq.qb.ph" => "__builtin_mips_precrq_qb_ph", + "precrq.rs.ph.w" => "__builtin_mips_precrq_rs_ph_w", + "precrqu.s.qb.ph" => "__builtin_mips_precrqu_s_qb_ph", + "prepend" => "__builtin_mips_prepend", + "raddu.w.qb" => "__builtin_mips_raddu_w_qb", + "rddsp" => "__builtin_mips_rddsp", + "repl.ph" => "__builtin_mips_repl_ph", + "repl.qb" => "__builtin_mips_repl_qb", + "sat.s.b" => "__builtin_msa_sat_s_b", + "sat.s.d" => "__builtin_msa_sat_s_d", + "sat.s.h" => "__builtin_msa_sat_s_h", + "sat.s.w" => "__builtin_msa_sat_s_w", + "sat.u.b" => "__builtin_msa_sat_u_b", + "sat.u.d" => "__builtin_msa_sat_u_d", + "sat.u.h" => "__builtin_msa_sat_u_h", + "sat.u.w" => "__builtin_msa_sat_u_w", + "shf.b" => "__builtin_msa_shf_b", + "shf.h" => "__builtin_msa_shf_h", + "shf.w" => "__builtin_msa_shf_w", + "shilo" => "__builtin_mips_shilo", + "shll.ph" => "__builtin_mips_shll_ph", + "shll.qb" => "__builtin_mips_shll_qb", + "shll.s.ph" => "__builtin_mips_shll_s_ph", + "shll.s.w" => "__builtin_mips_shll_s_w", + "shra.ph" => "__builtin_mips_shra_ph", + "shra.qb" => "__builtin_mips_shra_qb", + "shra.r.ph" => "__builtin_mips_shra_r_ph", + "shra.r.qb" => "__builtin_mips_shra_r_qb", + "shra.r.w" => "__builtin_mips_shra_r_w", + "shrl.ph" => "__builtin_mips_shrl_ph", + "shrl.qb" => "__builtin_mips_shrl_qb", + "sld.b" => "__builtin_msa_sld_b", + "sld.d" => "__builtin_msa_sld_d", + "sld.h" => "__builtin_msa_sld_h", + "sld.w" => "__builtin_msa_sld_w", + "sldi.b" => "__builtin_msa_sldi_b", + "sldi.d" => "__builtin_msa_sldi_d", + "sldi.h" => "__builtin_msa_sldi_h", + "sldi.w" => "__builtin_msa_sldi_w", + "sll.b" => "__builtin_msa_sll_b", + "sll.d" => "__builtin_msa_sll_d", + "sll.h" => "__builtin_msa_sll_h", + "sll.w" => "__builtin_msa_sll_w", + "slli.b" => "__builtin_msa_slli_b", + "slli.d" => "__builtin_msa_slli_d", + "slli.h" => "__builtin_msa_slli_h", + "slli.w" => "__builtin_msa_slli_w", + "splat.b" => "__builtin_msa_splat_b", + "splat.d" => "__builtin_msa_splat_d", + "splat.h" => "__builtin_msa_splat_h", + "splat.w" => "__builtin_msa_splat_w", + "splati.b" => "__builtin_msa_splati_b", + "splati.d" => "__builtin_msa_splati_d", + "splati.h" => "__builtin_msa_splati_h", + "splati.w" => "__builtin_msa_splati_w", + "sra.b" => "__builtin_msa_sra_b", + "sra.d" => "__builtin_msa_sra_d", + "sra.h" => "__builtin_msa_sra_h", + "sra.w" => "__builtin_msa_sra_w", + "srai.b" => "__builtin_msa_srai_b", + "srai.d" => "__builtin_msa_srai_d", + "srai.h" => "__builtin_msa_srai_h", + "srai.w" => "__builtin_msa_srai_w", + "srar.b" => "__builtin_msa_srar_b", + "srar.d" => "__builtin_msa_srar_d", + "srar.h" => "__builtin_msa_srar_h", + "srar.w" => "__builtin_msa_srar_w", + "srari.b" => "__builtin_msa_srari_b", + "srari.d" => "__builtin_msa_srari_d", + "srari.h" => "__builtin_msa_srari_h", + "srari.w" => "__builtin_msa_srari_w", + "srl.b" => "__builtin_msa_srl_b", + "srl.d" => "__builtin_msa_srl_d", + "srl.h" => "__builtin_msa_srl_h", + "srl.w" => "__builtin_msa_srl_w", + "srli.b" => "__builtin_msa_srli_b", + "srli.d" => "__builtin_msa_srli_d", + "srli.h" => "__builtin_msa_srli_h", + "srli.w" => "__builtin_msa_srli_w", + "srlr.b" => "__builtin_msa_srlr_b", + "srlr.d" => "__builtin_msa_srlr_d", + "srlr.h" => "__builtin_msa_srlr_h", + "srlr.w" => "__builtin_msa_srlr_w", + "srlri.b" => "__builtin_msa_srlri_b", + "srlri.d" => "__builtin_msa_srlri_d", + "srlri.h" => "__builtin_msa_srlri_h", + "srlri.w" => "__builtin_msa_srlri_w", + "st.b" => "__builtin_msa_st_b", + "st.d" => "__builtin_msa_st_d", + "st.h" => "__builtin_msa_st_h", + "st.w" => "__builtin_msa_st_w", + "str.d" => "__builtin_msa_str_d", + "str.w" => "__builtin_msa_str_w", + "subq.ph" => "__builtin_mips_subq_ph", + "subq.s.ph" => "__builtin_mips_subq_s_ph", + "subq.s.w" => "__builtin_mips_subq_s_w", + "subqh.ph" => "__builtin_mips_subqh_ph", + "subqh.r.ph" => "__builtin_mips_subqh_r_ph", + "subqh.r.w" => "__builtin_mips_subqh_r_w", + "subqh.w" => "__builtin_mips_subqh_w", + "subs.s.b" => "__builtin_msa_subs_s_b", + "subs.s.d" => "__builtin_msa_subs_s_d", + "subs.s.h" => "__builtin_msa_subs_s_h", + "subs.s.w" => "__builtin_msa_subs_s_w", + "subs.u.b" => "__builtin_msa_subs_u_b", + "subs.u.d" => "__builtin_msa_subs_u_d", + "subs.u.h" => "__builtin_msa_subs_u_h", + "subs.u.w" => "__builtin_msa_subs_u_w", + "subsus.u.b" => "__builtin_msa_subsus_u_b", + "subsus.u.d" => "__builtin_msa_subsus_u_d", + "subsus.u.h" => "__builtin_msa_subsus_u_h", + "subsus.u.w" => "__builtin_msa_subsus_u_w", + "subsuu.s.b" => "__builtin_msa_subsuu_s_b", + "subsuu.s.d" => "__builtin_msa_subsuu_s_d", + "subsuu.s.h" => "__builtin_msa_subsuu_s_h", + "subsuu.s.w" => "__builtin_msa_subsuu_s_w", + "subu.ph" => "__builtin_mips_subu_ph", + "subu.qb" => "__builtin_mips_subu_qb", + "subu.s.ph" => "__builtin_mips_subu_s_ph", + "subu.s.qb" => "__builtin_mips_subu_s_qb", + "subuh.qb" => "__builtin_mips_subuh_qb", + "subuh.r.qb" => "__builtin_mips_subuh_r_qb", + "subv.b" => "__builtin_msa_subv_b", + "subv.d" => "__builtin_msa_subv_d", + "subv.h" => "__builtin_msa_subv_h", + "subv.w" => "__builtin_msa_subv_w", + "subvi.b" => "__builtin_msa_subvi_b", + "subvi.d" => "__builtin_msa_subvi_d", + "subvi.h" => "__builtin_msa_subvi_h", + "subvi.w" => "__builtin_msa_subvi_w", + "vshf.b" => "__builtin_msa_vshf_b", + "vshf.d" => "__builtin_msa_vshf_d", + "vshf.h" => "__builtin_msa_vshf_h", + "vshf.w" => "__builtin_msa_vshf_w", + "wrdsp" => "__builtin_mips_wrdsp", + "xor.v" => "__builtin_msa_xor_v", + "xori.b" => "__builtin_msa_xori_b", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + mips(name) + } + "nvvm" => { + #[allow(non_snake_case)] + fn nvvm(name: &str) -> &str { + match name { + // nvvm + "abs.i" => "__nvvm_abs_i", + "abs.ll" => "__nvvm_abs_ll", + "activemask" => "__nvvm_activemask", + "add.rm.d" => "__nvvm_add_rm_d", + "add.rm.f" => "__nvvm_add_rm_f", + "add.rm.ftz.f" => "__nvvm_add_rm_ftz_f", + "add.rn.d" => "__nvvm_add_rn_d", + "add.rn.f" => "__nvvm_add_rn_f", + "add.rn.ftz.f" => "__nvvm_add_rn_ftz_f", + "add.rp.d" => "__nvvm_add_rp_d", + "add.rp.f" => "__nvvm_add_rp_f", + "add.rp.ftz.f" => "__nvvm_add_rp_ftz_f", + "add.rz.d" => "__nvvm_add_rz_d", + "add.rz.f" => "__nvvm_add_rz_f", + "add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", + "bar.sync" => "__nvvm_bar_sync", + "bar.warp.sync" => "__nvvm_bar_warp_sync", + "barrier0" => "__nvvm_bar0", + // [DUPLICATE]: "barrier0" => "__syncthreads", + "barrier0.and" => "__nvvm_bar0_and", + "barrier0.or" => "__nvvm_bar0_or", + "barrier0.popc" => "__nvvm_bar0_popc", + "bf16x2.to.ue8m0x2.rp" => "__nvvm_bf16x2_to_ue8m0x2_rp", + "bf16x2.to.ue8m0x2.rp.satfinite" => "__nvvm_bf16x2_to_ue8m0x2_rp_satfinite", + "bf16x2.to.ue8m0x2.rz" => "__nvvm_bf16x2_to_ue8m0x2_rz", + "bf16x2.to.ue8m0x2.rz.satfinite" => "__nvvm_bf16x2_to_ue8m0x2_rz_satfinite", + "bf2h.rn" => "__nvvm_bf2h_rn", + "bf2h.rn.ftz" => "__nvvm_bf2h_rn_ftz", + "bitcast.d2ll" => "__nvvm_bitcast_d2ll", + "bitcast.f2i" => "__nvvm_bitcast_f2i", + "bitcast.i2f" => "__nvvm_bitcast_i2f", + "bitcast.ll2d" => "__nvvm_bitcast_ll2d", + "brev32" => "__nvvm_brev32", + "brev64" => "__nvvm_brev64", + "ceil.d" => "__nvvm_ceil_d", + "ceil.f" => "__nvvm_ceil_f", + "ceil.ftz.f" => "__nvvm_ceil_ftz_f", + "clz.i" => "__nvvm_clz_i", + "clz.ll" => "__nvvm_clz_ll", + "cos.approx.f" => "__nvvm_cos_approx_f", + "cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", + "cp.async.commit.group" => "__nvvm_cp_async_commit_group", + "cp.async.mbarrier.arrive" => "__nvvm_cp_async_mbarrier_arrive", + "cp.async.mbarrier.arrive.noinc" => "__nvvm_cp_async_mbarrier_arrive_noinc", + "cp.async.mbarrier.arrive.noinc.shared" => { + "__nvvm_cp_async_mbarrier_arrive_noinc_shared" + } + "cp.async.mbarrier.arrive.shared" => "__nvvm_cp_async_mbarrier_arrive_shared", + "cp.async.wait.all" => "__nvvm_cp_async_wait_all", + "cp.async.wait.group" => "__nvvm_cp_async_wait_group", + "d2f.rm" => "__nvvm_d2f_rm", + "d2f.rm.ftz" => "__nvvm_d2f_rm_ftz", + "d2f.rn" => "__nvvm_d2f_rn", + "d2f.rn.ftz" => "__nvvm_d2f_rn_ftz", + "d2f.rp" => "__nvvm_d2f_rp", + "d2f.rp.ftz" => "__nvvm_d2f_rp_ftz", + "d2f.rz" => "__nvvm_d2f_rz", + "d2f.rz.ftz" => "__nvvm_d2f_rz_ftz", + "d2i.hi" => "__nvvm_d2i_hi", + "d2i.lo" => "__nvvm_d2i_lo", + "d2i.rm" => "__nvvm_d2i_rm", + "d2i.rn" => "__nvvm_d2i_rn", + "d2i.rp" => "__nvvm_d2i_rp", + "d2i.rz" => "__nvvm_d2i_rz", + "d2ll.rm" => "__nvvm_d2ll_rm", + "d2ll.rn" => "__nvvm_d2ll_rn", + "d2ll.rp" => "__nvvm_d2ll_rp", + "d2ll.rz" => "__nvvm_d2ll_rz", + "d2ui.rm" => "__nvvm_d2ui_rm", + "d2ui.rn" => "__nvvm_d2ui_rn", + "d2ui.rp" => "__nvvm_d2ui_rp", + "d2ui.rz" => "__nvvm_d2ui_rz", + "d2ull.rm" => "__nvvm_d2ull_rm", + "d2ull.rn" => "__nvvm_d2ull_rn", + "d2ull.rp" => "__nvvm_d2ull_rp", + "d2ull.rz" => "__nvvm_d2ull_rz", + "div.approx.f" => "__nvvm_div_approx_f", + "div.approx.ftz.f" => "__nvvm_div_approx_ftz_f", + "div.full" => "__nvvm_div_full", + "div.full.ftz" => "__nvvm_div_full_ftz", + "div.rm.d" => "__nvvm_div_rm_d", + "div.rm.f" => "__nvvm_div_rm_f", + "div.rm.ftz.f" => "__nvvm_div_rm_ftz_f", + "div.rn.d" => "__nvvm_div_rn_d", + "div.rn.f" => "__nvvm_div_rn_f", + "div.rn.ftz.f" => "__nvvm_div_rn_ftz_f", + "div.rp.d" => "__nvvm_div_rp_d", + "div.rp.f" => "__nvvm_div_rp_f", + "div.rp.ftz.f" => "__nvvm_div_rp_ftz_f", + "div.rz.d" => "__nvvm_div_rz_d", + "div.rz.f" => "__nvvm_div_rz_f", + "div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", + "e2m1x2.to.f16x2.rn" => "__nvvm_e2m1x2_to_f16x2_rn", + "e2m1x2.to.f16x2.rn.relu" => "__nvvm_e2m1x2_to_f16x2_rn_relu", + "e2m3x2.to.f16x2.rn" => "__nvvm_e2m3x2_to_f16x2_rn", + "e2m3x2.to.f16x2.rn.relu" => "__nvvm_e2m3x2_to_f16x2_rn_relu", + "e3m2x2.to.f16x2.rn" => "__nvvm_e3m2x2_to_f16x2_rn", + "e3m2x2.to.f16x2.rn.relu" => "__nvvm_e3m2x2_to_f16x2_rn_relu", + "e4m3x2.to.f16x2.rn" => "__nvvm_e4m3x2_to_f16x2_rn", + "e4m3x2.to.f16x2.rn.relu" => "__nvvm_e4m3x2_to_f16x2_rn_relu", + "e5m2x2.to.f16x2.rn" => "__nvvm_e5m2x2_to_f16x2_rn", + "e5m2x2.to.f16x2.rn.relu" => "__nvvm_e5m2x2_to_f16x2_rn_relu", + "ex2.approx.d" => "__nvvm_ex2_approx_d", + "ex2.approx.f" => "__nvvm_ex2_approx_f", + "ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", + "exit" => "__nvvm_exit", + "f16x2.to.e4m3x2.rn" => "__nvvm_f16x2_to_e4m3x2_rn", + "f16x2.to.e4m3x2.rn.relu" => "__nvvm_f16x2_to_e4m3x2_rn_relu", + "f16x2.to.e5m2x2.rn" => "__nvvm_f16x2_to_e5m2x2_rn", + "f16x2.to.e5m2x2.rn.relu" => "__nvvm_f16x2_to_e5m2x2_rn_relu", + "f2bf16.rn" => "__nvvm_f2bf16_rn", + "f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu", + "f2bf16.rz" => "__nvvm_f2bf16_rz", + "f2bf16.rz.relu" => "__nvvm_f2bf16_rz_relu", + "f2h.rn" => "__nvvm_f2h_rn", + "f2h.rn.ftz" => "__nvvm_f2h_rn_ftz", + "f2i.rm" => "__nvvm_f2i_rm", + "f2i.rm.ftz" => "__nvvm_f2i_rm_ftz", + "f2i.rn" => "__nvvm_f2i_rn", + "f2i.rn.ftz" => "__nvvm_f2i_rn_ftz", + "f2i.rp" => "__nvvm_f2i_rp", + "f2i.rp.ftz" => "__nvvm_f2i_rp_ftz", + "f2i.rz" => "__nvvm_f2i_rz", + "f2i.rz.ftz" => "__nvvm_f2i_rz_ftz", + "f2ll.rm" => "__nvvm_f2ll_rm", + "f2ll.rm.ftz" => "__nvvm_f2ll_rm_ftz", + "f2ll.rn" => "__nvvm_f2ll_rn", + "f2ll.rn.ftz" => "__nvvm_f2ll_rn_ftz", + "f2ll.rp" => "__nvvm_f2ll_rp", + "f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz", + "f2ll.rz" => "__nvvm_f2ll_rz", + "f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz", + "f2tf32.rn" => "__nvvm_f2tf32_rn", + "f2tf32.rn.relu" => "__nvvm_f2tf32_rn_relu", + "f2tf32.rn.relu.satfinite" => "__nvvm_f2tf32_rn_relu_satfinite", + "f2tf32.rn.satfinite" => "__nvvm_f2tf32_rn_satfinite", + "f2tf32.rna" => "__nvvm_f2tf32_rna", + "f2tf32.rna.satfinite" => "__nvvm_f2tf32_rna_satfinite", + "f2tf32.rz" => "__nvvm_f2tf32_rz", + "f2tf32.rz.relu" => "__nvvm_f2tf32_rz_relu", + "f2tf32.rz.relu.satfinite" => "__nvvm_f2tf32_rz_relu_satfinite", + "f2tf32.rz.satfinite" => "__nvvm_f2tf32_rz_satfinite", + "f2ui.rm" => "__nvvm_f2ui_rm", + "f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz", + "f2ui.rn" => "__nvvm_f2ui_rn", + "f2ui.rn.ftz" => "__nvvm_f2ui_rn_ftz", + "f2ui.rp" => "__nvvm_f2ui_rp", + "f2ui.rp.ftz" => "__nvvm_f2ui_rp_ftz", + "f2ui.rz" => "__nvvm_f2ui_rz", + "f2ui.rz.ftz" => "__nvvm_f2ui_rz_ftz", + "f2ull.rm" => "__nvvm_f2ull_rm", + "f2ull.rm.ftz" => "__nvvm_f2ull_rm_ftz", + "f2ull.rn" => "__nvvm_f2ull_rn", + "f2ull.rn.ftz" => "__nvvm_f2ull_rn_ftz", + "f2ull.rp" => "__nvvm_f2ull_rp", + "f2ull.rp.ftz" => "__nvvm_f2ull_rp_ftz", + "f2ull.rz" => "__nvvm_f2ull_rz", + "f2ull.rz.ftz" => "__nvvm_f2ull_rz_ftz", + "fabs.d" => "__nvvm_fabs_d", + "fabs.f" => "__nvvm_fabs_f", + "fabs.ftz.f" => "__nvvm_fabs_ftz_f", + "ff.to.e2m1x2.rn.relu.satfinite" => "__nvvm_ff_to_e2m1x2_rn_relu_satfinite", + "ff.to.e2m1x2.rn.satfinite" => "__nvvm_ff_to_e2m1x2_rn_satfinite", + "ff.to.e2m3x2.rn.relu.satfinite" => "__nvvm_ff_to_e2m3x2_rn_relu_satfinite", + "ff.to.e2m3x2.rn.satfinite" => "__nvvm_ff_to_e2m3x2_rn_satfinite", + "ff.to.e3m2x2.rn.relu.satfinite" => "__nvvm_ff_to_e3m2x2_rn_relu_satfinite", + "ff.to.e3m2x2.rn.satfinite" => "__nvvm_ff_to_e3m2x2_rn_satfinite", + "ff.to.e4m3x2.rn" => "__nvvm_ff_to_e4m3x2_rn", + "ff.to.e4m3x2.rn.relu" => "__nvvm_ff_to_e4m3x2_rn_relu", + "ff.to.e5m2x2.rn" => "__nvvm_ff_to_e5m2x2_rn", + "ff.to.e5m2x2.rn.relu" => "__nvvm_ff_to_e5m2x2_rn_relu", + "ff.to.ue8m0x2.rp" => "__nvvm_ff_to_ue8m0x2_rp", + "ff.to.ue8m0x2.rp.satfinite" => "__nvvm_ff_to_ue8m0x2_rp_satfinite", + "ff.to.ue8m0x2.rz" => "__nvvm_ff_to_ue8m0x2_rz", + "ff.to.ue8m0x2.rz.satfinite" => "__nvvm_ff_to_ue8m0x2_rz_satfinite", + "ff2bf16x2.rn" => "__nvvm_ff2bf16x2_rn", + "ff2bf16x2.rn.relu" => "__nvvm_ff2bf16x2_rn_relu", + "ff2bf16x2.rz" => "__nvvm_ff2bf16x2_rz", + "ff2bf16x2.rz.relu" => "__nvvm_ff2bf16x2_rz_relu", + "ff2f16x2.rn" => "__nvvm_ff2f16x2_rn", + "ff2f16x2.rn.relu" => "__nvvm_ff2f16x2_rn_relu", + "ff2f16x2.rz" => "__nvvm_ff2f16x2_rz", + "ff2f16x2.rz.relu" => "__nvvm_ff2f16x2_rz_relu", + "floor.d" => "__nvvm_floor_d", + "floor.f" => "__nvvm_floor_f", + "floor.ftz.f" => "__nvvm_floor_ftz_f", + "fma.rm.d" => "__nvvm_fma_rm_d", + "fma.rm.f" => "__nvvm_fma_rm_f", + "fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f", + "fma.rn.bf16" => "__nvvm_fma_rn_bf16", + "fma.rn.bf16x2" => "__nvvm_fma_rn_bf16x2", + "fma.rn.d" => "__nvvm_fma_rn_d", + "fma.rn.f" => "__nvvm_fma_rn_f", + "fma.rn.ftz.bf16" => "__nvvm_fma_rn_ftz_bf16", + "fma.rn.ftz.bf16x2" => "__nvvm_fma_rn_ftz_bf16x2", + "fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", + "fma.rn.ftz.relu.bf16" => "__nvvm_fma_rn_ftz_relu_bf16", + "fma.rn.ftz.relu.bf16x2" => "__nvvm_fma_rn_ftz_relu_bf16x2", + "fma.rn.ftz.sat.bf16" => "__nvvm_fma_rn_ftz_sat_bf16", + "fma.rn.ftz.sat.bf16x2" => "__nvvm_fma_rn_ftz_sat_bf16x2", + "fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16", + "fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2", + "fma.rn.sat.bf16" => "__nvvm_fma_rn_sat_bf16", + "fma.rn.sat.bf16x2" => "__nvvm_fma_rn_sat_bf16x2", + "fma.rp.d" => "__nvvm_fma_rp_d", + "fma.rp.f" => "__nvvm_fma_rp_f", + "fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", + "fma.rz.d" => "__nvvm_fma_rz_d", + "fma.rz.f" => "__nvvm_fma_rz_f", + "fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f", + "fmax.bf16" => "__nvvm_fmax_bf16", + "fmax.bf16x2" => "__nvvm_fmax_bf16x2", + "fmax.d" => "__nvvm_fmax_d", + "fmax.f" => "__nvvm_fmax_f", + "fmax.ftz.bf16" => "__nvvm_fmax_ftz_bf16", + "fmax.ftz.bf16x2" => "__nvvm_fmax_ftz_bf16x2", + "fmax.ftz.f" => "__nvvm_fmax_ftz_f", + "fmax.ftz.nan.bf16" => "__nvvm_fmax_ftz_nan_bf16", + "fmax.ftz.nan.bf16x2" => "__nvvm_fmax_ftz_nan_bf16x2", + "fmax.ftz.nan.f" => "__nvvm_fmax_ftz_nan_f", + "fmax.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16", + "fmax.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16x2", + "fmax.ftz.nan.xorsign.abs.f" => "__nvvm_fmax_ftz_nan_xorsign_abs_f", + "fmax.ftz.xorsign.abs.bf16" => "__nvvm_fmax_ftz_xorsign_abs_bf16", + "fmax.ftz.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_xorsign_abs_bf16x2", + "fmax.ftz.xorsign.abs.f" => "__nvvm_fmax_ftz_xorsign_abs_f", + "fmax.nan.bf16" => "__nvvm_fmax_nan_bf16", + "fmax.nan.bf16x2" => "__nvvm_fmax_nan_bf16x2", + "fmax.nan.f" => "__nvvm_fmax_nan_f", + "fmax.nan.xorsign.abs.bf16" => "__nvvm_fmax_nan_xorsign_abs_bf16", + "fmax.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_nan_xorsign_abs_bf16x2", + "fmax.nan.xorsign.abs.f" => "__nvvm_fmax_nan_xorsign_abs_f", + "fmax.xorsign.abs.bf16" => "__nvvm_fmax_xorsign_abs_bf16", + "fmax.xorsign.abs.bf16x2" => "__nvvm_fmax_xorsign_abs_bf16x2", + "fmax.xorsign.abs.f" => "__nvvm_fmax_xorsign_abs_f", + "fmin.bf16" => "__nvvm_fmin_bf16", + "fmin.bf16x2" => "__nvvm_fmin_bf16x2", + "fmin.d" => "__nvvm_fmin_d", + "fmin.f" => "__nvvm_fmin_f", + "fmin.ftz.bf16" => "__nvvm_fmin_ftz_bf16", + "fmin.ftz.bf16x2" => "__nvvm_fmin_ftz_bf16x2", + "fmin.ftz.f" => "__nvvm_fmin_ftz_f", + "fmin.ftz.nan.bf16" => "__nvvm_fmin_ftz_nan_bf16", + "fmin.ftz.nan.bf16x2" => "__nvvm_fmin_ftz_nan_bf16x2", + "fmin.ftz.nan.f" => "__nvvm_fmin_ftz_nan_f", + "fmin.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16", + "fmin.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16x2", + "fmin.ftz.nan.xorsign.abs.f" => "__nvvm_fmin_ftz_nan_xorsign_abs_f", + "fmin.ftz.xorsign.abs.bf16" => "__nvvm_fmin_ftz_xorsign_abs_bf16", + "fmin.ftz.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_xorsign_abs_bf16x2", + "fmin.ftz.xorsign.abs.f" => "__nvvm_fmin_ftz_xorsign_abs_f", + "fmin.nan.bf16" => "__nvvm_fmin_nan_bf16", + "fmin.nan.bf16x2" => "__nvvm_fmin_nan_bf16x2", + "fmin.nan.f" => "__nvvm_fmin_nan_f", + "fmin.nan.xorsign.abs.bf16" => "__nvvm_fmin_nan_xorsign_abs_bf16", + "fmin.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_nan_xorsign_abs_bf16x2", + "fmin.nan.xorsign.abs.f" => "__nvvm_fmin_nan_xorsign_abs_f", + "fmin.xorsign.abs.bf16" => "__nvvm_fmin_xorsign_abs_bf16", + "fmin.xorsign.abs.bf16x2" => "__nvvm_fmin_xorsign_abs_bf16x2", + "fmin.xorsign.abs.f" => "__nvvm_fmin_xorsign_abs_f", + "fns" => "__nvvm_fns", + "h2f" => "__nvvm_h2f", + "i2d.rm" => "__nvvm_i2d_rm", + "i2d.rn" => "__nvvm_i2d_rn", + "i2d.rp" => "__nvvm_i2d_rp", + "i2d.rz" => "__nvvm_i2d_rz", + "i2f.rm" => "__nvvm_i2f_rm", + "i2f.rn" => "__nvvm_i2f_rn", + "i2f.rp" => "__nvvm_i2f_rp", + "i2f.rz" => "__nvvm_i2f_rz", + "isspacep.const" => "__nvvm_isspacep_const", + "isspacep.global" => "__nvvm_isspacep_global", + "isspacep.local" => "__nvvm_isspacep_local", + "isspacep.shared" => "__nvvm_isspacep_shared", + "isspacep.shared.cluster" => "__nvvm_isspacep_shared_cluster", + "istypep.sampler" => "__nvvm_istypep_sampler", + "istypep.surface" => "__nvvm_istypep_surface", + "istypep.texture" => "__nvvm_istypep_texture", + "lg2.approx.d" => "__nvvm_lg2_approx_d", + "lg2.approx.f" => "__nvvm_lg2_approx_f", + "lg2.approx.ftz.f" => "__nvvm_lg2_approx_ftz_f", + "ll2d.rm" => "__nvvm_ll2d_rm", + "ll2d.rn" => "__nvvm_ll2d_rn", + "ll2d.rp" => "__nvvm_ll2d_rp", + "ll2d.rz" => "__nvvm_ll2d_rz", + "ll2f.rm" => "__nvvm_ll2f_rm", + "ll2f.rn" => "__nvvm_ll2f_rn", + "ll2f.rp" => "__nvvm_ll2f_rp", + "ll2f.rz" => "__nvvm_ll2f_rz", + "lohi.i2d" => "__nvvm_lohi_i2d", + "match.any.sync.i32" => "__nvvm_match_any_sync_i32", + "match.any.sync.i64" => "__nvvm_match_any_sync_i64", + "max.i" => "__nvvm_max_i", + "max.ll" => "__nvvm_max_ll", + "max.ui" => "__nvvm_max_ui", + "max.ull" => "__nvvm_max_ull", + "mbarrier.arrive" => "__nvvm_mbarrier_arrive", + "mbarrier.arrive.drop" => "__nvvm_mbarrier_arrive_drop", + "mbarrier.arrive.drop.noComplete" => "__nvvm_mbarrier_arrive_drop_noComplete", + "mbarrier.arrive.drop.noComplete.shared" => { + "__nvvm_mbarrier_arrive_drop_noComplete_shared" + } + "mbarrier.arrive.drop.shared" => "__nvvm_mbarrier_arrive_drop_shared", + "mbarrier.arrive.noComplete" => "__nvvm_mbarrier_arrive_noComplete", + "mbarrier.arrive.noComplete.shared" => { + "__nvvm_mbarrier_arrive_noComplete_shared" + } + "mbarrier.arrive.shared" => "__nvvm_mbarrier_arrive_shared", + "mbarrier.init" => "__nvvm_mbarrier_init", + "mbarrier.init.shared" => "__nvvm_mbarrier_init_shared", + "mbarrier.inval" => "__nvvm_mbarrier_inval", + "mbarrier.inval.shared" => "__nvvm_mbarrier_inval_shared", + "mbarrier.pending.count" => "__nvvm_mbarrier_pending_count", + "mbarrier.test.wait" => "__nvvm_mbarrier_test_wait", + "mbarrier.test.wait.shared" => "__nvvm_mbarrier_test_wait_shared", + "membar.cta" => "__nvvm_membar_cta", + "membar.gl" => "__nvvm_membar_gl", + "membar.sys" => "__nvvm_membar_sys", + "min.i" => "__nvvm_min_i", + "min.ll" => "__nvvm_min_ll", + "min.ui" => "__nvvm_min_ui", + "min.ull" => "__nvvm_min_ull", + "mul.rm.d" => "__nvvm_mul_rm_d", + "mul.rm.f" => "__nvvm_mul_rm_f", + "mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f", + "mul.rn.d" => "__nvvm_mul_rn_d", + "mul.rn.f" => "__nvvm_mul_rn_f", + "mul.rn.ftz.f" => "__nvvm_mul_rn_ftz_f", + "mul.rp.d" => "__nvvm_mul_rp_d", + "mul.rp.f" => "__nvvm_mul_rp_f", + "mul.rp.ftz.f" => "__nvvm_mul_rp_ftz_f", + "mul.rz.d" => "__nvvm_mul_rz_d", + "mul.rz.f" => "__nvvm_mul_rz_f", + "mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f", + "mul24.i" => "__nvvm_mul24_i", + "mul24.ui" => "__nvvm_mul24_ui", + "mulhi.i" => "__nvvm_mulhi_i", + "mulhi.ll" => "__nvvm_mulhi_ll", + "mulhi.s" => "__nvvm_mulhi_s", + "mulhi.ui" => "__nvvm_mulhi_ui", + "mulhi.ull" => "__nvvm_mulhi_ull", + "mulhi.us" => "__nvvm_mulhi_us", + "nanosleep" => "__nvvm_nanosleep", + "neg.bf16" => "__nvvm_neg_bf16", + "neg.bf16x2" => "__nvvm_neg_bf16x2", + "popc.i" => "__nvvm_popc_i", + "popc.ll" => "__nvvm_popc_ll", + "prmt" => "__nvvm_prmt", + "rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", + "rcp.approx.ftz.f" => "__nvvm_rcp_approx_ftz_f", + "rcp.rm.d" => "__nvvm_rcp_rm_d", + "rcp.rm.f" => "__nvvm_rcp_rm_f", + "rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f", + "rcp.rn.d" => "__nvvm_rcp_rn_d", + "rcp.rn.f" => "__nvvm_rcp_rn_f", + "rcp.rn.ftz.f" => "__nvvm_rcp_rn_ftz_f", + "rcp.rp.d" => "__nvvm_rcp_rp_d", + "rcp.rp.f" => "__nvvm_rcp_rp_f", + "rcp.rp.ftz.f" => "__nvvm_rcp_rp_ftz_f", + "rcp.rz.d" => "__nvvm_rcp_rz_d", + "rcp.rz.f" => "__nvvm_rcp_rz_f", + "rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", + "read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_clock", + // [DUPLICATE]: "read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_clock64", + // [DUPLICATE]: "read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.ctaid.w" => "__nvvm_read_ptx_sreg_ctaid_w", + "read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", + "read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", + "read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", + "read.ptx.sreg.envreg0" => "__nvvm_read_ptx_sreg_envreg0", + "read.ptx.sreg.envreg1" => "__nvvm_read_ptx_sreg_envreg1", + "read.ptx.sreg.envreg10" => "__nvvm_read_ptx_sreg_envreg10", + "read.ptx.sreg.envreg11" => "__nvvm_read_ptx_sreg_envreg11", + "read.ptx.sreg.envreg12" => "__nvvm_read_ptx_sreg_envreg12", + "read.ptx.sreg.envreg13" => "__nvvm_read_ptx_sreg_envreg13", + "read.ptx.sreg.envreg14" => "__nvvm_read_ptx_sreg_envreg14", + "read.ptx.sreg.envreg15" => "__nvvm_read_ptx_sreg_envreg15", + "read.ptx.sreg.envreg16" => "__nvvm_read_ptx_sreg_envreg16", + "read.ptx.sreg.envreg17" => "__nvvm_read_ptx_sreg_envreg17", + "read.ptx.sreg.envreg18" => "__nvvm_read_ptx_sreg_envreg18", + "read.ptx.sreg.envreg19" => "__nvvm_read_ptx_sreg_envreg19", + "read.ptx.sreg.envreg2" => "__nvvm_read_ptx_sreg_envreg2", + "read.ptx.sreg.envreg20" => "__nvvm_read_ptx_sreg_envreg20", + "read.ptx.sreg.envreg21" => "__nvvm_read_ptx_sreg_envreg21", + "read.ptx.sreg.envreg22" => "__nvvm_read_ptx_sreg_envreg22", + "read.ptx.sreg.envreg23" => "__nvvm_read_ptx_sreg_envreg23", + "read.ptx.sreg.envreg24" => "__nvvm_read_ptx_sreg_envreg24", + "read.ptx.sreg.envreg25" => "__nvvm_read_ptx_sreg_envreg25", + "read.ptx.sreg.envreg26" => "__nvvm_read_ptx_sreg_envreg26", + "read.ptx.sreg.envreg27" => "__nvvm_read_ptx_sreg_envreg27", + "read.ptx.sreg.envreg28" => "__nvvm_read_ptx_sreg_envreg28", + "read.ptx.sreg.envreg29" => "__nvvm_read_ptx_sreg_envreg29", + "read.ptx.sreg.envreg3" => "__nvvm_read_ptx_sreg_envreg3", + "read.ptx.sreg.envreg30" => "__nvvm_read_ptx_sreg_envreg30", + "read.ptx.sreg.envreg31" => "__nvvm_read_ptx_sreg_envreg31", + "read.ptx.sreg.envreg4" => "__nvvm_read_ptx_sreg_envreg4", + "read.ptx.sreg.envreg5" => "__nvvm_read_ptx_sreg_envreg5", + "read.ptx.sreg.envreg6" => "__nvvm_read_ptx_sreg_envreg6", + "read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", + "read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", + "read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", + "read.ptx.sreg.globaltimer" => "__nvvm_read_ptx_sreg_globaltimer", + "read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_gridid", + // [DUPLICATE]: "read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_laneid", + // [DUPLICATE]: "read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_lanemask_eq", + // [DUPLICATE]: "read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_lanemask_ge", + // [DUPLICATE]: "read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_lanemask_gt", + // [DUPLICATE]: "read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_lanemask_le", + // [DUPLICATE]: "read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_lanemask_lt", + // [DUPLICATE]: "read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.nctaid.w" => "__nvvm_read_ptx_sreg_nctaid_w", + "read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", + "read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", + "read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", + "read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_nsmid", + // [DUPLICATE]: "read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.ntid.w" => "__nvvm_read_ptx_sreg_ntid_w", + "read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", + "read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", + "read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", + "read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_nwarpid", + // [DUPLICATE]: "read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_pm0", + // [DUPLICATE]: "read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_pm1", + // [DUPLICATE]: "read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_pm2", + // [DUPLICATE]: "read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_pm3", + // [DUPLICATE]: "read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_smid", + // [DUPLICATE]: "read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.tid.w" => "__nvvm_read_ptx_sreg_tid_w", + "read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", + "read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", + "read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", + "read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_warpid", + // [DUPLICATE]: "read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_", + "read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", + // [DUPLICATE]: "read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_", + "redux.sync.add" => "__nvvm_redux_sync_add", + "redux.sync.and" => "__nvvm_redux_sync_and", + "redux.sync.fmax" => "__nvvm_redux_sync_fmax", + "redux.sync.fmax.NaN" => "__nvvm_redux_sync_fmax_NaN", + "redux.sync.fmax.abs" => "__nvvm_redux_sync_fmax_abs", + "redux.sync.fmax.abs.NaN" => "__nvvm_redux_sync_fmax_abs_NaN", + "redux.sync.fmin" => "__nvvm_redux_sync_fmin", + "redux.sync.fmin.NaN" => "__nvvm_redux_sync_fmin_NaN", + "redux.sync.fmin.abs" => "__nvvm_redux_sync_fmin_abs", + "redux.sync.fmin.abs.NaN" => "__nvvm_redux_sync_fmin_abs_NaN", + "redux.sync.max" => "__nvvm_redux_sync_max", + "redux.sync.min" => "__nvvm_redux_sync_min", + "redux.sync.or" => "__nvvm_redux_sync_or", + "redux.sync.umax" => "__nvvm_redux_sync_umax", + "redux.sync.umin" => "__nvvm_redux_sync_umin", + "redux.sync.xor" => "__nvvm_redux_sync_xor", + "reflect" => "__nvvm_reflect", + "rotate.b32" => "__nvvm_rotate_b32", + "rotate.b64" => "__nvvm_rotate_b64", + "rotate.right.b64" => "__nvvm_rotate_right_b64", + "round.d" => "__nvvm_round_d", + "round.f" => "__nvvm_round_f", + "round.ftz.f" => "__nvvm_round_ftz_f", + "rsqrt.approx.d" => "__nvvm_rsqrt_approx_d", + "rsqrt.approx.f" => "__nvvm_rsqrt_approx_f", + "rsqrt.approx.ftz.d" => "__nvvm_rsqrt_approx_ftz_d", + "rsqrt.approx.ftz.f" => "__nvvm_rsqrt_approx_ftz_f", + "sad.i" => "__nvvm_sad_i", + "sad.ll" => "__nvvm_sad_ll", + "sad.s" => "__nvvm_sad_s", + "sad.ui" => "__nvvm_sad_ui", + "sad.ull" => "__nvvm_sad_ull", + "sad.us" => "__nvvm_sad_us", + "saturate.d" => "__nvvm_saturate_d", + "saturate.f" => "__nvvm_saturate_f", + "saturate.ftz.f" => "__nvvm_saturate_ftz_f", + "shfl.bfly.f32" => "__nvvm_shfl_bfly_f32", + "shfl.bfly.i32" => "__nvvm_shfl_bfly_i32", + "shfl.down.f32" => "__nvvm_shfl_down_f32", + "shfl.down.i32" => "__nvvm_shfl_down_i32", + "shfl.idx.f32" => "__nvvm_shfl_idx_f32", + "shfl.idx.i32" => "__nvvm_shfl_idx_i32", + "shfl.sync.bfly.f32" => "__nvvm_shfl_sync_bfly_f32", + "shfl.sync.bfly.i32" => "__nvvm_shfl_sync_bfly_i32", + "shfl.sync.down.f32" => "__nvvm_shfl_sync_down_f32", + "shfl.sync.down.i32" => "__nvvm_shfl_sync_down_i32", + "shfl.sync.idx.f32" => "__nvvm_shfl_sync_idx_f32", + "shfl.sync.idx.i32" => "__nvvm_shfl_sync_idx_i32", + "shfl.sync.up.f32" => "__nvvm_shfl_sync_up_f32", + "shfl.sync.up.i32" => "__nvvm_shfl_sync_up_i32", + "shfl.up.f32" => "__nvvm_shfl_up_f32", + "shfl.up.i32" => "__nvvm_shfl_up_i32", + "sin.approx.f" => "__nvvm_sin_approx_f", + "sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f", + "sqrt.approx.f" => "__nvvm_sqrt_approx_f", + "sqrt.approx.ftz.f" => "__nvvm_sqrt_approx_ftz_f", + "sqrt.f" => "__nvvm_sqrt_f", + "sqrt.rm.d" => "__nvvm_sqrt_rm_d", + "sqrt.rm.f" => "__nvvm_sqrt_rm_f", + "sqrt.rm.ftz.f" => "__nvvm_sqrt_rm_ftz_f", + "sqrt.rn.d" => "__nvvm_sqrt_rn_d", + "sqrt.rn.f" => "__nvvm_sqrt_rn_f", + "sqrt.rn.ftz.f" => "__nvvm_sqrt_rn_ftz_f", + "sqrt.rp.d" => "__nvvm_sqrt_rp_d", + "sqrt.rp.f" => "__nvvm_sqrt_rp_f", + "sqrt.rp.ftz.f" => "__nvvm_sqrt_rp_ftz_f", + "sqrt.rz.d" => "__nvvm_sqrt_rz_d", + "sqrt.rz.f" => "__nvvm_sqrt_rz_f", + "sqrt.rz.ftz.f" => "__nvvm_sqrt_rz_ftz_f", + "suq.array.size" => "__nvvm_suq_array_size", + "suq.channel.data.type" => "__nvvm_suq_channel_data_type", + "suq.channel.order" => "__nvvm_suq_channel_order", + "suq.depth" => "__nvvm_suq_depth", + "suq.height" => "__nvvm_suq_height", + "suq.width" => "__nvvm_suq_width", + "sust.b.1d.array.i16.clamp" => "__nvvm_sust_b_1d_array_i16_clamp", + "sust.b.1d.array.i16.trap" => "__nvvm_sust_b_1d_array_i16_trap", + "sust.b.1d.array.i16.zero" => "__nvvm_sust_b_1d_array_i16_zero", + "sust.b.1d.array.i32.clamp" => "__nvvm_sust_b_1d_array_i32_clamp", + "sust.b.1d.array.i32.trap" => "__nvvm_sust_b_1d_array_i32_trap", + "sust.b.1d.array.i32.zero" => "__nvvm_sust_b_1d_array_i32_zero", + "sust.b.1d.array.i64.clamp" => "__nvvm_sust_b_1d_array_i64_clamp", + "sust.b.1d.array.i64.trap" => "__nvvm_sust_b_1d_array_i64_trap", + "sust.b.1d.array.i64.zero" => "__nvvm_sust_b_1d_array_i64_zero", + "sust.b.1d.array.i8.clamp" => "__nvvm_sust_b_1d_array_i8_clamp", + "sust.b.1d.array.i8.trap" => "__nvvm_sust_b_1d_array_i8_trap", + "sust.b.1d.array.i8.zero" => "__nvvm_sust_b_1d_array_i8_zero", + "sust.b.1d.array.v2i16.clamp" => "__nvvm_sust_b_1d_array_v2i16_clamp", + "sust.b.1d.array.v2i16.trap" => "__nvvm_sust_b_1d_array_v2i16_trap", + "sust.b.1d.array.v2i16.zero" => "__nvvm_sust_b_1d_array_v2i16_zero", + "sust.b.1d.array.v2i32.clamp" => "__nvvm_sust_b_1d_array_v2i32_clamp", + "sust.b.1d.array.v2i32.trap" => "__nvvm_sust_b_1d_array_v2i32_trap", + "sust.b.1d.array.v2i32.zero" => "__nvvm_sust_b_1d_array_v2i32_zero", + "sust.b.1d.array.v2i64.clamp" => "__nvvm_sust_b_1d_array_v2i64_clamp", + "sust.b.1d.array.v2i64.trap" => "__nvvm_sust_b_1d_array_v2i64_trap", + "sust.b.1d.array.v2i64.zero" => "__nvvm_sust_b_1d_array_v2i64_zero", + "sust.b.1d.array.v2i8.clamp" => "__nvvm_sust_b_1d_array_v2i8_clamp", + "sust.b.1d.array.v2i8.trap" => "__nvvm_sust_b_1d_array_v2i8_trap", + "sust.b.1d.array.v2i8.zero" => "__nvvm_sust_b_1d_array_v2i8_zero", + "sust.b.1d.array.v4i16.clamp" => "__nvvm_sust_b_1d_array_v4i16_clamp", + "sust.b.1d.array.v4i16.trap" => "__nvvm_sust_b_1d_array_v4i16_trap", + "sust.b.1d.array.v4i16.zero" => "__nvvm_sust_b_1d_array_v4i16_zero", + "sust.b.1d.array.v4i32.clamp" => "__nvvm_sust_b_1d_array_v4i32_clamp", + "sust.b.1d.array.v4i32.trap" => "__nvvm_sust_b_1d_array_v4i32_trap", + "sust.b.1d.array.v4i32.zero" => "__nvvm_sust_b_1d_array_v4i32_zero", + "sust.b.1d.array.v4i8.clamp" => "__nvvm_sust_b_1d_array_v4i8_clamp", + "sust.b.1d.array.v4i8.trap" => "__nvvm_sust_b_1d_array_v4i8_trap", + "sust.b.1d.array.v4i8.zero" => "__nvvm_sust_b_1d_array_v4i8_zero", + "sust.b.1d.i16.clamp" => "__nvvm_sust_b_1d_i16_clamp", + "sust.b.1d.i16.trap" => "__nvvm_sust_b_1d_i16_trap", + "sust.b.1d.i16.zero" => "__nvvm_sust_b_1d_i16_zero", + "sust.b.1d.i32.clamp" => "__nvvm_sust_b_1d_i32_clamp", + "sust.b.1d.i32.trap" => "__nvvm_sust_b_1d_i32_trap", + "sust.b.1d.i32.zero" => "__nvvm_sust_b_1d_i32_zero", + "sust.b.1d.i64.clamp" => "__nvvm_sust_b_1d_i64_clamp", + "sust.b.1d.i64.trap" => "__nvvm_sust_b_1d_i64_trap", + "sust.b.1d.i64.zero" => "__nvvm_sust_b_1d_i64_zero", + "sust.b.1d.i8.clamp" => "__nvvm_sust_b_1d_i8_clamp", + "sust.b.1d.i8.trap" => "__nvvm_sust_b_1d_i8_trap", + "sust.b.1d.i8.zero" => "__nvvm_sust_b_1d_i8_zero", + "sust.b.1d.v2i16.clamp" => "__nvvm_sust_b_1d_v2i16_clamp", + "sust.b.1d.v2i16.trap" => "__nvvm_sust_b_1d_v2i16_trap", + "sust.b.1d.v2i16.zero" => "__nvvm_sust_b_1d_v2i16_zero", + "sust.b.1d.v2i32.clamp" => "__nvvm_sust_b_1d_v2i32_clamp", + "sust.b.1d.v2i32.trap" => "__nvvm_sust_b_1d_v2i32_trap", + "sust.b.1d.v2i32.zero" => "__nvvm_sust_b_1d_v2i32_zero", + "sust.b.1d.v2i64.clamp" => "__nvvm_sust_b_1d_v2i64_clamp", + "sust.b.1d.v2i64.trap" => "__nvvm_sust_b_1d_v2i64_trap", + "sust.b.1d.v2i64.zero" => "__nvvm_sust_b_1d_v2i64_zero", + "sust.b.1d.v2i8.clamp" => "__nvvm_sust_b_1d_v2i8_clamp", + "sust.b.1d.v2i8.trap" => "__nvvm_sust_b_1d_v2i8_trap", + "sust.b.1d.v2i8.zero" => "__nvvm_sust_b_1d_v2i8_zero", + "sust.b.1d.v4i16.clamp" => "__nvvm_sust_b_1d_v4i16_clamp", + "sust.b.1d.v4i16.trap" => "__nvvm_sust_b_1d_v4i16_trap", + "sust.b.1d.v4i16.zero" => "__nvvm_sust_b_1d_v4i16_zero", + "sust.b.1d.v4i32.clamp" => "__nvvm_sust_b_1d_v4i32_clamp", + "sust.b.1d.v4i32.trap" => "__nvvm_sust_b_1d_v4i32_trap", + "sust.b.1d.v4i32.zero" => "__nvvm_sust_b_1d_v4i32_zero", + "sust.b.1d.v4i8.clamp" => "__nvvm_sust_b_1d_v4i8_clamp", + "sust.b.1d.v4i8.trap" => "__nvvm_sust_b_1d_v4i8_trap", + "sust.b.1d.v4i8.zero" => "__nvvm_sust_b_1d_v4i8_zero", + "sust.b.2d.array.i16.clamp" => "__nvvm_sust_b_2d_array_i16_clamp", + "sust.b.2d.array.i16.trap" => "__nvvm_sust_b_2d_array_i16_trap", + "sust.b.2d.array.i16.zero" => "__nvvm_sust_b_2d_array_i16_zero", + "sust.b.2d.array.i32.clamp" => "__nvvm_sust_b_2d_array_i32_clamp", + "sust.b.2d.array.i32.trap" => "__nvvm_sust_b_2d_array_i32_trap", + "sust.b.2d.array.i32.zero" => "__nvvm_sust_b_2d_array_i32_zero", + "sust.b.2d.array.i64.clamp" => "__nvvm_sust_b_2d_array_i64_clamp", + "sust.b.2d.array.i64.trap" => "__nvvm_sust_b_2d_array_i64_trap", + "sust.b.2d.array.i64.zero" => "__nvvm_sust_b_2d_array_i64_zero", + "sust.b.2d.array.i8.clamp" => "__nvvm_sust_b_2d_array_i8_clamp", + "sust.b.2d.array.i8.trap" => "__nvvm_sust_b_2d_array_i8_trap", + "sust.b.2d.array.i8.zero" => "__nvvm_sust_b_2d_array_i8_zero", + "sust.b.2d.array.v2i16.clamp" => "__nvvm_sust_b_2d_array_v2i16_clamp", + "sust.b.2d.array.v2i16.trap" => "__nvvm_sust_b_2d_array_v2i16_trap", + "sust.b.2d.array.v2i16.zero" => "__nvvm_sust_b_2d_array_v2i16_zero", + "sust.b.2d.array.v2i32.clamp" => "__nvvm_sust_b_2d_array_v2i32_clamp", + "sust.b.2d.array.v2i32.trap" => "__nvvm_sust_b_2d_array_v2i32_trap", + "sust.b.2d.array.v2i32.zero" => "__nvvm_sust_b_2d_array_v2i32_zero", + "sust.b.2d.array.v2i64.clamp" => "__nvvm_sust_b_2d_array_v2i64_clamp", + "sust.b.2d.array.v2i64.trap" => "__nvvm_sust_b_2d_array_v2i64_trap", + "sust.b.2d.array.v2i64.zero" => "__nvvm_sust_b_2d_array_v2i64_zero", + "sust.b.2d.array.v2i8.clamp" => "__nvvm_sust_b_2d_array_v2i8_clamp", + "sust.b.2d.array.v2i8.trap" => "__nvvm_sust_b_2d_array_v2i8_trap", + "sust.b.2d.array.v2i8.zero" => "__nvvm_sust_b_2d_array_v2i8_zero", + "sust.b.2d.array.v4i16.clamp" => "__nvvm_sust_b_2d_array_v4i16_clamp", + "sust.b.2d.array.v4i16.trap" => "__nvvm_sust_b_2d_array_v4i16_trap", + "sust.b.2d.array.v4i16.zero" => "__nvvm_sust_b_2d_array_v4i16_zero", + "sust.b.2d.array.v4i32.clamp" => "__nvvm_sust_b_2d_array_v4i32_clamp", + "sust.b.2d.array.v4i32.trap" => "__nvvm_sust_b_2d_array_v4i32_trap", + "sust.b.2d.array.v4i32.zero" => "__nvvm_sust_b_2d_array_v4i32_zero", + "sust.b.2d.array.v4i8.clamp" => "__nvvm_sust_b_2d_array_v4i8_clamp", + "sust.b.2d.array.v4i8.trap" => "__nvvm_sust_b_2d_array_v4i8_trap", + "sust.b.2d.array.v4i8.zero" => "__nvvm_sust_b_2d_array_v4i8_zero", + "sust.b.2d.i16.clamp" => "__nvvm_sust_b_2d_i16_clamp", + "sust.b.2d.i16.trap" => "__nvvm_sust_b_2d_i16_trap", + "sust.b.2d.i16.zero" => "__nvvm_sust_b_2d_i16_zero", + "sust.b.2d.i32.clamp" => "__nvvm_sust_b_2d_i32_clamp", + "sust.b.2d.i32.trap" => "__nvvm_sust_b_2d_i32_trap", + "sust.b.2d.i32.zero" => "__nvvm_sust_b_2d_i32_zero", + "sust.b.2d.i64.clamp" => "__nvvm_sust_b_2d_i64_clamp", + "sust.b.2d.i64.trap" => "__nvvm_sust_b_2d_i64_trap", + "sust.b.2d.i64.zero" => "__nvvm_sust_b_2d_i64_zero", + "sust.b.2d.i8.clamp" => "__nvvm_sust_b_2d_i8_clamp", + "sust.b.2d.i8.trap" => "__nvvm_sust_b_2d_i8_trap", + "sust.b.2d.i8.zero" => "__nvvm_sust_b_2d_i8_zero", + "sust.b.2d.v2i16.clamp" => "__nvvm_sust_b_2d_v2i16_clamp", + "sust.b.2d.v2i16.trap" => "__nvvm_sust_b_2d_v2i16_trap", + "sust.b.2d.v2i16.zero" => "__nvvm_sust_b_2d_v2i16_zero", + "sust.b.2d.v2i32.clamp" => "__nvvm_sust_b_2d_v2i32_clamp", + "sust.b.2d.v2i32.trap" => "__nvvm_sust_b_2d_v2i32_trap", + "sust.b.2d.v2i32.zero" => "__nvvm_sust_b_2d_v2i32_zero", + "sust.b.2d.v2i64.clamp" => "__nvvm_sust_b_2d_v2i64_clamp", + "sust.b.2d.v2i64.trap" => "__nvvm_sust_b_2d_v2i64_trap", + "sust.b.2d.v2i64.zero" => "__nvvm_sust_b_2d_v2i64_zero", + "sust.b.2d.v2i8.clamp" => "__nvvm_sust_b_2d_v2i8_clamp", + "sust.b.2d.v2i8.trap" => "__nvvm_sust_b_2d_v2i8_trap", + "sust.b.2d.v2i8.zero" => "__nvvm_sust_b_2d_v2i8_zero", + "sust.b.2d.v4i16.clamp" => "__nvvm_sust_b_2d_v4i16_clamp", + "sust.b.2d.v4i16.trap" => "__nvvm_sust_b_2d_v4i16_trap", + "sust.b.2d.v4i16.zero" => "__nvvm_sust_b_2d_v4i16_zero", + "sust.b.2d.v4i32.clamp" => "__nvvm_sust_b_2d_v4i32_clamp", + "sust.b.2d.v4i32.trap" => "__nvvm_sust_b_2d_v4i32_trap", + "sust.b.2d.v4i32.zero" => "__nvvm_sust_b_2d_v4i32_zero", + "sust.b.2d.v4i8.clamp" => "__nvvm_sust_b_2d_v4i8_clamp", + "sust.b.2d.v4i8.trap" => "__nvvm_sust_b_2d_v4i8_trap", + "sust.b.2d.v4i8.zero" => "__nvvm_sust_b_2d_v4i8_zero", + "sust.b.3d.i16.clamp" => "__nvvm_sust_b_3d_i16_clamp", + "sust.b.3d.i16.trap" => "__nvvm_sust_b_3d_i16_trap", + "sust.b.3d.i16.zero" => "__nvvm_sust_b_3d_i16_zero", + "sust.b.3d.i32.clamp" => "__nvvm_sust_b_3d_i32_clamp", + "sust.b.3d.i32.trap" => "__nvvm_sust_b_3d_i32_trap", + "sust.b.3d.i32.zero" => "__nvvm_sust_b_3d_i32_zero", + "sust.b.3d.i64.clamp" => "__nvvm_sust_b_3d_i64_clamp", + "sust.b.3d.i64.trap" => "__nvvm_sust_b_3d_i64_trap", + "sust.b.3d.i64.zero" => "__nvvm_sust_b_3d_i64_zero", + "sust.b.3d.i8.clamp" => "__nvvm_sust_b_3d_i8_clamp", + "sust.b.3d.i8.trap" => "__nvvm_sust_b_3d_i8_trap", + "sust.b.3d.i8.zero" => "__nvvm_sust_b_3d_i8_zero", + "sust.b.3d.v2i16.clamp" => "__nvvm_sust_b_3d_v2i16_clamp", + "sust.b.3d.v2i16.trap" => "__nvvm_sust_b_3d_v2i16_trap", + "sust.b.3d.v2i16.zero" => "__nvvm_sust_b_3d_v2i16_zero", + "sust.b.3d.v2i32.clamp" => "__nvvm_sust_b_3d_v2i32_clamp", + "sust.b.3d.v2i32.trap" => "__nvvm_sust_b_3d_v2i32_trap", + "sust.b.3d.v2i32.zero" => "__nvvm_sust_b_3d_v2i32_zero", + "sust.b.3d.v2i64.clamp" => "__nvvm_sust_b_3d_v2i64_clamp", + "sust.b.3d.v2i64.trap" => "__nvvm_sust_b_3d_v2i64_trap", + "sust.b.3d.v2i64.zero" => "__nvvm_sust_b_3d_v2i64_zero", + "sust.b.3d.v2i8.clamp" => "__nvvm_sust_b_3d_v2i8_clamp", + "sust.b.3d.v2i8.trap" => "__nvvm_sust_b_3d_v2i8_trap", + "sust.b.3d.v2i8.zero" => "__nvvm_sust_b_3d_v2i8_zero", + "sust.b.3d.v4i16.clamp" => "__nvvm_sust_b_3d_v4i16_clamp", + "sust.b.3d.v4i16.trap" => "__nvvm_sust_b_3d_v4i16_trap", + "sust.b.3d.v4i16.zero" => "__nvvm_sust_b_3d_v4i16_zero", + "sust.b.3d.v4i32.clamp" => "__nvvm_sust_b_3d_v4i32_clamp", + "sust.b.3d.v4i32.trap" => "__nvvm_sust_b_3d_v4i32_trap", + "sust.b.3d.v4i32.zero" => "__nvvm_sust_b_3d_v4i32_zero", + "sust.b.3d.v4i8.clamp" => "__nvvm_sust_b_3d_v4i8_clamp", + "sust.b.3d.v4i8.trap" => "__nvvm_sust_b_3d_v4i8_trap", + "sust.b.3d.v4i8.zero" => "__nvvm_sust_b_3d_v4i8_zero", + "sust.p.1d.array.i16.trap" => "__nvvm_sust_p_1d_array_i16_trap", + "sust.p.1d.array.i32.trap" => "__nvvm_sust_p_1d_array_i32_trap", + "sust.p.1d.array.i8.trap" => "__nvvm_sust_p_1d_array_i8_trap", + "sust.p.1d.array.v2i16.trap" => "__nvvm_sust_p_1d_array_v2i16_trap", + "sust.p.1d.array.v2i32.trap" => "__nvvm_sust_p_1d_array_v2i32_trap", + "sust.p.1d.array.v2i8.trap" => "__nvvm_sust_p_1d_array_v2i8_trap", + "sust.p.1d.array.v4i16.trap" => "__nvvm_sust_p_1d_array_v4i16_trap", + "sust.p.1d.array.v4i32.trap" => "__nvvm_sust_p_1d_array_v4i32_trap", + "sust.p.1d.array.v4i8.trap" => "__nvvm_sust_p_1d_array_v4i8_trap", + "sust.p.1d.i16.trap" => "__nvvm_sust_p_1d_i16_trap", + "sust.p.1d.i32.trap" => "__nvvm_sust_p_1d_i32_trap", + "sust.p.1d.i8.trap" => "__nvvm_sust_p_1d_i8_trap", + "sust.p.1d.v2i16.trap" => "__nvvm_sust_p_1d_v2i16_trap", + "sust.p.1d.v2i32.trap" => "__nvvm_sust_p_1d_v2i32_trap", + "sust.p.1d.v2i8.trap" => "__nvvm_sust_p_1d_v2i8_trap", + "sust.p.1d.v4i16.trap" => "__nvvm_sust_p_1d_v4i16_trap", + "sust.p.1d.v4i32.trap" => "__nvvm_sust_p_1d_v4i32_trap", + "sust.p.1d.v4i8.trap" => "__nvvm_sust_p_1d_v4i8_trap", + "sust.p.2d.array.i16.trap" => "__nvvm_sust_p_2d_array_i16_trap", + "sust.p.2d.array.i32.trap" => "__nvvm_sust_p_2d_array_i32_trap", + "sust.p.2d.array.i8.trap" => "__nvvm_sust_p_2d_array_i8_trap", + "sust.p.2d.array.v2i16.trap" => "__nvvm_sust_p_2d_array_v2i16_trap", + "sust.p.2d.array.v2i32.trap" => "__nvvm_sust_p_2d_array_v2i32_trap", + "sust.p.2d.array.v2i8.trap" => "__nvvm_sust_p_2d_array_v2i8_trap", + "sust.p.2d.array.v4i16.trap" => "__nvvm_sust_p_2d_array_v4i16_trap", + "sust.p.2d.array.v4i32.trap" => "__nvvm_sust_p_2d_array_v4i32_trap", + "sust.p.2d.array.v4i8.trap" => "__nvvm_sust_p_2d_array_v4i8_trap", + "sust.p.2d.i16.trap" => "__nvvm_sust_p_2d_i16_trap", + "sust.p.2d.i32.trap" => "__nvvm_sust_p_2d_i32_trap", + "sust.p.2d.i8.trap" => "__nvvm_sust_p_2d_i8_trap", + "sust.p.2d.v2i16.trap" => "__nvvm_sust_p_2d_v2i16_trap", + "sust.p.2d.v2i32.trap" => "__nvvm_sust_p_2d_v2i32_trap", + "sust.p.2d.v2i8.trap" => "__nvvm_sust_p_2d_v2i8_trap", + "sust.p.2d.v4i16.trap" => "__nvvm_sust_p_2d_v4i16_trap", + "sust.p.2d.v4i32.trap" => "__nvvm_sust_p_2d_v4i32_trap", + "sust.p.2d.v4i8.trap" => "__nvvm_sust_p_2d_v4i8_trap", + "sust.p.3d.i16.trap" => "__nvvm_sust_p_3d_i16_trap", + "sust.p.3d.i32.trap" => "__nvvm_sust_p_3d_i32_trap", + "sust.p.3d.i8.trap" => "__nvvm_sust_p_3d_i8_trap", + "sust.p.3d.v2i16.trap" => "__nvvm_sust_p_3d_v2i16_trap", + "sust.p.3d.v2i32.trap" => "__nvvm_sust_p_3d_v2i32_trap", + "sust.p.3d.v2i8.trap" => "__nvvm_sust_p_3d_v2i8_trap", + "sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap", + "sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap", + "sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap", + "swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64", + "trunc.d" => "__nvvm_trunc_d", + "trunc.f" => "__nvvm_trunc_f", + "trunc.ftz.f" => "__nvvm_trunc_ftz_f", + "txq.array.size" => "__nvvm_txq_array_size", + "txq.channel.data.type" => "__nvvm_txq_channel_data_type", + "txq.channel.order" => "__nvvm_txq_channel_order", + "txq.depth" => "__nvvm_txq_depth", + "txq.height" => "__nvvm_txq_height", + "txq.num.mipmap.levels" => "__nvvm_txq_num_mipmap_levels", + "txq.num.samples" => "__nvvm_txq_num_samples", + "txq.width" => "__nvvm_txq_width", + "ue8m0x2.to.bf16x2" => "__nvvm_ue8m0x2_to_bf16x2", + "ui2d.rm" => "__nvvm_ui2d_rm", + "ui2d.rn" => "__nvvm_ui2d_rn", + "ui2d.rp" => "__nvvm_ui2d_rp", + "ui2d.rz" => "__nvvm_ui2d_rz", + "ui2f.rm" => "__nvvm_ui2f_rm", + "ui2f.rn" => "__nvvm_ui2f_rn", + "ui2f.rp" => "__nvvm_ui2f_rp", + "ui2f.rz" => "__nvvm_ui2f_rz", + "ull2d.rm" => "__nvvm_ull2d_rm", + "ull2d.rn" => "__nvvm_ull2d_rn", + "ull2d.rp" => "__nvvm_ull2d_rp", + "ull2d.rz" => "__nvvm_ull2d_rz", + "ull2f.rm" => "__nvvm_ull2f_rm", + "ull2f.rn" => "__nvvm_ull2f_rn", + "ull2f.rp" => "__nvvm_ull2f_rp", + "ull2f.rz" => "__nvvm_ull2f_rz", + "vote.all" => "__nvvm_vote_all", + "vote.all.sync" => "__nvvm_vote_all_sync", + "vote.any" => "__nvvm_vote_any", + "vote.any.sync" => "__nvvm_vote_any_sync", + "vote.ballot" => "__nvvm_vote_ballot", + "vote.ballot.sync" => "__nvvm_vote_ballot_sync", + "vote.uni" => "__nvvm_vote_uni", + "vote.uni.sync" => "__nvvm_vote_uni_sync", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + nvvm(name) + } + "ppc" => { + #[allow(non_snake_case)] + fn ppc(name: &str) -> &str { + match name { + // ppc + "addex" => "__builtin_ppc_addex", + "addf128.round.to.odd" => "__builtin_addf128_round_to_odd", + "addg6s" => "__builtin_addg6s", + "addg6sd" => "__builtin_ppc_addg6s", + "altivec.crypto.vcipher" => "__builtin_altivec_crypto_vcipher", + "altivec.crypto.vcipherlast" => "__builtin_altivec_crypto_vcipherlast", + "altivec.crypto.vncipher" => "__builtin_altivec_crypto_vncipher", + "altivec.crypto.vncipherlast" => "__builtin_altivec_crypto_vncipherlast", + "altivec.crypto.vpermxor" => "__builtin_altivec_crypto_vpermxor", + "altivec.crypto.vpermxor.be" => "__builtin_altivec_crypto_vpermxor_be", + "altivec.crypto.vpmsumb" => "__builtin_altivec_crypto_vpmsumb", + "altivec.crypto.vpmsumd" => "__builtin_altivec_crypto_vpmsumd", + "altivec.crypto.vpmsumh" => "__builtin_altivec_crypto_vpmsumh", + "altivec.crypto.vpmsumw" => "__builtin_altivec_crypto_vpmsumw", + "altivec.crypto.vsbox" => "__builtin_altivec_crypto_vsbox", + "altivec.crypto.vshasigmad" => "__builtin_altivec_crypto_vshasigmad", + "altivec.crypto.vshasigmaw" => "__builtin_altivec_crypto_vshasigmaw", + "altivec.dss" => "__builtin_altivec_dss", + "altivec.dssall" => "__builtin_altivec_dssall", + "altivec.dst" => "__builtin_altivec_dst", + "altivec.dstst" => "__builtin_altivec_dstst", + "altivec.dststt" => "__builtin_altivec_dststt", + "altivec.dstt" => "__builtin_altivec_dstt", + "altivec.mfvscr" => "__builtin_altivec_mfvscr", + "altivec.mtvscr" => "__builtin_altivec_mtvscr", + "altivec.mtvsrbm" => "__builtin_altivec_mtvsrbm", + "altivec.mtvsrdm" => "__builtin_altivec_mtvsrdm", + "altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm", + "altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm", + "altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm", + "altivec.vabsdub" => "__builtin_altivec_vabsdub", + "altivec.vabsduh" => "__builtin_altivec_vabsduh", + "altivec.vabsduw" => "__builtin_altivec_vabsduw", + "altivec.vaddcuq" => "__builtin_altivec_vaddcuq", + "altivec.vaddcuw" => "__builtin_altivec_vaddcuw", + "altivec.vaddecuq" => "__builtin_altivec_vaddecuq", + "altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm", + "altivec.vaddsbs" => "__builtin_altivec_vaddsbs", + "altivec.vaddshs" => "__builtin_altivec_vaddshs", + "altivec.vaddsws" => "__builtin_altivec_vaddsws", + "altivec.vaddubs" => "__builtin_altivec_vaddubs", + "altivec.vadduhs" => "__builtin_altivec_vadduhs", + "altivec.vadduws" => "__builtin_altivec_vadduws", + "altivec.vavgsb" => "__builtin_altivec_vavgsb", + "altivec.vavgsh" => "__builtin_altivec_vavgsh", + "altivec.vavgsw" => "__builtin_altivec_vavgsw", + "altivec.vavgub" => "__builtin_altivec_vavgub", + "altivec.vavguh" => "__builtin_altivec_vavguh", + "altivec.vavguw" => "__builtin_altivec_vavguw", + "altivec.vbpermd" => "__builtin_altivec_vbpermd", + "altivec.vbpermq" => "__builtin_altivec_vbpermq", + "altivec.vcfsx" => "__builtin_altivec_vcfsx", + "altivec.vcfuged" => "__builtin_altivec_vcfuged", + "altivec.vcfux" => "__builtin_altivec_vcfux", + "altivec.vclrlb" => "__builtin_altivec_vclrlb", + "altivec.vclrrb" => "__builtin_altivec_vclrrb", + "altivec.vclzdm" => "__builtin_altivec_vclzdm", + "altivec.vclzlsbb" => "__builtin_altivec_vclzlsbb", + "altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp", + "altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p", + "altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp", + "altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p", + "altivec.vcmpequb" => "__builtin_altivec_vcmpequb", + "altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p", + "altivec.vcmpequd" => "__builtin_altivec_vcmpequd", + "altivec.vcmpequd.p" => "__builtin_altivec_vcmpequd_p", + "altivec.vcmpequh" => "__builtin_altivec_vcmpequh", + "altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p", + "altivec.vcmpequq" => "__builtin_altivec_vcmpequq", + "altivec.vcmpequq.p" => "__builtin_altivec_vcmpequq_p", + "altivec.vcmpequw" => "__builtin_altivec_vcmpequw", + "altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p", + "altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp", + "altivec.vcmpgefp.p" => "__builtin_altivec_vcmpgefp_p", + "altivec.vcmpgtfp" => "__builtin_altivec_vcmpgtfp", + "altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p", + "altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb", + "altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p", + "altivec.vcmpgtsd" => "__builtin_altivec_vcmpgtsd", + "altivec.vcmpgtsd.p" => "__builtin_altivec_vcmpgtsd_p", + "altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh", + "altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p", + "altivec.vcmpgtsq" => "__builtin_altivec_vcmpgtsq", + "altivec.vcmpgtsq.p" => "__builtin_altivec_vcmpgtsq_p", + "altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw", + "altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p", + "altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub", + "altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p", + "altivec.vcmpgtud" => "__builtin_altivec_vcmpgtud", + "altivec.vcmpgtud.p" => "__builtin_altivec_vcmpgtud_p", + "altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh", + "altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p", + "altivec.vcmpgtuq" => "__builtin_altivec_vcmpgtuq", + "altivec.vcmpgtuq.p" => "__builtin_altivec_vcmpgtuq_p", + "altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw", + "altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p", + "altivec.vcmpneb" => "__builtin_altivec_vcmpneb", + "altivec.vcmpneb.p" => "__builtin_altivec_vcmpneb_p", + "altivec.vcmpneh" => "__builtin_altivec_vcmpneh", + "altivec.vcmpneh.p" => "__builtin_altivec_vcmpneh_p", + "altivec.vcmpnew" => "__builtin_altivec_vcmpnew", + "altivec.vcmpnew.p" => "__builtin_altivec_vcmpnew_p", + "altivec.vcmpnezb" => "__builtin_altivec_vcmpnezb", + "altivec.vcmpnezb.p" => "__builtin_altivec_vcmpnezb_p", + "altivec.vcmpnezh" => "__builtin_altivec_vcmpnezh", + "altivec.vcmpnezh.p" => "__builtin_altivec_vcmpnezh_p", + "altivec.vcmpnezw" => "__builtin_altivec_vcmpnezw", + "altivec.vcmpnezw.p" => "__builtin_altivec_vcmpnezw_p", + "altivec.vcntmbb" => "__builtin_altivec_vcntmbb", + "altivec.vcntmbd" => "__builtin_altivec_vcntmbd", + "altivec.vcntmbh" => "__builtin_altivec_vcntmbh", + "altivec.vcntmbw" => "__builtin_altivec_vcntmbw", + "altivec.vctsxs" => "__builtin_altivec_vctsxs", + "altivec.vctuxs" => "__builtin_altivec_vctuxs", + "altivec.vctzdm" => "__builtin_altivec_vctzdm", + "altivec.vctzlsbb" => "__builtin_altivec_vctzlsbb", + "altivec.vdivesd" => "__builtin_altivec_vdivesd", + "altivec.vdivesq" => "__builtin_altivec_vdivesq", + "altivec.vdivesw" => "__builtin_altivec_vdivesw", + "altivec.vdiveud" => "__builtin_altivec_vdiveud", + "altivec.vdiveuq" => "__builtin_altivec_vdiveuq", + "altivec.vdiveuw" => "__builtin_altivec_vdiveuw", + "altivec.vexpandbm" => "__builtin_altivec_vexpandbm", + "altivec.vexpanddm" => "__builtin_altivec_vexpanddm", + "altivec.vexpandhm" => "__builtin_altivec_vexpandhm", + "altivec.vexpandqm" => "__builtin_altivec_vexpandqm", + "altivec.vexpandwm" => "__builtin_altivec_vexpandwm", + "altivec.vexptefp" => "__builtin_altivec_vexptefp", + "altivec.vextddvlx" => "__builtin_altivec_vextddvlx", + "altivec.vextddvrx" => "__builtin_altivec_vextddvrx", + "altivec.vextdubvlx" => "__builtin_altivec_vextdubvlx", + "altivec.vextdubvrx" => "__builtin_altivec_vextdubvrx", + "altivec.vextduhvlx" => "__builtin_altivec_vextduhvlx", + "altivec.vextduhvrx" => "__builtin_altivec_vextduhvrx", + "altivec.vextduwvlx" => "__builtin_altivec_vextduwvlx", + "altivec.vextduwvrx" => "__builtin_altivec_vextduwvrx", + "altivec.vextractbm" => "__builtin_altivec_vextractbm", + "altivec.vextractdm" => "__builtin_altivec_vextractdm", + "altivec.vextracthm" => "__builtin_altivec_vextracthm", + "altivec.vextractqm" => "__builtin_altivec_vextractqm", + "altivec.vextractwm" => "__builtin_altivec_vextractwm", + "altivec.vextsb2d" => "__builtin_altivec_vextsb2d", + "altivec.vextsb2w" => "__builtin_altivec_vextsb2w", + "altivec.vextsd2q" => "__builtin_altivec_vextsd2q", + "altivec.vextsh2d" => "__builtin_altivec_vextsh2d", + "altivec.vextsh2w" => "__builtin_altivec_vextsh2w", + "altivec.vextsw2d" => "__builtin_altivec_vextsw2d", + "altivec.vgbbd" => "__builtin_altivec_vgbbd", + "altivec.vgnb" => "__builtin_altivec_vgnb", + "altivec.vinsblx" => "__builtin_altivec_vinsblx", + "altivec.vinsbrx" => "__builtin_altivec_vinsbrx", + "altivec.vinsbvlx" => "__builtin_altivec_vinsbvlx", + "altivec.vinsbvrx" => "__builtin_altivec_vinsbvrx", + "altivec.vinsdlx" => "__builtin_altivec_vinsdlx", + "altivec.vinsdrx" => "__builtin_altivec_vinsdrx", + "altivec.vinshlx" => "__builtin_altivec_vinshlx", + "altivec.vinshrx" => "__builtin_altivec_vinshrx", + "altivec.vinshvlx" => "__builtin_altivec_vinshvlx", + "altivec.vinshvrx" => "__builtin_altivec_vinshvrx", + "altivec.vinswlx" => "__builtin_altivec_vinswlx", + "altivec.vinswrx" => "__builtin_altivec_vinswrx", + "altivec.vinswvlx" => "__builtin_altivec_vinswvlx", + "altivec.vinswvrx" => "__builtin_altivec_vinswvrx", + "altivec.vlogefp" => "__builtin_altivec_vlogefp", + "altivec.vmaddfp" => "__builtin_altivec_vmaddfp", + "altivec.vmaxfp" => "__builtin_altivec_vmaxfp", + "altivec.vmaxsb" => "__builtin_altivec_vmaxsb", + "altivec.vmaxsd" => "__builtin_altivec_vmaxsd", + "altivec.vmaxsh" => "__builtin_altivec_vmaxsh", + "altivec.vmaxsw" => "__builtin_altivec_vmaxsw", + "altivec.vmaxub" => "__builtin_altivec_vmaxub", + "altivec.vmaxud" => "__builtin_altivec_vmaxud", + "altivec.vmaxuh" => "__builtin_altivec_vmaxuh", + "altivec.vmaxuw" => "__builtin_altivec_vmaxuw", + "altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", + "altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", + "altivec.vminfp" => "__builtin_altivec_vminfp", + "altivec.vminsb" => "__builtin_altivec_vminsb", + "altivec.vminsd" => "__builtin_altivec_vminsd", + "altivec.vminsh" => "__builtin_altivec_vminsh", + "altivec.vminsw" => "__builtin_altivec_vminsw", + "altivec.vminub" => "__builtin_altivec_vminub", + "altivec.vminud" => "__builtin_altivec_vminud", + "altivec.vminuh" => "__builtin_altivec_vminuh", + "altivec.vminuw" => "__builtin_altivec_vminuw", + "altivec.vmladduhm" => "__builtin_altivec_vmladduhm", + "altivec.vmsumcud" => "__builtin_altivec_vmsumcud", + "altivec.vmsummbm" => "__builtin_altivec_vmsummbm", + "altivec.vmsumshm" => "__builtin_altivec_vmsumshm", + "altivec.vmsumshs" => "__builtin_altivec_vmsumshs", + "altivec.vmsumubm" => "__builtin_altivec_vmsumubm", + "altivec.vmsumudm" => "__builtin_altivec_vmsumudm", + "altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", + "altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", + "altivec.vmulesb" => "__builtin_altivec_vmulesb", + "altivec.vmulesd" => "__builtin_altivec_vmulesd", + "altivec.vmulesh" => "__builtin_altivec_vmulesh", + "altivec.vmulesw" => "__builtin_altivec_vmulesw", + "altivec.vmuleub" => "__builtin_altivec_vmuleub", + "altivec.vmuleud" => "__builtin_altivec_vmuleud", + "altivec.vmuleuh" => "__builtin_altivec_vmuleuh", + "altivec.vmuleuw" => "__builtin_altivec_vmuleuw", + "altivec.vmulhsd" => "__builtin_altivec_vmulhsd", + "altivec.vmulhsw" => "__builtin_altivec_vmulhsw", + "altivec.vmulhud" => "__builtin_altivec_vmulhud", + "altivec.vmulhuw" => "__builtin_altivec_vmulhuw", + "altivec.vmulosb" => "__builtin_altivec_vmulosb", + "altivec.vmulosd" => "__builtin_altivec_vmulosd", + "altivec.vmulosh" => "__builtin_altivec_vmulosh", + "altivec.vmulosw" => "__builtin_altivec_vmulosw", + "altivec.vmuloub" => "__builtin_altivec_vmuloub", + "altivec.vmuloud" => "__builtin_altivec_vmuloud", + "altivec.vmulouh" => "__builtin_altivec_vmulouh", + "altivec.vmulouw" => "__builtin_altivec_vmulouw", + "altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", + "altivec.vpdepd" => "__builtin_altivec_vpdepd", + "altivec.vperm" => "__builtin_altivec_vperm_4si", + "altivec.vpextd" => "__builtin_altivec_vpextd", + "altivec.vpkpx" => "__builtin_altivec_vpkpx", + "altivec.vpksdss" => "__builtin_altivec_vpksdss", + "altivec.vpksdus" => "__builtin_altivec_vpksdus", + "altivec.vpkshss" => "__builtin_altivec_vpkshss", + "altivec.vpkshus" => "__builtin_altivec_vpkshus", + "altivec.vpkswss" => "__builtin_altivec_vpkswss", + "altivec.vpkswus" => "__builtin_altivec_vpkswus", + "altivec.vpkudus" => "__builtin_altivec_vpkudus", + "altivec.vpkuhus" => "__builtin_altivec_vpkuhus", + "altivec.vpkuwus" => "__builtin_altivec_vpkuwus", + "altivec.vprtybd" => "__builtin_altivec_vprtybd", + "altivec.vprtybq" => "__builtin_altivec_vprtybq", + "altivec.vprtybw" => "__builtin_altivec_vprtybw", + "altivec.vrefp" => "__builtin_altivec_vrefp", + "altivec.vrfim" => "__builtin_altivec_vrfim", + "altivec.vrfin" => "__builtin_altivec_vrfin", + "altivec.vrfip" => "__builtin_altivec_vrfip", + "altivec.vrfiz" => "__builtin_altivec_vrfiz", + "altivec.vrlb" => "__builtin_altivec_vrlb", + "altivec.vrld" => "__builtin_altivec_vrld", + "altivec.vrldmi" => "__builtin_altivec_vrldmi", + "altivec.vrldnm" => "__builtin_altivec_vrldnm", + "altivec.vrlh" => "__builtin_altivec_vrlh", + "altivec.vrlqmi" => "__builtin_altivec_vrlqmi", + "altivec.vrlqnm" => "__builtin_altivec_vrlqnm", + "altivec.vrlw" => "__builtin_altivec_vrlw", + "altivec.vrlwmi" => "__builtin_altivec_vrlwmi", + "altivec.vrlwnm" => "__builtin_altivec_vrlwnm", + "altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", + "altivec.vsel" => "__builtin_altivec_vsel_4si", + "altivec.vsl" => "__builtin_altivec_vsl", + "altivec.vslb" => "__builtin_altivec_vslb", + "altivec.vsldbi" => "__builtin_altivec_vsldbi", + "altivec.vslh" => "__builtin_altivec_vslh", + "altivec.vslo" => "__builtin_altivec_vslo", + "altivec.vslv" => "__builtin_altivec_vslv", + "altivec.vslw" => "__builtin_altivec_vslw", + "altivec.vsr" => "__builtin_altivec_vsr", + "altivec.vsrab" => "__builtin_altivec_vsrab", + "altivec.vsrah" => "__builtin_altivec_vsrah", + "altivec.vsraw" => "__builtin_altivec_vsraw", + "altivec.vsrb" => "__builtin_altivec_vsrb", + "altivec.vsrdbi" => "__builtin_altivec_vsrdbi", + "altivec.vsrh" => "__builtin_altivec_vsrh", + "altivec.vsro" => "__builtin_altivec_vsro", + "altivec.vsrv" => "__builtin_altivec_vsrv", + "altivec.vsrw" => "__builtin_altivec_vsrw", + "altivec.vstribl" => "__builtin_altivec_vstribl", + "altivec.vstribl.p" => "__builtin_altivec_vstribl_p", + "altivec.vstribr" => "__builtin_altivec_vstribr", + "altivec.vstribr.p" => "__builtin_altivec_vstribr_p", + "altivec.vstrihl" => "__builtin_altivec_vstrihl", + "altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p", + "altivec.vstrihr" => "__builtin_altivec_vstrihr", + "altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p", + "altivec.vsubcuq" => "__builtin_altivec_vsubcuq", + "altivec.vsubcuw" => "__builtin_altivec_vsubcuw", + "altivec.vsubecuq" => "__builtin_altivec_vsubecuq", + "altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm", + "altivec.vsubsbs" => "__builtin_altivec_vsubsbs", + "altivec.vsubshs" => "__builtin_altivec_vsubshs", + "altivec.vsubsws" => "__builtin_altivec_vsubsws", + "altivec.vsububs" => "__builtin_altivec_vsububs", + "altivec.vsubuhs" => "__builtin_altivec_vsubuhs", + "altivec.vsubuws" => "__builtin_altivec_vsubuws", + "altivec.vsum2sws" => "__builtin_altivec_vsum2sws", + "altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", + "altivec.vsum4shs" => "__builtin_altivec_vsum4shs", + "altivec.vsum4ubs" => "__builtin_altivec_vsum4ubs", + "altivec.vsumsws" => "__builtin_altivec_vsumsws", + "altivec.vupkhpx" => "__builtin_altivec_vupkhpx", + "altivec.vupkhsb" => "__builtin_altivec_vupkhsb", + "altivec.vupkhsh" => "__builtin_altivec_vupkhsh", + "altivec.vupkhsw" => "__builtin_altivec_vupkhsw", + "altivec.vupklpx" => "__builtin_altivec_vupklpx", + "altivec.vupklsb" => "__builtin_altivec_vupklsb", + "altivec.vupklsh" => "__builtin_altivec_vupklsh", + "altivec.vupklsw" => "__builtin_altivec_vupklsw", + "bcdadd" => "__builtin_ppc_bcdadd", + "bcdadd.p" => "__builtin_ppc_bcdadd_p", + "bcdsub" => "__builtin_ppc_bcdsub", + "bcdsub.p" => "__builtin_ppc_bcdsub_p", + "bpermd" => "__builtin_bpermd", + "cbcdtd" => "__builtin_cbcdtd", + "cbcdtdd" => "__builtin_ppc_cbcdtd", + "cdtbcd" => "__builtin_cdtbcd", + "cdtbcdd" => "__builtin_ppc_cdtbcd", + "cfuged" => "__builtin_cfuged", + "cmpeqb" => "__builtin_ppc_cmpeqb", + "cmprb" => "__builtin_ppc_cmprb", + "cntlzdm" => "__builtin_cntlzdm", + "cnttzdm" => "__builtin_cnttzdm", + "compare.exp.eq" => "__builtin_ppc_compare_exp_eq", + "compare.exp.gt" => "__builtin_ppc_compare_exp_gt", + "compare.exp.lt" => "__builtin_ppc_compare_exp_lt", + "compare.exp.uo" => "__builtin_ppc_compare_exp_uo", + "darn" => "__builtin_darn", + "darn32" => "__builtin_darn_32", + "darnraw" => "__builtin_darn_raw", + "dcbf" => "__builtin_dcbf", + "dcbfl" => "__builtin_ppc_dcbfl", + "dcbflp" => "__builtin_ppc_dcbflp", + "dcbst" => "__builtin_ppc_dcbst", + "dcbt" => "__builtin_ppc_dcbt", + "dcbtst" => "__builtin_ppc_dcbtst", + "dcbtstt" => "__builtin_ppc_dcbtstt", + "dcbtt" => "__builtin_ppc_dcbtt", + "dcbz" => "__builtin_ppc_dcbz", + "divde" => "__builtin_divde", + "divdeu" => "__builtin_divdeu", + "divf128.round.to.odd" => "__builtin_divf128_round_to_odd", + "divwe" => "__builtin_divwe", + "divweu" => "__builtin_divweu", + "eieio" => "__builtin_ppc_eieio", + "extract.exp" => "__builtin_ppc_extract_exp", + "extract.sig" => "__builtin_ppc_extract_sig", + "fcfid" => "__builtin_ppc_fcfid", + "fcfud" => "__builtin_ppc_fcfud", + "fctid" => "__builtin_ppc_fctid", + "fctidz" => "__builtin_ppc_fctidz", + "fctiw" => "__builtin_ppc_fctiw", + "fctiwz" => "__builtin_ppc_fctiwz", + "fctudz" => "__builtin_ppc_fctudz", + "fctuwz" => "__builtin_ppc_fctuwz", + "fence" => "__builtin_ppc_fence", + "fmaf128.round.to.odd" => "__builtin_fmaf128_round_to_odd", + "fmsub" => "__builtin_ppc_fmsub", + "fmsubs" => "__builtin_ppc_fmsubs", + "fnabs" => "__builtin_ppc_fnabs", + "fnabss" => "__builtin_ppc_fnabss", + "fnmadd" => "__builtin_ppc_fnmadd", + "fnmadds" => "__builtin_ppc_fnmadds", + "fre" => "__builtin_ppc_fre", + "fres" => "__builtin_ppc_fres", + "frsqrte" => "__builtin_ppc_frsqrte", + "frsqrtes" => "__builtin_ppc_frsqrtes", + "fsel" => "__builtin_ppc_fsel", + "fsels" => "__builtin_ppc_fsels", + "get.texasr" => "__builtin_get_texasr", + "get.texasru" => "__builtin_get_texasru", + "get.tfhar" => "__builtin_get_tfhar", + "get.tfiar" => "__builtin_get_tfiar", + "icbt" => "__builtin_ppc_icbt", + "insert.exp" => "__builtin_ppc_insert_exp", + "iospace.eieio" => "__builtin_ppc_iospace_eieio", + "iospace.lwsync" => "__builtin_ppc_iospace_lwsync", + "iospace.sync" => "__builtin_ppc_iospace_sync", + "isync" => "__builtin_ppc_isync", + "load4r" => "__builtin_ppc_load4r", + "load8r" => "__builtin_ppc_load8r", + "lwsync" => "__builtin_ppc_lwsync", + "maddhd" => "__builtin_ppc_maddhd", + "maddhdu" => "__builtin_ppc_maddhdu", + "maddld" => "__builtin_ppc_maddld", + "mffsl" => "__builtin_ppc_mffsl", + "mfmsr" => "__builtin_ppc_mfmsr", + "mftbu" => "__builtin_ppc_mftbu", + "mtfsb0" => "__builtin_ppc_mtfsb0", + "mtfsb1" => "__builtin_ppc_mtfsb1", + "mtfsfi" => "__builtin_ppc_mtfsfi", + "mtmsr" => "__builtin_ppc_mtmsr", + "mulf128.round.to.odd" => "__builtin_mulf128_round_to_odd", + "mulhd" => "__builtin_ppc_mulhd", + "mulhdu" => "__builtin_ppc_mulhdu", + "mulhw" => "__builtin_ppc_mulhw", + "mulhwu" => "__builtin_ppc_mulhwu", + "pack.longdouble" => "__builtin_pack_longdouble", + "pdepd" => "__builtin_pdepd", + "pextd" => "__builtin_pextd", + "qpx.qvfabs" => "__builtin_qpx_qvfabs", + "qpx.qvfadd" => "__builtin_qpx_qvfadd", + "qpx.qvfadds" => "__builtin_qpx_qvfadds", + "qpx.qvfcfid" => "__builtin_qpx_qvfcfid", + "qpx.qvfcfids" => "__builtin_qpx_qvfcfids", + "qpx.qvfcfidu" => "__builtin_qpx_qvfcfidu", + "qpx.qvfcfidus" => "__builtin_qpx_qvfcfidus", + "qpx.qvfcmpeq" => "__builtin_qpx_qvfcmpeq", + "qpx.qvfcmpgt" => "__builtin_qpx_qvfcmpgt", + "qpx.qvfcmplt" => "__builtin_qpx_qvfcmplt", + "qpx.qvfcpsgn" => "__builtin_qpx_qvfcpsgn", + "qpx.qvfctid" => "__builtin_qpx_qvfctid", + "qpx.qvfctidu" => "__builtin_qpx_qvfctidu", + "qpx.qvfctiduz" => "__builtin_qpx_qvfctiduz", + "qpx.qvfctidz" => "__builtin_qpx_qvfctidz", + "qpx.qvfctiw" => "__builtin_qpx_qvfctiw", + "qpx.qvfctiwu" => "__builtin_qpx_qvfctiwu", + "qpx.qvfctiwuz" => "__builtin_qpx_qvfctiwuz", + "qpx.qvfctiwz" => "__builtin_qpx_qvfctiwz", + "qpx.qvflogical" => "__builtin_qpx_qvflogical", + "qpx.qvfmadd" => "__builtin_qpx_qvfmadd", + "qpx.qvfmadds" => "__builtin_qpx_qvfmadds", + "qpx.qvfmsub" => "__builtin_qpx_qvfmsub", + "qpx.qvfmsubs" => "__builtin_qpx_qvfmsubs", + "qpx.qvfmul" => "__builtin_qpx_qvfmul", + "qpx.qvfmuls" => "__builtin_qpx_qvfmuls", + "qpx.qvfnabs" => "__builtin_qpx_qvfnabs", + "qpx.qvfneg" => "__builtin_qpx_qvfneg", + "qpx.qvfnmadd" => "__builtin_qpx_qvfnmadd", + "qpx.qvfnmadds" => "__builtin_qpx_qvfnmadds", + "qpx.qvfnmsub" => "__builtin_qpx_qvfnmsub", + "qpx.qvfnmsubs" => "__builtin_qpx_qvfnmsubs", + "qpx.qvfperm" => "__builtin_qpx_qvfperm", + "qpx.qvfre" => "__builtin_qpx_qvfre", + "qpx.qvfres" => "__builtin_qpx_qvfres", + "qpx.qvfrim" => "__builtin_qpx_qvfrim", + "qpx.qvfrin" => "__builtin_qpx_qvfrin", + "qpx.qvfrip" => "__builtin_qpx_qvfrip", + "qpx.qvfriz" => "__builtin_qpx_qvfriz", + "qpx.qvfrsp" => "__builtin_qpx_qvfrsp", + "qpx.qvfrsqrte" => "__builtin_qpx_qvfrsqrte", + "qpx.qvfrsqrtes" => "__builtin_qpx_qvfrsqrtes", + "qpx.qvfsel" => "__builtin_qpx_qvfsel", + "qpx.qvfsub" => "__builtin_qpx_qvfsub", + "qpx.qvfsubs" => "__builtin_qpx_qvfsubs", + "qpx.qvftstnan" => "__builtin_qpx_qvftstnan", + "qpx.qvfxmadd" => "__builtin_qpx_qvfxmadd", + "qpx.qvfxmadds" => "__builtin_qpx_qvfxmadds", + "qpx.qvfxmul" => "__builtin_qpx_qvfxmul", + "qpx.qvfxmuls" => "__builtin_qpx_qvfxmuls", + "qpx.qvfxxcpnmadd" => "__builtin_qpx_qvfxxcpnmadd", + "qpx.qvfxxcpnmadds" => "__builtin_qpx_qvfxxcpnmadds", + "qpx.qvfxxmadd" => "__builtin_qpx_qvfxxmadd", + "qpx.qvfxxmadds" => "__builtin_qpx_qvfxxmadds", + "qpx.qvfxxnpmadd" => "__builtin_qpx_qvfxxnpmadd", + "qpx.qvfxxnpmadds" => "__builtin_qpx_qvfxxnpmadds", + "qpx.qvgpci" => "__builtin_qpx_qvgpci", + "qpx.qvlfcd" => "__builtin_qpx_qvlfcd", + "qpx.qvlfcda" => "__builtin_qpx_qvlfcda", + "qpx.qvlfcs" => "__builtin_qpx_qvlfcs", + "qpx.qvlfcsa" => "__builtin_qpx_qvlfcsa", + "qpx.qvlfd" => "__builtin_qpx_qvlfd", + "qpx.qvlfda" => "__builtin_qpx_qvlfda", + "qpx.qvlfiwa" => "__builtin_qpx_qvlfiwa", + "qpx.qvlfiwaa" => "__builtin_qpx_qvlfiwaa", + "qpx.qvlfiwz" => "__builtin_qpx_qvlfiwz", + "qpx.qvlfiwza" => "__builtin_qpx_qvlfiwza", + "qpx.qvlfs" => "__builtin_qpx_qvlfs", + "qpx.qvlfsa" => "__builtin_qpx_qvlfsa", + "qpx.qvlpcld" => "__builtin_qpx_qvlpcld", + "qpx.qvlpcls" => "__builtin_qpx_qvlpcls", + "qpx.qvlpcrd" => "__builtin_qpx_qvlpcrd", + "qpx.qvlpcrs" => "__builtin_qpx_qvlpcrs", + "qpx.qvstfcd" => "__builtin_qpx_qvstfcd", + "qpx.qvstfcda" => "__builtin_qpx_qvstfcda", + "qpx.qvstfcs" => "__builtin_qpx_qvstfcs", + "qpx.qvstfcsa" => "__builtin_qpx_qvstfcsa", + "qpx.qvstfd" => "__builtin_qpx_qvstfd", + "qpx.qvstfda" => "__builtin_qpx_qvstfda", + "qpx.qvstfiw" => "__builtin_qpx_qvstfiw", + "qpx.qvstfiwa" => "__builtin_qpx_qvstfiwa", + "qpx.qvstfs" => "__builtin_qpx_qvstfs", + "qpx.qvstfsa" => "__builtin_qpx_qvstfsa", + "readflm" => "__builtin_readflm", + "rlwimi" => "__builtin_ppc_rlwimi", + "rlwnm" => "__builtin_ppc_rlwnm", + "scalar.extract.expq" => "__builtin_vsx_scalar_extract_expq", + "scalar.insert.exp.qp" => "__builtin_vsx_scalar_insert_exp_qp", + "set.texasr" => "__builtin_set_texasr", + "set.texasru" => "__builtin_set_texasru", + "set.tfhar" => "__builtin_set_tfhar", + "set.tfiar" => "__builtin_set_tfiar", + "setb" => "__builtin_ppc_setb", + "setflm" => "__builtin_setflm", + "setrnd" => "__builtin_setrnd", + "sqrtf128.round.to.odd" => "__builtin_sqrtf128_round_to_odd", + "stbcx" => "__builtin_ppc_stbcx", + "stdcx" => "__builtin_ppc_stdcx", + "stfiw" => "__builtin_ppc_stfiw", + "store2r" => "__builtin_ppc_store2r", + "store4r" => "__builtin_ppc_store4r", + "store8r" => "__builtin_ppc_store8r", + "stwcx" => "__builtin_ppc_stwcx", + "subf128.round.to.odd" => "__builtin_subf128_round_to_odd", + "sync" => "__builtin_ppc_sync", + "tabort" => "__builtin_tabort", + "tabortdc" => "__builtin_tabortdc", + "tabortdci" => "__builtin_tabortdci", + "tabortwc" => "__builtin_tabortwc", + "tabortwci" => "__builtin_tabortwci", + "tbegin" => "__builtin_tbegin", + "tcheck" => "__builtin_tcheck", + "tdw" => "__builtin_ppc_tdw", + "tend" => "__builtin_tend", + "tendall" => "__builtin_tendall", + "trap" => "__builtin_ppc_trap", + "trapd" => "__builtin_ppc_trapd", + "trechkpt" => "__builtin_trechkpt", + "treclaim" => "__builtin_treclaim", + "tresume" => "__builtin_tresume", + "truncf128.round.to.odd" => "__builtin_truncf128_round_to_odd", + "tsr" => "__builtin_tsr", + "tsuspend" => "__builtin_tsuspend", + "ttest" => "__builtin_ttest", + "tw" => "__builtin_ppc_tw", + "unpack.longdouble" => "__builtin_unpack_longdouble", + "vsx.xsmaxdp" => "__builtin_vsx_xsmaxdp", + "vsx.xsmindp" => "__builtin_vsx_xsmindp", + "vsx.xvcmpeqdp" => "__builtin_vsx_xvcmpeqdp", + "vsx.xvcmpeqdp.p" => "__builtin_vsx_xvcmpeqdp_p", + "vsx.xvcmpeqsp" => "__builtin_vsx_xvcmpeqsp", + "vsx.xvcmpeqsp.p" => "__builtin_vsx_xvcmpeqsp_p", + "vsx.xvcmpgedp" => "__builtin_vsx_xvcmpgedp", + "vsx.xvcmpgedp.p" => "__builtin_vsx_xvcmpgedp_p", + "vsx.xvcmpgesp" => "__builtin_vsx_xvcmpgesp", + "vsx.xvcmpgesp.p" => "__builtin_vsx_xvcmpgesp_p", + "vsx.xvcmpgtdp" => "__builtin_vsx_xvcmpgtdp", + "vsx.xvcmpgtdp.p" => "__builtin_vsx_xvcmpgtdp_p", + "vsx.xvcmpgtsp" => "__builtin_vsx_xvcmpgtsp", + "vsx.xvcmpgtsp.p" => "__builtin_vsx_xvcmpgtsp_p", + "vsx.xvcvbf16spn" => "__builtin_vsx_xvcvbf16spn", + "vsx.xvcvdpsp" => "__builtin_vsx_xvcvdpsp", + "vsx.xvcvdpsxws" => "__builtin_vsx_xvcvdpsxws", + "vsx.xvcvdpuxws" => "__builtin_vsx_xvcvdpuxws", + "vsx.xvcvhpsp" => "__builtin_vsx_xvcvhpsp", + "vsx.xvcvspbf16" => "__builtin_vsx_xvcvspbf16", + "vsx.xvcvspdp" => "__builtin_vsx_xvcvspdp", + "vsx.xvcvsphp" => "__builtin_vsx_xvcvsphp", + "vsx.xvcvspsxds" => "__builtin_vsx_xvcvspsxds", + "vsx.xvcvspuxds" => "__builtin_vsx_xvcvspuxds", + "vsx.xvcvsxdsp" => "__builtin_vsx_xvcvsxdsp", + "vsx.xvcvsxwdp" => "__builtin_vsx_xvcvsxwdp", + "vsx.xvcvuxdsp" => "__builtin_vsx_xvcvuxdsp", + "vsx.xvcvuxwdp" => "__builtin_vsx_xvcvuxwdp", + "vsx.xvdivdp" => "__builtin_vsx_xvdivdp", + "vsx.xvdivsp" => "__builtin_vsx_xvdivsp", + "vsx.xviexpdp" => "__builtin_vsx_xviexpdp", + "vsx.xviexpsp" => "__builtin_vsx_xviexpsp", + "vsx.xvmaxdp" => "__builtin_vsx_xvmaxdp", + "vsx.xvmaxsp" => "__builtin_vsx_xvmaxsp", + "vsx.xvmindp" => "__builtin_vsx_xvmindp", + "vsx.xvminsp" => "__builtin_vsx_xvminsp", + "vsx.xvredp" => "__builtin_vsx_xvredp", + "vsx.xvresp" => "__builtin_vsx_xvresp", + "vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", + "vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", + "vsx.xvtdivdp" => "__builtin_vsx_xvtdivdp", + "vsx.xvtdivsp" => "__builtin_vsx_xvtdivsp", + "vsx.xvtlsbb" => "__builtin_vsx_xvtlsbb", + "vsx.xvtsqrtdp" => "__builtin_vsx_xvtsqrtdp", + "vsx.xvtsqrtsp" => "__builtin_vsx_xvtsqrtsp", + "vsx.xvtstdcdp" => "__builtin_vsx_xvtstdcdp", + "vsx.xvtstdcsp" => "__builtin_vsx_xvtstdcsp", + "vsx.xvxexpdp" => "__builtin_vsx_xvxexpdp", + "vsx.xvxexpsp" => "__builtin_vsx_xvxexpsp", + "vsx.xvxsigdp" => "__builtin_vsx_xvxsigdp", + "vsx.xvxsigsp" => "__builtin_vsx_xvxsigsp", + "vsx.xxblendvb" => "__builtin_vsx_xxblendvb", + "vsx.xxblendvd" => "__builtin_vsx_xxblendvd", + "vsx.xxblendvh" => "__builtin_vsx_xxblendvh", + "vsx.xxblendvw" => "__builtin_vsx_xxblendvw", + "vsx.xxeval" => "__builtin_vsx_xxeval", + "vsx.xxextractuw" => "__builtin_vsx_xxextractuw", + "vsx.xxgenpcvbm" => "__builtin_vsx_xxgenpcvbm", + "vsx.xxgenpcvdm" => "__builtin_vsx_xxgenpcvdm", + "vsx.xxgenpcvhm" => "__builtin_vsx_xxgenpcvhm", + "vsx.xxgenpcvwm" => "__builtin_vsx_xxgenpcvwm", + "vsx.xxinsertw" => "__builtin_vsx_xxinsertw", + "vsx.xxleqv" => "__builtin_vsx_xxleqv", + "vsx.xxpermx" => "__builtin_vsx_xxpermx", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + ppc(name) + } + "ptx" => { + #[allow(non_snake_case)] + fn ptx(name: &str) -> &str { + match name { + // ptx + "bar.sync" => "__builtin_ptx_bar_sync", + "read.clock" => "__builtin_ptx_read_clock", + "read.clock64" => "__builtin_ptx_read_clock64", + "read.gridid" => "__builtin_ptx_read_gridid", + "read.laneid" => "__builtin_ptx_read_laneid", + "read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", + "read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", + "read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", + "read.lanemask.le" => "__builtin_ptx_read_lanemask_le", + "read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", + "read.nsmid" => "__builtin_ptx_read_nsmid", + "read.nwarpid" => "__builtin_ptx_read_nwarpid", + "read.pm0" => "__builtin_ptx_read_pm0", + "read.pm1" => "__builtin_ptx_read_pm1", + "read.pm2" => "__builtin_ptx_read_pm2", + "read.pm3" => "__builtin_ptx_read_pm3", + "read.smid" => "__builtin_ptx_read_smid", + "read.warpid" => "__builtin_ptx_read_warpid", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + ptx(name) + } + "r600" => { + #[allow(non_snake_case)] + fn r600(name: &str) -> &str { + match name { + // r600 + "group.barrier" => "__builtin_r600_group_barrier", + "implicitarg.ptr" => "__builtin_r600_implicitarg_ptr", + "rat.store.typed" => "__builtin_r600_rat_store_typed", + "read.global.size.x" => "__builtin_r600_read_global_size_x", + "read.global.size.y" => "__builtin_r600_read_global_size_y", + "read.global.size.z" => "__builtin_r600_read_global_size_z", + "read.ngroups.x" => "__builtin_r600_read_ngroups_x", + "read.ngroups.y" => "__builtin_r600_read_ngroups_y", + "read.ngroups.z" => "__builtin_r600_read_ngroups_z", + "read.tgid.x" => "__builtin_r600_read_tgid_x", + "read.tgid.y" => "__builtin_r600_read_tgid_y", + "read.tgid.z" => "__builtin_r600_read_tgid_z", + "read.tidig.x" => "__builtin_r600_read_tidig_x", + "read.tidig.y" => "__builtin_r600_read_tidig_y", + "read.tidig.z" => "__builtin_r600_read_tidig_z", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + r600(name) + } + "riscv" => { + #[allow(non_snake_case)] + fn riscv(name: &str) -> &str { + match name { + // riscv + "aes32dsi" => "__builtin_riscv_aes32dsi", + "aes32dsmi" => "__builtin_riscv_aes32dsmi", + "aes32esi" => "__builtin_riscv_aes32esi", + "aes32esmi" => "__builtin_riscv_aes32esmi", + "aes64ds" => "__builtin_riscv_aes64ds", + "aes64dsm" => "__builtin_riscv_aes64dsm", + "aes64es" => "__builtin_riscv_aes64es", + "aes64esm" => "__builtin_riscv_aes64esm", + "aes64im" => "__builtin_riscv_aes64im", + "aes64ks1i" => "__builtin_riscv_aes64ks1i", + "aes64ks2" => "__builtin_riscv_aes64ks2", + "sha512sig0" => "__builtin_riscv_sha512sig0", + "sha512sig0h" => "__builtin_riscv_sha512sig0h", + "sha512sig0l" => "__builtin_riscv_sha512sig0l", + "sha512sig1" => "__builtin_riscv_sha512sig1", + "sha512sig1h" => "__builtin_riscv_sha512sig1h", + "sha512sig1l" => "__builtin_riscv_sha512sig1l", + "sha512sum0" => "__builtin_riscv_sha512sum0", + "sha512sum0r" => "__builtin_riscv_sha512sum0r", + "sha512sum1" => "__builtin_riscv_sha512sum1", + "sha512sum1r" => "__builtin_riscv_sha512sum1r", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + riscv(name) + } + "s390" => { + #[allow(non_snake_case)] + fn s390(name: &str) -> &str { + match name { + // s390 + "bdepg" => "__builtin_s390_bdepg", + "bextg" => "__builtin_s390_bextg", + "efpc" => "__builtin_s390_efpc", + "etnd" => "__builtin_tx_nesting_depth", + "lcbb" => "__builtin_s390_lcbb", + "ppa.txassist" => "__builtin_tx_assist", + "sfpc" => "__builtin_s390_sfpc", + "tend" => "__builtin_tend", + "vaccb" => "__builtin_s390_vaccb", + "vacccq" => "__builtin_s390_vacccq", + "vaccf" => "__builtin_s390_vaccf", + "vaccg" => "__builtin_s390_vaccg", + "vacch" => "__builtin_s390_vacch", + "vaccq" => "__builtin_s390_vaccq", + "vacq" => "__builtin_s390_vacq", + "vaq" => "__builtin_s390_vaq", + "vavgb" => "__builtin_s390_vavgb", + "vavgf" => "__builtin_s390_vavgf", + "vavgg" => "__builtin_s390_vavgg", + "vavgh" => "__builtin_s390_vavgh", + "vavglb" => "__builtin_s390_vavglb", + "vavglf" => "__builtin_s390_vavglf", + "vavglg" => "__builtin_s390_vavglg", + "vavglh" => "__builtin_s390_vavglh", + "vavglq" => "__builtin_s390_vavglq", + "vavgq" => "__builtin_s390_vavgq", + "vbperm" => "__builtin_s390_vbperm", + "vcfn" => "__builtin_s390_vcfn", + "vcksm" => "__builtin_s390_vcksm", + "vclfnhs" => "__builtin_s390_vclfnhs", + "vclfnls" => "__builtin_s390_vclfnls", + "vcnf" => "__builtin_s390_vcnf", + "vcrnfs" => "__builtin_s390_vcrnfs", + "verimb" => "__builtin_s390_verimb", + "verimf" => "__builtin_s390_verimf", + "verimg" => "__builtin_s390_verimg", + "verimh" => "__builtin_s390_verimh", + "veval" => "__builtin_s390_veval", + "vfaeb" => "__builtin_s390_vfaeb", + "vfaef" => "__builtin_s390_vfaef", + "vfaeh" => "__builtin_s390_vfaeh", + "vfaezb" => "__builtin_s390_vfaezb", + "vfaezf" => "__builtin_s390_vfaezf", + "vfaezh" => "__builtin_s390_vfaezh", + "vfeeb" => "__builtin_s390_vfeeb", + "vfeef" => "__builtin_s390_vfeef", + "vfeeh" => "__builtin_s390_vfeeh", + "vfeezb" => "__builtin_s390_vfeezb", + "vfeezf" => "__builtin_s390_vfeezf", + "vfeezh" => "__builtin_s390_vfeezh", + "vfeneb" => "__builtin_s390_vfeneb", + "vfenef" => "__builtin_s390_vfenef", + "vfeneh" => "__builtin_s390_vfeneh", + "vfenezb" => "__builtin_s390_vfenezb", + "vfenezf" => "__builtin_s390_vfenezf", + "vfenezh" => "__builtin_s390_vfenezh", + "vgemb" => "__builtin_s390_vgemb", + "vgemf" => "__builtin_s390_vgemf", + "vgemg" => "__builtin_s390_vgemg", + "vgemh" => "__builtin_s390_vgemh", + "vgemq" => "__builtin_s390_vgemq", + "vgfmab" => "__builtin_s390_vgfmab", + "vgfmaf" => "__builtin_s390_vgfmaf", + "vgfmag" => "__builtin_s390_vgfmag", + "vgfmah" => "__builtin_s390_vgfmah", + "vgfmb" => "__builtin_s390_vgfmb", + "vgfmf" => "__builtin_s390_vgfmf", + "vgfmg" => "__builtin_s390_vgfmg", + "vgfmh" => "__builtin_s390_vgfmh", + "vistrb" => "__builtin_s390_vistrb", + "vistrf" => "__builtin_s390_vistrf", + "vistrh" => "__builtin_s390_vistrh", + "vlbb" => "__builtin_s390_vlbb", + "vll" => "__builtin_s390_vll", + "vlrl" => "__builtin_s390_vlrlr", + "vmaeb" => "__builtin_s390_vmaeb", + "vmaef" => "__builtin_s390_vmaef", + "vmaeg" => "__builtin_s390_vmaeg", + "vmaeh" => "__builtin_s390_vmaeh", + "vmahb" => "__builtin_s390_vmahb", + "vmahf" => "__builtin_s390_vmahf", + "vmahg" => "__builtin_s390_vmahg", + "vmahh" => "__builtin_s390_vmahh", + "vmahq" => "__builtin_s390_vmahq", + "vmaleb" => "__builtin_s390_vmaleb", + "vmalef" => "__builtin_s390_vmalef", + "vmaleg" => "__builtin_s390_vmaleg", + "vmaleh" => "__builtin_s390_vmaleh", + "vmalhb" => "__builtin_s390_vmalhb", + "vmalhf" => "__builtin_s390_vmalhf", + "vmalhg" => "__builtin_s390_vmalhg", + "vmalhh" => "__builtin_s390_vmalhh", + "vmalhq" => "__builtin_s390_vmalhq", + "vmalob" => "__builtin_s390_vmalob", + "vmalof" => "__builtin_s390_vmalof", + "vmalog" => "__builtin_s390_vmalog", + "vmaloh" => "__builtin_s390_vmaloh", + "vmaob" => "__builtin_s390_vmaob", + "vmaof" => "__builtin_s390_vmaof", + "vmaog" => "__builtin_s390_vmaog", + "vmaoh" => "__builtin_s390_vmaoh", + "vmeb" => "__builtin_s390_vmeb", + "vmef" => "__builtin_s390_vmef", + "vmeg" => "__builtin_s390_vmeg", + "vmeh" => "__builtin_s390_vmeh", + "vmhb" => "__builtin_s390_vmhb", + "vmhf" => "__builtin_s390_vmhf", + "vmhg" => "__builtin_s390_vmhg", + "vmhh" => "__builtin_s390_vmhh", + "vmhq" => "__builtin_s390_vmhq", + "vmleb" => "__builtin_s390_vmleb", + "vmlef" => "__builtin_s390_vmlef", + "vmleg" => "__builtin_s390_vmleg", + "vmleh" => "__builtin_s390_vmleh", + "vmlhb" => "__builtin_s390_vmlhb", + "vmlhf" => "__builtin_s390_vmlhf", + "vmlhg" => "__builtin_s390_vmlhg", + "vmlhh" => "__builtin_s390_vmlhh", + "vmlhq" => "__builtin_s390_vmlhq", + "vmlob" => "__builtin_s390_vmlob", + "vmlof" => "__builtin_s390_vmlof", + "vmlog" => "__builtin_s390_vmlog", + "vmloh" => "__builtin_s390_vmloh", + "vmob" => "__builtin_s390_vmob", + "vmof" => "__builtin_s390_vmof", + "vmog" => "__builtin_s390_vmog", + "vmoh" => "__builtin_s390_vmoh", + "vmslg" => "__builtin_s390_vmslg", + "vpdi" => "__builtin_s390_vpdi", + "vperm" => "__builtin_s390_vperm", + "vpklsf" => "__builtin_s390_vpklsf", + "vpklsg" => "__builtin_s390_vpklsg", + "vpklsh" => "__builtin_s390_vpklsh", + "vpksf" => "__builtin_s390_vpksf", + "vpksg" => "__builtin_s390_vpksg", + "vpksh" => "__builtin_s390_vpksh", + "vsbcbiq" => "__builtin_s390_vsbcbiq", + "vsbiq" => "__builtin_s390_vsbiq", + "vscbib" => "__builtin_s390_vscbib", + "vscbif" => "__builtin_s390_vscbif", + "vscbig" => "__builtin_s390_vscbig", + "vscbih" => "__builtin_s390_vscbih", + "vscbiq" => "__builtin_s390_vscbiq", + "vsl" => "__builtin_s390_vsl", + "vslb" => "__builtin_s390_vslb", + "vsld" => "__builtin_s390_vsld", + "vsldb" => "__builtin_s390_vsldb", + "vsq" => "__builtin_s390_vsq", + "vsra" => "__builtin_s390_vsra", + "vsrab" => "__builtin_s390_vsrab", + "vsrd" => "__builtin_s390_vsrd", + "vsrl" => "__builtin_s390_vsrl", + "vsrlb" => "__builtin_s390_vsrlb", + "vstl" => "__builtin_s390_vstl", + "vstrcb" => "__builtin_s390_vstrcb", + "vstrcf" => "__builtin_s390_vstrcf", + "vstrch" => "__builtin_s390_vstrch", + "vstrczb" => "__builtin_s390_vstrczb", + "vstrczf" => "__builtin_s390_vstrczf", + "vstrczh" => "__builtin_s390_vstrczh", + "vstrl" => "__builtin_s390_vstrlr", + "vsumb" => "__builtin_s390_vsumb", + "vsumgf" => "__builtin_s390_vsumgf", + "vsumgh" => "__builtin_s390_vsumgh", + "vsumh" => "__builtin_s390_vsumh", + "vsumqf" => "__builtin_s390_vsumqf", + "vsumqg" => "__builtin_s390_vsumqg", + "vtm" => "__builtin_s390_vtm", + "vuphb" => "__builtin_s390_vuphb", + "vuphf" => "__builtin_s390_vuphf", + "vuphg" => "__builtin_s390_vuphg", + "vuphh" => "__builtin_s390_vuphh", + "vuplb" => "__builtin_s390_vuplb", + "vuplf" => "__builtin_s390_vuplf", + "vuplg" => "__builtin_s390_vuplg", + "vuplhb" => "__builtin_s390_vuplhb", + "vuplhf" => "__builtin_s390_vuplhf", + "vuplhg" => "__builtin_s390_vuplhg", + "vuplhh" => "__builtin_s390_vuplhh", + "vuplhw" => "__builtin_s390_vuplhw", + "vupllb" => "__builtin_s390_vupllb", + "vupllf" => "__builtin_s390_vupllf", + "vupllg" => "__builtin_s390_vupllg", + "vupllh" => "__builtin_s390_vupllh", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + s390(name) + } + "ve" => { + #[allow(non_snake_case)] + fn ve(name: &str) -> &str { + match name { + // ve + "vl.andm.MMM" => "__builtin_ve_vl_andm_MMM", + "vl.andm.mmm" => "__builtin_ve_vl_andm_mmm", + "vl.eqvm.MMM" => "__builtin_ve_vl_eqvm_MMM", + "vl.eqvm.mmm" => "__builtin_ve_vl_eqvm_mmm", + "vl.extract.vm512l" => "__builtin_ve_vl_extract_vm512l", + "vl.extract.vm512u" => "__builtin_ve_vl_extract_vm512u", + "vl.fencec.s" => "__builtin_ve_vl_fencec_s", + "vl.fencei" => "__builtin_ve_vl_fencei", + "vl.fencem.s" => "__builtin_ve_vl_fencem_s", + "vl.fidcr.sss" => "__builtin_ve_vl_fidcr_sss", + "vl.insert.vm512l" => "__builtin_ve_vl_insert_vm512l", + "vl.insert.vm512u" => "__builtin_ve_vl_insert_vm512u", + "vl.lcr.sss" => "__builtin_ve_vl_lcr_sss", + "vl.lsv.vvss" => "__builtin_ve_vl_lsv_vvss", + "vl.lvm.MMss" => "__builtin_ve_vl_lvm_MMss", + "vl.lvm.mmss" => "__builtin_ve_vl_lvm_mmss", + "vl.lvsd.svs" => "__builtin_ve_vl_lvsd_svs", + "vl.lvsl.svs" => "__builtin_ve_vl_lvsl_svs", + "vl.lvss.svs" => "__builtin_ve_vl_lvss_svs", + "vl.lzvm.sml" => "__builtin_ve_vl_lzvm_sml", + "vl.negm.MM" => "__builtin_ve_vl_negm_MM", + "vl.negm.mm" => "__builtin_ve_vl_negm_mm", + "vl.nndm.MMM" => "__builtin_ve_vl_nndm_MMM", + "vl.nndm.mmm" => "__builtin_ve_vl_nndm_mmm", + "vl.orm.MMM" => "__builtin_ve_vl_orm_MMM", + "vl.orm.mmm" => "__builtin_ve_vl_orm_mmm", + "vl.pack.f32a" => "__builtin_ve_vl_pack_f32a", + "vl.pack.f32p" => "__builtin_ve_vl_pack_f32p", + "vl.pcvm.sml" => "__builtin_ve_vl_pcvm_sml", + "vl.pfchv.ssl" => "__builtin_ve_vl_pfchv_ssl", + "vl.pfchvnc.ssl" => "__builtin_ve_vl_pfchvnc_ssl", + "vl.pvadds.vsvMvl" => "__builtin_ve_vl_pvadds_vsvMvl", + "vl.pvadds.vsvl" => "__builtin_ve_vl_pvadds_vsvl", + "vl.pvadds.vsvvl" => "__builtin_ve_vl_pvadds_vsvvl", + "vl.pvadds.vvvMvl" => "__builtin_ve_vl_pvadds_vvvMvl", + "vl.pvadds.vvvl" => "__builtin_ve_vl_pvadds_vvvl", + "vl.pvadds.vvvvl" => "__builtin_ve_vl_pvadds_vvvvl", + "vl.pvaddu.vsvMvl" => "__builtin_ve_vl_pvaddu_vsvMvl", + "vl.pvaddu.vsvl" => "__builtin_ve_vl_pvaddu_vsvl", + "vl.pvaddu.vsvvl" => "__builtin_ve_vl_pvaddu_vsvvl", + "vl.pvaddu.vvvMvl" => "__builtin_ve_vl_pvaddu_vvvMvl", + "vl.pvaddu.vvvl" => "__builtin_ve_vl_pvaddu_vvvl", + "vl.pvaddu.vvvvl" => "__builtin_ve_vl_pvaddu_vvvvl", + "vl.pvand.vsvMvl" => "__builtin_ve_vl_pvand_vsvMvl", + "vl.pvand.vsvl" => "__builtin_ve_vl_pvand_vsvl", + "vl.pvand.vsvvl" => "__builtin_ve_vl_pvand_vsvvl", + "vl.pvand.vvvMvl" => "__builtin_ve_vl_pvand_vvvMvl", + "vl.pvand.vvvl" => "__builtin_ve_vl_pvand_vvvl", + "vl.pvand.vvvvl" => "__builtin_ve_vl_pvand_vvvvl", + "vl.pvbrd.vsMvl" => "__builtin_ve_vl_pvbrd_vsMvl", + "vl.pvbrd.vsl" => "__builtin_ve_vl_pvbrd_vsl", + "vl.pvbrd.vsvl" => "__builtin_ve_vl_pvbrd_vsvl", + "vl.pvbrv.vvMvl" => "__builtin_ve_vl_pvbrv_vvMvl", + "vl.pvbrv.vvl" => "__builtin_ve_vl_pvbrv_vvl", + "vl.pvbrv.vvvl" => "__builtin_ve_vl_pvbrv_vvvl", + "vl.pvbrvlo.vvl" => "__builtin_ve_vl_pvbrvlo_vvl", + "vl.pvbrvlo.vvmvl" => "__builtin_ve_vl_pvbrvlo_vvmvl", + "vl.pvbrvlo.vvvl" => "__builtin_ve_vl_pvbrvlo_vvvl", + "vl.pvbrvup.vvl" => "__builtin_ve_vl_pvbrvup_vvl", + "vl.pvbrvup.vvmvl" => "__builtin_ve_vl_pvbrvup_vvmvl", + "vl.pvbrvup.vvvl" => "__builtin_ve_vl_pvbrvup_vvvl", + "vl.pvcmps.vsvMvl" => "__builtin_ve_vl_pvcmps_vsvMvl", + "vl.pvcmps.vsvl" => "__builtin_ve_vl_pvcmps_vsvl", + "vl.pvcmps.vsvvl" => "__builtin_ve_vl_pvcmps_vsvvl", + "vl.pvcmps.vvvMvl" => "__builtin_ve_vl_pvcmps_vvvMvl", + "vl.pvcmps.vvvl" => "__builtin_ve_vl_pvcmps_vvvl", + "vl.pvcmps.vvvvl" => "__builtin_ve_vl_pvcmps_vvvvl", + "vl.pvcmpu.vsvMvl" => "__builtin_ve_vl_pvcmpu_vsvMvl", + "vl.pvcmpu.vsvl" => "__builtin_ve_vl_pvcmpu_vsvl", + "vl.pvcmpu.vsvvl" => "__builtin_ve_vl_pvcmpu_vsvvl", + "vl.pvcmpu.vvvMvl" => "__builtin_ve_vl_pvcmpu_vvvMvl", + "vl.pvcmpu.vvvl" => "__builtin_ve_vl_pvcmpu_vvvl", + "vl.pvcmpu.vvvvl" => "__builtin_ve_vl_pvcmpu_vvvvl", + "vl.pvcvtsw.vvl" => "__builtin_ve_vl_pvcvtsw_vvl", + "vl.pvcvtsw.vvvl" => "__builtin_ve_vl_pvcvtsw_vvvl", + "vl.pvcvtws.vvMvl" => "__builtin_ve_vl_pvcvtws_vvMvl", + "vl.pvcvtws.vvl" => "__builtin_ve_vl_pvcvtws_vvl", + "vl.pvcvtws.vvvl" => "__builtin_ve_vl_pvcvtws_vvvl", + "vl.pvcvtwsrz.vvMvl" => "__builtin_ve_vl_pvcvtwsrz_vvMvl", + "vl.pvcvtwsrz.vvl" => "__builtin_ve_vl_pvcvtwsrz_vvl", + "vl.pvcvtwsrz.vvvl" => "__builtin_ve_vl_pvcvtwsrz_vvvl", + "vl.pveqv.vsvMvl" => "__builtin_ve_vl_pveqv_vsvMvl", + "vl.pveqv.vsvl" => "__builtin_ve_vl_pveqv_vsvl", + "vl.pveqv.vsvvl" => "__builtin_ve_vl_pveqv_vsvvl", + "vl.pveqv.vvvMvl" => "__builtin_ve_vl_pveqv_vvvMvl", + "vl.pveqv.vvvl" => "__builtin_ve_vl_pveqv_vvvl", + "vl.pveqv.vvvvl" => "__builtin_ve_vl_pveqv_vvvvl", + "vl.pvfadd.vsvMvl" => "__builtin_ve_vl_pvfadd_vsvMvl", + "vl.pvfadd.vsvl" => "__builtin_ve_vl_pvfadd_vsvl", + "vl.pvfadd.vsvvl" => "__builtin_ve_vl_pvfadd_vsvvl", + "vl.pvfadd.vvvMvl" => "__builtin_ve_vl_pvfadd_vvvMvl", + "vl.pvfadd.vvvl" => "__builtin_ve_vl_pvfadd_vvvl", + "vl.pvfadd.vvvvl" => "__builtin_ve_vl_pvfadd_vvvvl", + "vl.pvfcmp.vsvMvl" => "__builtin_ve_vl_pvfcmp_vsvMvl", + "vl.pvfcmp.vsvl" => "__builtin_ve_vl_pvfcmp_vsvl", + "vl.pvfcmp.vsvvl" => "__builtin_ve_vl_pvfcmp_vsvvl", + "vl.pvfcmp.vvvMvl" => "__builtin_ve_vl_pvfcmp_vvvMvl", + "vl.pvfcmp.vvvl" => "__builtin_ve_vl_pvfcmp_vvvl", + "vl.pvfcmp.vvvvl" => "__builtin_ve_vl_pvfcmp_vvvvl", + "vl.pvfmad.vsvvMvl" => "__builtin_ve_vl_pvfmad_vsvvMvl", + "vl.pvfmad.vsvvl" => "__builtin_ve_vl_pvfmad_vsvvl", + "vl.pvfmad.vsvvvl" => "__builtin_ve_vl_pvfmad_vsvvvl", + "vl.pvfmad.vvsvMvl" => "__builtin_ve_vl_pvfmad_vvsvMvl", + "vl.pvfmad.vvsvl" => "__builtin_ve_vl_pvfmad_vvsvl", + "vl.pvfmad.vvsvvl" => "__builtin_ve_vl_pvfmad_vvsvvl", + "vl.pvfmad.vvvvMvl" => "__builtin_ve_vl_pvfmad_vvvvMvl", + "vl.pvfmad.vvvvl" => "__builtin_ve_vl_pvfmad_vvvvl", + "vl.pvfmad.vvvvvl" => "__builtin_ve_vl_pvfmad_vvvvvl", + "vl.pvfmax.vsvMvl" => "__builtin_ve_vl_pvfmax_vsvMvl", + "vl.pvfmax.vsvl" => "__builtin_ve_vl_pvfmax_vsvl", + "vl.pvfmax.vsvvl" => "__builtin_ve_vl_pvfmax_vsvvl", + "vl.pvfmax.vvvMvl" => "__builtin_ve_vl_pvfmax_vvvMvl", + "vl.pvfmax.vvvl" => "__builtin_ve_vl_pvfmax_vvvl", + "vl.pvfmax.vvvvl" => "__builtin_ve_vl_pvfmax_vvvvl", + "vl.pvfmin.vsvMvl" => "__builtin_ve_vl_pvfmin_vsvMvl", + "vl.pvfmin.vsvl" => "__builtin_ve_vl_pvfmin_vsvl", + "vl.pvfmin.vsvvl" => "__builtin_ve_vl_pvfmin_vsvvl", + "vl.pvfmin.vvvMvl" => "__builtin_ve_vl_pvfmin_vvvMvl", + "vl.pvfmin.vvvl" => "__builtin_ve_vl_pvfmin_vvvl", + "vl.pvfmin.vvvvl" => "__builtin_ve_vl_pvfmin_vvvvl", + "vl.pvfmkaf.Ml" => "__builtin_ve_vl_pvfmkaf_Ml", + "vl.pvfmkat.Ml" => "__builtin_ve_vl_pvfmkat_Ml", + "vl.pvfmkseq.MvMl" => "__builtin_ve_vl_pvfmkseq_MvMl", + "vl.pvfmkseq.Mvl" => "__builtin_ve_vl_pvfmkseq_Mvl", + "vl.pvfmkseqnan.MvMl" => "__builtin_ve_vl_pvfmkseqnan_MvMl", + "vl.pvfmkseqnan.Mvl" => "__builtin_ve_vl_pvfmkseqnan_Mvl", + "vl.pvfmksge.MvMl" => "__builtin_ve_vl_pvfmksge_MvMl", + "vl.pvfmksge.Mvl" => "__builtin_ve_vl_pvfmksge_Mvl", + "vl.pvfmksgenan.MvMl" => "__builtin_ve_vl_pvfmksgenan_MvMl", + "vl.pvfmksgenan.Mvl" => "__builtin_ve_vl_pvfmksgenan_Mvl", + "vl.pvfmksgt.MvMl" => "__builtin_ve_vl_pvfmksgt_MvMl", + "vl.pvfmksgt.Mvl" => "__builtin_ve_vl_pvfmksgt_Mvl", + "vl.pvfmksgtnan.MvMl" => "__builtin_ve_vl_pvfmksgtnan_MvMl", + "vl.pvfmksgtnan.Mvl" => "__builtin_ve_vl_pvfmksgtnan_Mvl", + "vl.pvfmksle.MvMl" => "__builtin_ve_vl_pvfmksle_MvMl", + "vl.pvfmksle.Mvl" => "__builtin_ve_vl_pvfmksle_Mvl", + "vl.pvfmkslenan.MvMl" => "__builtin_ve_vl_pvfmkslenan_MvMl", + "vl.pvfmkslenan.Mvl" => "__builtin_ve_vl_pvfmkslenan_Mvl", + "vl.pvfmksloeq.mvl" => "__builtin_ve_vl_pvfmksloeq_mvl", + "vl.pvfmksloeq.mvml" => "__builtin_ve_vl_pvfmksloeq_mvml", + "vl.pvfmksloeqnan.mvl" => "__builtin_ve_vl_pvfmksloeqnan_mvl", + "vl.pvfmksloeqnan.mvml" => "__builtin_ve_vl_pvfmksloeqnan_mvml", + "vl.pvfmksloge.mvl" => "__builtin_ve_vl_pvfmksloge_mvl", + "vl.pvfmksloge.mvml" => "__builtin_ve_vl_pvfmksloge_mvml", + "vl.pvfmkslogenan.mvl" => "__builtin_ve_vl_pvfmkslogenan_mvl", + "vl.pvfmkslogenan.mvml" => "__builtin_ve_vl_pvfmkslogenan_mvml", + "vl.pvfmkslogt.mvl" => "__builtin_ve_vl_pvfmkslogt_mvl", + "vl.pvfmkslogt.mvml" => "__builtin_ve_vl_pvfmkslogt_mvml", + "vl.pvfmkslogtnan.mvl" => "__builtin_ve_vl_pvfmkslogtnan_mvl", + "vl.pvfmkslogtnan.mvml" => "__builtin_ve_vl_pvfmkslogtnan_mvml", + "vl.pvfmkslole.mvl" => "__builtin_ve_vl_pvfmkslole_mvl", + "vl.pvfmkslole.mvml" => "__builtin_ve_vl_pvfmkslole_mvml", + "vl.pvfmkslolenan.mvl" => "__builtin_ve_vl_pvfmkslolenan_mvl", + "vl.pvfmkslolenan.mvml" => "__builtin_ve_vl_pvfmkslolenan_mvml", + "vl.pvfmkslolt.mvl" => "__builtin_ve_vl_pvfmkslolt_mvl", + "vl.pvfmkslolt.mvml" => "__builtin_ve_vl_pvfmkslolt_mvml", + "vl.pvfmksloltnan.mvl" => "__builtin_ve_vl_pvfmksloltnan_mvl", + "vl.pvfmksloltnan.mvml" => "__builtin_ve_vl_pvfmksloltnan_mvml", + "vl.pvfmkslonan.mvl" => "__builtin_ve_vl_pvfmkslonan_mvl", + "vl.pvfmkslonan.mvml" => "__builtin_ve_vl_pvfmkslonan_mvml", + "vl.pvfmkslone.mvl" => "__builtin_ve_vl_pvfmkslone_mvl", + "vl.pvfmkslone.mvml" => "__builtin_ve_vl_pvfmkslone_mvml", + "vl.pvfmkslonenan.mvl" => "__builtin_ve_vl_pvfmkslonenan_mvl", + "vl.pvfmkslonenan.mvml" => "__builtin_ve_vl_pvfmkslonenan_mvml", + "vl.pvfmkslonum.mvl" => "__builtin_ve_vl_pvfmkslonum_mvl", + "vl.pvfmkslonum.mvml" => "__builtin_ve_vl_pvfmkslonum_mvml", + "vl.pvfmkslt.MvMl" => "__builtin_ve_vl_pvfmkslt_MvMl", + "vl.pvfmkslt.Mvl" => "__builtin_ve_vl_pvfmkslt_Mvl", + "vl.pvfmksltnan.MvMl" => "__builtin_ve_vl_pvfmksltnan_MvMl", + "vl.pvfmksltnan.Mvl" => "__builtin_ve_vl_pvfmksltnan_Mvl", + "vl.pvfmksnan.MvMl" => "__builtin_ve_vl_pvfmksnan_MvMl", + "vl.pvfmksnan.Mvl" => "__builtin_ve_vl_pvfmksnan_Mvl", + "vl.pvfmksne.MvMl" => "__builtin_ve_vl_pvfmksne_MvMl", + "vl.pvfmksne.Mvl" => "__builtin_ve_vl_pvfmksne_Mvl", + "vl.pvfmksnenan.MvMl" => "__builtin_ve_vl_pvfmksnenan_MvMl", + "vl.pvfmksnenan.Mvl" => "__builtin_ve_vl_pvfmksnenan_Mvl", + "vl.pvfmksnum.MvMl" => "__builtin_ve_vl_pvfmksnum_MvMl", + "vl.pvfmksnum.Mvl" => "__builtin_ve_vl_pvfmksnum_Mvl", + "vl.pvfmksupeq.mvl" => "__builtin_ve_vl_pvfmksupeq_mvl", + "vl.pvfmksupeq.mvml" => "__builtin_ve_vl_pvfmksupeq_mvml", + "vl.pvfmksupeqnan.mvl" => "__builtin_ve_vl_pvfmksupeqnan_mvl", + "vl.pvfmksupeqnan.mvml" => "__builtin_ve_vl_pvfmksupeqnan_mvml", + "vl.pvfmksupge.mvl" => "__builtin_ve_vl_pvfmksupge_mvl", + "vl.pvfmksupge.mvml" => "__builtin_ve_vl_pvfmksupge_mvml", + "vl.pvfmksupgenan.mvl" => "__builtin_ve_vl_pvfmksupgenan_mvl", + "vl.pvfmksupgenan.mvml" => "__builtin_ve_vl_pvfmksupgenan_mvml", + "vl.pvfmksupgt.mvl" => "__builtin_ve_vl_pvfmksupgt_mvl", + "vl.pvfmksupgt.mvml" => "__builtin_ve_vl_pvfmksupgt_mvml", + "vl.pvfmksupgtnan.mvl" => "__builtin_ve_vl_pvfmksupgtnan_mvl", + "vl.pvfmksupgtnan.mvml" => "__builtin_ve_vl_pvfmksupgtnan_mvml", + "vl.pvfmksuple.mvl" => "__builtin_ve_vl_pvfmksuple_mvl", + "vl.pvfmksuple.mvml" => "__builtin_ve_vl_pvfmksuple_mvml", + "vl.pvfmksuplenan.mvl" => "__builtin_ve_vl_pvfmksuplenan_mvl", + "vl.pvfmksuplenan.mvml" => "__builtin_ve_vl_pvfmksuplenan_mvml", + "vl.pvfmksuplt.mvl" => "__builtin_ve_vl_pvfmksuplt_mvl", + "vl.pvfmksuplt.mvml" => "__builtin_ve_vl_pvfmksuplt_mvml", + "vl.pvfmksupltnan.mvl" => "__builtin_ve_vl_pvfmksupltnan_mvl", + "vl.pvfmksupltnan.mvml" => "__builtin_ve_vl_pvfmksupltnan_mvml", + "vl.pvfmksupnan.mvl" => "__builtin_ve_vl_pvfmksupnan_mvl", + "vl.pvfmksupnan.mvml" => "__builtin_ve_vl_pvfmksupnan_mvml", + "vl.pvfmksupne.mvl" => "__builtin_ve_vl_pvfmksupne_mvl", + "vl.pvfmksupne.mvml" => "__builtin_ve_vl_pvfmksupne_mvml", + "vl.pvfmksupnenan.mvl" => "__builtin_ve_vl_pvfmksupnenan_mvl", + "vl.pvfmksupnenan.mvml" => "__builtin_ve_vl_pvfmksupnenan_mvml", + "vl.pvfmksupnum.mvl" => "__builtin_ve_vl_pvfmksupnum_mvl", + "vl.pvfmksupnum.mvml" => "__builtin_ve_vl_pvfmksupnum_mvml", + "vl.pvfmkweq.MvMl" => "__builtin_ve_vl_pvfmkweq_MvMl", + "vl.pvfmkweq.Mvl" => "__builtin_ve_vl_pvfmkweq_Mvl", + "vl.pvfmkweqnan.MvMl" => "__builtin_ve_vl_pvfmkweqnan_MvMl", + "vl.pvfmkweqnan.Mvl" => "__builtin_ve_vl_pvfmkweqnan_Mvl", + "vl.pvfmkwge.MvMl" => "__builtin_ve_vl_pvfmkwge_MvMl", + "vl.pvfmkwge.Mvl" => "__builtin_ve_vl_pvfmkwge_Mvl", + "vl.pvfmkwgenan.MvMl" => "__builtin_ve_vl_pvfmkwgenan_MvMl", + "vl.pvfmkwgenan.Mvl" => "__builtin_ve_vl_pvfmkwgenan_Mvl", + "vl.pvfmkwgt.MvMl" => "__builtin_ve_vl_pvfmkwgt_MvMl", + "vl.pvfmkwgt.Mvl" => "__builtin_ve_vl_pvfmkwgt_Mvl", + "vl.pvfmkwgtnan.MvMl" => "__builtin_ve_vl_pvfmkwgtnan_MvMl", + "vl.pvfmkwgtnan.Mvl" => "__builtin_ve_vl_pvfmkwgtnan_Mvl", + "vl.pvfmkwle.MvMl" => "__builtin_ve_vl_pvfmkwle_MvMl", + "vl.pvfmkwle.Mvl" => "__builtin_ve_vl_pvfmkwle_Mvl", + "vl.pvfmkwlenan.MvMl" => "__builtin_ve_vl_pvfmkwlenan_MvMl", + "vl.pvfmkwlenan.Mvl" => "__builtin_ve_vl_pvfmkwlenan_Mvl", + "vl.pvfmkwloeq.mvl" => "__builtin_ve_vl_pvfmkwloeq_mvl", + "vl.pvfmkwloeq.mvml" => "__builtin_ve_vl_pvfmkwloeq_mvml", + "vl.pvfmkwloeqnan.mvl" => "__builtin_ve_vl_pvfmkwloeqnan_mvl", + "vl.pvfmkwloeqnan.mvml" => "__builtin_ve_vl_pvfmkwloeqnan_mvml", + "vl.pvfmkwloge.mvl" => "__builtin_ve_vl_pvfmkwloge_mvl", + "vl.pvfmkwloge.mvml" => "__builtin_ve_vl_pvfmkwloge_mvml", + "vl.pvfmkwlogenan.mvl" => "__builtin_ve_vl_pvfmkwlogenan_mvl", + "vl.pvfmkwlogenan.mvml" => "__builtin_ve_vl_pvfmkwlogenan_mvml", + "vl.pvfmkwlogt.mvl" => "__builtin_ve_vl_pvfmkwlogt_mvl", + "vl.pvfmkwlogt.mvml" => "__builtin_ve_vl_pvfmkwlogt_mvml", + "vl.pvfmkwlogtnan.mvl" => "__builtin_ve_vl_pvfmkwlogtnan_mvl", + "vl.pvfmkwlogtnan.mvml" => "__builtin_ve_vl_pvfmkwlogtnan_mvml", + "vl.pvfmkwlole.mvl" => "__builtin_ve_vl_pvfmkwlole_mvl", + "vl.pvfmkwlole.mvml" => "__builtin_ve_vl_pvfmkwlole_mvml", + "vl.pvfmkwlolenan.mvl" => "__builtin_ve_vl_pvfmkwlolenan_mvl", + "vl.pvfmkwlolenan.mvml" => "__builtin_ve_vl_pvfmkwlolenan_mvml", + "vl.pvfmkwlolt.mvl" => "__builtin_ve_vl_pvfmkwlolt_mvl", + "vl.pvfmkwlolt.mvml" => "__builtin_ve_vl_pvfmkwlolt_mvml", + "vl.pvfmkwloltnan.mvl" => "__builtin_ve_vl_pvfmkwloltnan_mvl", + "vl.pvfmkwloltnan.mvml" => "__builtin_ve_vl_pvfmkwloltnan_mvml", + "vl.pvfmkwlonan.mvl" => "__builtin_ve_vl_pvfmkwlonan_mvl", + "vl.pvfmkwlonan.mvml" => "__builtin_ve_vl_pvfmkwlonan_mvml", + "vl.pvfmkwlone.mvl" => "__builtin_ve_vl_pvfmkwlone_mvl", + "vl.pvfmkwlone.mvml" => "__builtin_ve_vl_pvfmkwlone_mvml", + "vl.pvfmkwlonenan.mvl" => "__builtin_ve_vl_pvfmkwlonenan_mvl", + "vl.pvfmkwlonenan.mvml" => "__builtin_ve_vl_pvfmkwlonenan_mvml", + "vl.pvfmkwlonum.mvl" => "__builtin_ve_vl_pvfmkwlonum_mvl", + "vl.pvfmkwlonum.mvml" => "__builtin_ve_vl_pvfmkwlonum_mvml", + "vl.pvfmkwlt.MvMl" => "__builtin_ve_vl_pvfmkwlt_MvMl", + "vl.pvfmkwlt.Mvl" => "__builtin_ve_vl_pvfmkwlt_Mvl", + "vl.pvfmkwltnan.MvMl" => "__builtin_ve_vl_pvfmkwltnan_MvMl", + "vl.pvfmkwltnan.Mvl" => "__builtin_ve_vl_pvfmkwltnan_Mvl", + "vl.pvfmkwnan.MvMl" => "__builtin_ve_vl_pvfmkwnan_MvMl", + "vl.pvfmkwnan.Mvl" => "__builtin_ve_vl_pvfmkwnan_Mvl", + "vl.pvfmkwne.MvMl" => "__builtin_ve_vl_pvfmkwne_MvMl", + "vl.pvfmkwne.Mvl" => "__builtin_ve_vl_pvfmkwne_Mvl", + "vl.pvfmkwnenan.MvMl" => "__builtin_ve_vl_pvfmkwnenan_MvMl", + "vl.pvfmkwnenan.Mvl" => "__builtin_ve_vl_pvfmkwnenan_Mvl", + "vl.pvfmkwnum.MvMl" => "__builtin_ve_vl_pvfmkwnum_MvMl", + "vl.pvfmkwnum.Mvl" => "__builtin_ve_vl_pvfmkwnum_Mvl", + "vl.pvfmkwupeq.mvl" => "__builtin_ve_vl_pvfmkwupeq_mvl", + "vl.pvfmkwupeq.mvml" => "__builtin_ve_vl_pvfmkwupeq_mvml", + "vl.pvfmkwupeqnan.mvl" => "__builtin_ve_vl_pvfmkwupeqnan_mvl", + "vl.pvfmkwupeqnan.mvml" => "__builtin_ve_vl_pvfmkwupeqnan_mvml", + "vl.pvfmkwupge.mvl" => "__builtin_ve_vl_pvfmkwupge_mvl", + "vl.pvfmkwupge.mvml" => "__builtin_ve_vl_pvfmkwupge_mvml", + "vl.pvfmkwupgenan.mvl" => "__builtin_ve_vl_pvfmkwupgenan_mvl", + "vl.pvfmkwupgenan.mvml" => "__builtin_ve_vl_pvfmkwupgenan_mvml", + "vl.pvfmkwupgt.mvl" => "__builtin_ve_vl_pvfmkwupgt_mvl", + "vl.pvfmkwupgt.mvml" => "__builtin_ve_vl_pvfmkwupgt_mvml", + "vl.pvfmkwupgtnan.mvl" => "__builtin_ve_vl_pvfmkwupgtnan_mvl", + "vl.pvfmkwupgtnan.mvml" => "__builtin_ve_vl_pvfmkwupgtnan_mvml", + "vl.pvfmkwuple.mvl" => "__builtin_ve_vl_pvfmkwuple_mvl", + "vl.pvfmkwuple.mvml" => "__builtin_ve_vl_pvfmkwuple_mvml", + "vl.pvfmkwuplenan.mvl" => "__builtin_ve_vl_pvfmkwuplenan_mvl", + "vl.pvfmkwuplenan.mvml" => "__builtin_ve_vl_pvfmkwuplenan_mvml", + "vl.pvfmkwuplt.mvl" => "__builtin_ve_vl_pvfmkwuplt_mvl", + "vl.pvfmkwuplt.mvml" => "__builtin_ve_vl_pvfmkwuplt_mvml", + "vl.pvfmkwupltnan.mvl" => "__builtin_ve_vl_pvfmkwupltnan_mvl", + "vl.pvfmkwupltnan.mvml" => "__builtin_ve_vl_pvfmkwupltnan_mvml", + "vl.pvfmkwupnan.mvl" => "__builtin_ve_vl_pvfmkwupnan_mvl", + "vl.pvfmkwupnan.mvml" => "__builtin_ve_vl_pvfmkwupnan_mvml", + "vl.pvfmkwupne.mvl" => "__builtin_ve_vl_pvfmkwupne_mvl", + "vl.pvfmkwupne.mvml" => "__builtin_ve_vl_pvfmkwupne_mvml", + "vl.pvfmkwupnenan.mvl" => "__builtin_ve_vl_pvfmkwupnenan_mvl", + "vl.pvfmkwupnenan.mvml" => "__builtin_ve_vl_pvfmkwupnenan_mvml", + "vl.pvfmkwupnum.mvl" => "__builtin_ve_vl_pvfmkwupnum_mvl", + "vl.pvfmkwupnum.mvml" => "__builtin_ve_vl_pvfmkwupnum_mvml", + "vl.pvfmsb.vsvvMvl" => "__builtin_ve_vl_pvfmsb_vsvvMvl", + "vl.pvfmsb.vsvvl" => "__builtin_ve_vl_pvfmsb_vsvvl", + "vl.pvfmsb.vsvvvl" => "__builtin_ve_vl_pvfmsb_vsvvvl", + "vl.pvfmsb.vvsvMvl" => "__builtin_ve_vl_pvfmsb_vvsvMvl", + "vl.pvfmsb.vvsvl" => "__builtin_ve_vl_pvfmsb_vvsvl", + "vl.pvfmsb.vvsvvl" => "__builtin_ve_vl_pvfmsb_vvsvvl", + "vl.pvfmsb.vvvvMvl" => "__builtin_ve_vl_pvfmsb_vvvvMvl", + "vl.pvfmsb.vvvvl" => "__builtin_ve_vl_pvfmsb_vvvvl", + "vl.pvfmsb.vvvvvl" => "__builtin_ve_vl_pvfmsb_vvvvvl", + "vl.pvfmul.vsvMvl" => "__builtin_ve_vl_pvfmul_vsvMvl", + "vl.pvfmul.vsvl" => "__builtin_ve_vl_pvfmul_vsvl", + "vl.pvfmul.vsvvl" => "__builtin_ve_vl_pvfmul_vsvvl", + "vl.pvfmul.vvvMvl" => "__builtin_ve_vl_pvfmul_vvvMvl", + "vl.pvfmul.vvvl" => "__builtin_ve_vl_pvfmul_vvvl", + "vl.pvfmul.vvvvl" => "__builtin_ve_vl_pvfmul_vvvvl", + "vl.pvfnmad.vsvvMvl" => "__builtin_ve_vl_pvfnmad_vsvvMvl", + "vl.pvfnmad.vsvvl" => "__builtin_ve_vl_pvfnmad_vsvvl", + "vl.pvfnmad.vsvvvl" => "__builtin_ve_vl_pvfnmad_vsvvvl", + "vl.pvfnmad.vvsvMvl" => "__builtin_ve_vl_pvfnmad_vvsvMvl", + "vl.pvfnmad.vvsvl" => "__builtin_ve_vl_pvfnmad_vvsvl", + "vl.pvfnmad.vvsvvl" => "__builtin_ve_vl_pvfnmad_vvsvvl", + "vl.pvfnmad.vvvvMvl" => "__builtin_ve_vl_pvfnmad_vvvvMvl", + "vl.pvfnmad.vvvvl" => "__builtin_ve_vl_pvfnmad_vvvvl", + "vl.pvfnmad.vvvvvl" => "__builtin_ve_vl_pvfnmad_vvvvvl", + "vl.pvfnmsb.vsvvMvl" => "__builtin_ve_vl_pvfnmsb_vsvvMvl", + "vl.pvfnmsb.vsvvl" => "__builtin_ve_vl_pvfnmsb_vsvvl", + "vl.pvfnmsb.vsvvvl" => "__builtin_ve_vl_pvfnmsb_vsvvvl", + "vl.pvfnmsb.vvsvMvl" => "__builtin_ve_vl_pvfnmsb_vvsvMvl", + "vl.pvfnmsb.vvsvl" => "__builtin_ve_vl_pvfnmsb_vvsvl", + "vl.pvfnmsb.vvsvvl" => "__builtin_ve_vl_pvfnmsb_vvsvvl", + "vl.pvfnmsb.vvvvMvl" => "__builtin_ve_vl_pvfnmsb_vvvvMvl", + "vl.pvfnmsb.vvvvl" => "__builtin_ve_vl_pvfnmsb_vvvvl", + "vl.pvfnmsb.vvvvvl" => "__builtin_ve_vl_pvfnmsb_vvvvvl", + "vl.pvfsub.vsvMvl" => "__builtin_ve_vl_pvfsub_vsvMvl", + "vl.pvfsub.vsvl" => "__builtin_ve_vl_pvfsub_vsvl", + "vl.pvfsub.vsvvl" => "__builtin_ve_vl_pvfsub_vsvvl", + "vl.pvfsub.vvvMvl" => "__builtin_ve_vl_pvfsub_vvvMvl", + "vl.pvfsub.vvvl" => "__builtin_ve_vl_pvfsub_vvvl", + "vl.pvfsub.vvvvl" => "__builtin_ve_vl_pvfsub_vvvvl", + "vl.pvldz.vvMvl" => "__builtin_ve_vl_pvldz_vvMvl", + "vl.pvldz.vvl" => "__builtin_ve_vl_pvldz_vvl", + "vl.pvldz.vvvl" => "__builtin_ve_vl_pvldz_vvvl", + "vl.pvldzlo.vvl" => "__builtin_ve_vl_pvldzlo_vvl", + "vl.pvldzlo.vvmvl" => "__builtin_ve_vl_pvldzlo_vvmvl", + "vl.pvldzlo.vvvl" => "__builtin_ve_vl_pvldzlo_vvvl", + "vl.pvldzup.vvl" => "__builtin_ve_vl_pvldzup_vvl", + "vl.pvldzup.vvmvl" => "__builtin_ve_vl_pvldzup_vvmvl", + "vl.pvldzup.vvvl" => "__builtin_ve_vl_pvldzup_vvvl", + "vl.pvmaxs.vsvMvl" => "__builtin_ve_vl_pvmaxs_vsvMvl", + "vl.pvmaxs.vsvl" => "__builtin_ve_vl_pvmaxs_vsvl", + "vl.pvmaxs.vsvvl" => "__builtin_ve_vl_pvmaxs_vsvvl", + "vl.pvmaxs.vvvMvl" => "__builtin_ve_vl_pvmaxs_vvvMvl", + "vl.pvmaxs.vvvl" => "__builtin_ve_vl_pvmaxs_vvvl", + "vl.pvmaxs.vvvvl" => "__builtin_ve_vl_pvmaxs_vvvvl", + "vl.pvmins.vsvMvl" => "__builtin_ve_vl_pvmins_vsvMvl", + "vl.pvmins.vsvl" => "__builtin_ve_vl_pvmins_vsvl", + "vl.pvmins.vsvvl" => "__builtin_ve_vl_pvmins_vsvvl", + "vl.pvmins.vvvMvl" => "__builtin_ve_vl_pvmins_vvvMvl", + "vl.pvmins.vvvl" => "__builtin_ve_vl_pvmins_vvvl", + "vl.pvmins.vvvvl" => "__builtin_ve_vl_pvmins_vvvvl", + "vl.pvor.vsvMvl" => "__builtin_ve_vl_pvor_vsvMvl", + "vl.pvor.vsvl" => "__builtin_ve_vl_pvor_vsvl", + "vl.pvor.vsvvl" => "__builtin_ve_vl_pvor_vsvvl", + "vl.pvor.vvvMvl" => "__builtin_ve_vl_pvor_vvvMvl", + "vl.pvor.vvvl" => "__builtin_ve_vl_pvor_vvvl", + "vl.pvor.vvvvl" => "__builtin_ve_vl_pvor_vvvvl", + "vl.pvpcnt.vvMvl" => "__builtin_ve_vl_pvpcnt_vvMvl", + "vl.pvpcnt.vvl" => "__builtin_ve_vl_pvpcnt_vvl", + "vl.pvpcnt.vvvl" => "__builtin_ve_vl_pvpcnt_vvvl", + "vl.pvpcntlo.vvl" => "__builtin_ve_vl_pvpcntlo_vvl", + "vl.pvpcntlo.vvmvl" => "__builtin_ve_vl_pvpcntlo_vvmvl", + "vl.pvpcntlo.vvvl" => "__builtin_ve_vl_pvpcntlo_vvvl", + "vl.pvpcntup.vvl" => "__builtin_ve_vl_pvpcntup_vvl", + "vl.pvpcntup.vvmvl" => "__builtin_ve_vl_pvpcntup_vvmvl", + "vl.pvpcntup.vvvl" => "__builtin_ve_vl_pvpcntup_vvvl", + "vl.pvrcp.vvl" => "__builtin_ve_vl_pvrcp_vvl", + "vl.pvrcp.vvvl" => "__builtin_ve_vl_pvrcp_vvvl", + "vl.pvrsqrt.vvl" => "__builtin_ve_vl_pvrsqrt_vvl", + "vl.pvrsqrt.vvvl" => "__builtin_ve_vl_pvrsqrt_vvvl", + "vl.pvrsqrtnex.vvl" => "__builtin_ve_vl_pvrsqrtnex_vvl", + "vl.pvrsqrtnex.vvvl" => "__builtin_ve_vl_pvrsqrtnex_vvvl", + "vl.pvseq.vl" => "__builtin_ve_vl_pvseq_vl", + "vl.pvseq.vvl" => "__builtin_ve_vl_pvseq_vvl", + "vl.pvseqlo.vl" => "__builtin_ve_vl_pvseqlo_vl", + "vl.pvseqlo.vvl" => "__builtin_ve_vl_pvseqlo_vvl", + "vl.pvsequp.vl" => "__builtin_ve_vl_pvsequp_vl", + "vl.pvsequp.vvl" => "__builtin_ve_vl_pvsequp_vvl", + "vl.pvsla.vvsMvl" => "__builtin_ve_vl_pvsla_vvsMvl", + "vl.pvsla.vvsl" => "__builtin_ve_vl_pvsla_vvsl", + "vl.pvsla.vvsvl" => "__builtin_ve_vl_pvsla_vvsvl", + "vl.pvsla.vvvMvl" => "__builtin_ve_vl_pvsla_vvvMvl", + "vl.pvsla.vvvl" => "__builtin_ve_vl_pvsla_vvvl", + "vl.pvsla.vvvvl" => "__builtin_ve_vl_pvsla_vvvvl", + "vl.pvsll.vvsMvl" => "__builtin_ve_vl_pvsll_vvsMvl", + "vl.pvsll.vvsl" => "__builtin_ve_vl_pvsll_vvsl", + "vl.pvsll.vvsvl" => "__builtin_ve_vl_pvsll_vvsvl", + "vl.pvsll.vvvMvl" => "__builtin_ve_vl_pvsll_vvvMvl", + "vl.pvsll.vvvl" => "__builtin_ve_vl_pvsll_vvvl", + "vl.pvsll.vvvvl" => "__builtin_ve_vl_pvsll_vvvvl", + "vl.pvsra.vvsMvl" => "__builtin_ve_vl_pvsra_vvsMvl", + "vl.pvsra.vvsl" => "__builtin_ve_vl_pvsra_vvsl", + "vl.pvsra.vvsvl" => "__builtin_ve_vl_pvsra_vvsvl", + "vl.pvsra.vvvMvl" => "__builtin_ve_vl_pvsra_vvvMvl", + "vl.pvsra.vvvl" => "__builtin_ve_vl_pvsra_vvvl", + "vl.pvsra.vvvvl" => "__builtin_ve_vl_pvsra_vvvvl", + "vl.pvsrl.vvsMvl" => "__builtin_ve_vl_pvsrl_vvsMvl", + "vl.pvsrl.vvsl" => "__builtin_ve_vl_pvsrl_vvsl", + "vl.pvsrl.vvsvl" => "__builtin_ve_vl_pvsrl_vvsvl", + "vl.pvsrl.vvvMvl" => "__builtin_ve_vl_pvsrl_vvvMvl", + "vl.pvsrl.vvvl" => "__builtin_ve_vl_pvsrl_vvvl", + "vl.pvsrl.vvvvl" => "__builtin_ve_vl_pvsrl_vvvvl", + "vl.pvsubs.vsvMvl" => "__builtin_ve_vl_pvsubs_vsvMvl", + "vl.pvsubs.vsvl" => "__builtin_ve_vl_pvsubs_vsvl", + "vl.pvsubs.vsvvl" => "__builtin_ve_vl_pvsubs_vsvvl", + "vl.pvsubs.vvvMvl" => "__builtin_ve_vl_pvsubs_vvvMvl", + "vl.pvsubs.vvvl" => "__builtin_ve_vl_pvsubs_vvvl", + "vl.pvsubs.vvvvl" => "__builtin_ve_vl_pvsubs_vvvvl", + "vl.pvsubu.vsvMvl" => "__builtin_ve_vl_pvsubu_vsvMvl", + "vl.pvsubu.vsvl" => "__builtin_ve_vl_pvsubu_vsvl", + "vl.pvsubu.vsvvl" => "__builtin_ve_vl_pvsubu_vsvvl", + "vl.pvsubu.vvvMvl" => "__builtin_ve_vl_pvsubu_vvvMvl", + "vl.pvsubu.vvvl" => "__builtin_ve_vl_pvsubu_vvvl", + "vl.pvsubu.vvvvl" => "__builtin_ve_vl_pvsubu_vvvvl", + "vl.pvxor.vsvMvl" => "__builtin_ve_vl_pvxor_vsvMvl", + "vl.pvxor.vsvl" => "__builtin_ve_vl_pvxor_vsvl", + "vl.pvxor.vsvvl" => "__builtin_ve_vl_pvxor_vsvvl", + "vl.pvxor.vvvMvl" => "__builtin_ve_vl_pvxor_vvvMvl", + "vl.pvxor.vvvl" => "__builtin_ve_vl_pvxor_vvvl", + "vl.pvxor.vvvvl" => "__builtin_ve_vl_pvxor_vvvvl", + "vl.scr.sss" => "__builtin_ve_vl_scr_sss", + "vl.svm.sMs" => "__builtin_ve_vl_svm_sMs", + "vl.svm.sms" => "__builtin_ve_vl_svm_sms", + "vl.svob" => "__builtin_ve_vl_svob", + "vl.tovm.sml" => "__builtin_ve_vl_tovm_sml", + "vl.tscr.ssss" => "__builtin_ve_vl_tscr_ssss", + "vl.vaddsl.vsvl" => "__builtin_ve_vl_vaddsl_vsvl", + "vl.vaddsl.vsvmvl" => "__builtin_ve_vl_vaddsl_vsvmvl", + "vl.vaddsl.vsvvl" => "__builtin_ve_vl_vaddsl_vsvvl", + "vl.vaddsl.vvvl" => "__builtin_ve_vl_vaddsl_vvvl", + "vl.vaddsl.vvvmvl" => "__builtin_ve_vl_vaddsl_vvvmvl", + "vl.vaddsl.vvvvl" => "__builtin_ve_vl_vaddsl_vvvvl", + "vl.vaddswsx.vsvl" => "__builtin_ve_vl_vaddswsx_vsvl", + "vl.vaddswsx.vsvmvl" => "__builtin_ve_vl_vaddswsx_vsvmvl", + "vl.vaddswsx.vsvvl" => "__builtin_ve_vl_vaddswsx_vsvvl", + "vl.vaddswsx.vvvl" => "__builtin_ve_vl_vaddswsx_vvvl", + "vl.vaddswsx.vvvmvl" => "__builtin_ve_vl_vaddswsx_vvvmvl", + "vl.vaddswsx.vvvvl" => "__builtin_ve_vl_vaddswsx_vvvvl", + "vl.vaddswzx.vsvl" => "__builtin_ve_vl_vaddswzx_vsvl", + "vl.vaddswzx.vsvmvl" => "__builtin_ve_vl_vaddswzx_vsvmvl", + "vl.vaddswzx.vsvvl" => "__builtin_ve_vl_vaddswzx_vsvvl", + "vl.vaddswzx.vvvl" => "__builtin_ve_vl_vaddswzx_vvvl", + "vl.vaddswzx.vvvmvl" => "__builtin_ve_vl_vaddswzx_vvvmvl", + "vl.vaddswzx.vvvvl" => "__builtin_ve_vl_vaddswzx_vvvvl", + "vl.vaddul.vsvl" => "__builtin_ve_vl_vaddul_vsvl", + "vl.vaddul.vsvmvl" => "__builtin_ve_vl_vaddul_vsvmvl", + "vl.vaddul.vsvvl" => "__builtin_ve_vl_vaddul_vsvvl", + "vl.vaddul.vvvl" => "__builtin_ve_vl_vaddul_vvvl", + "vl.vaddul.vvvmvl" => "__builtin_ve_vl_vaddul_vvvmvl", + "vl.vaddul.vvvvl" => "__builtin_ve_vl_vaddul_vvvvl", + "vl.vadduw.vsvl" => "__builtin_ve_vl_vadduw_vsvl", + "vl.vadduw.vsvmvl" => "__builtin_ve_vl_vadduw_vsvmvl", + "vl.vadduw.vsvvl" => "__builtin_ve_vl_vadduw_vsvvl", + "vl.vadduw.vvvl" => "__builtin_ve_vl_vadduw_vvvl", + "vl.vadduw.vvvmvl" => "__builtin_ve_vl_vadduw_vvvmvl", + "vl.vadduw.vvvvl" => "__builtin_ve_vl_vadduw_vvvvl", + "vl.vand.vsvl" => "__builtin_ve_vl_vand_vsvl", + "vl.vand.vsvmvl" => "__builtin_ve_vl_vand_vsvmvl", + "vl.vand.vsvvl" => "__builtin_ve_vl_vand_vsvvl", + "vl.vand.vvvl" => "__builtin_ve_vl_vand_vvvl", + "vl.vand.vvvmvl" => "__builtin_ve_vl_vand_vvvmvl", + "vl.vand.vvvvl" => "__builtin_ve_vl_vand_vvvvl", + "vl.vbrdd.vsl" => "__builtin_ve_vl_vbrdd_vsl", + "vl.vbrdd.vsmvl" => "__builtin_ve_vl_vbrdd_vsmvl", + "vl.vbrdd.vsvl" => "__builtin_ve_vl_vbrdd_vsvl", + "vl.vbrdl.vsl" => "__builtin_ve_vl_vbrdl_vsl", + "vl.vbrdl.vsmvl" => "__builtin_ve_vl_vbrdl_vsmvl", + "vl.vbrdl.vsvl" => "__builtin_ve_vl_vbrdl_vsvl", + "vl.vbrds.vsl" => "__builtin_ve_vl_vbrds_vsl", + "vl.vbrds.vsmvl" => "__builtin_ve_vl_vbrds_vsmvl", + "vl.vbrds.vsvl" => "__builtin_ve_vl_vbrds_vsvl", + "vl.vbrdw.vsl" => "__builtin_ve_vl_vbrdw_vsl", + "vl.vbrdw.vsmvl" => "__builtin_ve_vl_vbrdw_vsmvl", + "vl.vbrdw.vsvl" => "__builtin_ve_vl_vbrdw_vsvl", + "vl.vbrv.vvl" => "__builtin_ve_vl_vbrv_vvl", + "vl.vbrv.vvmvl" => "__builtin_ve_vl_vbrv_vvmvl", + "vl.vbrv.vvvl" => "__builtin_ve_vl_vbrv_vvvl", + "vl.vcmpsl.vsvl" => "__builtin_ve_vl_vcmpsl_vsvl", + "vl.vcmpsl.vsvmvl" => "__builtin_ve_vl_vcmpsl_vsvmvl", + "vl.vcmpsl.vsvvl" => "__builtin_ve_vl_vcmpsl_vsvvl", + "vl.vcmpsl.vvvl" => "__builtin_ve_vl_vcmpsl_vvvl", + "vl.vcmpsl.vvvmvl" => "__builtin_ve_vl_vcmpsl_vvvmvl", + "vl.vcmpsl.vvvvl" => "__builtin_ve_vl_vcmpsl_vvvvl", + "vl.vcmpswsx.vsvl" => "__builtin_ve_vl_vcmpswsx_vsvl", + "vl.vcmpswsx.vsvmvl" => "__builtin_ve_vl_vcmpswsx_vsvmvl", + "vl.vcmpswsx.vsvvl" => "__builtin_ve_vl_vcmpswsx_vsvvl", + "vl.vcmpswsx.vvvl" => "__builtin_ve_vl_vcmpswsx_vvvl", + "vl.vcmpswsx.vvvmvl" => "__builtin_ve_vl_vcmpswsx_vvvmvl", + "vl.vcmpswsx.vvvvl" => "__builtin_ve_vl_vcmpswsx_vvvvl", + "vl.vcmpswzx.vsvl" => "__builtin_ve_vl_vcmpswzx_vsvl", + "vl.vcmpswzx.vsvmvl" => "__builtin_ve_vl_vcmpswzx_vsvmvl", + "vl.vcmpswzx.vsvvl" => "__builtin_ve_vl_vcmpswzx_vsvvl", + "vl.vcmpswzx.vvvl" => "__builtin_ve_vl_vcmpswzx_vvvl", + "vl.vcmpswzx.vvvmvl" => "__builtin_ve_vl_vcmpswzx_vvvmvl", + "vl.vcmpswzx.vvvvl" => "__builtin_ve_vl_vcmpswzx_vvvvl", + "vl.vcmpul.vsvl" => "__builtin_ve_vl_vcmpul_vsvl", + "vl.vcmpul.vsvmvl" => "__builtin_ve_vl_vcmpul_vsvmvl", + "vl.vcmpul.vsvvl" => "__builtin_ve_vl_vcmpul_vsvvl", + "vl.vcmpul.vvvl" => "__builtin_ve_vl_vcmpul_vvvl", + "vl.vcmpul.vvvmvl" => "__builtin_ve_vl_vcmpul_vvvmvl", + "vl.vcmpul.vvvvl" => "__builtin_ve_vl_vcmpul_vvvvl", + "vl.vcmpuw.vsvl" => "__builtin_ve_vl_vcmpuw_vsvl", + "vl.vcmpuw.vsvmvl" => "__builtin_ve_vl_vcmpuw_vsvmvl", + "vl.vcmpuw.vsvvl" => "__builtin_ve_vl_vcmpuw_vsvvl", + "vl.vcmpuw.vvvl" => "__builtin_ve_vl_vcmpuw_vvvl", + "vl.vcmpuw.vvvmvl" => "__builtin_ve_vl_vcmpuw_vvvmvl", + "vl.vcmpuw.vvvvl" => "__builtin_ve_vl_vcmpuw_vvvvl", + "vl.vcp.vvmvl" => "__builtin_ve_vl_vcp_vvmvl", + "vl.vcvtdl.vvl" => "__builtin_ve_vl_vcvtdl_vvl", + "vl.vcvtdl.vvvl" => "__builtin_ve_vl_vcvtdl_vvvl", + "vl.vcvtds.vvl" => "__builtin_ve_vl_vcvtds_vvl", + "vl.vcvtds.vvvl" => "__builtin_ve_vl_vcvtds_vvvl", + "vl.vcvtdw.vvl" => "__builtin_ve_vl_vcvtdw_vvl", + "vl.vcvtdw.vvvl" => "__builtin_ve_vl_vcvtdw_vvvl", + "vl.vcvtld.vvl" => "__builtin_ve_vl_vcvtld_vvl", + "vl.vcvtld.vvmvl" => "__builtin_ve_vl_vcvtld_vvmvl", + "vl.vcvtld.vvvl" => "__builtin_ve_vl_vcvtld_vvvl", + "vl.vcvtldrz.vvl" => "__builtin_ve_vl_vcvtldrz_vvl", + "vl.vcvtldrz.vvmvl" => "__builtin_ve_vl_vcvtldrz_vvmvl", + "vl.vcvtldrz.vvvl" => "__builtin_ve_vl_vcvtldrz_vvvl", + "vl.vcvtsd.vvl" => "__builtin_ve_vl_vcvtsd_vvl", + "vl.vcvtsd.vvvl" => "__builtin_ve_vl_vcvtsd_vvvl", + "vl.vcvtsw.vvl" => "__builtin_ve_vl_vcvtsw_vvl", + "vl.vcvtsw.vvvl" => "__builtin_ve_vl_vcvtsw_vvvl", + "vl.vcvtwdsx.vvl" => "__builtin_ve_vl_vcvtwdsx_vvl", + "vl.vcvtwdsx.vvmvl" => "__builtin_ve_vl_vcvtwdsx_vvmvl", + "vl.vcvtwdsx.vvvl" => "__builtin_ve_vl_vcvtwdsx_vvvl", + "vl.vcvtwdsxrz.vvl" => "__builtin_ve_vl_vcvtwdsxrz_vvl", + "vl.vcvtwdsxrz.vvmvl" => "__builtin_ve_vl_vcvtwdsxrz_vvmvl", + "vl.vcvtwdsxrz.vvvl" => "__builtin_ve_vl_vcvtwdsxrz_vvvl", + "vl.vcvtwdzx.vvl" => "__builtin_ve_vl_vcvtwdzx_vvl", + "vl.vcvtwdzx.vvmvl" => "__builtin_ve_vl_vcvtwdzx_vvmvl", + "vl.vcvtwdzx.vvvl" => "__builtin_ve_vl_vcvtwdzx_vvvl", + "vl.vcvtwdzxrz.vvl" => "__builtin_ve_vl_vcvtwdzxrz_vvl", + "vl.vcvtwdzxrz.vvmvl" => "__builtin_ve_vl_vcvtwdzxrz_vvmvl", + "vl.vcvtwdzxrz.vvvl" => "__builtin_ve_vl_vcvtwdzxrz_vvvl", + "vl.vcvtwssx.vvl" => "__builtin_ve_vl_vcvtwssx_vvl", + "vl.vcvtwssx.vvmvl" => "__builtin_ve_vl_vcvtwssx_vvmvl", + "vl.vcvtwssx.vvvl" => "__builtin_ve_vl_vcvtwssx_vvvl", + "vl.vcvtwssxrz.vvl" => "__builtin_ve_vl_vcvtwssxrz_vvl", + "vl.vcvtwssxrz.vvmvl" => "__builtin_ve_vl_vcvtwssxrz_vvmvl", + "vl.vcvtwssxrz.vvvl" => "__builtin_ve_vl_vcvtwssxrz_vvvl", + "vl.vcvtwszx.vvl" => "__builtin_ve_vl_vcvtwszx_vvl", + "vl.vcvtwszx.vvmvl" => "__builtin_ve_vl_vcvtwszx_vvmvl", + "vl.vcvtwszx.vvvl" => "__builtin_ve_vl_vcvtwszx_vvvl", + "vl.vcvtwszxrz.vvl" => "__builtin_ve_vl_vcvtwszxrz_vvl", + "vl.vcvtwszxrz.vvmvl" => "__builtin_ve_vl_vcvtwszxrz_vvmvl", + "vl.vcvtwszxrz.vvvl" => "__builtin_ve_vl_vcvtwszxrz_vvvl", + "vl.vdivsl.vsvl" => "__builtin_ve_vl_vdivsl_vsvl", + "vl.vdivsl.vsvmvl" => "__builtin_ve_vl_vdivsl_vsvmvl", + "vl.vdivsl.vsvvl" => "__builtin_ve_vl_vdivsl_vsvvl", + "vl.vdivsl.vvsl" => "__builtin_ve_vl_vdivsl_vvsl", + "vl.vdivsl.vvsmvl" => "__builtin_ve_vl_vdivsl_vvsmvl", + "vl.vdivsl.vvsvl" => "__builtin_ve_vl_vdivsl_vvsvl", + "vl.vdivsl.vvvl" => "__builtin_ve_vl_vdivsl_vvvl", + "vl.vdivsl.vvvmvl" => "__builtin_ve_vl_vdivsl_vvvmvl", + "vl.vdivsl.vvvvl" => "__builtin_ve_vl_vdivsl_vvvvl", + "vl.vdivswsx.vsvl" => "__builtin_ve_vl_vdivswsx_vsvl", + "vl.vdivswsx.vsvmvl" => "__builtin_ve_vl_vdivswsx_vsvmvl", + "vl.vdivswsx.vsvvl" => "__builtin_ve_vl_vdivswsx_vsvvl", + "vl.vdivswsx.vvsl" => "__builtin_ve_vl_vdivswsx_vvsl", + "vl.vdivswsx.vvsmvl" => "__builtin_ve_vl_vdivswsx_vvsmvl", + "vl.vdivswsx.vvsvl" => "__builtin_ve_vl_vdivswsx_vvsvl", + "vl.vdivswsx.vvvl" => "__builtin_ve_vl_vdivswsx_vvvl", + "vl.vdivswsx.vvvmvl" => "__builtin_ve_vl_vdivswsx_vvvmvl", + "vl.vdivswsx.vvvvl" => "__builtin_ve_vl_vdivswsx_vvvvl", + "vl.vdivswzx.vsvl" => "__builtin_ve_vl_vdivswzx_vsvl", + "vl.vdivswzx.vsvmvl" => "__builtin_ve_vl_vdivswzx_vsvmvl", + "vl.vdivswzx.vsvvl" => "__builtin_ve_vl_vdivswzx_vsvvl", + "vl.vdivswzx.vvsl" => "__builtin_ve_vl_vdivswzx_vvsl", + "vl.vdivswzx.vvsmvl" => "__builtin_ve_vl_vdivswzx_vvsmvl", + "vl.vdivswzx.vvsvl" => "__builtin_ve_vl_vdivswzx_vvsvl", + "vl.vdivswzx.vvvl" => "__builtin_ve_vl_vdivswzx_vvvl", + "vl.vdivswzx.vvvmvl" => "__builtin_ve_vl_vdivswzx_vvvmvl", + "vl.vdivswzx.vvvvl" => "__builtin_ve_vl_vdivswzx_vvvvl", + "vl.vdivul.vsvl" => "__builtin_ve_vl_vdivul_vsvl", + "vl.vdivul.vsvmvl" => "__builtin_ve_vl_vdivul_vsvmvl", + "vl.vdivul.vsvvl" => "__builtin_ve_vl_vdivul_vsvvl", + "vl.vdivul.vvsl" => "__builtin_ve_vl_vdivul_vvsl", + "vl.vdivul.vvsmvl" => "__builtin_ve_vl_vdivul_vvsmvl", + "vl.vdivul.vvsvl" => "__builtin_ve_vl_vdivul_vvsvl", + "vl.vdivul.vvvl" => "__builtin_ve_vl_vdivul_vvvl", + "vl.vdivul.vvvmvl" => "__builtin_ve_vl_vdivul_vvvmvl", + "vl.vdivul.vvvvl" => "__builtin_ve_vl_vdivul_vvvvl", + "vl.vdivuw.vsvl" => "__builtin_ve_vl_vdivuw_vsvl", + "vl.vdivuw.vsvmvl" => "__builtin_ve_vl_vdivuw_vsvmvl", + "vl.vdivuw.vsvvl" => "__builtin_ve_vl_vdivuw_vsvvl", + "vl.vdivuw.vvsl" => "__builtin_ve_vl_vdivuw_vvsl", + "vl.vdivuw.vvsmvl" => "__builtin_ve_vl_vdivuw_vvsmvl", + "vl.vdivuw.vvsvl" => "__builtin_ve_vl_vdivuw_vvsvl", + "vl.vdivuw.vvvl" => "__builtin_ve_vl_vdivuw_vvvl", + "vl.vdivuw.vvvmvl" => "__builtin_ve_vl_vdivuw_vvvmvl", + "vl.vdivuw.vvvvl" => "__builtin_ve_vl_vdivuw_vvvvl", + "vl.veqv.vsvl" => "__builtin_ve_vl_veqv_vsvl", + "vl.veqv.vsvmvl" => "__builtin_ve_vl_veqv_vsvmvl", + "vl.veqv.vsvvl" => "__builtin_ve_vl_veqv_vsvvl", + "vl.veqv.vvvl" => "__builtin_ve_vl_veqv_vvvl", + "vl.veqv.vvvmvl" => "__builtin_ve_vl_veqv_vvvmvl", + "vl.veqv.vvvvl" => "__builtin_ve_vl_veqv_vvvvl", + "vl.vex.vvmvl" => "__builtin_ve_vl_vex_vvmvl", + "vl.vfaddd.vsvl" => "__builtin_ve_vl_vfaddd_vsvl", + "vl.vfaddd.vsvmvl" => "__builtin_ve_vl_vfaddd_vsvmvl", + "vl.vfaddd.vsvvl" => "__builtin_ve_vl_vfaddd_vsvvl", + "vl.vfaddd.vvvl" => "__builtin_ve_vl_vfaddd_vvvl", + "vl.vfaddd.vvvmvl" => "__builtin_ve_vl_vfaddd_vvvmvl", + "vl.vfaddd.vvvvl" => "__builtin_ve_vl_vfaddd_vvvvl", + "vl.vfadds.vsvl" => "__builtin_ve_vl_vfadds_vsvl", + "vl.vfadds.vsvmvl" => "__builtin_ve_vl_vfadds_vsvmvl", + "vl.vfadds.vsvvl" => "__builtin_ve_vl_vfadds_vsvvl", + "vl.vfadds.vvvl" => "__builtin_ve_vl_vfadds_vvvl", + "vl.vfadds.vvvmvl" => "__builtin_ve_vl_vfadds_vvvmvl", + "vl.vfadds.vvvvl" => "__builtin_ve_vl_vfadds_vvvvl", + "vl.vfcmpd.vsvl" => "__builtin_ve_vl_vfcmpd_vsvl", + "vl.vfcmpd.vsvmvl" => "__builtin_ve_vl_vfcmpd_vsvmvl", + "vl.vfcmpd.vsvvl" => "__builtin_ve_vl_vfcmpd_vsvvl", + "vl.vfcmpd.vvvl" => "__builtin_ve_vl_vfcmpd_vvvl", + "vl.vfcmpd.vvvmvl" => "__builtin_ve_vl_vfcmpd_vvvmvl", + "vl.vfcmpd.vvvvl" => "__builtin_ve_vl_vfcmpd_vvvvl", + "vl.vfcmps.vsvl" => "__builtin_ve_vl_vfcmps_vsvl", + "vl.vfcmps.vsvmvl" => "__builtin_ve_vl_vfcmps_vsvmvl", + "vl.vfcmps.vsvvl" => "__builtin_ve_vl_vfcmps_vsvvl", + "vl.vfcmps.vvvl" => "__builtin_ve_vl_vfcmps_vvvl", + "vl.vfcmps.vvvmvl" => "__builtin_ve_vl_vfcmps_vvvmvl", + "vl.vfcmps.vvvvl" => "__builtin_ve_vl_vfcmps_vvvvl", + "vl.vfdivd.vsvl" => "__builtin_ve_vl_vfdivd_vsvl", + "vl.vfdivd.vsvmvl" => "__builtin_ve_vl_vfdivd_vsvmvl", + "vl.vfdivd.vsvvl" => "__builtin_ve_vl_vfdivd_vsvvl", + "vl.vfdivd.vvvl" => "__builtin_ve_vl_vfdivd_vvvl", + "vl.vfdivd.vvvmvl" => "__builtin_ve_vl_vfdivd_vvvmvl", + "vl.vfdivd.vvvvl" => "__builtin_ve_vl_vfdivd_vvvvl", + "vl.vfdivs.vsvl" => "__builtin_ve_vl_vfdivs_vsvl", + "vl.vfdivs.vsvmvl" => "__builtin_ve_vl_vfdivs_vsvmvl", + "vl.vfdivs.vsvvl" => "__builtin_ve_vl_vfdivs_vsvvl", + "vl.vfdivs.vvvl" => "__builtin_ve_vl_vfdivs_vvvl", + "vl.vfdivs.vvvmvl" => "__builtin_ve_vl_vfdivs_vvvmvl", + "vl.vfdivs.vvvvl" => "__builtin_ve_vl_vfdivs_vvvvl", + "vl.vfmadd.vsvvl" => "__builtin_ve_vl_vfmadd_vsvvl", + "vl.vfmadd.vsvvmvl" => "__builtin_ve_vl_vfmadd_vsvvmvl", + "vl.vfmadd.vsvvvl" => "__builtin_ve_vl_vfmadd_vsvvvl", + "vl.vfmadd.vvsvl" => "__builtin_ve_vl_vfmadd_vvsvl", + "vl.vfmadd.vvsvmvl" => "__builtin_ve_vl_vfmadd_vvsvmvl", + "vl.vfmadd.vvsvvl" => "__builtin_ve_vl_vfmadd_vvsvvl", + "vl.vfmadd.vvvvl" => "__builtin_ve_vl_vfmadd_vvvvl", + "vl.vfmadd.vvvvmvl" => "__builtin_ve_vl_vfmadd_vvvvmvl", + "vl.vfmadd.vvvvvl" => "__builtin_ve_vl_vfmadd_vvvvvl", + "vl.vfmads.vsvvl" => "__builtin_ve_vl_vfmads_vsvvl", + "vl.vfmads.vsvvmvl" => "__builtin_ve_vl_vfmads_vsvvmvl", + "vl.vfmads.vsvvvl" => "__builtin_ve_vl_vfmads_vsvvvl", + "vl.vfmads.vvsvl" => "__builtin_ve_vl_vfmads_vvsvl", + "vl.vfmads.vvsvmvl" => "__builtin_ve_vl_vfmads_vvsvmvl", + "vl.vfmads.vvsvvl" => "__builtin_ve_vl_vfmads_vvsvvl", + "vl.vfmads.vvvvl" => "__builtin_ve_vl_vfmads_vvvvl", + "vl.vfmads.vvvvmvl" => "__builtin_ve_vl_vfmads_vvvvmvl", + "vl.vfmads.vvvvvl" => "__builtin_ve_vl_vfmads_vvvvvl", + "vl.vfmaxd.vsvl" => "__builtin_ve_vl_vfmaxd_vsvl", + "vl.vfmaxd.vsvmvl" => "__builtin_ve_vl_vfmaxd_vsvmvl", + "vl.vfmaxd.vsvvl" => "__builtin_ve_vl_vfmaxd_vsvvl", + "vl.vfmaxd.vvvl" => "__builtin_ve_vl_vfmaxd_vvvl", + "vl.vfmaxd.vvvmvl" => "__builtin_ve_vl_vfmaxd_vvvmvl", + "vl.vfmaxd.vvvvl" => "__builtin_ve_vl_vfmaxd_vvvvl", + "vl.vfmaxs.vsvl" => "__builtin_ve_vl_vfmaxs_vsvl", + "vl.vfmaxs.vsvmvl" => "__builtin_ve_vl_vfmaxs_vsvmvl", + "vl.vfmaxs.vsvvl" => "__builtin_ve_vl_vfmaxs_vsvvl", + "vl.vfmaxs.vvvl" => "__builtin_ve_vl_vfmaxs_vvvl", + "vl.vfmaxs.vvvmvl" => "__builtin_ve_vl_vfmaxs_vvvmvl", + "vl.vfmaxs.vvvvl" => "__builtin_ve_vl_vfmaxs_vvvvl", + "vl.vfmind.vsvl" => "__builtin_ve_vl_vfmind_vsvl", + "vl.vfmind.vsvmvl" => "__builtin_ve_vl_vfmind_vsvmvl", + "vl.vfmind.vsvvl" => "__builtin_ve_vl_vfmind_vsvvl", + "vl.vfmind.vvvl" => "__builtin_ve_vl_vfmind_vvvl", + "vl.vfmind.vvvmvl" => "__builtin_ve_vl_vfmind_vvvmvl", + "vl.vfmind.vvvvl" => "__builtin_ve_vl_vfmind_vvvvl", + "vl.vfmins.vsvl" => "__builtin_ve_vl_vfmins_vsvl", + "vl.vfmins.vsvmvl" => "__builtin_ve_vl_vfmins_vsvmvl", + "vl.vfmins.vsvvl" => "__builtin_ve_vl_vfmins_vsvvl", + "vl.vfmins.vvvl" => "__builtin_ve_vl_vfmins_vvvl", + "vl.vfmins.vvvmvl" => "__builtin_ve_vl_vfmins_vvvmvl", + "vl.vfmins.vvvvl" => "__builtin_ve_vl_vfmins_vvvvl", + "vl.vfmkdeq.mvl" => "__builtin_ve_vl_vfmkdeq_mvl", + "vl.vfmkdeq.mvml" => "__builtin_ve_vl_vfmkdeq_mvml", + "vl.vfmkdeqnan.mvl" => "__builtin_ve_vl_vfmkdeqnan_mvl", + "vl.vfmkdeqnan.mvml" => "__builtin_ve_vl_vfmkdeqnan_mvml", + "vl.vfmkdge.mvl" => "__builtin_ve_vl_vfmkdge_mvl", + "vl.vfmkdge.mvml" => "__builtin_ve_vl_vfmkdge_mvml", + "vl.vfmkdgenan.mvl" => "__builtin_ve_vl_vfmkdgenan_mvl", + "vl.vfmkdgenan.mvml" => "__builtin_ve_vl_vfmkdgenan_mvml", + "vl.vfmkdgt.mvl" => "__builtin_ve_vl_vfmkdgt_mvl", + "vl.vfmkdgt.mvml" => "__builtin_ve_vl_vfmkdgt_mvml", + "vl.vfmkdgtnan.mvl" => "__builtin_ve_vl_vfmkdgtnan_mvl", + "vl.vfmkdgtnan.mvml" => "__builtin_ve_vl_vfmkdgtnan_mvml", + "vl.vfmkdle.mvl" => "__builtin_ve_vl_vfmkdle_mvl", + "vl.vfmkdle.mvml" => "__builtin_ve_vl_vfmkdle_mvml", + "vl.vfmkdlenan.mvl" => "__builtin_ve_vl_vfmkdlenan_mvl", + "vl.vfmkdlenan.mvml" => "__builtin_ve_vl_vfmkdlenan_mvml", + "vl.vfmkdlt.mvl" => "__builtin_ve_vl_vfmkdlt_mvl", + "vl.vfmkdlt.mvml" => "__builtin_ve_vl_vfmkdlt_mvml", + "vl.vfmkdltnan.mvl" => "__builtin_ve_vl_vfmkdltnan_mvl", + "vl.vfmkdltnan.mvml" => "__builtin_ve_vl_vfmkdltnan_mvml", + "vl.vfmkdnan.mvl" => "__builtin_ve_vl_vfmkdnan_mvl", + "vl.vfmkdnan.mvml" => "__builtin_ve_vl_vfmkdnan_mvml", + "vl.vfmkdne.mvl" => "__builtin_ve_vl_vfmkdne_mvl", + "vl.vfmkdne.mvml" => "__builtin_ve_vl_vfmkdne_mvml", + "vl.vfmkdnenan.mvl" => "__builtin_ve_vl_vfmkdnenan_mvl", + "vl.vfmkdnenan.mvml" => "__builtin_ve_vl_vfmkdnenan_mvml", + "vl.vfmkdnum.mvl" => "__builtin_ve_vl_vfmkdnum_mvl", + "vl.vfmkdnum.mvml" => "__builtin_ve_vl_vfmkdnum_mvml", + "vl.vfmklaf.ml" => "__builtin_ve_vl_vfmklaf_ml", + "vl.vfmklat.ml" => "__builtin_ve_vl_vfmklat_ml", + "vl.vfmkleq.mvl" => "__builtin_ve_vl_vfmkleq_mvl", + "vl.vfmkleq.mvml" => "__builtin_ve_vl_vfmkleq_mvml", + "vl.vfmkleqnan.mvl" => "__builtin_ve_vl_vfmkleqnan_mvl", + "vl.vfmkleqnan.mvml" => "__builtin_ve_vl_vfmkleqnan_mvml", + "vl.vfmklge.mvl" => "__builtin_ve_vl_vfmklge_mvl", + "vl.vfmklge.mvml" => "__builtin_ve_vl_vfmklge_mvml", + "vl.vfmklgenan.mvl" => "__builtin_ve_vl_vfmklgenan_mvl", + "vl.vfmklgenan.mvml" => "__builtin_ve_vl_vfmklgenan_mvml", + "vl.vfmklgt.mvl" => "__builtin_ve_vl_vfmklgt_mvl", + "vl.vfmklgt.mvml" => "__builtin_ve_vl_vfmklgt_mvml", + "vl.vfmklgtnan.mvl" => "__builtin_ve_vl_vfmklgtnan_mvl", + "vl.vfmklgtnan.mvml" => "__builtin_ve_vl_vfmklgtnan_mvml", + "vl.vfmklle.mvl" => "__builtin_ve_vl_vfmklle_mvl", + "vl.vfmklle.mvml" => "__builtin_ve_vl_vfmklle_mvml", + "vl.vfmkllenan.mvl" => "__builtin_ve_vl_vfmkllenan_mvl", + "vl.vfmkllenan.mvml" => "__builtin_ve_vl_vfmkllenan_mvml", + "vl.vfmkllt.mvl" => "__builtin_ve_vl_vfmkllt_mvl", + "vl.vfmkllt.mvml" => "__builtin_ve_vl_vfmkllt_mvml", + "vl.vfmklltnan.mvl" => "__builtin_ve_vl_vfmklltnan_mvl", + "vl.vfmklltnan.mvml" => "__builtin_ve_vl_vfmklltnan_mvml", + "vl.vfmklnan.mvl" => "__builtin_ve_vl_vfmklnan_mvl", + "vl.vfmklnan.mvml" => "__builtin_ve_vl_vfmklnan_mvml", + "vl.vfmklne.mvl" => "__builtin_ve_vl_vfmklne_mvl", + "vl.vfmklne.mvml" => "__builtin_ve_vl_vfmklne_mvml", + "vl.vfmklnenan.mvl" => "__builtin_ve_vl_vfmklnenan_mvl", + "vl.vfmklnenan.mvml" => "__builtin_ve_vl_vfmklnenan_mvml", + "vl.vfmklnum.mvl" => "__builtin_ve_vl_vfmklnum_mvl", + "vl.vfmklnum.mvml" => "__builtin_ve_vl_vfmklnum_mvml", + "vl.vfmkseq.mvl" => "__builtin_ve_vl_vfmkseq_mvl", + "vl.vfmkseq.mvml" => "__builtin_ve_vl_vfmkseq_mvml", + "vl.vfmkseqnan.mvl" => "__builtin_ve_vl_vfmkseqnan_mvl", + "vl.vfmkseqnan.mvml" => "__builtin_ve_vl_vfmkseqnan_mvml", + "vl.vfmksge.mvl" => "__builtin_ve_vl_vfmksge_mvl", + "vl.vfmksge.mvml" => "__builtin_ve_vl_vfmksge_mvml", + "vl.vfmksgenan.mvl" => "__builtin_ve_vl_vfmksgenan_mvl", + "vl.vfmksgenan.mvml" => "__builtin_ve_vl_vfmksgenan_mvml", + "vl.vfmksgt.mvl" => "__builtin_ve_vl_vfmksgt_mvl", + "vl.vfmksgt.mvml" => "__builtin_ve_vl_vfmksgt_mvml", + "vl.vfmksgtnan.mvl" => "__builtin_ve_vl_vfmksgtnan_mvl", + "vl.vfmksgtnan.mvml" => "__builtin_ve_vl_vfmksgtnan_mvml", + "vl.vfmksle.mvl" => "__builtin_ve_vl_vfmksle_mvl", + "vl.vfmksle.mvml" => "__builtin_ve_vl_vfmksle_mvml", + "vl.vfmkslenan.mvl" => "__builtin_ve_vl_vfmkslenan_mvl", + "vl.vfmkslenan.mvml" => "__builtin_ve_vl_vfmkslenan_mvml", + "vl.vfmkslt.mvl" => "__builtin_ve_vl_vfmkslt_mvl", + "vl.vfmkslt.mvml" => "__builtin_ve_vl_vfmkslt_mvml", + "vl.vfmksltnan.mvl" => "__builtin_ve_vl_vfmksltnan_mvl", + "vl.vfmksltnan.mvml" => "__builtin_ve_vl_vfmksltnan_mvml", + "vl.vfmksnan.mvl" => "__builtin_ve_vl_vfmksnan_mvl", + "vl.vfmksnan.mvml" => "__builtin_ve_vl_vfmksnan_mvml", + "vl.vfmksne.mvl" => "__builtin_ve_vl_vfmksne_mvl", + "vl.vfmksne.mvml" => "__builtin_ve_vl_vfmksne_mvml", + "vl.vfmksnenan.mvl" => "__builtin_ve_vl_vfmksnenan_mvl", + "vl.vfmksnenan.mvml" => "__builtin_ve_vl_vfmksnenan_mvml", + "vl.vfmksnum.mvl" => "__builtin_ve_vl_vfmksnum_mvl", + "vl.vfmksnum.mvml" => "__builtin_ve_vl_vfmksnum_mvml", + "vl.vfmkweq.mvl" => "__builtin_ve_vl_vfmkweq_mvl", + "vl.vfmkweq.mvml" => "__builtin_ve_vl_vfmkweq_mvml", + "vl.vfmkweqnan.mvl" => "__builtin_ve_vl_vfmkweqnan_mvl", + "vl.vfmkweqnan.mvml" => "__builtin_ve_vl_vfmkweqnan_mvml", + "vl.vfmkwge.mvl" => "__builtin_ve_vl_vfmkwge_mvl", + "vl.vfmkwge.mvml" => "__builtin_ve_vl_vfmkwge_mvml", + "vl.vfmkwgenan.mvl" => "__builtin_ve_vl_vfmkwgenan_mvl", + "vl.vfmkwgenan.mvml" => "__builtin_ve_vl_vfmkwgenan_mvml", + "vl.vfmkwgt.mvl" => "__builtin_ve_vl_vfmkwgt_mvl", + "vl.vfmkwgt.mvml" => "__builtin_ve_vl_vfmkwgt_mvml", + "vl.vfmkwgtnan.mvl" => "__builtin_ve_vl_vfmkwgtnan_mvl", + "vl.vfmkwgtnan.mvml" => "__builtin_ve_vl_vfmkwgtnan_mvml", + "vl.vfmkwle.mvl" => "__builtin_ve_vl_vfmkwle_mvl", + "vl.vfmkwle.mvml" => "__builtin_ve_vl_vfmkwle_mvml", + "vl.vfmkwlenan.mvl" => "__builtin_ve_vl_vfmkwlenan_mvl", + "vl.vfmkwlenan.mvml" => "__builtin_ve_vl_vfmkwlenan_mvml", + "vl.vfmkwlt.mvl" => "__builtin_ve_vl_vfmkwlt_mvl", + "vl.vfmkwlt.mvml" => "__builtin_ve_vl_vfmkwlt_mvml", + "vl.vfmkwltnan.mvl" => "__builtin_ve_vl_vfmkwltnan_mvl", + "vl.vfmkwltnan.mvml" => "__builtin_ve_vl_vfmkwltnan_mvml", + "vl.vfmkwnan.mvl" => "__builtin_ve_vl_vfmkwnan_mvl", + "vl.vfmkwnan.mvml" => "__builtin_ve_vl_vfmkwnan_mvml", + "vl.vfmkwne.mvl" => "__builtin_ve_vl_vfmkwne_mvl", + "vl.vfmkwne.mvml" => "__builtin_ve_vl_vfmkwne_mvml", + "vl.vfmkwnenan.mvl" => "__builtin_ve_vl_vfmkwnenan_mvl", + "vl.vfmkwnenan.mvml" => "__builtin_ve_vl_vfmkwnenan_mvml", + "vl.vfmkwnum.mvl" => "__builtin_ve_vl_vfmkwnum_mvl", + "vl.vfmkwnum.mvml" => "__builtin_ve_vl_vfmkwnum_mvml", + "vl.vfmsbd.vsvvl" => "__builtin_ve_vl_vfmsbd_vsvvl", + "vl.vfmsbd.vsvvmvl" => "__builtin_ve_vl_vfmsbd_vsvvmvl", + "vl.vfmsbd.vsvvvl" => "__builtin_ve_vl_vfmsbd_vsvvvl", + "vl.vfmsbd.vvsvl" => "__builtin_ve_vl_vfmsbd_vvsvl", + "vl.vfmsbd.vvsvmvl" => "__builtin_ve_vl_vfmsbd_vvsvmvl", + "vl.vfmsbd.vvsvvl" => "__builtin_ve_vl_vfmsbd_vvsvvl", + "vl.vfmsbd.vvvvl" => "__builtin_ve_vl_vfmsbd_vvvvl", + "vl.vfmsbd.vvvvmvl" => "__builtin_ve_vl_vfmsbd_vvvvmvl", + "vl.vfmsbd.vvvvvl" => "__builtin_ve_vl_vfmsbd_vvvvvl", + "vl.vfmsbs.vsvvl" => "__builtin_ve_vl_vfmsbs_vsvvl", + "vl.vfmsbs.vsvvmvl" => "__builtin_ve_vl_vfmsbs_vsvvmvl", + "vl.vfmsbs.vsvvvl" => "__builtin_ve_vl_vfmsbs_vsvvvl", + "vl.vfmsbs.vvsvl" => "__builtin_ve_vl_vfmsbs_vvsvl", + "vl.vfmsbs.vvsvmvl" => "__builtin_ve_vl_vfmsbs_vvsvmvl", + "vl.vfmsbs.vvsvvl" => "__builtin_ve_vl_vfmsbs_vvsvvl", + "vl.vfmsbs.vvvvl" => "__builtin_ve_vl_vfmsbs_vvvvl", + "vl.vfmsbs.vvvvmvl" => "__builtin_ve_vl_vfmsbs_vvvvmvl", + "vl.vfmsbs.vvvvvl" => "__builtin_ve_vl_vfmsbs_vvvvvl", + "vl.vfmuld.vsvl" => "__builtin_ve_vl_vfmuld_vsvl", + "vl.vfmuld.vsvmvl" => "__builtin_ve_vl_vfmuld_vsvmvl", + "vl.vfmuld.vsvvl" => "__builtin_ve_vl_vfmuld_vsvvl", + "vl.vfmuld.vvvl" => "__builtin_ve_vl_vfmuld_vvvl", + "vl.vfmuld.vvvmvl" => "__builtin_ve_vl_vfmuld_vvvmvl", + "vl.vfmuld.vvvvl" => "__builtin_ve_vl_vfmuld_vvvvl", + "vl.vfmuls.vsvl" => "__builtin_ve_vl_vfmuls_vsvl", + "vl.vfmuls.vsvmvl" => "__builtin_ve_vl_vfmuls_vsvmvl", + "vl.vfmuls.vsvvl" => "__builtin_ve_vl_vfmuls_vsvvl", + "vl.vfmuls.vvvl" => "__builtin_ve_vl_vfmuls_vvvl", + "vl.vfmuls.vvvmvl" => "__builtin_ve_vl_vfmuls_vvvmvl", + "vl.vfmuls.vvvvl" => "__builtin_ve_vl_vfmuls_vvvvl", + "vl.vfnmadd.vsvvl" => "__builtin_ve_vl_vfnmadd_vsvvl", + "vl.vfnmadd.vsvvmvl" => "__builtin_ve_vl_vfnmadd_vsvvmvl", + "vl.vfnmadd.vsvvvl" => "__builtin_ve_vl_vfnmadd_vsvvvl", + "vl.vfnmadd.vvsvl" => "__builtin_ve_vl_vfnmadd_vvsvl", + "vl.vfnmadd.vvsvmvl" => "__builtin_ve_vl_vfnmadd_vvsvmvl", + "vl.vfnmadd.vvsvvl" => "__builtin_ve_vl_vfnmadd_vvsvvl", + "vl.vfnmadd.vvvvl" => "__builtin_ve_vl_vfnmadd_vvvvl", + "vl.vfnmadd.vvvvmvl" => "__builtin_ve_vl_vfnmadd_vvvvmvl", + "vl.vfnmadd.vvvvvl" => "__builtin_ve_vl_vfnmadd_vvvvvl", + "vl.vfnmads.vsvvl" => "__builtin_ve_vl_vfnmads_vsvvl", + "vl.vfnmads.vsvvmvl" => "__builtin_ve_vl_vfnmads_vsvvmvl", + "vl.vfnmads.vsvvvl" => "__builtin_ve_vl_vfnmads_vsvvvl", + "vl.vfnmads.vvsvl" => "__builtin_ve_vl_vfnmads_vvsvl", + "vl.vfnmads.vvsvmvl" => "__builtin_ve_vl_vfnmads_vvsvmvl", + "vl.vfnmads.vvsvvl" => "__builtin_ve_vl_vfnmads_vvsvvl", + "vl.vfnmads.vvvvl" => "__builtin_ve_vl_vfnmads_vvvvl", + "vl.vfnmads.vvvvmvl" => "__builtin_ve_vl_vfnmads_vvvvmvl", + "vl.vfnmads.vvvvvl" => "__builtin_ve_vl_vfnmads_vvvvvl", + "vl.vfnmsbd.vsvvl" => "__builtin_ve_vl_vfnmsbd_vsvvl", + "vl.vfnmsbd.vsvvmvl" => "__builtin_ve_vl_vfnmsbd_vsvvmvl", + "vl.vfnmsbd.vsvvvl" => "__builtin_ve_vl_vfnmsbd_vsvvvl", + "vl.vfnmsbd.vvsvl" => "__builtin_ve_vl_vfnmsbd_vvsvl", + "vl.vfnmsbd.vvsvmvl" => "__builtin_ve_vl_vfnmsbd_vvsvmvl", + "vl.vfnmsbd.vvsvvl" => "__builtin_ve_vl_vfnmsbd_vvsvvl", + "vl.vfnmsbd.vvvvl" => "__builtin_ve_vl_vfnmsbd_vvvvl", + "vl.vfnmsbd.vvvvmvl" => "__builtin_ve_vl_vfnmsbd_vvvvmvl", + "vl.vfnmsbd.vvvvvl" => "__builtin_ve_vl_vfnmsbd_vvvvvl", + "vl.vfnmsbs.vsvvl" => "__builtin_ve_vl_vfnmsbs_vsvvl", + "vl.vfnmsbs.vsvvmvl" => "__builtin_ve_vl_vfnmsbs_vsvvmvl", + "vl.vfnmsbs.vsvvvl" => "__builtin_ve_vl_vfnmsbs_vsvvvl", + "vl.vfnmsbs.vvsvl" => "__builtin_ve_vl_vfnmsbs_vvsvl", + "vl.vfnmsbs.vvsvmvl" => "__builtin_ve_vl_vfnmsbs_vvsvmvl", + "vl.vfnmsbs.vvsvvl" => "__builtin_ve_vl_vfnmsbs_vvsvvl", + "vl.vfnmsbs.vvvvl" => "__builtin_ve_vl_vfnmsbs_vvvvl", + "vl.vfnmsbs.vvvvmvl" => "__builtin_ve_vl_vfnmsbs_vvvvmvl", + "vl.vfnmsbs.vvvvvl" => "__builtin_ve_vl_vfnmsbs_vvvvvl", + "vl.vfrmaxdfst.vvl" => "__builtin_ve_vl_vfrmaxdfst_vvl", + "vl.vfrmaxdfst.vvvl" => "__builtin_ve_vl_vfrmaxdfst_vvvl", + "vl.vfrmaxdlst.vvl" => "__builtin_ve_vl_vfrmaxdlst_vvl", + "vl.vfrmaxdlst.vvvl" => "__builtin_ve_vl_vfrmaxdlst_vvvl", + "vl.vfrmaxsfst.vvl" => "__builtin_ve_vl_vfrmaxsfst_vvl", + "vl.vfrmaxsfst.vvvl" => "__builtin_ve_vl_vfrmaxsfst_vvvl", + "vl.vfrmaxslst.vvl" => "__builtin_ve_vl_vfrmaxslst_vvl", + "vl.vfrmaxslst.vvvl" => "__builtin_ve_vl_vfrmaxslst_vvvl", + "vl.vfrmindfst.vvl" => "__builtin_ve_vl_vfrmindfst_vvl", + "vl.vfrmindfst.vvvl" => "__builtin_ve_vl_vfrmindfst_vvvl", + "vl.vfrmindlst.vvl" => "__builtin_ve_vl_vfrmindlst_vvl", + "vl.vfrmindlst.vvvl" => "__builtin_ve_vl_vfrmindlst_vvvl", + "vl.vfrminsfst.vvl" => "__builtin_ve_vl_vfrminsfst_vvl", + "vl.vfrminsfst.vvvl" => "__builtin_ve_vl_vfrminsfst_vvvl", + "vl.vfrminslst.vvl" => "__builtin_ve_vl_vfrminslst_vvl", + "vl.vfrminslst.vvvl" => "__builtin_ve_vl_vfrminslst_vvvl", + "vl.vfsqrtd.vvl" => "__builtin_ve_vl_vfsqrtd_vvl", + "vl.vfsqrtd.vvvl" => "__builtin_ve_vl_vfsqrtd_vvvl", + "vl.vfsqrts.vvl" => "__builtin_ve_vl_vfsqrts_vvl", + "vl.vfsqrts.vvvl" => "__builtin_ve_vl_vfsqrts_vvvl", + "vl.vfsubd.vsvl" => "__builtin_ve_vl_vfsubd_vsvl", + "vl.vfsubd.vsvmvl" => "__builtin_ve_vl_vfsubd_vsvmvl", + "vl.vfsubd.vsvvl" => "__builtin_ve_vl_vfsubd_vsvvl", + "vl.vfsubd.vvvl" => "__builtin_ve_vl_vfsubd_vvvl", + "vl.vfsubd.vvvmvl" => "__builtin_ve_vl_vfsubd_vvvmvl", + "vl.vfsubd.vvvvl" => "__builtin_ve_vl_vfsubd_vvvvl", + "vl.vfsubs.vsvl" => "__builtin_ve_vl_vfsubs_vsvl", + "vl.vfsubs.vsvmvl" => "__builtin_ve_vl_vfsubs_vsvmvl", + "vl.vfsubs.vsvvl" => "__builtin_ve_vl_vfsubs_vsvvl", + "vl.vfsubs.vvvl" => "__builtin_ve_vl_vfsubs_vvvl", + "vl.vfsubs.vvvmvl" => "__builtin_ve_vl_vfsubs_vvvmvl", + "vl.vfsubs.vvvvl" => "__builtin_ve_vl_vfsubs_vvvvl", + "vl.vfsumd.vvl" => "__builtin_ve_vl_vfsumd_vvl", + "vl.vfsumd.vvml" => "__builtin_ve_vl_vfsumd_vvml", + "vl.vfsums.vvl" => "__builtin_ve_vl_vfsums_vvl", + "vl.vfsums.vvml" => "__builtin_ve_vl_vfsums_vvml", + "vl.vgt.vvssl" => "__builtin_ve_vl_vgt_vvssl", + "vl.vgt.vvssml" => "__builtin_ve_vl_vgt_vvssml", + "vl.vgt.vvssmvl" => "__builtin_ve_vl_vgt_vvssmvl", + "vl.vgt.vvssvl" => "__builtin_ve_vl_vgt_vvssvl", + "vl.vgtlsx.vvssl" => "__builtin_ve_vl_vgtlsx_vvssl", + "vl.vgtlsx.vvssml" => "__builtin_ve_vl_vgtlsx_vvssml", + "vl.vgtlsx.vvssmvl" => "__builtin_ve_vl_vgtlsx_vvssmvl", + "vl.vgtlsx.vvssvl" => "__builtin_ve_vl_vgtlsx_vvssvl", + "vl.vgtlsxnc.vvssl" => "__builtin_ve_vl_vgtlsxnc_vvssl", + "vl.vgtlsxnc.vvssml" => "__builtin_ve_vl_vgtlsxnc_vvssml", + "vl.vgtlsxnc.vvssmvl" => "__builtin_ve_vl_vgtlsxnc_vvssmvl", + "vl.vgtlsxnc.vvssvl" => "__builtin_ve_vl_vgtlsxnc_vvssvl", + "vl.vgtlzx.vvssl" => "__builtin_ve_vl_vgtlzx_vvssl", + "vl.vgtlzx.vvssml" => "__builtin_ve_vl_vgtlzx_vvssml", + "vl.vgtlzx.vvssmvl" => "__builtin_ve_vl_vgtlzx_vvssmvl", + "vl.vgtlzx.vvssvl" => "__builtin_ve_vl_vgtlzx_vvssvl", + "vl.vgtlzxnc.vvssl" => "__builtin_ve_vl_vgtlzxnc_vvssl", + "vl.vgtlzxnc.vvssml" => "__builtin_ve_vl_vgtlzxnc_vvssml", + "vl.vgtlzxnc.vvssmvl" => "__builtin_ve_vl_vgtlzxnc_vvssmvl", + "vl.vgtlzxnc.vvssvl" => "__builtin_ve_vl_vgtlzxnc_vvssvl", + "vl.vgtnc.vvssl" => "__builtin_ve_vl_vgtnc_vvssl", + "vl.vgtnc.vvssml" => "__builtin_ve_vl_vgtnc_vvssml", + "vl.vgtnc.vvssmvl" => "__builtin_ve_vl_vgtnc_vvssmvl", + "vl.vgtnc.vvssvl" => "__builtin_ve_vl_vgtnc_vvssvl", + "vl.vgtu.vvssl" => "__builtin_ve_vl_vgtu_vvssl", + "vl.vgtu.vvssml" => "__builtin_ve_vl_vgtu_vvssml", + "vl.vgtu.vvssmvl" => "__builtin_ve_vl_vgtu_vvssmvl", + "vl.vgtu.vvssvl" => "__builtin_ve_vl_vgtu_vvssvl", + "vl.vgtunc.vvssl" => "__builtin_ve_vl_vgtunc_vvssl", + "vl.vgtunc.vvssml" => "__builtin_ve_vl_vgtunc_vvssml", + "vl.vgtunc.vvssmvl" => "__builtin_ve_vl_vgtunc_vvssmvl", + "vl.vgtunc.vvssvl" => "__builtin_ve_vl_vgtunc_vvssvl", + "vl.vld.vssl" => "__builtin_ve_vl_vld_vssl", + "vl.vld.vssvl" => "__builtin_ve_vl_vld_vssvl", + "vl.vld2d.vssl" => "__builtin_ve_vl_vld2d_vssl", + "vl.vld2d.vssvl" => "__builtin_ve_vl_vld2d_vssvl", + "vl.vld2dnc.vssl" => "__builtin_ve_vl_vld2dnc_vssl", + "vl.vld2dnc.vssvl" => "__builtin_ve_vl_vld2dnc_vssvl", + "vl.vldl2dsx.vssl" => "__builtin_ve_vl_vldl2dsx_vssl", + "vl.vldl2dsx.vssvl" => "__builtin_ve_vl_vldl2dsx_vssvl", + "vl.vldl2dsxnc.vssl" => "__builtin_ve_vl_vldl2dsxnc_vssl", + "vl.vldl2dsxnc.vssvl" => "__builtin_ve_vl_vldl2dsxnc_vssvl", + "vl.vldl2dzx.vssl" => "__builtin_ve_vl_vldl2dzx_vssl", + "vl.vldl2dzx.vssvl" => "__builtin_ve_vl_vldl2dzx_vssvl", + "vl.vldl2dzxnc.vssl" => "__builtin_ve_vl_vldl2dzxnc_vssl", + "vl.vldl2dzxnc.vssvl" => "__builtin_ve_vl_vldl2dzxnc_vssvl", + "vl.vldlsx.vssl" => "__builtin_ve_vl_vldlsx_vssl", + "vl.vldlsx.vssvl" => "__builtin_ve_vl_vldlsx_vssvl", + "vl.vldlsxnc.vssl" => "__builtin_ve_vl_vldlsxnc_vssl", + "vl.vldlsxnc.vssvl" => "__builtin_ve_vl_vldlsxnc_vssvl", + "vl.vldlzx.vssl" => "__builtin_ve_vl_vldlzx_vssl", + "vl.vldlzx.vssvl" => "__builtin_ve_vl_vldlzx_vssvl", + "vl.vldlzxnc.vssl" => "__builtin_ve_vl_vldlzxnc_vssl", + "vl.vldlzxnc.vssvl" => "__builtin_ve_vl_vldlzxnc_vssvl", + "vl.vldnc.vssl" => "__builtin_ve_vl_vldnc_vssl", + "vl.vldnc.vssvl" => "__builtin_ve_vl_vldnc_vssvl", + "vl.vldu.vssl" => "__builtin_ve_vl_vldu_vssl", + "vl.vldu.vssvl" => "__builtin_ve_vl_vldu_vssvl", + "vl.vldu2d.vssl" => "__builtin_ve_vl_vldu2d_vssl", + "vl.vldu2d.vssvl" => "__builtin_ve_vl_vldu2d_vssvl", + "vl.vldu2dnc.vssl" => "__builtin_ve_vl_vldu2dnc_vssl", + "vl.vldu2dnc.vssvl" => "__builtin_ve_vl_vldu2dnc_vssvl", + "vl.vldunc.vssl" => "__builtin_ve_vl_vldunc_vssl", + "vl.vldunc.vssvl" => "__builtin_ve_vl_vldunc_vssvl", + "vl.vldz.vvl" => "__builtin_ve_vl_vldz_vvl", + "vl.vldz.vvmvl" => "__builtin_ve_vl_vldz_vvmvl", + "vl.vldz.vvvl" => "__builtin_ve_vl_vldz_vvvl", + "vl.vmaxsl.vsvl" => "__builtin_ve_vl_vmaxsl_vsvl", + "vl.vmaxsl.vsvmvl" => "__builtin_ve_vl_vmaxsl_vsvmvl", + "vl.vmaxsl.vsvvl" => "__builtin_ve_vl_vmaxsl_vsvvl", + "vl.vmaxsl.vvvl" => "__builtin_ve_vl_vmaxsl_vvvl", + "vl.vmaxsl.vvvmvl" => "__builtin_ve_vl_vmaxsl_vvvmvl", + "vl.vmaxsl.vvvvl" => "__builtin_ve_vl_vmaxsl_vvvvl", + "vl.vmaxswsx.vsvl" => "__builtin_ve_vl_vmaxswsx_vsvl", + "vl.vmaxswsx.vsvmvl" => "__builtin_ve_vl_vmaxswsx_vsvmvl", + "vl.vmaxswsx.vsvvl" => "__builtin_ve_vl_vmaxswsx_vsvvl", + "vl.vmaxswsx.vvvl" => "__builtin_ve_vl_vmaxswsx_vvvl", + "vl.vmaxswsx.vvvmvl" => "__builtin_ve_vl_vmaxswsx_vvvmvl", + "vl.vmaxswsx.vvvvl" => "__builtin_ve_vl_vmaxswsx_vvvvl", + "vl.vmaxswzx.vsvl" => "__builtin_ve_vl_vmaxswzx_vsvl", + "vl.vmaxswzx.vsvmvl" => "__builtin_ve_vl_vmaxswzx_vsvmvl", + "vl.vmaxswzx.vsvvl" => "__builtin_ve_vl_vmaxswzx_vsvvl", + "vl.vmaxswzx.vvvl" => "__builtin_ve_vl_vmaxswzx_vvvl", + "vl.vmaxswzx.vvvmvl" => "__builtin_ve_vl_vmaxswzx_vvvmvl", + "vl.vmaxswzx.vvvvl" => "__builtin_ve_vl_vmaxswzx_vvvvl", + "vl.vminsl.vsvl" => "__builtin_ve_vl_vminsl_vsvl", + "vl.vminsl.vsvmvl" => "__builtin_ve_vl_vminsl_vsvmvl", + "vl.vminsl.vsvvl" => "__builtin_ve_vl_vminsl_vsvvl", + "vl.vminsl.vvvl" => "__builtin_ve_vl_vminsl_vvvl", + "vl.vminsl.vvvmvl" => "__builtin_ve_vl_vminsl_vvvmvl", + "vl.vminsl.vvvvl" => "__builtin_ve_vl_vminsl_vvvvl", + "vl.vminswsx.vsvl" => "__builtin_ve_vl_vminswsx_vsvl", + "vl.vminswsx.vsvmvl" => "__builtin_ve_vl_vminswsx_vsvmvl", + "vl.vminswsx.vsvvl" => "__builtin_ve_vl_vminswsx_vsvvl", + "vl.vminswsx.vvvl" => "__builtin_ve_vl_vminswsx_vvvl", + "vl.vminswsx.vvvmvl" => "__builtin_ve_vl_vminswsx_vvvmvl", + "vl.vminswsx.vvvvl" => "__builtin_ve_vl_vminswsx_vvvvl", + "vl.vminswzx.vsvl" => "__builtin_ve_vl_vminswzx_vsvl", + "vl.vminswzx.vsvmvl" => "__builtin_ve_vl_vminswzx_vsvmvl", + "vl.vminswzx.vsvvl" => "__builtin_ve_vl_vminswzx_vsvvl", + "vl.vminswzx.vvvl" => "__builtin_ve_vl_vminswzx_vvvl", + "vl.vminswzx.vvvmvl" => "__builtin_ve_vl_vminswzx_vvvmvl", + "vl.vminswzx.vvvvl" => "__builtin_ve_vl_vminswzx_vvvvl", + "vl.vmrg.vsvml" => "__builtin_ve_vl_vmrg_vsvml", + "vl.vmrg.vsvmvl" => "__builtin_ve_vl_vmrg_vsvmvl", + "vl.vmrg.vvvml" => "__builtin_ve_vl_vmrg_vvvml", + "vl.vmrg.vvvmvl" => "__builtin_ve_vl_vmrg_vvvmvl", + "vl.vmrgw.vsvMl" => "__builtin_ve_vl_vmrgw_vsvMl", + "vl.vmrgw.vsvMvl" => "__builtin_ve_vl_vmrgw_vsvMvl", + "vl.vmrgw.vvvMl" => "__builtin_ve_vl_vmrgw_vvvMl", + "vl.vmrgw.vvvMvl" => "__builtin_ve_vl_vmrgw_vvvMvl", + "vl.vmulsl.vsvl" => "__builtin_ve_vl_vmulsl_vsvl", + "vl.vmulsl.vsvmvl" => "__builtin_ve_vl_vmulsl_vsvmvl", + "vl.vmulsl.vsvvl" => "__builtin_ve_vl_vmulsl_vsvvl", + "vl.vmulsl.vvvl" => "__builtin_ve_vl_vmulsl_vvvl", + "vl.vmulsl.vvvmvl" => "__builtin_ve_vl_vmulsl_vvvmvl", + "vl.vmulsl.vvvvl" => "__builtin_ve_vl_vmulsl_vvvvl", + "vl.vmulslw.vsvl" => "__builtin_ve_vl_vmulslw_vsvl", + "vl.vmulslw.vsvvl" => "__builtin_ve_vl_vmulslw_vsvvl", + "vl.vmulslw.vvvl" => "__builtin_ve_vl_vmulslw_vvvl", + "vl.vmulslw.vvvvl" => "__builtin_ve_vl_vmulslw_vvvvl", + "vl.vmulswsx.vsvl" => "__builtin_ve_vl_vmulswsx_vsvl", + "vl.vmulswsx.vsvmvl" => "__builtin_ve_vl_vmulswsx_vsvmvl", + "vl.vmulswsx.vsvvl" => "__builtin_ve_vl_vmulswsx_vsvvl", + "vl.vmulswsx.vvvl" => "__builtin_ve_vl_vmulswsx_vvvl", + "vl.vmulswsx.vvvmvl" => "__builtin_ve_vl_vmulswsx_vvvmvl", + "vl.vmulswsx.vvvvl" => "__builtin_ve_vl_vmulswsx_vvvvl", + "vl.vmulswzx.vsvl" => "__builtin_ve_vl_vmulswzx_vsvl", + "vl.vmulswzx.vsvmvl" => "__builtin_ve_vl_vmulswzx_vsvmvl", + "vl.vmulswzx.vsvvl" => "__builtin_ve_vl_vmulswzx_vsvvl", + "vl.vmulswzx.vvvl" => "__builtin_ve_vl_vmulswzx_vvvl", + "vl.vmulswzx.vvvmvl" => "__builtin_ve_vl_vmulswzx_vvvmvl", + "vl.vmulswzx.vvvvl" => "__builtin_ve_vl_vmulswzx_vvvvl", + "vl.vmulul.vsvl" => "__builtin_ve_vl_vmulul_vsvl", + "vl.vmulul.vsvmvl" => "__builtin_ve_vl_vmulul_vsvmvl", + "vl.vmulul.vsvvl" => "__builtin_ve_vl_vmulul_vsvvl", + "vl.vmulul.vvvl" => "__builtin_ve_vl_vmulul_vvvl", + "vl.vmulul.vvvmvl" => "__builtin_ve_vl_vmulul_vvvmvl", + "vl.vmulul.vvvvl" => "__builtin_ve_vl_vmulul_vvvvl", + "vl.vmuluw.vsvl" => "__builtin_ve_vl_vmuluw_vsvl", + "vl.vmuluw.vsvmvl" => "__builtin_ve_vl_vmuluw_vsvmvl", + "vl.vmuluw.vsvvl" => "__builtin_ve_vl_vmuluw_vsvvl", + "vl.vmuluw.vvvl" => "__builtin_ve_vl_vmuluw_vvvl", + "vl.vmuluw.vvvmvl" => "__builtin_ve_vl_vmuluw_vvvmvl", + "vl.vmuluw.vvvvl" => "__builtin_ve_vl_vmuluw_vvvvl", + "vl.vmv.vsvl" => "__builtin_ve_vl_vmv_vsvl", + "vl.vmv.vsvmvl" => "__builtin_ve_vl_vmv_vsvmvl", + "vl.vmv.vsvvl" => "__builtin_ve_vl_vmv_vsvvl", + "vl.vor.vsvl" => "__builtin_ve_vl_vor_vsvl", + "vl.vor.vsvmvl" => "__builtin_ve_vl_vor_vsvmvl", + "vl.vor.vsvvl" => "__builtin_ve_vl_vor_vsvvl", + "vl.vor.vvvl" => "__builtin_ve_vl_vor_vvvl", + "vl.vor.vvvmvl" => "__builtin_ve_vl_vor_vvvmvl", + "vl.vor.vvvvl" => "__builtin_ve_vl_vor_vvvvl", + "vl.vpcnt.vvl" => "__builtin_ve_vl_vpcnt_vvl", + "vl.vpcnt.vvmvl" => "__builtin_ve_vl_vpcnt_vvmvl", + "vl.vpcnt.vvvl" => "__builtin_ve_vl_vpcnt_vvvl", + "vl.vrand.vvl" => "__builtin_ve_vl_vrand_vvl", + "vl.vrand.vvml" => "__builtin_ve_vl_vrand_vvml", + "vl.vrcpd.vvl" => "__builtin_ve_vl_vrcpd_vvl", + "vl.vrcpd.vvvl" => "__builtin_ve_vl_vrcpd_vvvl", + "vl.vrcps.vvl" => "__builtin_ve_vl_vrcps_vvl", + "vl.vrcps.vvvl" => "__builtin_ve_vl_vrcps_vvvl", + "vl.vrmaxslfst.vvl" => "__builtin_ve_vl_vrmaxslfst_vvl", + "vl.vrmaxslfst.vvvl" => "__builtin_ve_vl_vrmaxslfst_vvvl", + "vl.vrmaxsllst.vvl" => "__builtin_ve_vl_vrmaxsllst_vvl", + "vl.vrmaxsllst.vvvl" => "__builtin_ve_vl_vrmaxsllst_vvvl", + "vl.vrmaxswfstsx.vvl" => "__builtin_ve_vl_vrmaxswfstsx_vvl", + "vl.vrmaxswfstsx.vvvl" => "__builtin_ve_vl_vrmaxswfstsx_vvvl", + "vl.vrmaxswfstzx.vvl" => "__builtin_ve_vl_vrmaxswfstzx_vvl", + "vl.vrmaxswfstzx.vvvl" => "__builtin_ve_vl_vrmaxswfstzx_vvvl", + "vl.vrmaxswlstsx.vvl" => "__builtin_ve_vl_vrmaxswlstsx_vvl", + "vl.vrmaxswlstsx.vvvl" => "__builtin_ve_vl_vrmaxswlstsx_vvvl", + "vl.vrmaxswlstzx.vvl" => "__builtin_ve_vl_vrmaxswlstzx_vvl", + "vl.vrmaxswlstzx.vvvl" => "__builtin_ve_vl_vrmaxswlstzx_vvvl", + "vl.vrminslfst.vvl" => "__builtin_ve_vl_vrminslfst_vvl", + "vl.vrminslfst.vvvl" => "__builtin_ve_vl_vrminslfst_vvvl", + "vl.vrminsllst.vvl" => "__builtin_ve_vl_vrminsllst_vvl", + "vl.vrminsllst.vvvl" => "__builtin_ve_vl_vrminsllst_vvvl", + "vl.vrminswfstsx.vvl" => "__builtin_ve_vl_vrminswfstsx_vvl", + "vl.vrminswfstsx.vvvl" => "__builtin_ve_vl_vrminswfstsx_vvvl", + "vl.vrminswfstzx.vvl" => "__builtin_ve_vl_vrminswfstzx_vvl", + "vl.vrminswfstzx.vvvl" => "__builtin_ve_vl_vrminswfstzx_vvvl", + "vl.vrminswlstsx.vvl" => "__builtin_ve_vl_vrminswlstsx_vvl", + "vl.vrminswlstsx.vvvl" => "__builtin_ve_vl_vrminswlstsx_vvvl", + "vl.vrminswlstzx.vvl" => "__builtin_ve_vl_vrminswlstzx_vvl", + "vl.vrminswlstzx.vvvl" => "__builtin_ve_vl_vrminswlstzx_vvvl", + "vl.vror.vvl" => "__builtin_ve_vl_vror_vvl", + "vl.vror.vvml" => "__builtin_ve_vl_vror_vvml", + "vl.vrsqrtd.vvl" => "__builtin_ve_vl_vrsqrtd_vvl", + "vl.vrsqrtd.vvvl" => "__builtin_ve_vl_vrsqrtd_vvvl", + "vl.vrsqrtdnex.vvl" => "__builtin_ve_vl_vrsqrtdnex_vvl", + "vl.vrsqrtdnex.vvvl" => "__builtin_ve_vl_vrsqrtdnex_vvvl", + "vl.vrsqrts.vvl" => "__builtin_ve_vl_vrsqrts_vvl", + "vl.vrsqrts.vvvl" => "__builtin_ve_vl_vrsqrts_vvvl", + "vl.vrsqrtsnex.vvl" => "__builtin_ve_vl_vrsqrtsnex_vvl", + "vl.vrsqrtsnex.vvvl" => "__builtin_ve_vl_vrsqrtsnex_vvvl", + "vl.vrxor.vvl" => "__builtin_ve_vl_vrxor_vvl", + "vl.vrxor.vvml" => "__builtin_ve_vl_vrxor_vvml", + "vl.vsc.vvssl" => "__builtin_ve_vl_vsc_vvssl", + "vl.vsc.vvssml" => "__builtin_ve_vl_vsc_vvssml", + "vl.vscl.vvssl" => "__builtin_ve_vl_vscl_vvssl", + "vl.vscl.vvssml" => "__builtin_ve_vl_vscl_vvssml", + "vl.vsclnc.vvssl" => "__builtin_ve_vl_vsclnc_vvssl", + "vl.vsclnc.vvssml" => "__builtin_ve_vl_vsclnc_vvssml", + "vl.vsclncot.vvssl" => "__builtin_ve_vl_vsclncot_vvssl", + "vl.vsclncot.vvssml" => "__builtin_ve_vl_vsclncot_vvssml", + "vl.vsclot.vvssl" => "__builtin_ve_vl_vsclot_vvssl", + "vl.vsclot.vvssml" => "__builtin_ve_vl_vsclot_vvssml", + "vl.vscnc.vvssl" => "__builtin_ve_vl_vscnc_vvssl", + "vl.vscnc.vvssml" => "__builtin_ve_vl_vscnc_vvssml", + "vl.vscncot.vvssl" => "__builtin_ve_vl_vscncot_vvssl", + "vl.vscncot.vvssml" => "__builtin_ve_vl_vscncot_vvssml", + "vl.vscot.vvssl" => "__builtin_ve_vl_vscot_vvssl", + "vl.vscot.vvssml" => "__builtin_ve_vl_vscot_vvssml", + "vl.vscu.vvssl" => "__builtin_ve_vl_vscu_vvssl", + "vl.vscu.vvssml" => "__builtin_ve_vl_vscu_vvssml", + "vl.vscunc.vvssl" => "__builtin_ve_vl_vscunc_vvssl", + "vl.vscunc.vvssml" => "__builtin_ve_vl_vscunc_vvssml", + "vl.vscuncot.vvssl" => "__builtin_ve_vl_vscuncot_vvssl", + "vl.vscuncot.vvssml" => "__builtin_ve_vl_vscuncot_vvssml", + "vl.vscuot.vvssl" => "__builtin_ve_vl_vscuot_vvssl", + "vl.vscuot.vvssml" => "__builtin_ve_vl_vscuot_vvssml", + "vl.vseq.vl" => "__builtin_ve_vl_vseq_vl", + "vl.vseq.vvl" => "__builtin_ve_vl_vseq_vvl", + "vl.vsfa.vvssl" => "__builtin_ve_vl_vsfa_vvssl", + "vl.vsfa.vvssmvl" => "__builtin_ve_vl_vsfa_vvssmvl", + "vl.vsfa.vvssvl" => "__builtin_ve_vl_vsfa_vvssvl", + "vl.vshf.vvvsl" => "__builtin_ve_vl_vshf_vvvsl", + "vl.vshf.vvvsvl" => "__builtin_ve_vl_vshf_vvvsvl", + "vl.vslal.vvsl" => "__builtin_ve_vl_vslal_vvsl", + "vl.vslal.vvsmvl" => "__builtin_ve_vl_vslal_vvsmvl", + "vl.vslal.vvsvl" => "__builtin_ve_vl_vslal_vvsvl", + "vl.vslal.vvvl" => "__builtin_ve_vl_vslal_vvvl", + "vl.vslal.vvvmvl" => "__builtin_ve_vl_vslal_vvvmvl", + "vl.vslal.vvvvl" => "__builtin_ve_vl_vslal_vvvvl", + "vl.vslawsx.vvsl" => "__builtin_ve_vl_vslawsx_vvsl", + "vl.vslawsx.vvsmvl" => "__builtin_ve_vl_vslawsx_vvsmvl", + "vl.vslawsx.vvsvl" => "__builtin_ve_vl_vslawsx_vvsvl", + "vl.vslawsx.vvvl" => "__builtin_ve_vl_vslawsx_vvvl", + "vl.vslawsx.vvvmvl" => "__builtin_ve_vl_vslawsx_vvvmvl", + "vl.vslawsx.vvvvl" => "__builtin_ve_vl_vslawsx_vvvvl", + "vl.vslawzx.vvsl" => "__builtin_ve_vl_vslawzx_vvsl", + "vl.vslawzx.vvsmvl" => "__builtin_ve_vl_vslawzx_vvsmvl", + "vl.vslawzx.vvsvl" => "__builtin_ve_vl_vslawzx_vvsvl", + "vl.vslawzx.vvvl" => "__builtin_ve_vl_vslawzx_vvvl", + "vl.vslawzx.vvvmvl" => "__builtin_ve_vl_vslawzx_vvvmvl", + "vl.vslawzx.vvvvl" => "__builtin_ve_vl_vslawzx_vvvvl", + "vl.vsll.vvsl" => "__builtin_ve_vl_vsll_vvsl", + "vl.vsll.vvsmvl" => "__builtin_ve_vl_vsll_vvsmvl", + "vl.vsll.vvsvl" => "__builtin_ve_vl_vsll_vvsvl", + "vl.vsll.vvvl" => "__builtin_ve_vl_vsll_vvvl", + "vl.vsll.vvvmvl" => "__builtin_ve_vl_vsll_vvvmvl", + "vl.vsll.vvvvl" => "__builtin_ve_vl_vsll_vvvvl", + "vl.vsral.vvsl" => "__builtin_ve_vl_vsral_vvsl", + "vl.vsral.vvsmvl" => "__builtin_ve_vl_vsral_vvsmvl", + "vl.vsral.vvsvl" => "__builtin_ve_vl_vsral_vvsvl", + "vl.vsral.vvvl" => "__builtin_ve_vl_vsral_vvvl", + "vl.vsral.vvvmvl" => "__builtin_ve_vl_vsral_vvvmvl", + "vl.vsral.vvvvl" => "__builtin_ve_vl_vsral_vvvvl", + "vl.vsrawsx.vvsl" => "__builtin_ve_vl_vsrawsx_vvsl", + "vl.vsrawsx.vvsmvl" => "__builtin_ve_vl_vsrawsx_vvsmvl", + "vl.vsrawsx.vvsvl" => "__builtin_ve_vl_vsrawsx_vvsvl", + "vl.vsrawsx.vvvl" => "__builtin_ve_vl_vsrawsx_vvvl", + "vl.vsrawsx.vvvmvl" => "__builtin_ve_vl_vsrawsx_vvvmvl", + "vl.vsrawsx.vvvvl" => "__builtin_ve_vl_vsrawsx_vvvvl", + "vl.vsrawzx.vvsl" => "__builtin_ve_vl_vsrawzx_vvsl", + "vl.vsrawzx.vvsmvl" => "__builtin_ve_vl_vsrawzx_vvsmvl", + "vl.vsrawzx.vvsvl" => "__builtin_ve_vl_vsrawzx_vvsvl", + "vl.vsrawzx.vvvl" => "__builtin_ve_vl_vsrawzx_vvvl", + "vl.vsrawzx.vvvmvl" => "__builtin_ve_vl_vsrawzx_vvvmvl", + "vl.vsrawzx.vvvvl" => "__builtin_ve_vl_vsrawzx_vvvvl", + "vl.vsrl.vvsl" => "__builtin_ve_vl_vsrl_vvsl", + "vl.vsrl.vvsmvl" => "__builtin_ve_vl_vsrl_vvsmvl", + "vl.vsrl.vvsvl" => "__builtin_ve_vl_vsrl_vvsvl", + "vl.vsrl.vvvl" => "__builtin_ve_vl_vsrl_vvvl", + "vl.vsrl.vvvmvl" => "__builtin_ve_vl_vsrl_vvvmvl", + "vl.vsrl.vvvvl" => "__builtin_ve_vl_vsrl_vvvvl", + "vl.vst.vssl" => "__builtin_ve_vl_vst_vssl", + "vl.vst.vssml" => "__builtin_ve_vl_vst_vssml", + "vl.vst2d.vssl" => "__builtin_ve_vl_vst2d_vssl", + "vl.vst2d.vssml" => "__builtin_ve_vl_vst2d_vssml", + "vl.vst2dnc.vssl" => "__builtin_ve_vl_vst2dnc_vssl", + "vl.vst2dnc.vssml" => "__builtin_ve_vl_vst2dnc_vssml", + "vl.vst2dncot.vssl" => "__builtin_ve_vl_vst2dncot_vssl", + "vl.vst2dncot.vssml" => "__builtin_ve_vl_vst2dncot_vssml", + "vl.vst2dot.vssl" => "__builtin_ve_vl_vst2dot_vssl", + "vl.vst2dot.vssml" => "__builtin_ve_vl_vst2dot_vssml", + "vl.vstl.vssl" => "__builtin_ve_vl_vstl_vssl", + "vl.vstl.vssml" => "__builtin_ve_vl_vstl_vssml", + "vl.vstl2d.vssl" => "__builtin_ve_vl_vstl2d_vssl", + "vl.vstl2d.vssml" => "__builtin_ve_vl_vstl2d_vssml", + "vl.vstl2dnc.vssl" => "__builtin_ve_vl_vstl2dnc_vssl", + "vl.vstl2dnc.vssml" => "__builtin_ve_vl_vstl2dnc_vssml", + "vl.vstl2dncot.vssl" => "__builtin_ve_vl_vstl2dncot_vssl", + "vl.vstl2dncot.vssml" => "__builtin_ve_vl_vstl2dncot_vssml", + "vl.vstl2dot.vssl" => "__builtin_ve_vl_vstl2dot_vssl", + "vl.vstl2dot.vssml" => "__builtin_ve_vl_vstl2dot_vssml", + "vl.vstlnc.vssl" => "__builtin_ve_vl_vstlnc_vssl", + "vl.vstlnc.vssml" => "__builtin_ve_vl_vstlnc_vssml", + "vl.vstlncot.vssl" => "__builtin_ve_vl_vstlncot_vssl", + "vl.vstlncot.vssml" => "__builtin_ve_vl_vstlncot_vssml", + "vl.vstlot.vssl" => "__builtin_ve_vl_vstlot_vssl", + "vl.vstlot.vssml" => "__builtin_ve_vl_vstlot_vssml", + "vl.vstnc.vssl" => "__builtin_ve_vl_vstnc_vssl", + "vl.vstnc.vssml" => "__builtin_ve_vl_vstnc_vssml", + "vl.vstncot.vssl" => "__builtin_ve_vl_vstncot_vssl", + "vl.vstncot.vssml" => "__builtin_ve_vl_vstncot_vssml", + "vl.vstot.vssl" => "__builtin_ve_vl_vstot_vssl", + "vl.vstot.vssml" => "__builtin_ve_vl_vstot_vssml", + "vl.vstu.vssl" => "__builtin_ve_vl_vstu_vssl", + "vl.vstu.vssml" => "__builtin_ve_vl_vstu_vssml", + "vl.vstu2d.vssl" => "__builtin_ve_vl_vstu2d_vssl", + "vl.vstu2d.vssml" => "__builtin_ve_vl_vstu2d_vssml", + "vl.vstu2dnc.vssl" => "__builtin_ve_vl_vstu2dnc_vssl", + "vl.vstu2dnc.vssml" => "__builtin_ve_vl_vstu2dnc_vssml", + "vl.vstu2dncot.vssl" => "__builtin_ve_vl_vstu2dncot_vssl", + "vl.vstu2dncot.vssml" => "__builtin_ve_vl_vstu2dncot_vssml", + "vl.vstu2dot.vssl" => "__builtin_ve_vl_vstu2dot_vssl", + "vl.vstu2dot.vssml" => "__builtin_ve_vl_vstu2dot_vssml", + "vl.vstunc.vssl" => "__builtin_ve_vl_vstunc_vssl", + "vl.vstunc.vssml" => "__builtin_ve_vl_vstunc_vssml", + "vl.vstuncot.vssl" => "__builtin_ve_vl_vstuncot_vssl", + "vl.vstuncot.vssml" => "__builtin_ve_vl_vstuncot_vssml", + "vl.vstuot.vssl" => "__builtin_ve_vl_vstuot_vssl", + "vl.vstuot.vssml" => "__builtin_ve_vl_vstuot_vssml", + "vl.vsubsl.vsvl" => "__builtin_ve_vl_vsubsl_vsvl", + "vl.vsubsl.vsvmvl" => "__builtin_ve_vl_vsubsl_vsvmvl", + "vl.vsubsl.vsvvl" => "__builtin_ve_vl_vsubsl_vsvvl", + "vl.vsubsl.vvvl" => "__builtin_ve_vl_vsubsl_vvvl", + "vl.vsubsl.vvvmvl" => "__builtin_ve_vl_vsubsl_vvvmvl", + "vl.vsubsl.vvvvl" => "__builtin_ve_vl_vsubsl_vvvvl", + "vl.vsubswsx.vsvl" => "__builtin_ve_vl_vsubswsx_vsvl", + "vl.vsubswsx.vsvmvl" => "__builtin_ve_vl_vsubswsx_vsvmvl", + "vl.vsubswsx.vsvvl" => "__builtin_ve_vl_vsubswsx_vsvvl", + "vl.vsubswsx.vvvl" => "__builtin_ve_vl_vsubswsx_vvvl", + "vl.vsubswsx.vvvmvl" => "__builtin_ve_vl_vsubswsx_vvvmvl", + "vl.vsubswsx.vvvvl" => "__builtin_ve_vl_vsubswsx_vvvvl", + "vl.vsubswzx.vsvl" => "__builtin_ve_vl_vsubswzx_vsvl", + "vl.vsubswzx.vsvmvl" => "__builtin_ve_vl_vsubswzx_vsvmvl", + "vl.vsubswzx.vsvvl" => "__builtin_ve_vl_vsubswzx_vsvvl", + "vl.vsubswzx.vvvl" => "__builtin_ve_vl_vsubswzx_vvvl", + "vl.vsubswzx.vvvmvl" => "__builtin_ve_vl_vsubswzx_vvvmvl", + "vl.vsubswzx.vvvvl" => "__builtin_ve_vl_vsubswzx_vvvvl", + "vl.vsubul.vsvl" => "__builtin_ve_vl_vsubul_vsvl", + "vl.vsubul.vsvmvl" => "__builtin_ve_vl_vsubul_vsvmvl", + "vl.vsubul.vsvvl" => "__builtin_ve_vl_vsubul_vsvvl", + "vl.vsubul.vvvl" => "__builtin_ve_vl_vsubul_vvvl", + "vl.vsubul.vvvmvl" => "__builtin_ve_vl_vsubul_vvvmvl", + "vl.vsubul.vvvvl" => "__builtin_ve_vl_vsubul_vvvvl", + "vl.vsubuw.vsvl" => "__builtin_ve_vl_vsubuw_vsvl", + "vl.vsubuw.vsvmvl" => "__builtin_ve_vl_vsubuw_vsvmvl", + "vl.vsubuw.vsvvl" => "__builtin_ve_vl_vsubuw_vsvvl", + "vl.vsubuw.vvvl" => "__builtin_ve_vl_vsubuw_vvvl", + "vl.vsubuw.vvvmvl" => "__builtin_ve_vl_vsubuw_vvvmvl", + "vl.vsubuw.vvvvl" => "__builtin_ve_vl_vsubuw_vvvvl", + "vl.vsuml.vvl" => "__builtin_ve_vl_vsuml_vvl", + "vl.vsuml.vvml" => "__builtin_ve_vl_vsuml_vvml", + "vl.vsumwsx.vvl" => "__builtin_ve_vl_vsumwsx_vvl", + "vl.vsumwsx.vvml" => "__builtin_ve_vl_vsumwsx_vvml", + "vl.vsumwzx.vvl" => "__builtin_ve_vl_vsumwzx_vvl", + "vl.vsumwzx.vvml" => "__builtin_ve_vl_vsumwzx_vvml", + "vl.vxor.vsvl" => "__builtin_ve_vl_vxor_vsvl", + "vl.vxor.vsvmvl" => "__builtin_ve_vl_vxor_vsvmvl", + "vl.vxor.vsvvl" => "__builtin_ve_vl_vxor_vsvvl", + "vl.vxor.vvvl" => "__builtin_ve_vl_vxor_vvvl", + "vl.vxor.vvvmvl" => "__builtin_ve_vl_vxor_vvvmvl", + "vl.vxor.vvvvl" => "__builtin_ve_vl_vxor_vvvvl", + "vl.xorm.MMM" => "__builtin_ve_vl_xorm_MMM", + "vl.xorm.mmm" => "__builtin_ve_vl_xorm_mmm", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + ve(name) + } + "x86" => { + #[allow(non_snake_case)] + fn x86(name: &str) -> &str { + match name { + // x86 + "aadd32" => "__builtin_ia32_aadd32", + "aadd64" => "__builtin_ia32_aadd64", + "aand32" => "__builtin_ia32_aand32", + "aand64" => "__builtin_ia32_aand64", + "addcarry.u32" => "__builtin_ia32_addcarry_u32", + "addcarry.u64" => "__builtin_ia32_addcarry_u64", + "addcarryx.u32" => "__builtin_ia32_addcarryx_u32", + "addcarryx.u64" => "__builtin_ia32_addcarryx_u64", + "aesni.aesdec" => "__builtin_ia32_aesdec128", + "aesni.aesdec.256" => "__builtin_ia32_aesdec256", + "aesni.aesdec.512" => "__builtin_ia32_aesdec512", + "aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", + "aesni.aesdeclast.256" => "__builtin_ia32_aesdeclast256", + "aesni.aesdeclast.512" => "__builtin_ia32_aesdeclast512", + "aesni.aesenc" => "__builtin_ia32_aesenc128", + "aesni.aesenc.256" => "__builtin_ia32_aesenc256", + "aesni.aesenc.512" => "__builtin_ia32_aesenc512", + "aesni.aesenclast" => "__builtin_ia32_aesenclast128", + "aesni.aesenclast.256" => "__builtin_ia32_aesenclast256", + "aesni.aesenclast.512" => "__builtin_ia32_aesenclast512", + "aesni.aesimc" => "__builtin_ia32_aesimc128", + "aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", + "aor32" => "__builtin_ia32_aor32", + "aor64" => "__builtin_ia32_aor64", + "avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", + "avx.addsub.ps.256" => "__builtin_ia32_addsubps256", + "avx.blend.pd.256" => "__builtin_ia32_blendpd256", + "avx.blend.ps.256" => "__builtin_ia32_blendps256", + "avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", + "avx.blendv.ps.256" => "__builtin_ia32_blendvps256", + "avx.cmp.pd.256" => "__builtin_ia32_cmppd256", + "avx.cmp.ps.256" => "__builtin_ia32_cmpps256", + "avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", + "avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", + "avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", + "avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", + "avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", + "avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", + "avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", + "avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", + "avx.dp.ps.256" => "__builtin_ia32_dpps256", + "avx.hadd.pd.256" => "__builtin_ia32_haddpd256", + "avx.hadd.ps.256" => "__builtin_ia32_haddps256", + "avx.hsub.pd.256" => "__builtin_ia32_hsubpd256", + "avx.hsub.ps.256" => "__builtin_ia32_hsubps256", + "avx.ldu.dq.256" => "__builtin_ia32_lddqu256", + "avx.maskload.pd" => "__builtin_ia32_maskloadpd", + "avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256", + "avx.maskload.ps" => "__builtin_ia32_maskloadps", + "avx.maskload.ps.256" => "__builtin_ia32_maskloadps256", + "avx.maskstore.pd" => "__builtin_ia32_maskstorepd", + "avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256", + "avx.maskstore.ps" => "__builtin_ia32_maskstoreps", + "avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256", + "avx.max.pd.256" => "__builtin_ia32_maxpd256", + "avx.max.ps.256" => "__builtin_ia32_maxps256", + "avx.min.pd.256" => "__builtin_ia32_minpd256", + "avx.min.ps.256" => "__builtin_ia32_minps256", + "avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256", + "avx.movmsk.ps.256" => "__builtin_ia32_movmskps256", + "avx.ptestc.256" => "__builtin_ia32_ptestc256", + "avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256", + "avx.ptestz.256" => "__builtin_ia32_ptestz256", + "avx.rcp.ps.256" => "__builtin_ia32_rcpps256", + "avx.round.pd.256" => "__builtin_ia32_roundpd256", + "avx.round.ps.256" => "__builtin_ia32_roundps256", + "avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", + "avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", + "avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", + "avx.storeu.dq.256" => "__builtin_ia32_storedqu256", + "avx.storeu.pd.256" => "__builtin_ia32_storeupd256", + "avx.storeu.ps.256" => "__builtin_ia32_storeups256", + "avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", + "avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", + "avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", + "avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", + "avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", + "avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", + "avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", + "avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", + "avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", + "avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", + "avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", + "avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", + "avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", + "avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", + "avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256", + "avx.vtestc.pd" => "__builtin_ia32_vtestcpd", + "avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256", + "avx.vtestc.ps" => "__builtin_ia32_vtestcps", + "avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256", + "avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd", + "avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256", + "avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps", + "avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256", + "avx.vtestz.pd" => "__builtin_ia32_vtestzpd", + "avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256", + "avx.vtestz.ps" => "__builtin_ia32_vtestzps", + "avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256", + "avx.vzeroall" => "__builtin_ia32_vzeroall", + "avx.vzeroupper" => "__builtin_ia32_vzeroupper", + "avx10.mask.getexp.bf16.128" => "__builtin_ia32_vgetexpbf16128_mask", + "avx10.mask.getexp.bf16.256" => "__builtin_ia32_vgetexpbf16256_mask", + "avx10.mask.getexp.bf16.512" => "__builtin_ia32_vgetexpbf16512_mask", + "avx10.mask.getmant.bf16.128" => "__builtin_ia32_vgetmantbf16128_mask", + "avx10.mask.getmant.bf16.256" => "__builtin_ia32_vgetmantbf16256_mask", + "avx10.mask.getmant.bf16.512" => "__builtin_ia32_vgetmantbf16512_mask", + "avx10.mask.rcp.bf16.128" => "__builtin_ia32_vrcpbf16128_mask", + "avx10.mask.rcp.bf16.256" => "__builtin_ia32_vrcpbf16256_mask", + "avx10.mask.rcp.bf16.512" => "__builtin_ia32_vrcpbf16512_mask", + "avx10.mask.reduce.bf16.128" => "__builtin_ia32_vreducebf16128_mask", + "avx10.mask.reduce.bf16.256" => "__builtin_ia32_vreducebf16256_mask", + "avx10.mask.reduce.bf16.512" => "__builtin_ia32_vreducebf16512_mask", + "avx10.mask.rndscale.bf16.128" => "__builtin_ia32_vrndscalebf16_128_mask", + "avx10.mask.rndscale.bf16.256" => "__builtin_ia32_vrndscalebf16_256_mask", + "avx10.mask.rndscale.bf16.512" => "__builtin_ia32_vrndscalebf16_mask", + "avx10.mask.rsqrt.bf16.128" => "__builtin_ia32_vrsqrtbf16128_mask", + "avx10.mask.rsqrt.bf16.256" => "__builtin_ia32_vrsqrtbf16256_mask", + "avx10.mask.rsqrt.bf16.512" => "__builtin_ia32_vrsqrtbf16512_mask", + "avx10.mask.scalef.bf16.128" => "__builtin_ia32_vscalefbf16128_mask", + "avx10.mask.scalef.bf16.256" => "__builtin_ia32_vscalefbf16256_mask", + "avx10.mask.scalef.bf16.512" => "__builtin_ia32_vscalefbf16512_mask", + "avx10.mask.vcvt2ps2phx.128" => "__builtin_ia32_vcvt2ps2phx128_mask", + "avx10.mask.vcvt2ps2phx.256" => "__builtin_ia32_vcvt2ps2phx256_mask", + "avx10.mask.vcvt2ps2phx.512" => "__builtin_ia32_vcvt2ps2phx512_mask", + "avx10.mask.vcvtbiasph2bf8128" => "__builtin_ia32_vcvtbiasph2bf8_128_mask", + "avx10.mask.vcvtbiasph2bf8256" => "__builtin_ia32_vcvtbiasph2bf8_256_mask", + "avx10.mask.vcvtbiasph2bf8512" => "__builtin_ia32_vcvtbiasph2bf8_512_mask", + "avx10.mask.vcvtbiasph2bf8s128" => "__builtin_ia32_vcvtbiasph2bf8s_128_mask", + "avx10.mask.vcvtbiasph2bf8s256" => "__builtin_ia32_vcvtbiasph2bf8s_256_mask", + "avx10.mask.vcvtbiasph2bf8s512" => "__builtin_ia32_vcvtbiasph2bf8s_512_mask", + "avx10.mask.vcvtbiasph2hf8128" => "__builtin_ia32_vcvtbiasph2hf8_128_mask", + "avx10.mask.vcvtbiasph2hf8256" => "__builtin_ia32_vcvtbiasph2hf8_256_mask", + "avx10.mask.vcvtbiasph2hf8512" => "__builtin_ia32_vcvtbiasph2hf8_512_mask", + "avx10.mask.vcvtbiasph2hf8s128" => "__builtin_ia32_vcvtbiasph2hf8s_128_mask", + "avx10.mask.vcvtbiasph2hf8s256" => "__builtin_ia32_vcvtbiasph2hf8s_256_mask", + "avx10.mask.vcvtbiasph2hf8s512" => "__builtin_ia32_vcvtbiasph2hf8s_512_mask", + "avx10.mask.vcvthf82ph128" => "__builtin_ia32_vcvthf8_2ph128_mask", + "avx10.mask.vcvthf82ph256" => "__builtin_ia32_vcvthf8_2ph256_mask", + "avx10.mask.vcvthf82ph512" => "__builtin_ia32_vcvthf8_2ph512_mask", + "avx10.mask.vcvtph2bf8128" => "__builtin_ia32_vcvtph2bf8_128_mask", + "avx10.mask.vcvtph2bf8256" => "__builtin_ia32_vcvtph2bf8_256_mask", + "avx10.mask.vcvtph2bf8512" => "__builtin_ia32_vcvtph2bf8_512_mask", + "avx10.mask.vcvtph2bf8s128" => "__builtin_ia32_vcvtph2bf8s_128_mask", + "avx10.mask.vcvtph2bf8s256" => "__builtin_ia32_vcvtph2bf8s_256_mask", + "avx10.mask.vcvtph2bf8s512" => "__builtin_ia32_vcvtph2bf8s_512_mask", + "avx10.mask.vcvtph2hf8128" => "__builtin_ia32_vcvtph2hf8_128_mask", + "avx10.mask.vcvtph2hf8256" => "__builtin_ia32_vcvtph2hf8_256_mask", + "avx10.mask.vcvtph2hf8512" => "__builtin_ia32_vcvtph2hf8_512_mask", + "avx10.mask.vcvtph2hf8s128" => "__builtin_ia32_vcvtph2hf8s_128_mask", + "avx10.mask.vcvtph2hf8s256" => "__builtin_ia32_vcvtph2hf8s_256_mask", + "avx10.mask.vcvtph2hf8s512" => "__builtin_ia32_vcvtph2hf8s_512_mask", + "avx10.mask.vcvtph2ibs128" => "__builtin_ia32_vcvtph2ibs128_mask", + "avx10.mask.vcvtph2ibs256" => "__builtin_ia32_vcvtph2ibs256_mask", + "avx10.mask.vcvtph2ibs512" => "__builtin_ia32_vcvtph2ibs512_mask", + "avx10.mask.vcvtph2iubs128" => "__builtin_ia32_vcvtph2iubs128_mask", + "avx10.mask.vcvtph2iubs256" => "__builtin_ia32_vcvtph2iubs256_mask", + "avx10.mask.vcvtph2iubs512" => "__builtin_ia32_vcvtph2iubs512_mask", + "avx10.mask.vcvtps2ibs128" => "__builtin_ia32_vcvtps2ibs128_mask", + "avx10.mask.vcvtps2ibs256" => "__builtin_ia32_vcvtps2ibs256_mask", + "avx10.mask.vcvtps2ibs512" => "__builtin_ia32_vcvtps2ibs512_mask", + "avx10.mask.vcvtps2iubs128" => "__builtin_ia32_vcvtps2iubs128_mask", + "avx10.mask.vcvtps2iubs256" => "__builtin_ia32_vcvtps2iubs256_mask", + "avx10.mask.vcvtps2iubs512" => "__builtin_ia32_vcvtps2iubs512_mask", + "avx10.mask.vcvttpd2dqs.128" => "__builtin_ia32_vcvttpd2dqs128_mask", + "avx10.mask.vcvttpd2dqs.256" => "__builtin_ia32_vcvttpd2dqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttpd2dqs.round.512" => "__builtin_ia32_vcvttpd2dqs512_round_mask", + "avx10.mask.vcvttpd2qqs.128" => "__builtin_ia32_vcvttpd2qqs128_mask", + "avx10.mask.vcvttpd2qqs.256" => "__builtin_ia32_vcvttpd2qqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttpd2qqs.round.512" => "__builtin_ia32_vcvttpd2qqs512_round_mask", + "avx10.mask.vcvttpd2udqs.128" => "__builtin_ia32_vcvttpd2udqs128_mask", + "avx10.mask.vcvttpd2udqs.256" => "__builtin_ia32_vcvttpd2udqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttpd2udqs.round.512" => "__builtin_ia32_vcvttpd2udqs512_round_mask", + "avx10.mask.vcvttpd2uqqs.128" => "__builtin_ia32_vcvttpd2uqqs128_mask", + "avx10.mask.vcvttpd2uqqs.256" => "__builtin_ia32_vcvttpd2uqqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttpd2uqqs.round.512" => "__builtin_ia32_vcvttpd2uqqs512_round_mask", + "avx10.mask.vcvttph2ibs128" => "__builtin_ia32_vcvttph2ibs128_mask", + "avx10.mask.vcvttph2ibs256" => "__builtin_ia32_vcvttph2ibs256_mask", + "avx10.mask.vcvttph2ibs512" => "__builtin_ia32_vcvttph2ibs512_mask", + "avx10.mask.vcvttph2iubs128" => "__builtin_ia32_vcvttph2iubs128_mask", + "avx10.mask.vcvttph2iubs256" => "__builtin_ia32_vcvttph2iubs256_mask", + "avx10.mask.vcvttph2iubs512" => "__builtin_ia32_vcvttph2iubs512_mask", + "avx10.mask.vcvttps2dqs.128" => "__builtin_ia32_vcvttps2dqs128_mask", + "avx10.mask.vcvttps2dqs.256" => "__builtin_ia32_vcvttps2dqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttps2dqs.round.512" => "__builtin_ia32_vcvttps2dqs512_round_mask", + "avx10.mask.vcvttps2ibs128" => "__builtin_ia32_vcvttps2ibs128_mask", + "avx10.mask.vcvttps2ibs256" => "__builtin_ia32_vcvttps2ibs256_mask", + "avx10.mask.vcvttps2ibs512" => "__builtin_ia32_vcvttps2ibs512_mask", + "avx10.mask.vcvttps2iubs128" => "__builtin_ia32_vcvttps2iubs128_mask", + "avx10.mask.vcvttps2iubs256" => "__builtin_ia32_vcvttps2iubs256_mask", + "avx10.mask.vcvttps2iubs512" => "__builtin_ia32_vcvttps2iubs512_mask", + "avx10.mask.vcvttps2qqs.128" => "__builtin_ia32_vcvttps2qqs128_mask", + "avx10.mask.vcvttps2qqs.256" => "__builtin_ia32_vcvttps2qqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttps2qqs.round.512" => "__builtin_ia32_vcvttps2qqs512_round_mask", + "avx10.mask.vcvttps2udqs.128" => "__builtin_ia32_vcvttps2udqs128_mask", + "avx10.mask.vcvttps2udqs.256" => "__builtin_ia32_vcvttps2udqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttps2udqs.round.512" => "__builtin_ia32_vcvttps2udqs512_round_mask", + "avx10.mask.vcvttps2uqqs.128" => "__builtin_ia32_vcvttps2uqqs128_mask", + "avx10.mask.vcvttps2uqqs.256" => "__builtin_ia32_vcvttps2uqqs256_mask", + // [INVALID CONVERSION]: "avx10.mask.vcvttps2uqqs.round.512" => "__builtin_ia32_vcvttps2uqqs512_round_mask", + // [INVALID CONVERSION]: "avx10.mask.vminmaxpd.round" => "__builtin_ia32_vminmaxpd512_round_mask", + "avx10.mask.vminmaxpd128" => "__builtin_ia32_vminmaxpd128_mask", + "avx10.mask.vminmaxpd256" => "__builtin_ia32_vminmaxpd256_mask", + // [INVALID CONVERSION]: "avx10.mask.vminmaxph.round" => "__builtin_ia32_vminmaxph512_round_mask", + "avx10.mask.vminmaxph128" => "__builtin_ia32_vminmaxph128_mask", + "avx10.mask.vminmaxph256" => "__builtin_ia32_vminmaxph256_mask", + // [INVALID CONVERSION]: "avx10.mask.vminmaxps.round" => "__builtin_ia32_vminmaxps512_round_mask", + "avx10.mask.vminmaxps128" => "__builtin_ia32_vminmaxps128_mask", + "avx10.mask.vminmaxps256" => "__builtin_ia32_vminmaxps256_mask", + // [INVALID CONVERSION]: "avx10.mask.vminmaxsd.round" => "__builtin_ia32_vminmaxsd_round_mask", + // [INVALID CONVERSION]: "avx10.mask.vminmaxsh.round" => "__builtin_ia32_vminmaxsh_round_mask", + // [INVALID CONVERSION]: "avx10.mask.vminmaxss.round" => "__builtin_ia32_vminmaxss_round_mask", + "avx10.vaddbf16128" => "__builtin_ia32_vaddbf16128", + "avx10.vaddbf16256" => "__builtin_ia32_vaddbf16256", + "avx10.vaddbf16512" => "__builtin_ia32_vaddbf16512", + "avx10.vaddpd256" => "__builtin_ia32_vaddpd256_round", + "avx10.vaddph256" => "__builtin_ia32_vaddph256_round", + "avx10.vaddps256" => "__builtin_ia32_vaddps256_round", + "avx10.vcomisbf16eq" => "__builtin_ia32_vcomisbf16eq", + "avx10.vcomisbf16ge" => "__builtin_ia32_vcomisbf16ge", + "avx10.vcomisbf16gt" => "__builtin_ia32_vcomisbf16gt", + "avx10.vcomisbf16le" => "__builtin_ia32_vcomisbf16le", + "avx10.vcomisbf16lt" => "__builtin_ia32_vcomisbf16lt", + "avx10.vcomisbf16neq" => "__builtin_ia32_vcomisbf16neq", + "avx10.vcvt2ph2bf8128" => "__builtin_ia32_vcvt2ph2bf8_128", + "avx10.vcvt2ph2bf8256" => "__builtin_ia32_vcvt2ph2bf8_256", + "avx10.vcvt2ph2bf8512" => "__builtin_ia32_vcvt2ph2bf8_512", + "avx10.vcvt2ph2bf8s128" => "__builtin_ia32_vcvt2ph2bf8s_128", + "avx10.vcvt2ph2bf8s256" => "__builtin_ia32_vcvt2ph2bf8s_256", + "avx10.vcvt2ph2bf8s512" => "__builtin_ia32_vcvt2ph2bf8s_512", + "avx10.vcvt2ph2hf8128" => "__builtin_ia32_vcvt2ph2hf8_128", + "avx10.vcvt2ph2hf8256" => "__builtin_ia32_vcvt2ph2hf8_256", + "avx10.vcvt2ph2hf8512" => "__builtin_ia32_vcvt2ph2hf8_512", + "avx10.vcvt2ph2hf8s128" => "__builtin_ia32_vcvt2ph2hf8s_128", + "avx10.vcvt2ph2hf8s256" => "__builtin_ia32_vcvt2ph2hf8s_256", + "avx10.vcvt2ph2hf8s512" => "__builtin_ia32_vcvt2ph2hf8s_512", + "avx10.vcvtbf162ibs128" => "__builtin_ia32_vcvtbf162ibs128", + "avx10.vcvtbf162ibs256" => "__builtin_ia32_vcvtbf162ibs256", + "avx10.vcvtbf162ibs512" => "__builtin_ia32_vcvtbf162ibs512", + "avx10.vcvtbf162iubs128" => "__builtin_ia32_vcvtbf162iubs128", + "avx10.vcvtbf162iubs256" => "__builtin_ia32_vcvtbf162iubs256", + "avx10.vcvtbf162iubs512" => "__builtin_ia32_vcvtbf162iubs512", + "avx10.vcvttbf162ibs128" => "__builtin_ia32_vcvttbf162ibs128", + "avx10.vcvttbf162ibs256" => "__builtin_ia32_vcvttbf162ibs256", + "avx10.vcvttbf162ibs512" => "__builtin_ia32_vcvttbf162ibs512", + "avx10.vcvttbf162iubs128" => "__builtin_ia32_vcvttbf162iubs128", + "avx10.vcvttbf162iubs256" => "__builtin_ia32_vcvttbf162iubs256", + "avx10.vcvttbf162iubs512" => "__builtin_ia32_vcvttbf162iubs512", + "avx10.vcvttsd2sis" => "__builtin_ia32_vcvttsd2sis32", + "avx10.vcvttsd2sis64" => "__builtin_ia32_vcvttsd2sis64", + "avx10.vcvttsd2usis" => "__builtin_ia32_vcvttsd2usis32", + "avx10.vcvttsd2usis64" => "__builtin_ia32_vcvttsd2usis64", + "avx10.vcvttss2sis" => "__builtin_ia32_vcvttss2sis32", + "avx10.vcvttss2sis64" => "__builtin_ia32_vcvttss2sis64", + "avx10.vcvttss2usis" => "__builtin_ia32_vcvttss2usis32", + "avx10.vcvttss2usis64" => "__builtin_ia32_vcvttss2usis64", + "avx10.vdivbf16128" => "__builtin_ia32_vdivbf16128", + "avx10.vdivbf16256" => "__builtin_ia32_vdivbf16256", + "avx10.vdivbf16512" => "__builtin_ia32_vdivbf16512", + "avx10.vdpphps.128" => "__builtin_ia32_vdpphps128", + "avx10.vdpphps.256" => "__builtin_ia32_vdpphps256", + "avx10.vdpphps.512" => "__builtin_ia32_vdpphps512", + "avx10.vfmadd132bf16128" => "__builtin_ia32_vfmadd132bf16128", + "avx10.vfmadd132bf16256" => "__builtin_ia32_vfmadd132bf16256", + "avx10.vfmadd132bf16512" => "__builtin_ia32_vfmadd132bf16512", + "avx10.vfmadd213bf16128" => "__builtin_ia32_vfmadd213bf16128", + "avx10.vfmadd213bf16256" => "__builtin_ia32_vfmadd213bf16256", + "avx10.vfmadd231bf16128" => "__builtin_ia32_vfmadd231bf16128", + "avx10.vfmadd231bf16256" => "__builtin_ia32_vfmadd231bf16256", + "avx10.vfmadd231bf16512" => "__builtin_ia32_vfmadd231bf16512", + "avx10.vfmsub132bf16128" => "__builtin_ia32_vfmsub132bf16128", + "avx10.vfmsub132bf16256" => "__builtin_ia32_vfmsub132bf16256", + "avx10.vfmsub132bf16512" => "__builtin_ia32_vfmsub132bf16512", + "avx10.vfmsub213bf16128" => "__builtin_ia32_vfmsub213bf16128", + "avx10.vfmsub213bf16256" => "__builtin_ia32_vfmsub213bf16256", + "avx10.vfmsub213bf16512" => "__builtin_ia32_vfmsub213bf16512", + "avx10.vfmsub231bf16128" => "__builtin_ia32_vfmsub231bf16128", + "avx10.vfmsub231bf16256" => "__builtin_ia32_vfmsub231bf16256", + "avx10.vfmsub231bf16512" => "__builtin_ia32_vfmsub231bf16512", + "avx10.vfnmadd132bf16128" => "__builtin_ia32_vfnmadd132bf16128", + "avx10.vfnmadd132bf16256" => "__builtin_ia32_vfnmadd132bf16256", + "avx10.vfnmadd132bf16512" => "__builtin_ia32_vfnmadd132bf16512", + "avx10.vfnmadd213bf16128" => "__builtin_ia32_vfnmadd213bf16128", + "avx10.vfnmadd213bf16256" => "__builtin_ia32_vfnmadd213bf16256", + "avx10.vfnmadd213bf16512" => "__builtin_ia32_vfnmadd213bf16512", + "avx10.vfnmadd231bf16128" => "__builtin_ia32_vfnmadd231bf16128", + "avx10.vfnmadd231bf16256" => "__builtin_ia32_vfnmadd231bf16256", + "avx10.vfnmadd231bf16512" => "__builtin_ia32_vfnmadd231bf16512", + "avx10.vfnmsub132bf16128" => "__builtin_ia32_vfnmsub132bf16128", + "avx10.vfnmsub132bf16256" => "__builtin_ia32_vfnmsub132bf16256", + "avx10.vfnmsub132bf16512" => "__builtin_ia32_vfnmsub132bf16512", + "avx10.vfnmsub213bf16128" => "__builtin_ia32_vfnmsub213bf16128", + "avx10.vfnmsub213bf16256" => "__builtin_ia32_vfnmsub213bf16256", + "avx10.vfnmsub213bf16512" => "__builtin_ia32_vfnmsub213bf16512", + "avx10.vfnmsub231bf16128" => "__builtin_ia32_vfnmsub231bf16128", + "avx10.vfnmsub231bf16256" => "__builtin_ia32_vfnmsub231bf16256", + "avx10.vfnmsub231bf16512" => "__builtin_ia32_vfnmsub231bf16512", + "avx10.vmaxbf16128" => "__builtin_ia32_vmaxbf16128", + "avx10.vmaxbf16256" => "__builtin_ia32_vmaxbf16256", + "avx10.vmaxbf16512" => "__builtin_ia32_vmaxbf16512", + "avx10.vminbf16128" => "__builtin_ia32_vminbf16128", + "avx10.vminbf16256" => "__builtin_ia32_vminbf16256", + "avx10.vminbf16512" => "__builtin_ia32_vminbf16512", + "avx10.vminmaxbf16128" => "__builtin_ia32_vminmaxbf16128", + "avx10.vminmaxbf16256" => "__builtin_ia32_vminmaxbf16256", + "avx10.vminmaxbf16512" => "__builtin_ia32_vminmaxbf16512", + "avx10.vminmaxpd128" => "__builtin_ia32_vminmaxpd128", + "avx10.vminmaxpd256" => "__builtin_ia32_vminmaxpd256", + "avx10.vminmaxph128" => "__builtin_ia32_vminmaxph128", + "avx10.vminmaxph256" => "__builtin_ia32_vminmaxph256", + "avx10.vminmaxps128" => "__builtin_ia32_vminmaxps128", + "avx10.vminmaxps256" => "__builtin_ia32_vminmaxps256", + "avx10.vmovrsb128" => "__builtin_ia32_vmovrsb128", + "avx10.vmovrsb256" => "__builtin_ia32_vmovrsb256", + "avx10.vmovrsb512" => "__builtin_ia32_vmovrsb512", + "avx10.vmovrsd128" => "__builtin_ia32_vmovrsd128", + "avx10.vmovrsd256" => "__builtin_ia32_vmovrsd256", + "avx10.vmovrsd512" => "__builtin_ia32_vmovrsd512", + "avx10.vmovrsq128" => "__builtin_ia32_vmovrsq128", + "avx10.vmovrsq256" => "__builtin_ia32_vmovrsq256", + "avx10.vmovrsq512" => "__builtin_ia32_vmovrsq512", + "avx10.vmovrsw128" => "__builtin_ia32_vmovrsw128", + "avx10.vmovrsw256" => "__builtin_ia32_vmovrsw256", + "avx10.vmovrsw512" => "__builtin_ia32_vmovrsw512", + "avx10.vmpsadbw.512" => "__builtin_ia32_mpsadbw512", + "avx10.vmulbf16128" => "__builtin_ia32_vmulbf16128", + "avx10.vmulbf16256" => "__builtin_ia32_vmulbf16256", + "avx10.vmulbf16512" => "__builtin_ia32_vmulbf16512", + "avx10.vpdpbssd.512" => "__builtin_ia32_vpdpbssd512", + "avx10.vpdpbssds.512" => "__builtin_ia32_vpdpbssds512", + "avx10.vpdpbsud.512" => "__builtin_ia32_vpdpbsud512", + "avx10.vpdpbsuds.512" => "__builtin_ia32_vpdpbsuds512", + "avx10.vpdpbuud.512" => "__builtin_ia32_vpdpbuud512", + "avx10.vpdpbuuds.512" => "__builtin_ia32_vpdpbuuds512", + "avx10.vpdpwsud.512" => "__builtin_ia32_vpdpwsud512", + "avx10.vpdpwsuds.512" => "__builtin_ia32_vpdpwsuds512", + "avx10.vpdpwusd.512" => "__builtin_ia32_vpdpwusd512", + "avx10.vpdpwusds.512" => "__builtin_ia32_vpdpwusds512", + "avx10.vpdpwuud.512" => "__builtin_ia32_vpdpwuud512", + "avx10.vpdpwuuds.512" => "__builtin_ia32_vpdpwuuds512", + "avx10.vsubbf16128" => "__builtin_ia32_vsubbf16128", + "avx10.vsubbf16256" => "__builtin_ia32_vsubbf16256", + "avx10.vsubbf16512" => "__builtin_ia32_vsubbf16512", + "avx2.gather.d.d" => "__builtin_ia32_gatherd_d", + "avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256", + "avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd", + "avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256", + "avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps", + "avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256", + "avx2.gather.d.q" => "__builtin_ia32_gatherd_q", + "avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256", + "avx2.gather.q.d" => "__builtin_ia32_gatherq_d", + "avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256", + "avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd", + "avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256", + "avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps", + "avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256", + "avx2.gather.q.q" => "__builtin_ia32_gatherq_q", + "avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256", + "avx2.maskload.d" => "__builtin_ia32_maskloadd", + "avx2.maskload.d.256" => "__builtin_ia32_maskloadd256", + "avx2.maskload.q" => "__builtin_ia32_maskloadq", + "avx2.maskload.q.256" => "__builtin_ia32_maskloadq256", + "avx2.maskstore.d" => "__builtin_ia32_maskstored", + "avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", + "avx2.maskstore.q" => "__builtin_ia32_maskstoreq", + "avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", + "avx2.movntdqa" => "__builtin_ia32_movntdqa256", + "avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", + "avx2.pabs.b" => "__builtin_ia32_pabsb256", + "avx2.pabs.d" => "__builtin_ia32_pabsd256", + "avx2.pabs.w" => "__builtin_ia32_pabsw256", + "avx2.packssdw" => "__builtin_ia32_packssdw256", + "avx2.packsswb" => "__builtin_ia32_packsswb256", + "avx2.packusdw" => "__builtin_ia32_packusdw256", + "avx2.packuswb" => "__builtin_ia32_packuswb256", + "avx2.padds.b" => "__builtin_ia32_paddsb256", + "avx2.padds.w" => "__builtin_ia32_paddsw256", + "avx2.paddus.b" => "__builtin_ia32_paddusb256", + "avx2.paddus.w" => "__builtin_ia32_paddusw256", + "avx2.pavg.b" => "__builtin_ia32_pavgb256", + "avx2.pavg.w" => "__builtin_ia32_pavgw256", + "avx2.pblendd.128" => "__builtin_ia32_pblendd128", + "avx2.pblendd.256" => "__builtin_ia32_pblendd256", + "avx2.pblendvb" => "__builtin_ia32_pblendvb256", + "avx2.pblendw" => "__builtin_ia32_pblendw256", + "avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", + "avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", + "avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", + "avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", + "avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", + "avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", + "avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", + "avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", + "avx2.permd" => "__builtin_ia32_permvarsi256", + "avx2.permps" => "__builtin_ia32_permvarsf256", + "avx2.phadd.d" => "__builtin_ia32_phaddd256", + "avx2.phadd.sw" => "__builtin_ia32_phaddsw256", + "avx2.phadd.w" => "__builtin_ia32_phaddw256", + "avx2.phsub.d" => "__builtin_ia32_phsubd256", + "avx2.phsub.sw" => "__builtin_ia32_phsubsw256", + "avx2.phsub.w" => "__builtin_ia32_phsubw256", + "avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", + "avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", + "avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", + "avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", + "avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", + "avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", + "avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", + "avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", + "avx2.pmins.b" => "__builtin_ia32_pminsb256", + "avx2.pmins.d" => "__builtin_ia32_pminsd256", + "avx2.pmins.w" => "__builtin_ia32_pminsw256", + "avx2.pminu.b" => "__builtin_ia32_pminub256", + "avx2.pminu.d" => "__builtin_ia32_pminud256", + "avx2.pminu.w" => "__builtin_ia32_pminuw256", + "avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", + "avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", + "avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", + "avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", + "avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", + "avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", + "avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", + "avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", + "avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", + "avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", + "avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", + "avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", + "avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", + "avx2.pmul.dq" => "__builtin_ia32_pmuldq256", + "avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", + "avx2.pmulh.w" => "__builtin_ia32_pmulhw256", + "avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", + "avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", + "avx2.psad.bw" => "__builtin_ia32_psadbw256", + "avx2.pshuf.b" => "__builtin_ia32_pshufb256", + "avx2.psign.b" => "__builtin_ia32_psignb256", + "avx2.psign.d" => "__builtin_ia32_psignd256", + "avx2.psign.w" => "__builtin_ia32_psignw256", + "avx2.psll.d" => "__builtin_ia32_pslld256", + "avx2.psll.dq" => "__builtin_ia32_pslldqi256", + "avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", + "avx2.psll.q" => "__builtin_ia32_psllq256", + "avx2.psll.w" => "__builtin_ia32_psllw256", + "avx2.pslli.d" => "__builtin_ia32_pslldi256", + "avx2.pslli.q" => "__builtin_ia32_psllqi256", + "avx2.pslli.w" => "__builtin_ia32_psllwi256", + "avx2.psllv.d" => "__builtin_ia32_psllv4si", + "avx2.psllv.d.256" => "__builtin_ia32_psllv8si", + "avx2.psllv.q" => "__builtin_ia32_psllv2di", + "avx2.psllv.q.256" => "__builtin_ia32_psllv4di", + "avx2.psra.d" => "__builtin_ia32_psrad256", + "avx2.psra.w" => "__builtin_ia32_psraw256", + "avx2.psrai.d" => "__builtin_ia32_psradi256", + "avx2.psrai.w" => "__builtin_ia32_psrawi256", + "avx2.psrav.d" => "__builtin_ia32_psrav4si", + "avx2.psrav.d.256" => "__builtin_ia32_psrav8si", + "avx2.psrl.d" => "__builtin_ia32_psrld256", + "avx2.psrl.dq" => "__builtin_ia32_psrldqi256", + "avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", + "avx2.psrl.q" => "__builtin_ia32_psrlq256", + "avx2.psrl.w" => "__builtin_ia32_psrlw256", + "avx2.psrli.d" => "__builtin_ia32_psrldi256", + "avx2.psrli.q" => "__builtin_ia32_psrlqi256", + "avx2.psrli.w" => "__builtin_ia32_psrlwi256", + "avx2.psrlv.d" => "__builtin_ia32_psrlv4si", + "avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", + "avx2.psrlv.q" => "__builtin_ia32_psrlv2di", + "avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", + "avx2.psubs.b" => "__builtin_ia32_psubsb256", + "avx2.psubs.w" => "__builtin_ia32_psubsw256", + "avx2.psubus.b" => "__builtin_ia32_psubusb256", + "avx2.psubus.w" => "__builtin_ia32_psubusw256", + "avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", + "avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", + "avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", + "avx2.vextracti128" => "__builtin_ia32_extract128i256", + "avx2.vinserti128" => "__builtin_ia32_insert128i256", + "avx2.vpdpbssd.128" => "__builtin_ia32_vpdpbssd128", + "avx2.vpdpbssd.256" => "__builtin_ia32_vpdpbssd256", + "avx2.vpdpbssds.128" => "__builtin_ia32_vpdpbssds128", + "avx2.vpdpbssds.256" => "__builtin_ia32_vpdpbssds256", + "avx2.vpdpbsud.128" => "__builtin_ia32_vpdpbsud128", + "avx2.vpdpbsud.256" => "__builtin_ia32_vpdpbsud256", + "avx2.vpdpbsuds.128" => "__builtin_ia32_vpdpbsuds128", + "avx2.vpdpbsuds.256" => "__builtin_ia32_vpdpbsuds256", + "avx2.vpdpbuud.128" => "__builtin_ia32_vpdpbuud128", + "avx2.vpdpbuud.256" => "__builtin_ia32_vpdpbuud256", + "avx2.vpdpbuuds.128" => "__builtin_ia32_vpdpbuuds128", + "avx2.vpdpbuuds.256" => "__builtin_ia32_vpdpbuuds256", + "avx2.vpdpwsud.128" => "__builtin_ia32_vpdpwsud128", + "avx2.vpdpwsud.256" => "__builtin_ia32_vpdpwsud256", + "avx2.vpdpwsuds.128" => "__builtin_ia32_vpdpwsuds128", + "avx2.vpdpwsuds.256" => "__builtin_ia32_vpdpwsuds256", + "avx2.vpdpwusd.128" => "__builtin_ia32_vpdpwusd128", + "avx2.vpdpwusd.256" => "__builtin_ia32_vpdpwusd256", + "avx2.vpdpwusds.128" => "__builtin_ia32_vpdpwusds128", + "avx2.vpdpwusds.256" => "__builtin_ia32_vpdpwusds256", + "avx2.vpdpwuud.128" => "__builtin_ia32_vpdpwuud128", + "avx2.vpdpwuud.256" => "__builtin_ia32_vpdpwuud256", + "avx2.vpdpwuuds.128" => "__builtin_ia32_vpdpwuuds128", + "avx2.vpdpwuuds.256" => "__builtin_ia32_vpdpwuuds256", + "avx2.vperm2i128" => "__builtin_ia32_permti256", + "avx512.add.pd.512" => "__builtin_ia32_addpd512", + "avx512.add.ps.512" => "__builtin_ia32_addps512", + "avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128", + "avx512.broadcastmb.256" => "__builtin_ia32_broadcastmb256", + "avx512.broadcastmb.512" => "__builtin_ia32_broadcastmb512", + "avx512.broadcastmw.128" => "__builtin_ia32_broadcastmw128", + "avx512.broadcastmw.256" => "__builtin_ia32_broadcastmw256", + "avx512.broadcastmw.512" => "__builtin_ia32_broadcastmw512", + "avx512.conflict.d.128" => "__builtin_ia32_vpconflictsi_128", + "avx512.conflict.d.256" => "__builtin_ia32_vpconflictsi_256", + "avx512.conflict.d.512" => "__builtin_ia32_vpconflictsi_512", + "avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", + "avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", + "avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", + "avx512.cvtb2mask.128" => "__builtin_ia32_cvtb2mask128", + "avx512.cvtb2mask.256" => "__builtin_ia32_cvtb2mask256", + "avx512.cvtb2mask.512" => "__builtin_ia32_cvtb2mask512", + "avx512.cvtd2mask.128" => "__builtin_ia32_cvtd2mask128", + "avx512.cvtd2mask.256" => "__builtin_ia32_cvtd2mask256", + "avx512.cvtd2mask.512" => "__builtin_ia32_cvtd2mask512", + "avx512.cvtmask2b.128" => "__builtin_ia32_cvtmask2b128", + "avx512.cvtmask2b.256" => "__builtin_ia32_cvtmask2b256", + "avx512.cvtmask2b.512" => "__builtin_ia32_cvtmask2b512", + "avx512.cvtmask2d.128" => "__builtin_ia32_cvtmask2d128", + "avx512.cvtmask2d.256" => "__builtin_ia32_cvtmask2d256", + "avx512.cvtmask2d.512" => "__builtin_ia32_cvtmask2d512", + "avx512.cvtmask2q.128" => "__builtin_ia32_cvtmask2q128", + "avx512.cvtmask2q.256" => "__builtin_ia32_cvtmask2q256", + "avx512.cvtmask2q.512" => "__builtin_ia32_cvtmask2q512", + "avx512.cvtmask2w.128" => "__builtin_ia32_cvtmask2w128", + "avx512.cvtmask2w.256" => "__builtin_ia32_cvtmask2w256", + "avx512.cvtmask2w.512" => "__builtin_ia32_cvtmask2w512", + "avx512.cvtq2mask.128" => "__builtin_ia32_cvtq2mask128", + "avx512.cvtq2mask.256" => "__builtin_ia32_cvtq2mask256", + "avx512.cvtq2mask.512" => "__builtin_ia32_cvtq2mask512", + "avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", + "avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", + "avx512.cvtsi2sd32" => "__builtin_ia32_cvtsi2sd32", + "avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", + "avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", + "avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", + "avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", + "avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", + "avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", + "avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", + "avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", + // [DUPLICATE]: "avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", + "avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", + // [DUPLICATE]: "avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", + "avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", + "avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", + "avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", + // [DUPLICATE]: "avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", + "avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", + // [DUPLICATE]: "avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", + "avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", + // [DUPLICATE]: "avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd32", + "avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", + // [DUPLICATE]: "avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", + "avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", + // [DUPLICATE]: "avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", + "avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", + // [DUPLICATE]: "avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", + "avx512.cvtw2mask.128" => "__builtin_ia32_cvtw2mask128", + "avx512.cvtw2mask.256" => "__builtin_ia32_cvtw2mask256", + "avx512.cvtw2mask.512" => "__builtin_ia32_cvtw2mask512", + "avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", + "avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", + "avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", + "avx512.div.pd.512" => "__builtin_ia32_divpd512", + "avx512.div.ps.512" => "__builtin_ia32_divps512", + "avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask", + "avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask", + "avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", + "avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", + "avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", + "avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", + "avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", + "avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", + "avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", + "avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", + "avx512.gather3div2.df" => "__builtin_ia32_gather3div2df", + "avx512.gather3div2.di" => "__builtin_ia32_gather3div2di", + "avx512.gather3div4.df" => "__builtin_ia32_gather3div4df", + "avx512.gather3div4.di" => "__builtin_ia32_gather3div4di", + "avx512.gather3div4.sf" => "__builtin_ia32_gather3div4sf", + "avx512.gather3div4.si" => "__builtin_ia32_gather3div4si", + "avx512.gather3div8.sf" => "__builtin_ia32_gather3div8sf", + "avx512.gather3div8.si" => "__builtin_ia32_gather3div8si", + "avx512.gather3siv2.df" => "__builtin_ia32_gather3siv2df", + "avx512.gather3siv2.di" => "__builtin_ia32_gather3siv2di", + "avx512.gather3siv4.df" => "__builtin_ia32_gather3siv4df", + "avx512.gather3siv4.di" => "__builtin_ia32_gather3siv4di", + "avx512.gather3siv4.sf" => "__builtin_ia32_gather3siv4sf", + "avx512.gather3siv4.si" => "__builtin_ia32_gather3siv4si", + "avx512.gather3siv8.sf" => "__builtin_ia32_gather3siv8sf", + "avx512.gather3siv8.si" => "__builtin_ia32_gather3siv8si", + "avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", + "avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", + "avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", + "avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", + "avx512.kand.w" => "__builtin_ia32_kandhi", + "avx512.kandn.w" => "__builtin_ia32_kandnhi", + "avx512.knot.w" => "__builtin_ia32_knothi", + "avx512.kor.w" => "__builtin_ia32_korhi", + "avx512.kortestc.w" => "__builtin_ia32_kortestchi", + "avx512.kortestz.w" => "__builtin_ia32_kortestzhi", + "avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", + "avx512.kunpck.dq" => "__builtin_ia32_kunpckdi", + "avx512.kunpck.wd" => "__builtin_ia32_kunpcksi", + "avx512.kxnor.w" => "__builtin_ia32_kxnorhi", + "avx512.kxor.w" => "__builtin_ia32_kxorhi", + "avx512.mask.add.pd.128" => "__builtin_ia32_addpd128_mask", + "avx512.mask.add.pd.256" => "__builtin_ia32_addpd256_mask", + "avx512.mask.add.pd.512" => "__builtin_ia32_addpd512_mask", + "avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask", + "avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask", + "avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask", + // [INVALID CONVERSION]: "avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", + "avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask", + "avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask", + "avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask", + "avx512.mask.and.ps.128" => "__builtin_ia32_andps128_mask", + "avx512.mask.and.ps.256" => "__builtin_ia32_andps256_mask", + "avx512.mask.and.ps.512" => "__builtin_ia32_andps512_mask", + "avx512.mask.andn.pd.128" => "__builtin_ia32_andnpd128_mask", + "avx512.mask.andn.pd.256" => "__builtin_ia32_andnpd256_mask", + "avx512.mask.andn.pd.512" => "__builtin_ia32_andnpd512_mask", + "avx512.mask.andn.ps.128" => "__builtin_ia32_andnps128_mask", + "avx512.mask.andn.ps.256" => "__builtin_ia32_andnps256_mask", + "avx512.mask.andn.ps.512" => "__builtin_ia32_andnps512_mask", + "avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", + "avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", + "avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", + "avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", + "avx512.mask.broadcastf32x2.256" => "__builtin_ia32_broadcastf32x2_256_mask", + "avx512.mask.broadcastf32x2.512" => "__builtin_ia32_broadcastf32x2_512_mask", + "avx512.mask.broadcastf32x4.256" => "__builtin_ia32_broadcastf32x4_256_mask", + "avx512.mask.broadcastf32x4.512" => "__builtin_ia32_broadcastf32x4_512", + "avx512.mask.broadcastf32x8.512" => "__builtin_ia32_broadcastf32x8_512_mask", + "avx512.mask.broadcastf64x2.256" => "__builtin_ia32_broadcastf64x2_256_mask", + "avx512.mask.broadcastf64x2.512" => "__builtin_ia32_broadcastf64x2_512_mask", + "avx512.mask.broadcastf64x4.512" => "__builtin_ia32_broadcastf64x4_512", + "avx512.mask.broadcasti32x2.128" => "__builtin_ia32_broadcasti32x2_128_mask", + "avx512.mask.broadcasti32x2.256" => "__builtin_ia32_broadcasti32x2_256_mask", + "avx512.mask.broadcasti32x2.512" => "__builtin_ia32_broadcasti32x2_512_mask", + "avx512.mask.broadcasti32x4.256" => "__builtin_ia32_broadcasti32x4_256_mask", + "avx512.mask.broadcasti32x4.512" => "__builtin_ia32_broadcasti32x4_512", + "avx512.mask.broadcasti32x8.512" => "__builtin_ia32_broadcasti32x8_512_mask", + "avx512.mask.broadcasti64x2.256" => "__builtin_ia32_broadcasti64x2_256_mask", + "avx512.mask.broadcasti64x2.512" => "__builtin_ia32_broadcasti64x2_512_mask", + "avx512.mask.broadcasti64x4.512" => "__builtin_ia32_broadcasti64x4_512", + "avx512.mask.cmp.pd.128" => "__builtin_ia32_cmppd128_mask", + "avx512.mask.cmp.pd.256" => "__builtin_ia32_cmppd256_mask", + "avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", + "avx512.mask.cmp.ps.128" => "__builtin_ia32_cmpps128_mask", + "avx512.mask.cmp.ps.256" => "__builtin_ia32_cmpps256_mask", + "avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", + "avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", + "avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", + "avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask", + "avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask", + "avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask", + "avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask", + "avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask", + "avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask", + "avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask", + "avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask", + "avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask", + "avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask", + "avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask", + "avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask", + "avx512.mask.compress.store.d.128" => "__builtin_ia32_compressstoresi128_mask", + "avx512.mask.compress.store.d.256" => "__builtin_ia32_compressstoresi256_mask", + "avx512.mask.compress.store.d.512" => "__builtin_ia32_compressstoresi512_mask", + "avx512.mask.compress.store.pd.128" => "__builtin_ia32_compressstoredf128_mask", + "avx512.mask.compress.store.pd.256" => "__builtin_ia32_compressstoredf256_mask", + "avx512.mask.compress.store.pd.512" => "__builtin_ia32_compressstoredf512_mask", + "avx512.mask.compress.store.ps.128" => "__builtin_ia32_compressstoresf128_mask", + "avx512.mask.compress.store.ps.256" => "__builtin_ia32_compressstoresf256_mask", + "avx512.mask.compress.store.ps.512" => "__builtin_ia32_compressstoresf512_mask", + "avx512.mask.compress.store.q.128" => "__builtin_ia32_compressstoredi128_mask", + "avx512.mask.compress.store.q.256" => "__builtin_ia32_compressstoredi256_mask", + "avx512.mask.compress.store.q.512" => "__builtin_ia32_compressstoredi512_mask", + "avx512.mask.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask", + "avx512.mask.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask", + "avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", + "avx512.mask.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask", + "avx512.mask.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask", + "avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", + "avx512.mask.cvtdq2pd.128" => "__builtin_ia32_cvtdq2pd128_mask", + "avx512.mask.cvtdq2pd.256" => "__builtin_ia32_cvtdq2pd256_mask", + "avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", + "avx512.mask.cvtdq2ps.128" => "__builtin_ia32_cvtdq2ps128_mask", + "avx512.mask.cvtdq2ps.256" => "__builtin_ia32_cvtdq2ps256_mask", + "avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", + "avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", + "avx512.mask.cvtpd2dq.256" => "__builtin_ia32_cvtpd2dq256_mask", + "avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", + "avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", + "avx512.mask.cvtpd2ps.256" => "__builtin_ia32_cvtpd2ps256_mask", + "avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", + "avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask", + "avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask", + "avx512.mask.cvtpd2qq.512" => "__builtin_ia32_cvtpd2qq512_mask", + "avx512.mask.cvtpd2udq.128" => "__builtin_ia32_cvtpd2udq128_mask", + "avx512.mask.cvtpd2udq.256" => "__builtin_ia32_cvtpd2udq256_mask", + "avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", + "avx512.mask.cvtpd2uqq.128" => "__builtin_ia32_cvtpd2uqq128_mask", + "avx512.mask.cvtpd2uqq.256" => "__builtin_ia32_cvtpd2uqq256_mask", + "avx512.mask.cvtpd2uqq.512" => "__builtin_ia32_cvtpd2uqq512_mask", + "avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask", + "avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask", + "avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", + "avx512.mask.cvtps2pd.128" => "__builtin_ia32_cvtps2pd128_mask", + "avx512.mask.cvtps2pd.256" => "__builtin_ia32_cvtps2pd256_mask", + "avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask", + "avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask", + "avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask", + "avx512.mask.cvtps2qq.512" => "__builtin_ia32_cvtps2qq512_mask", + "avx512.mask.cvtps2udq.128" => "__builtin_ia32_cvtps2udq128_mask", + "avx512.mask.cvtps2udq.256" => "__builtin_ia32_cvtps2udq256_mask", + "avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", + "avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask", + "avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask", + "avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask", + "avx512.mask.cvtqq2pd.128" => "__builtin_ia32_cvtqq2pd128_mask", + "avx512.mask.cvtqq2pd.256" => "__builtin_ia32_cvtqq2pd256_mask", + "avx512.mask.cvtqq2pd.512" => "__builtin_ia32_cvtqq2pd512_mask", + "avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask", + "avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask", + "avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask", + // [INVALID CONVERSION]: "avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", + // [INVALID CONVERSION]: "avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", + "avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask", + "avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask", + "avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", + "avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask", + "avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask", + "avx512.mask.cvttpd2qq.512" => "__builtin_ia32_cvttpd2qq512_mask", + "avx512.mask.cvttpd2udq.128" => "__builtin_ia32_cvttpd2udq128_mask", + "avx512.mask.cvttpd2udq.256" => "__builtin_ia32_cvttpd2udq256_mask", + "avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", + "avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask", + "avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask", + "avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask", + "avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask", + "avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask", + "avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", + "avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask", + "avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask", + "avx512.mask.cvttps2qq.512" => "__builtin_ia32_cvttps2qq512_mask", + "avx512.mask.cvttps2udq.128" => "__builtin_ia32_cvttps2udq128_mask", + "avx512.mask.cvttps2udq.256" => "__builtin_ia32_cvttps2udq256_mask", + "avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", + "avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", + "avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", + "avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", + "avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask", + "avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask", + "avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", + "avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask", + "avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask", + "avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", + "avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask", + "avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask", + "avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask", + "avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", + "avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask", + "avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask", + "avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask", + "avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask", + "avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask", + "avx512.mask.div.pd.128" => "__builtin_ia32_divpd_mask", + "avx512.mask.div.pd.256" => "__builtin_ia32_divpd256_mask", + "avx512.mask.div.pd.512" => "__builtin_ia32_divpd512_mask", + "avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask", + "avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask", + "avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask", + // [INVALID CONVERSION]: "avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", + "avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask", + "avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask", + "avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask", + "avx512.mask.expand.load.d.128" => "__builtin_ia32_expandloadsi128_mask", + "avx512.mask.expand.load.d.256" => "__builtin_ia32_expandloadsi256_mask", + "avx512.mask.expand.load.d.512" => "__builtin_ia32_expandloadsi512_mask", + "avx512.mask.expand.load.pd.128" => "__builtin_ia32_expandloaddf128_mask", + "avx512.mask.expand.load.pd.256" => "__builtin_ia32_expandloaddf256_mask", + "avx512.mask.expand.load.pd.512" => "__builtin_ia32_expandloaddf512_mask", + "avx512.mask.expand.load.ps.128" => "__builtin_ia32_expandloadsf128_mask", + "avx512.mask.expand.load.ps.256" => "__builtin_ia32_expandloadsf256_mask", + "avx512.mask.expand.load.ps.512" => "__builtin_ia32_expandloadsf512_mask", + "avx512.mask.expand.load.q.128" => "__builtin_ia32_expandloaddi128_mask", + "avx512.mask.expand.load.q.256" => "__builtin_ia32_expandloaddi256_mask", + "avx512.mask.expand.load.q.512" => "__builtin_ia32_expandloaddi512_mask", + "avx512.mask.expand.pd.128" => "__builtin_ia32_expanddf128_mask", + "avx512.mask.expand.pd.256" => "__builtin_ia32_expanddf256_mask", + "avx512.mask.expand.pd.512" => "__builtin_ia32_expanddf512_mask", + "avx512.mask.expand.ps.128" => "__builtin_ia32_expandsf128_mask", + "avx512.mask.expand.ps.256" => "__builtin_ia32_expandsf256_mask", + "avx512.mask.expand.ps.512" => "__builtin_ia32_expandsf512_mask", + "avx512.mask.expand.q.128" => "__builtin_ia32_expanddi128_mask", + "avx512.mask.expand.q.256" => "__builtin_ia32_expanddi256_mask", + "avx512.mask.expand.q.512" => "__builtin_ia32_expanddi512_mask", + "avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask", + "avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask", + "avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask", + "avx512.mask.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_mask", + "avx512.mask.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_mask", + "avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask", + "avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask", + "avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask", + "avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask", + "avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask", + "avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask", + "avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask", + "avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask", + "avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask", + "avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask", + "avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask", + "avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", + "avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask", + "avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask", + "avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask", + "avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask", + "avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask", + // [INVALID CONVERSION]: "avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask", + // [INVALID CONVERSION]: "avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask", + "avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask", + "avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask", + "avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask", + "avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask", + "avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask", + "avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", + // [INVALID CONVERSION]: "avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", + "avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask", + "avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask", + "avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask", + "avx512.mask.insertf64x2.256" => "__builtin_ia32_insertf64x2_256_mask", + "avx512.mask.insertf64x2.512" => "__builtin_ia32_insertf64x2_512_mask", + "avx512.mask.insertf64x4.512" => "__builtin_ia32_insertf64x4_mask", + "avx512.mask.inserti32x4.256" => "__builtin_ia32_inserti32x4_256_mask", + "avx512.mask.inserti32x4.512" => "__builtin_ia32_inserti32x4_mask", + "avx512.mask.inserti32x8.512" => "__builtin_ia32_inserti32x8_mask", + "avx512.mask.inserti64x2.256" => "__builtin_ia32_inserti64x2_256_mask", + "avx512.mask.inserti64x2.512" => "__builtin_ia32_inserti64x2_512_mask", + "avx512.mask.inserti64x4.512" => "__builtin_ia32_inserti64x4_mask", + "avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", + "avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", + "avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", + "avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", + "avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", + "avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", + "avx512.mask.max.pd.128" => "__builtin_ia32_maxpd_mask", + "avx512.mask.max.pd.256" => "__builtin_ia32_maxpd256_mask", + "avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", + "avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask", + "avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask", + "avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", + // [INVALID CONVERSION]: "avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", + "avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask", + "avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask", + "avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", + "avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask", + "avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask", + "avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", + // [INVALID CONVERSION]: "avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", + "avx512.mask.move.sd" => "__builtin_ia32_movsd_mask", + "avx512.mask.move.ss" => "__builtin_ia32_movss_mask", + "avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask", + "avx512.mask.mul.pd.256" => "__builtin_ia32_mulpd256_mask", + "avx512.mask.mul.pd.512" => "__builtin_ia32_mulpd512_mask", + "avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask", + "avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask", + "avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask", + // [INVALID CONVERSION]: "avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", + "avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask", + "avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask", + "avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask", + "avx512.mask.or.ps.128" => "__builtin_ia32_orps128_mask", + "avx512.mask.or.ps.256" => "__builtin_ia32_orps256_mask", + "avx512.mask.or.ps.512" => "__builtin_ia32_orps512_mask", + "avx512.mask.pabs.b.128" => "__builtin_ia32_pabsb128_mask", + "avx512.mask.pabs.b.256" => "__builtin_ia32_pabsb256_mask", + "avx512.mask.pabs.b.512" => "__builtin_ia32_pabsb512_mask", + "avx512.mask.pabs.d.128" => "__builtin_ia32_pabsd128_mask", + "avx512.mask.pabs.d.256" => "__builtin_ia32_pabsd256_mask", + "avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", + "avx512.mask.pabs.q.128" => "__builtin_ia32_pabsq128_mask", + "avx512.mask.pabs.q.256" => "__builtin_ia32_pabsq256_mask", + "avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", + "avx512.mask.pabs.w.128" => "__builtin_ia32_pabsw128_mask", + "avx512.mask.pabs.w.256" => "__builtin_ia32_pabsw256_mask", + "avx512.mask.pabs.w.512" => "__builtin_ia32_pabsw512_mask", + "avx512.mask.packssdw.128" => "__builtin_ia32_packssdw128_mask", + "avx512.mask.packssdw.256" => "__builtin_ia32_packssdw256_mask", + "avx512.mask.packssdw.512" => "__builtin_ia32_packssdw512_mask", + "avx512.mask.packsswb.128" => "__builtin_ia32_packsswb128_mask", + "avx512.mask.packsswb.256" => "__builtin_ia32_packsswb256_mask", + "avx512.mask.packsswb.512" => "__builtin_ia32_packsswb512_mask", + "avx512.mask.packusdw.128" => "__builtin_ia32_packusdw128_mask", + "avx512.mask.packusdw.256" => "__builtin_ia32_packusdw256_mask", + "avx512.mask.packusdw.512" => "__builtin_ia32_packusdw512_mask", + "avx512.mask.packuswb.128" => "__builtin_ia32_packuswb128_mask", + "avx512.mask.packuswb.256" => "__builtin_ia32_packuswb256_mask", + "avx512.mask.packuswb.512" => "__builtin_ia32_packuswb512_mask", + "avx512.mask.padd.b.128" => "__builtin_ia32_paddb128_mask", + "avx512.mask.padd.b.256" => "__builtin_ia32_paddb256_mask", + "avx512.mask.padd.b.512" => "__builtin_ia32_paddb512_mask", + "avx512.mask.padd.d.128" => "__builtin_ia32_paddd128_mask", + "avx512.mask.padd.d.256" => "__builtin_ia32_paddd256_mask", + "avx512.mask.padd.d.512" => "__builtin_ia32_paddd512_mask", + "avx512.mask.padd.q.128" => "__builtin_ia32_paddq128_mask", + "avx512.mask.padd.q.256" => "__builtin_ia32_paddq256_mask", + "avx512.mask.padd.q.512" => "__builtin_ia32_paddq512_mask", + "avx512.mask.padd.w.128" => "__builtin_ia32_paddw128_mask", + "avx512.mask.padd.w.256" => "__builtin_ia32_paddw256_mask", + "avx512.mask.padd.w.512" => "__builtin_ia32_paddw512_mask", + "avx512.mask.padds.b.128" => "__builtin_ia32_paddsb128_mask", + "avx512.mask.padds.b.256" => "__builtin_ia32_paddsb256_mask", + "avx512.mask.padds.b.512" => "__builtin_ia32_paddsb512_mask", + "avx512.mask.padds.w.128" => "__builtin_ia32_paddsw128_mask", + "avx512.mask.padds.w.256" => "__builtin_ia32_paddsw256_mask", + "avx512.mask.padds.w.512" => "__builtin_ia32_paddsw512_mask", + "avx512.mask.paddus.b.128" => "__builtin_ia32_paddusb128_mask", + "avx512.mask.paddus.b.256" => "__builtin_ia32_paddusb256_mask", + "avx512.mask.paddus.b.512" => "__builtin_ia32_paddusb512_mask", + "avx512.mask.paddus.w.128" => "__builtin_ia32_paddusw128_mask", + "avx512.mask.paddus.w.256" => "__builtin_ia32_paddusw256_mask", + "avx512.mask.paddus.w.512" => "__builtin_ia32_paddusw512_mask", + "avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", + "avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", + "avx512.mask.pavg.b.128" => "__builtin_ia32_pavgb128_mask", + "avx512.mask.pavg.b.256" => "__builtin_ia32_pavgb256_mask", + "avx512.mask.pavg.b.512" => "__builtin_ia32_pavgb512_mask", + "avx512.mask.pavg.w.128" => "__builtin_ia32_pavgw128_mask", + "avx512.mask.pavg.w.256" => "__builtin_ia32_pavgw256_mask", + "avx512.mask.pavg.w.512" => "__builtin_ia32_pavgw512_mask", + "avx512.mask.pbroadcast.b.gpr.128" => "__builtin_ia32_pbroadcastb128_gpr_mask", + "avx512.mask.pbroadcast.b.gpr.256" => "__builtin_ia32_pbroadcastb256_gpr_mask", + "avx512.mask.pbroadcast.b.gpr.512" => "__builtin_ia32_pbroadcastb512_gpr_mask", + "avx512.mask.pbroadcast.d.gpr.128" => "__builtin_ia32_pbroadcastd128_gpr_mask", + "avx512.mask.pbroadcast.d.gpr.256" => "__builtin_ia32_pbroadcastd256_gpr_mask", + "avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", + "avx512.mask.pbroadcast.q.gpr.128" => "__builtin_ia32_pbroadcastq128_gpr_mask", + "avx512.mask.pbroadcast.q.gpr.256" => "__builtin_ia32_pbroadcastq256_gpr_mask", + "avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", + "avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", + "avx512.mask.pbroadcast.w.gpr.128" => "__builtin_ia32_pbroadcastw128_gpr_mask", + "avx512.mask.pbroadcast.w.gpr.256" => "__builtin_ia32_pbroadcastw256_gpr_mask", + "avx512.mask.pbroadcast.w.gpr.512" => "__builtin_ia32_pbroadcastw512_gpr_mask", + "avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", + "avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", + "avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", + "avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", + "avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", + "avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", + "avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", + "avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", + "avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", + "avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", + "avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", + "avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", + "avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", + "avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", + "avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", + "avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", + "avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", + "avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", + "avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", + "avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", + "avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", + "avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", + "avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", + "avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", + "avx512.mask.permvar.df.256" => "__builtin_ia32_permvardf256_mask", + "avx512.mask.permvar.df.512" => "__builtin_ia32_permvardf512_mask", + "avx512.mask.permvar.di.256" => "__builtin_ia32_permvardi256_mask", + "avx512.mask.permvar.di.512" => "__builtin_ia32_permvardi512_mask", + "avx512.mask.permvar.hi.128" => "__builtin_ia32_permvarhi128_mask", + "avx512.mask.permvar.hi.256" => "__builtin_ia32_permvarhi256_mask", + "avx512.mask.permvar.hi.512" => "__builtin_ia32_permvarhi512_mask", + "avx512.mask.permvar.qi.128" => "__builtin_ia32_permvarqi128_mask", + "avx512.mask.permvar.qi.256" => "__builtin_ia32_permvarqi256_mask", + "avx512.mask.permvar.qi.512" => "__builtin_ia32_permvarqi512_mask", + "avx512.mask.permvar.sf.256" => "__builtin_ia32_permvarsf256_mask", + "avx512.mask.permvar.sf.512" => "__builtin_ia32_permvarsf512_mask", + "avx512.mask.permvar.si.256" => "__builtin_ia32_permvarsi256_mask", + "avx512.mask.permvar.si.512" => "__builtin_ia32_permvarsi512_mask", + "avx512.mask.pmaddubs.w.128" => "__builtin_ia32_pmaddubsw128_mask", + "avx512.mask.pmaddubs.w.256" => "__builtin_ia32_pmaddubsw256_mask", + "avx512.mask.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512_mask", + "avx512.mask.pmaddw.d.128" => "__builtin_ia32_pmaddwd128_mask", + "avx512.mask.pmaddw.d.256" => "__builtin_ia32_pmaddwd256_mask", + "avx512.mask.pmaddw.d.512" => "__builtin_ia32_pmaddwd512_mask", + "avx512.mask.pmaxs.b.128" => "__builtin_ia32_pmaxsb128_mask", + "avx512.mask.pmaxs.b.256" => "__builtin_ia32_pmaxsb256_mask", + "avx512.mask.pmaxs.b.512" => "__builtin_ia32_pmaxsb512_mask", + "avx512.mask.pmaxs.d.128" => "__builtin_ia32_pmaxsd128_mask", + "avx512.mask.pmaxs.d.256" => "__builtin_ia32_pmaxsd256_mask", + "avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", + "avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask", + "avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask", + "avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", + "avx512.mask.pmaxs.w.128" => "__builtin_ia32_pmaxsw128_mask", + "avx512.mask.pmaxs.w.256" => "__builtin_ia32_pmaxsw256_mask", + "avx512.mask.pmaxs.w.512" => "__builtin_ia32_pmaxsw512_mask", + "avx512.mask.pmaxu.b.128" => "__builtin_ia32_pmaxub128_mask", + "avx512.mask.pmaxu.b.256" => "__builtin_ia32_pmaxub256_mask", + "avx512.mask.pmaxu.b.512" => "__builtin_ia32_pmaxub512_mask", + "avx512.mask.pmaxu.d.128" => "__builtin_ia32_pmaxud128_mask", + "avx512.mask.pmaxu.d.256" => "__builtin_ia32_pmaxud256_mask", + "avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", + "avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask", + "avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask", + "avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", + "avx512.mask.pmaxu.w.128" => "__builtin_ia32_pmaxuw128_mask", + "avx512.mask.pmaxu.w.256" => "__builtin_ia32_pmaxuw256_mask", + "avx512.mask.pmaxu.w.512" => "__builtin_ia32_pmaxuw512_mask", + "avx512.mask.pmins.b.128" => "__builtin_ia32_pminsb128_mask", + "avx512.mask.pmins.b.256" => "__builtin_ia32_pminsb256_mask", + "avx512.mask.pmins.b.512" => "__builtin_ia32_pminsb512_mask", + "avx512.mask.pmins.d.128" => "__builtin_ia32_pminsd128_mask", + "avx512.mask.pmins.d.256" => "__builtin_ia32_pminsd256_mask", + "avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", + "avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask", + "avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask", + "avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", + "avx512.mask.pmins.w.128" => "__builtin_ia32_pminsw128_mask", + "avx512.mask.pmins.w.256" => "__builtin_ia32_pminsw256_mask", + "avx512.mask.pmins.w.512" => "__builtin_ia32_pminsw512_mask", + "avx512.mask.pminu.b.128" => "__builtin_ia32_pminub128_mask", + "avx512.mask.pminu.b.256" => "__builtin_ia32_pminub256_mask", + "avx512.mask.pminu.b.512" => "__builtin_ia32_pminub512_mask", + "avx512.mask.pminu.d.128" => "__builtin_ia32_pminud128_mask", + "avx512.mask.pminu.d.256" => "__builtin_ia32_pminud256_mask", + "avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", + "avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask", + "avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask", + "avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", + "avx512.mask.pminu.w.128" => "__builtin_ia32_pminuw128_mask", + "avx512.mask.pminu.w.256" => "__builtin_ia32_pminuw256_mask", + "avx512.mask.pminu.w.512" => "__builtin_ia32_pminuw512_mask", + "avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", + "avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", + "avx512.mask.pmov.db.512" => "__builtin_ia32_pmovdb512_mask", + "avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", + "avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask", + "avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask", + "avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask", + "avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask", + "avx512.mask.pmov.dw.512" => "__builtin_ia32_pmovdw512_mask", + "avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask", + "avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask", + "avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask", + "avx512.mask.pmov.qb.128" => "__builtin_ia32_pmovqb128_mask", + "avx512.mask.pmov.qb.256" => "__builtin_ia32_pmovqb256_mask", + "avx512.mask.pmov.qb.512" => "__builtin_ia32_pmovqb512_mask", + "avx512.mask.pmov.qb.mem.128" => "__builtin_ia32_pmovqb128mem_mask", + "avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask", + "avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask", + "avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask", + "avx512.mask.pmov.qd.256" => "__builtin_ia32_pmovqd256_mask", + "avx512.mask.pmov.qd.512" => "__builtin_ia32_pmovqd512_mask", + "avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask", + "avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask", + "avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask", + "avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask", + "avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask", + "avx512.mask.pmov.qw.512" => "__builtin_ia32_pmovqw512_mask", + "avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask", + "avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask", + "avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask", + "avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask", + "avx512.mask.pmov.wb.256" => "__builtin_ia32_pmovwb256_mask", + "avx512.mask.pmov.wb.512" => "__builtin_ia32_pmovwb512_mask", + "avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask", + "avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask", + "avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask", + "avx512.mask.pmovs.db.128" => "__builtin_ia32_pmovsdb128_mask", + "avx512.mask.pmovs.db.256" => "__builtin_ia32_pmovsdb256_mask", + "avx512.mask.pmovs.db.512" => "__builtin_ia32_pmovsdb512_mask", + "avx512.mask.pmovs.db.mem.128" => "__builtin_ia32_pmovsdb128mem_mask", + "avx512.mask.pmovs.db.mem.256" => "__builtin_ia32_pmovsdb256mem_mask", + "avx512.mask.pmovs.db.mem.512" => "__builtin_ia32_pmovsdb512mem_mask", + "avx512.mask.pmovs.dw.128" => "__builtin_ia32_pmovsdw128_mask", + "avx512.mask.pmovs.dw.256" => "__builtin_ia32_pmovsdw256_mask", + "avx512.mask.pmovs.dw.512" => "__builtin_ia32_pmovsdw512_mask", + "avx512.mask.pmovs.dw.mem.128" => "__builtin_ia32_pmovsdw128mem_mask", + "avx512.mask.pmovs.dw.mem.256" => "__builtin_ia32_pmovsdw256mem_mask", + "avx512.mask.pmovs.dw.mem.512" => "__builtin_ia32_pmovsdw512mem_mask", + "avx512.mask.pmovs.qb.128" => "__builtin_ia32_pmovsqb128_mask", + "avx512.mask.pmovs.qb.256" => "__builtin_ia32_pmovsqb256_mask", + "avx512.mask.pmovs.qb.512" => "__builtin_ia32_pmovsqb512_mask", + "avx512.mask.pmovs.qb.mem.128" => "__builtin_ia32_pmovsqb128mem_mask", + "avx512.mask.pmovs.qb.mem.256" => "__builtin_ia32_pmovsqb256mem_mask", + "avx512.mask.pmovs.qb.mem.512" => "__builtin_ia32_pmovsqb512mem_mask", + "avx512.mask.pmovs.qd.128" => "__builtin_ia32_pmovsqd128_mask", + "avx512.mask.pmovs.qd.256" => "__builtin_ia32_pmovsqd256_mask", + "avx512.mask.pmovs.qd.512" => "__builtin_ia32_pmovsqd512_mask", + "avx512.mask.pmovs.qd.mem.128" => "__builtin_ia32_pmovsqd128mem_mask", + "avx512.mask.pmovs.qd.mem.256" => "__builtin_ia32_pmovsqd256mem_mask", + "avx512.mask.pmovs.qd.mem.512" => "__builtin_ia32_pmovsqd512mem_mask", + "avx512.mask.pmovs.qw.128" => "__builtin_ia32_pmovsqw128_mask", + "avx512.mask.pmovs.qw.256" => "__builtin_ia32_pmovsqw256_mask", + "avx512.mask.pmovs.qw.512" => "__builtin_ia32_pmovsqw512_mask", + "avx512.mask.pmovs.qw.mem.128" => "__builtin_ia32_pmovsqw128mem_mask", + "avx512.mask.pmovs.qw.mem.256" => "__builtin_ia32_pmovsqw256mem_mask", + "avx512.mask.pmovs.qw.mem.512" => "__builtin_ia32_pmovsqw512mem_mask", + "avx512.mask.pmovs.wb.128" => "__builtin_ia32_pmovswb128_mask", + "avx512.mask.pmovs.wb.256" => "__builtin_ia32_pmovswb256_mask", + "avx512.mask.pmovs.wb.512" => "__builtin_ia32_pmovswb512_mask", + "avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask", + "avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask", + "avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask", + "avx512.mask.pmovsxb.d.128" => "__builtin_ia32_pmovsxbd128_mask", + "avx512.mask.pmovsxb.d.256" => "__builtin_ia32_pmovsxbd256_mask", + "avx512.mask.pmovsxb.d.512" => "__builtin_ia32_pmovsxbd512_mask", + "avx512.mask.pmovsxb.q.128" => "__builtin_ia32_pmovsxbq128_mask", + "avx512.mask.pmovsxb.q.256" => "__builtin_ia32_pmovsxbq256_mask", + "avx512.mask.pmovsxb.q.512" => "__builtin_ia32_pmovsxbq512_mask", + "avx512.mask.pmovsxb.w.128" => "__builtin_ia32_pmovsxbw128_mask", + "avx512.mask.pmovsxb.w.256" => "__builtin_ia32_pmovsxbw256_mask", + "avx512.mask.pmovsxb.w.512" => "__builtin_ia32_pmovsxbw512_mask", + "avx512.mask.pmovsxd.q.128" => "__builtin_ia32_pmovsxdq128_mask", + "avx512.mask.pmovsxd.q.256" => "__builtin_ia32_pmovsxdq256_mask", + "avx512.mask.pmovsxd.q.512" => "__builtin_ia32_pmovsxdq512_mask", + "avx512.mask.pmovsxw.d.128" => "__builtin_ia32_pmovsxwd128_mask", + "avx512.mask.pmovsxw.d.256" => "__builtin_ia32_pmovsxwd256_mask", + "avx512.mask.pmovsxw.d.512" => "__builtin_ia32_pmovsxwd512_mask", + "avx512.mask.pmovsxw.q.128" => "__builtin_ia32_pmovsxwq128_mask", + "avx512.mask.pmovsxw.q.256" => "__builtin_ia32_pmovsxwq256_mask", + "avx512.mask.pmovsxw.q.512" => "__builtin_ia32_pmovsxwq512_mask", + "avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask", + "avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask", + "avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask", + "avx512.mask.pmovus.db.mem.128" => "__builtin_ia32_pmovusdb128mem_mask", + "avx512.mask.pmovus.db.mem.256" => "__builtin_ia32_pmovusdb256mem_mask", + "avx512.mask.pmovus.db.mem.512" => "__builtin_ia32_pmovusdb512mem_mask", + "avx512.mask.pmovus.dw.128" => "__builtin_ia32_pmovusdw128_mask", + "avx512.mask.pmovus.dw.256" => "__builtin_ia32_pmovusdw256_mask", + "avx512.mask.pmovus.dw.512" => "__builtin_ia32_pmovusdw512_mask", + "avx512.mask.pmovus.dw.mem.128" => "__builtin_ia32_pmovusdw128mem_mask", + "avx512.mask.pmovus.dw.mem.256" => "__builtin_ia32_pmovusdw256mem_mask", + "avx512.mask.pmovus.dw.mem.512" => "__builtin_ia32_pmovusdw512mem_mask", + "avx512.mask.pmovus.qb.128" => "__builtin_ia32_pmovusqb128_mask", + "avx512.mask.pmovus.qb.256" => "__builtin_ia32_pmovusqb256_mask", + "avx512.mask.pmovus.qb.512" => "__builtin_ia32_pmovusqb512_mask", + "avx512.mask.pmovus.qb.mem.128" => "__builtin_ia32_pmovusqb128mem_mask", + "avx512.mask.pmovus.qb.mem.256" => "__builtin_ia32_pmovusqb256mem_mask", + "avx512.mask.pmovus.qb.mem.512" => "__builtin_ia32_pmovusqb512mem_mask", + "avx512.mask.pmovus.qd.128" => "__builtin_ia32_pmovusqd128_mask", + "avx512.mask.pmovus.qd.256" => "__builtin_ia32_pmovusqd256_mask", + "avx512.mask.pmovus.qd.512" => "__builtin_ia32_pmovusqd512_mask", + "avx512.mask.pmovus.qd.mem.128" => "__builtin_ia32_pmovusqd128mem_mask", + "avx512.mask.pmovus.qd.mem.256" => "__builtin_ia32_pmovusqd256mem_mask", + "avx512.mask.pmovus.qd.mem.512" => "__builtin_ia32_pmovusqd512mem_mask", + "avx512.mask.pmovus.qw.128" => "__builtin_ia32_pmovusqw128_mask", + "avx512.mask.pmovus.qw.256" => "__builtin_ia32_pmovusqw256_mask", + "avx512.mask.pmovus.qw.512" => "__builtin_ia32_pmovusqw512_mask", + "avx512.mask.pmovus.qw.mem.128" => "__builtin_ia32_pmovusqw128mem_mask", + "avx512.mask.pmovus.qw.mem.256" => "__builtin_ia32_pmovusqw256mem_mask", + "avx512.mask.pmovus.qw.mem.512" => "__builtin_ia32_pmovusqw512mem_mask", + "avx512.mask.pmovus.wb.128" => "__builtin_ia32_pmovuswb128_mask", + "avx512.mask.pmovus.wb.256" => "__builtin_ia32_pmovuswb256_mask", + "avx512.mask.pmovus.wb.512" => "__builtin_ia32_pmovuswb512_mask", + "avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", + "avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", + "avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", + "avx512.mask.pmovzxb.d.128" => "__builtin_ia32_pmovzxbd128_mask", + "avx512.mask.pmovzxb.d.256" => "__builtin_ia32_pmovzxbd256_mask", + "avx512.mask.pmovzxb.d.512" => "__builtin_ia32_pmovzxbd512_mask", + "avx512.mask.pmovzxb.q.128" => "__builtin_ia32_pmovzxbq128_mask", + "avx512.mask.pmovzxb.q.256" => "__builtin_ia32_pmovzxbq256_mask", + "avx512.mask.pmovzxb.q.512" => "__builtin_ia32_pmovzxbq512_mask", + "avx512.mask.pmovzxb.w.128" => "__builtin_ia32_pmovzxbw128_mask", + "avx512.mask.pmovzxb.w.256" => "__builtin_ia32_pmovzxbw256_mask", + "avx512.mask.pmovzxb.w.512" => "__builtin_ia32_pmovzxbw512_mask", + "avx512.mask.pmovzxd.q.128" => "__builtin_ia32_pmovzxdq128_mask", + "avx512.mask.pmovzxd.q.256" => "__builtin_ia32_pmovzxdq256_mask", + "avx512.mask.pmovzxd.q.512" => "__builtin_ia32_pmovzxdq512_mask", + "avx512.mask.pmovzxw.d.128" => "__builtin_ia32_pmovzxwd128_mask", + "avx512.mask.pmovzxw.d.256" => "__builtin_ia32_pmovzxwd256_mask", + "avx512.mask.pmovzxw.d.512" => "__builtin_ia32_pmovzxwd512_mask", + "avx512.mask.pmovzxw.q.128" => "__builtin_ia32_pmovzxwq128_mask", + "avx512.mask.pmovzxw.q.256" => "__builtin_ia32_pmovzxwq256_mask", + "avx512.mask.pmovzxw.q.512" => "__builtin_ia32_pmovzxwq512_mask", + "avx512.mask.pmul.dq.128" => "__builtin_ia32_pmuldq128_mask", + "avx512.mask.pmul.dq.256" => "__builtin_ia32_pmuldq256_mask", + "avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", + "avx512.mask.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128_mask", + "avx512.mask.pmul.hr.sw.256" => "__builtin_ia32_pmulhrsw256_mask", + "avx512.mask.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask", + "avx512.mask.pmulh.w.128" => "__builtin_ia32_pmulhw128_mask", + "avx512.mask.pmulh.w.256" => "__builtin_ia32_pmulhw256_mask", + "avx512.mask.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask", + "avx512.mask.pmulhu.w.128" => "__builtin_ia32_pmulhuw128_mask", + "avx512.mask.pmulhu.w.256" => "__builtin_ia32_pmulhuw256_mask", + "avx512.mask.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask", + "avx512.mask.pmull.d.128" => "__builtin_ia32_pmulld128_mask", + "avx512.mask.pmull.d.256" => "__builtin_ia32_pmulld256_mask", + "avx512.mask.pmull.d.512" => "__builtin_ia32_pmulld512_mask", + "avx512.mask.pmull.q.128" => "__builtin_ia32_pmullq128_mask", + "avx512.mask.pmull.q.256" => "__builtin_ia32_pmullq256_mask", + "avx512.mask.pmull.q.512" => "__builtin_ia32_pmullq512_mask", + "avx512.mask.pmull.w.128" => "__builtin_ia32_pmullw128_mask", + "avx512.mask.pmull.w.256" => "__builtin_ia32_pmullw256_mask", + "avx512.mask.pmull.w.512" => "__builtin_ia32_pmullw512_mask", + "avx512.mask.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask", + "avx512.mask.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask", + "avx512.mask.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask", + "avx512.mask.pmulu.dq.128" => "__builtin_ia32_pmuludq128_mask", + "avx512.mask.pmulu.dq.256" => "__builtin_ia32_pmuludq256_mask", + "avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", + "avx512.mask.prol.d.128" => "__builtin_ia32_prold128_mask", + "avx512.mask.prol.d.256" => "__builtin_ia32_prold256_mask", + "avx512.mask.prol.d.512" => "__builtin_ia32_prold512_mask", + "avx512.mask.prol.q.128" => "__builtin_ia32_prolq128_mask", + "avx512.mask.prol.q.256" => "__builtin_ia32_prolq256_mask", + "avx512.mask.prol.q.512" => "__builtin_ia32_prolq512_mask", + "avx512.mask.prolv.d.128" => "__builtin_ia32_prolvd128_mask", + "avx512.mask.prolv.d.256" => "__builtin_ia32_prolvd256_mask", + "avx512.mask.prolv.d.512" => "__builtin_ia32_prolvd512_mask", + "avx512.mask.prolv.q.128" => "__builtin_ia32_prolvq128_mask", + "avx512.mask.prolv.q.256" => "__builtin_ia32_prolvq256_mask", + "avx512.mask.prolv.q.512" => "__builtin_ia32_prolvq512_mask", + "avx512.mask.pror.d.128" => "__builtin_ia32_prord128_mask", + "avx512.mask.pror.d.256" => "__builtin_ia32_prord256_mask", + "avx512.mask.pror.d.512" => "__builtin_ia32_prord512_mask", + "avx512.mask.pror.q.128" => "__builtin_ia32_prorq128_mask", + "avx512.mask.pror.q.256" => "__builtin_ia32_prorq256_mask", + "avx512.mask.pror.q.512" => "__builtin_ia32_prorq512_mask", + "avx512.mask.prorv.d.128" => "__builtin_ia32_prorvd128_mask", + "avx512.mask.prorv.d.256" => "__builtin_ia32_prorvd256_mask", + "avx512.mask.prorv.d.512" => "__builtin_ia32_prorvd512_mask", + "avx512.mask.prorv.q.128" => "__builtin_ia32_prorvq128_mask", + "avx512.mask.prorv.q.256" => "__builtin_ia32_prorvq256_mask", + "avx512.mask.prorv.q.512" => "__builtin_ia32_prorvq512_mask", + "avx512.mask.pshuf.b.128" => "__builtin_ia32_pshufb128_mask", + "avx512.mask.pshuf.b.256" => "__builtin_ia32_pshufb256_mask", + "avx512.mask.pshuf.b.512" => "__builtin_ia32_pshufb512_mask", + "avx512.mask.psll.d" => "__builtin_ia32_pslld512_mask", + "avx512.mask.psll.d.128" => "__builtin_ia32_pslld128_mask", + "avx512.mask.psll.d.256" => "__builtin_ia32_pslld256_mask", + "avx512.mask.psll.di.128" => "__builtin_ia32_pslldi128_mask", + "avx512.mask.psll.di.256" => "__builtin_ia32_pslldi256_mask", + "avx512.mask.psll.di.512" => "__builtin_ia32_pslldi512_mask", + "avx512.mask.psll.q" => "__builtin_ia32_psllq512_mask", + "avx512.mask.psll.q.128" => "__builtin_ia32_psllq128_mask", + "avx512.mask.psll.q.256" => "__builtin_ia32_psllq256_mask", + "avx512.mask.psll.qi.128" => "__builtin_ia32_psllqi128_mask", + "avx512.mask.psll.qi.256" => "__builtin_ia32_psllqi256_mask", + "avx512.mask.psll.qi.512" => "__builtin_ia32_psllqi512_mask", + "avx512.mask.psll.w.128" => "__builtin_ia32_psllw128_mask", + "avx512.mask.psll.w.256" => "__builtin_ia32_psllw256_mask", + "avx512.mask.psll.w.512" => "__builtin_ia32_psllw512_mask", + "avx512.mask.psll.wi.128" => "__builtin_ia32_psllwi128_mask", + "avx512.mask.psll.wi.256" => "__builtin_ia32_psllwi256_mask", + "avx512.mask.psll.wi.512" => "__builtin_ia32_psllwi512_mask", + "avx512.mask.psllv.d" => "__builtin_ia32_psllv16si_mask", + "avx512.mask.psllv.q" => "__builtin_ia32_psllv8di_mask", + "avx512.mask.psllv16.hi" => "__builtin_ia32_psllv16hi_mask", + "avx512.mask.psllv2.di" => "__builtin_ia32_psllv2di_mask", + "avx512.mask.psllv32hi" => "__builtin_ia32_psllv32hi_mask", + "avx512.mask.psllv4.di" => "__builtin_ia32_psllv4di_mask", + "avx512.mask.psllv4.si" => "__builtin_ia32_psllv4si_mask", + "avx512.mask.psllv8.hi" => "__builtin_ia32_psllv8hi_mask", + "avx512.mask.psllv8.si" => "__builtin_ia32_psllv8si_mask", + "avx512.mask.psra.d" => "__builtin_ia32_psrad512_mask", + "avx512.mask.psra.d.128" => "__builtin_ia32_psrad128_mask", + "avx512.mask.psra.d.256" => "__builtin_ia32_psrad256_mask", + "avx512.mask.psra.di.128" => "__builtin_ia32_psradi128_mask", + "avx512.mask.psra.di.256" => "__builtin_ia32_psradi256_mask", + "avx512.mask.psra.di.512" => "__builtin_ia32_psradi512_mask", + "avx512.mask.psra.q" => "__builtin_ia32_psraq512_mask", + "avx512.mask.psra.q.128" => "__builtin_ia32_psraq128_mask", + "avx512.mask.psra.q.256" => "__builtin_ia32_psraq256_mask", + "avx512.mask.psra.qi.128" => "__builtin_ia32_psraqi128_mask", + "avx512.mask.psra.qi.256" => "__builtin_ia32_psraqi256_mask", + "avx512.mask.psra.qi.512" => "__builtin_ia32_psraqi512_mask", + "avx512.mask.psra.w.128" => "__builtin_ia32_psraw128_mask", + "avx512.mask.psra.w.256" => "__builtin_ia32_psraw256_mask", + "avx512.mask.psra.w.512" => "__builtin_ia32_psraw512_mask", + "avx512.mask.psra.wi.128" => "__builtin_ia32_psrawi128_mask", + "avx512.mask.psra.wi.256" => "__builtin_ia32_psrawi256_mask", + "avx512.mask.psra.wi.512" => "__builtin_ia32_psrawi512_mask", + "avx512.mask.psrav.d" => "__builtin_ia32_psrav16si_mask", + "avx512.mask.psrav.q" => "__builtin_ia32_psrav8di_mask", + "avx512.mask.psrav.q.128" => "__builtin_ia32_psravq128_mask", + "avx512.mask.psrav.q.256" => "__builtin_ia32_psravq256_mask", + "avx512.mask.psrav16.hi" => "__builtin_ia32_psrav16hi_mask", + "avx512.mask.psrav32.hi" => "__builtin_ia32_psrav32hi_mask", + "avx512.mask.psrav4.si" => "__builtin_ia32_psrav4si_mask", + "avx512.mask.psrav8.hi" => "__builtin_ia32_psrav8hi_mask", + "avx512.mask.psrav8.si" => "__builtin_ia32_psrav8si_mask", + "avx512.mask.psrl.d" => "__builtin_ia32_psrld512_mask", + "avx512.mask.psrl.d.128" => "__builtin_ia32_psrld128_mask", + "avx512.mask.psrl.d.256" => "__builtin_ia32_psrld256_mask", + "avx512.mask.psrl.di.128" => "__builtin_ia32_psrldi128_mask", + "avx512.mask.psrl.di.256" => "__builtin_ia32_psrldi256_mask", + "avx512.mask.psrl.di.512" => "__builtin_ia32_psrldi512_mask", + "avx512.mask.psrl.q" => "__builtin_ia32_psrlq512_mask", + "avx512.mask.psrl.q.128" => "__builtin_ia32_psrlq128_mask", + "avx512.mask.psrl.q.256" => "__builtin_ia32_psrlq256_mask", + "avx512.mask.psrl.qi.128" => "__builtin_ia32_psrlqi128_mask", + "avx512.mask.psrl.qi.256" => "__builtin_ia32_psrlqi256_mask", + "avx512.mask.psrl.qi.512" => "__builtin_ia32_psrlqi512_mask", + "avx512.mask.psrl.w.128" => "__builtin_ia32_psrlw128_mask", + "avx512.mask.psrl.w.256" => "__builtin_ia32_psrlw256_mask", + "avx512.mask.psrl.w.512" => "__builtin_ia32_psrlw512_mask", + "avx512.mask.psrl.wi.128" => "__builtin_ia32_psrlwi128_mask", + "avx512.mask.psrl.wi.256" => "__builtin_ia32_psrlwi256_mask", + "avx512.mask.psrl.wi.512" => "__builtin_ia32_psrlwi512_mask", + "avx512.mask.psrlv.d" => "__builtin_ia32_psrlv16si_mask", + "avx512.mask.psrlv.q" => "__builtin_ia32_psrlv8di_mask", + "avx512.mask.psrlv16.hi" => "__builtin_ia32_psrlv16hi_mask", + "avx512.mask.psrlv2.di" => "__builtin_ia32_psrlv2di_mask", + "avx512.mask.psrlv32hi" => "__builtin_ia32_psrlv32hi_mask", + "avx512.mask.psrlv4.di" => "__builtin_ia32_psrlv4di_mask", + "avx512.mask.psrlv4.si" => "__builtin_ia32_psrlv4si_mask", + "avx512.mask.psrlv8.hi" => "__builtin_ia32_psrlv8hi_mask", + "avx512.mask.psrlv8.si" => "__builtin_ia32_psrlv8si_mask", + "avx512.mask.psub.b.128" => "__builtin_ia32_psubb128_mask", + "avx512.mask.psub.b.256" => "__builtin_ia32_psubb256_mask", + "avx512.mask.psub.b.512" => "__builtin_ia32_psubb512_mask", + "avx512.mask.psub.d.128" => "__builtin_ia32_psubd128_mask", + "avx512.mask.psub.d.256" => "__builtin_ia32_psubd256_mask", + "avx512.mask.psub.d.512" => "__builtin_ia32_psubd512_mask", + "avx512.mask.psub.q.128" => "__builtin_ia32_psubq128_mask", + "avx512.mask.psub.q.256" => "__builtin_ia32_psubq256_mask", + "avx512.mask.psub.q.512" => "__builtin_ia32_psubq512_mask", + "avx512.mask.psub.w.128" => "__builtin_ia32_psubw128_mask", + "avx512.mask.psub.w.256" => "__builtin_ia32_psubw256_mask", + "avx512.mask.psub.w.512" => "__builtin_ia32_psubw512_mask", + "avx512.mask.psubs.b.128" => "__builtin_ia32_psubsb128_mask", + "avx512.mask.psubs.b.256" => "__builtin_ia32_psubsb256_mask", + "avx512.mask.psubs.b.512" => "__builtin_ia32_psubsb512_mask", + "avx512.mask.psubs.w.128" => "__builtin_ia32_psubsw128_mask", + "avx512.mask.psubs.w.256" => "__builtin_ia32_psubsw256_mask", + "avx512.mask.psubs.w.512" => "__builtin_ia32_psubsw512_mask", + "avx512.mask.psubus.b.128" => "__builtin_ia32_psubusb128_mask", + "avx512.mask.psubus.b.256" => "__builtin_ia32_psubusb256_mask", + "avx512.mask.psubus.b.512" => "__builtin_ia32_psubusb512_mask", + "avx512.mask.psubus.w.128" => "__builtin_ia32_psubusw128_mask", + "avx512.mask.psubus.w.256" => "__builtin_ia32_psubusw256_mask", + "avx512.mask.psubus.w.512" => "__builtin_ia32_psubusw512_mask", + "avx512.mask.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask", + "avx512.mask.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask", + "avx512.mask.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask", + "avx512.mask.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask", + "avx512.mask.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask", + "avx512.mask.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask", + "avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", + "avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", + "avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", + "avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask", + "avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask", + "avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask", + "avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask", + "avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask", + // [INVALID CONVERSION]: "avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask", + // [INVALID CONVERSION]: "avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask", + "avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask", + "avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask", + "avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask", + "avx512.mask.reduce.ps.128" => "__builtin_ia32_reduceps128_mask", + "avx512.mask.reduce.ps.256" => "__builtin_ia32_reduceps256_mask", + "avx512.mask.reduce.ps.512" => "__builtin_ia32_reduceps512_mask", + "avx512.mask.reduce.sd" => "__builtin_ia32_reducesd_mask", + "avx512.mask.reduce.ss" => "__builtin_ia32_reducess_mask", + "avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask", + "avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask", + "avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", + "avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask", + "avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask", + "avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", + // [INVALID CONVERSION]: "avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask", + "avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask", + "avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask", + "avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask", + "avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask", + "avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask", + "avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", + // [INVALID CONVERSION]: "avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", + "avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask", + "avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask", + "avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask", + "avx512.mask.shuf.f64x2.256" => "__builtin_ia32_shuf_f64x2_256_mask", + "avx512.mask.shuf.i32x4" => "__builtin_ia32_shuf_i32x4_mask", + "avx512.mask.shuf.i32x4.256" => "__builtin_ia32_shuf_i32x4_256_mask", + "avx512.mask.shuf.i64x2" => "__builtin_ia32_shuf_i64x2_mask", + "avx512.mask.shuf.i64x2.256" => "__builtin_ia32_shuf_i64x2_256_mask", + "avx512.mask.shuf.pd.128" => "__builtin_ia32_shufpd128_mask", + "avx512.mask.shuf.pd.256" => "__builtin_ia32_shufpd256_mask", + "avx512.mask.shuf.pd.512" => "__builtin_ia32_shufpd512_mask", + "avx512.mask.shuf.ps.128" => "__builtin_ia32_shufps128_mask", + "avx512.mask.shuf.ps.256" => "__builtin_ia32_shufps256_mask", + "avx512.mask.shuf.ps.512" => "__builtin_ia32_shufps512_mask", + "avx512.mask.sqrt.pd.128" => "__builtin_ia32_sqrtpd128_mask", + "avx512.mask.sqrt.pd.256" => "__builtin_ia32_sqrtpd256_mask", + "avx512.mask.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", + "avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask", + "avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask", + "avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", + // [INVALID CONVERSION]: "avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask", + "avx512.mask.store.ss" => "__builtin_ia32_storess_mask", + "avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", + "avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", + "avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", + "avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", + "avx512.mask.sub.pd.128" => "__builtin_ia32_subpd128_mask", + "avx512.mask.sub.pd.256" => "__builtin_ia32_subpd256_mask", + "avx512.mask.sub.pd.512" => "__builtin_ia32_subpd512_mask", + "avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask", + "avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask", + "avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask", + // [INVALID CONVERSION]: "avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", + // [INVALID CONVERSION]: "avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", + "avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask", + "avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask", + "avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", + "avx512.mask.valign.q.128" => "__builtin_ia32_alignq128_mask", + "avx512.mask.valign.q.256" => "__builtin_ia32_alignq256_mask", + "avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", + "avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask", + "avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask", + "avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", + "avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", + "avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", + "avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", + "avx512.mask.vextractf32x4.256" => "__builtin_ia32_extractf32x4_256_mask", + "avx512.mask.vextractf32x4.512" => "__builtin_ia32_extractf32x4_mask", + "avx512.mask.vextractf32x8.512" => "__builtin_ia32_extractf32x8_mask", + "avx512.mask.vextractf64x2.256" => "__builtin_ia32_extractf64x2_256_mask", + "avx512.mask.vextractf64x2.512" => "__builtin_ia32_extractf64x2_512_mask", + "avx512.mask.vextractf64x4.512" => "__builtin_ia32_extractf64x4_mask", + "avx512.mask.vextracti32x4.256" => "__builtin_ia32_extracti32x4_256_mask", + "avx512.mask.vextracti32x4.512" => "__builtin_ia32_extracti32x4_mask", + "avx512.mask.vextracti32x8.512" => "__builtin_ia32_extracti32x8_mask", + "avx512.mask.vextracti64x2.256" => "__builtin_ia32_extracti64x2_256_mask", + "avx512.mask.vextracti64x2.512" => "__builtin_ia32_extracti64x2_512_mask", + "avx512.mask.vextracti64x4.512" => "__builtin_ia32_extracti64x4_mask", + "avx512.mask.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask", + "avx512.mask.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask", + "avx512.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "avx512.mask.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask", + "avx512.mask.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask", + "avx512.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "avx512.mask.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask", + "avx512.mask.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask", + "avx512.mask.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask", + "avx512.mask.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask", + "avx512.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", + "avx512.mask.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask", + "avx512.mask.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask", + "avx512.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", + "avx512.mask.vfnmadd.pd.128" => "__builtin_ia32_vfnmaddpd128_mask", + "avx512.mask.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256_mask", + "avx512.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", + "avx512.mask.vfnmadd.ps.128" => "__builtin_ia32_vfnmaddps128_mask", + "avx512.mask.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256_mask", + "avx512.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", + "avx512.mask.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask", + "avx512.mask.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask", + "avx512.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", + "avx512.mask.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask", + "avx512.mask.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask", + "avx512.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", + "avx512.mask.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask", + "avx512.mask.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask", + "avx512.mask.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask", + "avx512.mask.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128_mask", + "avx512.mask.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256_mask", + "avx512.mask.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512_mask", + "avx512.mask.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask", + "avx512.mask.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask", + "avx512.mask.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask", + "avx512.mask.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask", + "avx512.mask.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask", + "avx512.mask.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask", + "avx512.mask.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask", + "avx512.mask.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask", + "avx512.mask.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask", + "avx512.mask.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128_mask", + "avx512.mask.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256_mask", + "avx512.mask.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512_mask", + "avx512.mask.vpermilvar.pd.128" => "__builtin_ia32_vpermilvarpd_mask", + "avx512.mask.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256_mask", + "avx512.mask.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask", + "avx512.mask.vpermilvar.ps.128" => "__builtin_ia32_vpermilvarps_mask", + "avx512.mask.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256_mask", + "avx512.mask.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask", + "avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", + "avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", + "avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", + "avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", + "avx512.mask.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_mask", + "avx512.mask.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_mask", + "avx512.mask.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_mask", + "avx512.mask.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask", + "avx512.mask.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask", + "avx512.mask.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask", + "avx512.mask.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_mask", + "avx512.mask.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_mask", + "avx512.mask.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", + "avx512.mask.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_mask", + "avx512.mask.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_mask", + "avx512.mask.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_mask", + "avx512.mask.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_mask", + "avx512.mask.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_mask", + "avx512.mask.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_mask", + "avx512.mask.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask", + "avx512.mask.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask", + "avx512.mask.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask", + "avx512.mask.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask", + "avx512.mask.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask", + "avx512.mask.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask", + "avx512.mask.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_mask", + "avx512.mask.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask", + "avx512.mask.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask", + "avx512.mask.xor.pd.128" => "__builtin_ia32_xorpd128_mask", + "avx512.mask.xor.pd.256" => "__builtin_ia32_xorpd256_mask", + "avx512.mask.xor.pd.512" => "__builtin_ia32_xorpd512_mask", + "avx512.mask.xor.ps.128" => "__builtin_ia32_xorps128_mask", + "avx512.mask.xor.ps.256" => "__builtin_ia32_xorps256_mask", + "avx512.mask.xor.ps.512" => "__builtin_ia32_xorps512_mask", + "avx512.mask3.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask3", + "avx512.mask3.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask3", + "avx512.mask3.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask3", + "avx512.mask3.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask3", + "avx512.mask3.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask3", + "avx512.mask3.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask3", + "avx512.mask3.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask3", + "avx512.mask3.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask3", + "avx512.mask3.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask3", + "avx512.mask3.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask3", + "avx512.mask3.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask3", + "avx512.mask3.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask3", + "avx512.mask3.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask3", + "avx512.mask3.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask3", + "avx512.mask3.vfmsub.pd.128" => "__builtin_ia32_vfmsubpd128_mask3", + "avx512.mask3.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256_mask3", + "avx512.mask3.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask3", + "avx512.mask3.vfmsub.ps.128" => "__builtin_ia32_vfmsubps128_mask3", + "avx512.mask3.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256_mask3", + "avx512.mask3.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask3", + "avx512.mask3.vfmsubadd.pd.128" => "__builtin_ia32_vfmsubaddpd128_mask3", + "avx512.mask3.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256_mask3", + "avx512.mask3.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask3", + "avx512.mask3.vfmsubadd.ps.128" => "__builtin_ia32_vfmsubaddps128_mask3", + "avx512.mask3.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256_mask3", + "avx512.mask3.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask3", + "avx512.mask3.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask3", + "avx512.mask3.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask3", + "avx512.mask3.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask3", + "avx512.mask3.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask3", + "avx512.mask3.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask3", + "avx512.mask3.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask3", + "avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", + "avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", + "avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", + "avx512.maskz.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_maskz", + "avx512.maskz.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_maskz", + "avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz", + "avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz", + "avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz", + "avx512.maskz.pternlog.d.128" => "__builtin_ia32_pternlogd128_maskz", + "avx512.maskz.pternlog.d.256" => "__builtin_ia32_pternlogd256_maskz", + "avx512.maskz.pternlog.d.512" => "__builtin_ia32_pternlogd512_maskz", + "avx512.maskz.pternlog.q.128" => "__builtin_ia32_pternlogq128_maskz", + "avx512.maskz.pternlog.q.256" => "__builtin_ia32_pternlogq256_maskz", + "avx512.maskz.pternlog.q.512" => "__builtin_ia32_pternlogq512_maskz", + "avx512.maskz.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_maskz", + "avx512.maskz.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_maskz", + "avx512.maskz.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_maskz", + "avx512.maskz.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_maskz", + "avx512.maskz.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_maskz", + "avx512.maskz.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_maskz", + "avx512.maskz.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_maskz", + "avx512.maskz.vfmadd.ss" => "__builtin_ia32_vfmaddss3_maskz", + "avx512.maskz.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_maskz", + "avx512.maskz.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_maskz", + "avx512.maskz.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_maskz", + "avx512.maskz.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_maskz", + "avx512.maskz.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_maskz", + "avx512.maskz.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_maskz", + "avx512.maskz.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_maskz", + "avx512.maskz.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_maskz", + "avx512.maskz.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_maskz", + "avx512.maskz.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_maskz", + "avx512.maskz.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_maskz", + "avx512.maskz.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_maskz", + "avx512.maskz.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_maskz", + "avx512.maskz.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_maskz", + "avx512.maskz.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_maskz", + "avx512.maskz.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_maskz", + "avx512.maskz.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_maskz", + "avx512.maskz.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_maskz", + "avx512.maskz.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_maskz", + "avx512.maskz.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_maskz", + "avx512.maskz.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_maskz", + "avx512.maskz.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_maskz", + "avx512.maskz.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_maskz", + "avx512.maskz.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_maskz", + "avx512.maskz.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_maskz", + "avx512.maskz.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_maskz", + "avx512.maskz.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_maskz", + "avx512.maskz.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_maskz", + "avx512.maskz.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_maskz", + "avx512.maskz.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_maskz", + "avx512.max.pd.512" => "__builtin_ia32_maxpd512", + "avx512.max.ps.512" => "__builtin_ia32_maxps512", + "avx512.min.pd.512" => "__builtin_ia32_minpd512", + "avx512.min.ps.512" => "__builtin_ia32_minps512", + "avx512.movntdqa" => "__builtin_ia32_movntdqa512", + "avx512.mul.pd.512" => "__builtin_ia32_mulpd512", + "avx512.mul.ps.512" => "__builtin_ia32_mulps512", + "avx512.packssdw.512" => "__builtin_ia32_packssdw512", + "avx512.packsswb.512" => "__builtin_ia32_packsswb512", + "avx512.packusdw.512" => "__builtin_ia32_packusdw512", + "avx512.packuswb.512" => "__builtin_ia32_packuswb512", + "avx512.pavg.b.512" => "__builtin_ia32_pavgb512", + "avx512.pavg.w.512" => "__builtin_ia32_pavgw512", + "avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", + "avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", + "avx512.permvar.df.256" => "__builtin_ia32_permvardf256", + "avx512.permvar.df.512" => "__builtin_ia32_permvardf512", + "avx512.permvar.di.256" => "__builtin_ia32_permvardi256", + "avx512.permvar.di.512" => "__builtin_ia32_permvardi512", + "avx512.permvar.hi.128" => "__builtin_ia32_permvarhi128", + "avx512.permvar.hi.256" => "__builtin_ia32_permvarhi256", + "avx512.permvar.hi.512" => "__builtin_ia32_permvarhi512", + "avx512.permvar.qi.128" => "__builtin_ia32_permvarqi128", + "avx512.permvar.qi.256" => "__builtin_ia32_permvarqi256", + "avx512.permvar.qi.512" => "__builtin_ia32_permvarqi512", + "avx512.permvar.sf.512" => "__builtin_ia32_permvarsf512", + "avx512.permvar.si.512" => "__builtin_ia32_permvarsi512", + "avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512", + "avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512", + "avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", + "avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", + "avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", + "avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", + "avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", + "avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512", + "avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512", + "avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512", + "avx512.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128", + "avx512.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256", + "avx512.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512", + "avx512.psad.bw.512" => "__builtin_ia32_psadbw512", + "avx512.pshuf.b.512" => "__builtin_ia32_pshufb512", + "avx512.psll.d.512" => "__builtin_ia32_pslld512", + "avx512.psll.dq" => "__builtin_ia32_pslldqi512", + "avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", + "avx512.psll.q.512" => "__builtin_ia32_psllq512", + "avx512.psll.w.512" => "__builtin_ia32_psllw512", + "avx512.pslli.d.512" => "__builtin_ia32_pslldi512", + "avx512.pslli.q.512" => "__builtin_ia32_psllqi512", + "avx512.pslli.w.512" => "__builtin_ia32_psllwi512", + "avx512.psllv.d.512" => "__builtin_ia32_psllv16si", + "avx512.psllv.q.512" => "__builtin_ia32_psllv8di", + "avx512.psllv.w.128" => "__builtin_ia32_psllv8hi", + "avx512.psllv.w.256" => "__builtin_ia32_psllv16hi", + "avx512.psllv.w.512" => "__builtin_ia32_psllv32hi", + "avx512.psra.d.512" => "__builtin_ia32_psrad512", + "avx512.psra.q.128" => "__builtin_ia32_psraq128", + "avx512.psra.q.256" => "__builtin_ia32_psraq256", + "avx512.psra.q.512" => "__builtin_ia32_psraq512", + "avx512.psra.w.512" => "__builtin_ia32_psraw512", + "avx512.psrai.d.512" => "__builtin_ia32_psradi512", + "avx512.psrai.q.128" => "__builtin_ia32_psraqi128", + "avx512.psrai.q.256" => "__builtin_ia32_psraqi256", + "avx512.psrai.q.512" => "__builtin_ia32_psraqi512", + "avx512.psrai.w.512" => "__builtin_ia32_psrawi512", + "avx512.psrav.d.512" => "__builtin_ia32_psrav16si", + "avx512.psrav.q.128" => "__builtin_ia32_psravq128", + "avx512.psrav.q.256" => "__builtin_ia32_psravq256", + "avx512.psrav.q.512" => "__builtin_ia32_psrav8di", + "avx512.psrav.w.128" => "__builtin_ia32_psrav8hi", + "avx512.psrav.w.256" => "__builtin_ia32_psrav16hi", + "avx512.psrav.w.512" => "__builtin_ia32_psrav32hi", + "avx512.psrl.d.512" => "__builtin_ia32_psrld512", + "avx512.psrl.dq" => "__builtin_ia32_psrldqi512", + "avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", + "avx512.psrl.q.512" => "__builtin_ia32_psrlq512", + "avx512.psrl.w.512" => "__builtin_ia32_psrlw512", + "avx512.psrli.d.512" => "__builtin_ia32_psrldi512", + "avx512.psrli.q.512" => "__builtin_ia32_psrlqi512", + "avx512.psrli.w.512" => "__builtin_ia32_psrlwi512", + "avx512.psrlv.d.512" => "__builtin_ia32_psrlv16si", + "avx512.psrlv.q.512" => "__builtin_ia32_psrlv8di", + "avx512.psrlv.w.128" => "__builtin_ia32_psrlv8hi", + "avx512.psrlv.w.256" => "__builtin_ia32_psrlv16hi", + "avx512.psrlv.w.512" => "__builtin_ia32_psrlv32hi", + "avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128", + "avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256", + "avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512", + "avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128", + "avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256", + "avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512", + "avx512.ptestm.b.128" => "__builtin_ia32_ptestmb128", + "avx512.ptestm.b.256" => "__builtin_ia32_ptestmb256", + "avx512.ptestm.b.512" => "__builtin_ia32_ptestmb512", + "avx512.ptestm.d.128" => "__builtin_ia32_ptestmd128", + "avx512.ptestm.d.256" => "__builtin_ia32_ptestmd256", + "avx512.ptestm.d.512" => "__builtin_ia32_ptestmd512", + "avx512.ptestm.q.128" => "__builtin_ia32_ptestmq128", + "avx512.ptestm.q.256" => "__builtin_ia32_ptestmq256", + "avx512.ptestm.q.512" => "__builtin_ia32_ptestmq512", + "avx512.ptestm.w.128" => "__builtin_ia32_ptestmw128", + "avx512.ptestm.w.256" => "__builtin_ia32_ptestmw256", + "avx512.ptestm.w.512" => "__builtin_ia32_ptestmw512", + "avx512.ptestnm.b.128" => "__builtin_ia32_ptestnmb128", + "avx512.ptestnm.b.256" => "__builtin_ia32_ptestnmb256", + "avx512.ptestnm.b.512" => "__builtin_ia32_ptestnmb512", + "avx512.ptestnm.d.128" => "__builtin_ia32_ptestnmd128", + "avx512.ptestnm.d.256" => "__builtin_ia32_ptestnmd256", + "avx512.ptestnm.d.512" => "__builtin_ia32_ptestnmd512", + "avx512.ptestnm.q.128" => "__builtin_ia32_ptestnmq128", + "avx512.ptestnm.q.256" => "__builtin_ia32_ptestnmq256", + "avx512.ptestnm.q.512" => "__builtin_ia32_ptestnmq512", + "avx512.ptestnm.w.128" => "__builtin_ia32_ptestnmw128", + "avx512.ptestnm.w.256" => "__builtin_ia32_ptestnmw256", + "avx512.ptestnm.w.512" => "__builtin_ia32_ptestnmw512", + "avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", + "avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", + "avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", + "avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask", + "avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask", + "avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", + "avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", + "avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", + "avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", + "avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", + "avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", + // [DUPLICATE]: "avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", + "avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", + // [DUPLICATE]: "avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + "avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", + "avx512.rndscale.ss" => "__builtin_ia32_rndscaless", + "avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", + "avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", + "avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", + "avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask", + "avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask", + "avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", + "avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", + "avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", + "avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", + "avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", + "avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", + // [DUPLICATE]: "avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", + "avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", + // [DUPLICATE]: "avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + "avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", + "avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", + "avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", + "avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", + "avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", + "avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", + "avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", + "avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", + "avx512.scatterdiv2.df" => "__builtin_ia32_scatterdiv2df", + "avx512.scatterdiv2.di" => "__builtin_ia32_scatterdiv2di", + "avx512.scatterdiv4.df" => "__builtin_ia32_scatterdiv4df", + "avx512.scatterdiv4.di" => "__builtin_ia32_scatterdiv4di", + "avx512.scatterdiv4.sf" => "__builtin_ia32_scatterdiv4sf", + "avx512.scatterdiv4.si" => "__builtin_ia32_scatterdiv4si", + "avx512.scatterdiv8.sf" => "__builtin_ia32_scatterdiv8sf", + "avx512.scatterdiv8.si" => "__builtin_ia32_scatterdiv8si", + "avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", + "avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", + "avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", + "avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", + "avx512.scattersiv2.df" => "__builtin_ia32_scattersiv2df", + "avx512.scattersiv2.di" => "__builtin_ia32_scattersiv2di", + "avx512.scattersiv4.df" => "__builtin_ia32_scattersiv4df", + "avx512.scattersiv4.di" => "__builtin_ia32_scattersiv4di", + "avx512.scattersiv4.sf" => "__builtin_ia32_scattersiv4sf", + "avx512.scattersiv4.si" => "__builtin_ia32_scattersiv4si", + "avx512.scattersiv8.sf" => "__builtin_ia32_scattersiv8sf", + "avx512.scattersiv8.si" => "__builtin_ia32_scattersiv8si", + "avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", + "avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", + "avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", + "avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", + "avx512.sub.pd.512" => "__builtin_ia32_subpd512", + "avx512.sub.ps.512" => "__builtin_ia32_subps512", + "avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", + "avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", + "avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", + "avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", + "avx512.vcomi.sd" => "__builtin_ia32_vcomisd", + "avx512.vcomi.ss" => "__builtin_ia32_vcomiss", + "avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32", + "avx512.vcvtsd2si64" => "__builtin_ia32_vcvtsd2si64", + "avx512.vcvtsd2usi32" => "__builtin_ia32_vcvtsd2usi32", + "avx512.vcvtsd2usi64" => "__builtin_ia32_vcvtsd2usi64", + "avx512.vcvtss2si32" => "__builtin_ia32_vcvtss2si32", + "avx512.vcvtss2si64" => "__builtin_ia32_vcvtss2si64", + "avx512.vcvtss2usi32" => "__builtin_ia32_vcvtss2usi32", + "avx512.vcvtss2usi64" => "__builtin_ia32_vcvtss2usi64", + "avx512.vpdpbusd.128" => "__builtin_ia32_vpdpbusd128", + "avx512.vpdpbusd.256" => "__builtin_ia32_vpdpbusd256", + "avx512.vpdpbusd.512" => "__builtin_ia32_vpdpbusd512", + "avx512.vpdpbusds.128" => "__builtin_ia32_vpdpbusds128", + "avx512.vpdpbusds.256" => "__builtin_ia32_vpdpbusds256", + "avx512.vpdpbusds.512" => "__builtin_ia32_vpdpbusds512", + "avx512.vpdpwssd.128" => "__builtin_ia32_vpdpwssd128", + "avx512.vpdpwssd.256" => "__builtin_ia32_vpdpwssd256", + "avx512.vpdpwssd.512" => "__builtin_ia32_vpdpwssd512", + "avx512.vpdpwssds.128" => "__builtin_ia32_vpdpwssds128", + "avx512.vpdpwssds.256" => "__builtin_ia32_vpdpwssds256", + "avx512.vpdpwssds.512" => "__builtin_ia32_vpdpwssds512", + "avx512.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128", + "avx512.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256", + "avx512.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512", + "avx512.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128", + "avx512.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256", + "avx512.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512", + "avx512.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128", + "avx512.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256", + "avx512.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512", + "avx512.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128", + "avx512.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256", + "avx512.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512", + "avx512.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128", + "avx512.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256", + "avx512.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512", + "avx512.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128", + "avx512.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256", + "avx512.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512", + "avx512.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512", + "avx512.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512", + "avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128", + "avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256", + "avx512.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512", + "avx512.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128", + "avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256", + "avx512.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512", + "avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_128", + "avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_256", + "avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_512", + "avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_256", + "avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_512", + "avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_128", + "avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_256", + "avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512", + "avx512fp16.add.ph.512" => "__builtin_ia32_addph512", + "avx512fp16.div.ph.512" => "__builtin_ia32_divph512", + // [INVALID CONVERSION]: "avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask", + "avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask", + "avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask", + "avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask", + "avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask", + "avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask", + "avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask", + "avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask", + "avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask", + "avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask", + "avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask", + "avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask", + "avx512fp16.mask.rcp.sh" => "__builtin_ia32_rcpsh_mask", + "avx512fp16.mask.reduce.ph.128" => "__builtin_ia32_reduceph128_mask", + "avx512fp16.mask.reduce.ph.256" => "__builtin_ia32_reduceph256_mask", + "avx512fp16.mask.reduce.ph.512" => "__builtin_ia32_reduceph512_mask", + "avx512fp16.mask.reduce.sh" => "__builtin_ia32_reducesh_mask", + "avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask", + "avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask", + "avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask", + "avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask", + "avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask", + "avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask", + "avx512fp16.mask.rsqrt.sh" => "__builtin_ia32_rsqrtsh_mask", + "avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask", + "avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask", + "avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask", + "avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask", + "avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask", + "avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask", + "avx512fp16.mask.vcvtpd2ph.512" => "__builtin_ia32_vcvtpd2ph512_mask", + "avx512fp16.mask.vcvtph2dq.128" => "__builtin_ia32_vcvtph2dq128_mask", + "avx512fp16.mask.vcvtph2dq.256" => "__builtin_ia32_vcvtph2dq256_mask", + "avx512fp16.mask.vcvtph2dq.512" => "__builtin_ia32_vcvtph2dq512_mask", + "avx512fp16.mask.vcvtph2pd.128" => "__builtin_ia32_vcvtph2pd128_mask", + "avx512fp16.mask.vcvtph2pd.256" => "__builtin_ia32_vcvtph2pd256_mask", + "avx512fp16.mask.vcvtph2pd.512" => "__builtin_ia32_vcvtph2pd512_mask", + "avx512fp16.mask.vcvtph2psx.128" => "__builtin_ia32_vcvtph2psx128_mask", + "avx512fp16.mask.vcvtph2psx.256" => "__builtin_ia32_vcvtph2psx256_mask", + "avx512fp16.mask.vcvtph2psx.512" => "__builtin_ia32_vcvtph2psx512_mask", + "avx512fp16.mask.vcvtph2qq.128" => "__builtin_ia32_vcvtph2qq128_mask", + "avx512fp16.mask.vcvtph2qq.256" => "__builtin_ia32_vcvtph2qq256_mask", + "avx512fp16.mask.vcvtph2qq.512" => "__builtin_ia32_vcvtph2qq512_mask", + "avx512fp16.mask.vcvtph2udq.128" => "__builtin_ia32_vcvtph2udq128_mask", + "avx512fp16.mask.vcvtph2udq.256" => "__builtin_ia32_vcvtph2udq256_mask", + "avx512fp16.mask.vcvtph2udq.512" => "__builtin_ia32_vcvtph2udq512_mask", + "avx512fp16.mask.vcvtph2uqq.128" => "__builtin_ia32_vcvtph2uqq128_mask", + "avx512fp16.mask.vcvtph2uqq.256" => "__builtin_ia32_vcvtph2uqq256_mask", + "avx512fp16.mask.vcvtph2uqq.512" => "__builtin_ia32_vcvtph2uqq512_mask", + "avx512fp16.mask.vcvtph2uw.128" => "__builtin_ia32_vcvtph2uw128_mask", + "avx512fp16.mask.vcvtph2uw.256" => "__builtin_ia32_vcvtph2uw256_mask", + "avx512fp16.mask.vcvtph2uw.512" => "__builtin_ia32_vcvtph2uw512_mask", + "avx512fp16.mask.vcvtph2w.128" => "__builtin_ia32_vcvtph2w128_mask", + "avx512fp16.mask.vcvtph2w.256" => "__builtin_ia32_vcvtph2w256_mask", + "avx512fp16.mask.vcvtph2w.512" => "__builtin_ia32_vcvtph2w512_mask", + "avx512fp16.mask.vcvtps2phx.128" => "__builtin_ia32_vcvtps2phx128_mask", + "avx512fp16.mask.vcvtps2phx.256" => "__builtin_ia32_vcvtps2phx256_mask", + "avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask", + "avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask", + "avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask", + // [INVALID CONVERSION]: "avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask", + "avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask", + "avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask", + "avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask", + "avx512fp16.mask.vcvttph2qq.128" => "__builtin_ia32_vcvttph2qq128_mask", + "avx512fp16.mask.vcvttph2qq.256" => "__builtin_ia32_vcvttph2qq256_mask", + "avx512fp16.mask.vcvttph2qq.512" => "__builtin_ia32_vcvttph2qq512_mask", + "avx512fp16.mask.vcvttph2udq.128" => "__builtin_ia32_vcvttph2udq128_mask", + "avx512fp16.mask.vcvttph2udq.256" => "__builtin_ia32_vcvttph2udq256_mask", + "avx512fp16.mask.vcvttph2udq.512" => "__builtin_ia32_vcvttph2udq512_mask", + "avx512fp16.mask.vcvttph2uqq.128" => "__builtin_ia32_vcvttph2uqq128_mask", + "avx512fp16.mask.vcvttph2uqq.256" => "__builtin_ia32_vcvttph2uqq256_mask", + "avx512fp16.mask.vcvttph2uqq.512" => "__builtin_ia32_vcvttph2uqq512_mask", + "avx512fp16.mask.vcvttph2uw.128" => "__builtin_ia32_vcvttph2uw128_mask", + "avx512fp16.mask.vcvttph2uw.256" => "__builtin_ia32_vcvttph2uw256_mask", + "avx512fp16.mask.vcvttph2uw.512" => "__builtin_ia32_vcvttph2uw512_mask", + "avx512fp16.mask.vcvttph2w.128" => "__builtin_ia32_vcvttph2w128_mask", + "avx512fp16.mask.vcvttph2w.256" => "__builtin_ia32_vcvttph2w256_mask", + "avx512fp16.mask.vcvttph2w.512" => "__builtin_ia32_vcvttph2w512_mask", + "avx512fp16.mask.vcvtudq2ph.128" => "__builtin_ia32_vcvtudq2ph128_mask", + "avx512fp16.mask.vcvtuqq2ph.128" => "__builtin_ia32_vcvtuqq2ph128_mask", + "avx512fp16.mask.vcvtuqq2ph.256" => "__builtin_ia32_vcvtuqq2ph256_mask", + "avx512fp16.mask.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_mask", + "avx512fp16.mask.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_mask", + "avx512fp16.mask.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_mask3", + "avx512fp16.mask.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_mask", + "avx512fp16.mask.vfcmul.cph.128" => "__builtin_ia32_vfcmulcph128_mask", + "avx512fp16.mask.vfcmul.cph.256" => "__builtin_ia32_vfcmulcph256_mask", + "avx512fp16.mask.vfcmul.cph.512" => "__builtin_ia32_vfcmulcph512_mask", + "avx512fp16.mask.vfcmul.csh" => "__builtin_ia32_vfcmulcsh_mask", + "avx512fp16.mask.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_mask", + "avx512fp16.mask.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_mask", + "avx512fp16.mask.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_mask3", + "avx512fp16.mask.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_mask", + "avx512fp16.mask.vfmul.cph.128" => "__builtin_ia32_vfmulcph128_mask", + "avx512fp16.mask.vfmul.cph.256" => "__builtin_ia32_vfmulcph256_mask", + "avx512fp16.mask.vfmul.cph.512" => "__builtin_ia32_vfmulcph512_mask", + "avx512fp16.mask.vfmul.csh" => "__builtin_ia32_vfmulcsh_mask", + "avx512fp16.maskz.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_maskz", + "avx512fp16.maskz.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_maskz", + "avx512fp16.maskz.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_maskz", + "avx512fp16.maskz.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_maskz", + "avx512fp16.maskz.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_maskz", + "avx512fp16.maskz.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_maskz", + "avx512fp16.maskz.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_maskz", + "avx512fp16.maskz.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_maskz", + "avx512fp16.max.ph.128" => "__builtin_ia32_maxph128", + "avx512fp16.max.ph.256" => "__builtin_ia32_maxph256", + "avx512fp16.max.ph.512" => "__builtin_ia32_maxph512", + "avx512fp16.min.ph.128" => "__builtin_ia32_minph128", + "avx512fp16.min.ph.256" => "__builtin_ia32_minph256", + "avx512fp16.min.ph.512" => "__builtin_ia32_minph512", + "avx512fp16.mul.ph.512" => "__builtin_ia32_mulph512", + "avx512fp16.sub.ph.512" => "__builtin_ia32_subph512", + "avx512fp16.vcomi.sh" => "__builtin_ia32_vcomish", + "avx512fp16.vcvtsh2si32" => "__builtin_ia32_vcvtsh2si32", + "avx512fp16.vcvtsh2si64" => "__builtin_ia32_vcvtsh2si64", + "avx512fp16.vcvtsh2usi32" => "__builtin_ia32_vcvtsh2usi32", + "avx512fp16.vcvtsh2usi64" => "__builtin_ia32_vcvtsh2usi64", + "avx512fp16.vcvtsi2sh" => "__builtin_ia32_vcvtsi2sh", + "avx512fp16.vcvtsi642sh" => "__builtin_ia32_vcvtsi642sh", + "avx512fp16.vcvttsh2si32" => "__builtin_ia32_vcvttsh2si32", + "avx512fp16.vcvttsh2si64" => "__builtin_ia32_vcvttsh2si64", + "avx512fp16.vcvttsh2usi32" => "__builtin_ia32_vcvttsh2usi32", + "avx512fp16.vcvttsh2usi64" => "__builtin_ia32_vcvttsh2usi64", + "avx512fp16.vcvtusi2sh" => "__builtin_ia32_vcvtusi2sh", + "avx512fp16.vcvtusi642sh" => "__builtin_ia32_vcvtusi642sh", + "avx512fp16.vfmaddsub.ph.128" => "__builtin_ia32_vfmaddsubph", + "avx512fp16.vfmaddsub.ph.256" => "__builtin_ia32_vfmaddsubph256", + "axor32" => "__builtin_ia32_axor32", + "axor64" => "__builtin_ia32_axor64", + "bmi.bextr.32" => "__builtin_ia32_bextr_u32", + "bmi.bextr.64" => "__builtin_ia32_bextr_u64", + "bmi.bzhi.32" => "__builtin_ia32_bzhi_si", + "bmi.bzhi.64" => "__builtin_ia32_bzhi_di", + "bmi.pdep.32" => "__builtin_ia32_pdep_si", + "bmi.pdep.64" => "__builtin_ia32_pdep_di", + "bmi.pext.32" => "__builtin_ia32_pext_si", + "bmi.pext.64" => "__builtin_ia32_pext_di", + "cldemote" => "__builtin_ia32_cldemote", + "clflushopt" => "__builtin_ia32_clflushopt", + "clrssbsy" => "__builtin_ia32_clrssbsy", + "clui" => "__builtin_ia32_clui", + "clwb" => "__builtin_ia32_clwb", + "clzero" => "__builtin_ia32_clzero", + "cmpccxadd32" => "__builtin_ia32_cmpccxadd32", + "cmpccxadd64" => "__builtin_ia32_cmpccxadd64", + "directstore32" => "__builtin_ia32_directstore_u32", + "directstore64" => "__builtin_ia32_directstore_u64", + "enqcmd" => "__builtin_ia32_enqcmd", + "enqcmds" => "__builtin_ia32_enqcmds", + "flags.read.u32" => "__builtin_ia32_readeflags_u32", + "flags.read.u64" => "__builtin_ia32_readeflags_u64", + "flags.write.u32" => "__builtin_ia32_writeeflags_u32", + "flags.write.u64" => "__builtin_ia32_writeeflags_u64", + "fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", + "fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", + "fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", + "fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", + "fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", + "fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", + "fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", + "fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", + "fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", + "fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", + "fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", + "fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", + "fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", + "fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", + "fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", + "fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", + "fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", + "fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", + "fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", + "fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", + "fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", + "fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", + "fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", + "fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", + "fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", + "fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", + "fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", + "fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", + "fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", + "fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", + "fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", + "fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", + "fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", + "fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", + "fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", + "fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", + "fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", + "fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", + "fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", + "fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", + "fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", + "fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", + "fxrstor" => "__builtin_ia32_fxrstor", + "fxrstor64" => "__builtin_ia32_fxrstor64", + "fxsave" => "__builtin_ia32_fxsave", + "fxsave64" => "__builtin_ia32_fxsave64", + "incsspd" => "__builtin_ia32_incsspd", + "incsspq" => "__builtin_ia32_incsspq", + "invpcid" => "__builtin_ia32_invpcid", + "ldtilecfg" => "__builtin_ia32_tile_loadconfig", + "ldtilecfg.internal" => "__builtin_ia32_tile_loadconfig_internal", + "llwpcb" => "__builtin_ia32_llwpcb", + "loadiwkey" => "__builtin_ia32_loadiwkey", + "lwpins32" => "__builtin_ia32_lwpins32", + "lwpins64" => "__builtin_ia32_lwpins64", + "lwpval32" => "__builtin_ia32_lwpval32", + "lwpval64" => "__builtin_ia32_lwpval64", + "mmx.emms" => "__builtin_ia32_emms", + "mmx.femms" => "__builtin_ia32_femms", + "monitorx" => "__builtin_ia32_monitorx", + "movdir64b" => "__builtin_ia32_movdir64b", + "movrsdi" => "__builtin_ia32_movrsdi", + "movrshi" => "__builtin_ia32_movrshi", + "movrsqi" => "__builtin_ia32_movrsqi", + "movrssi" => "__builtin_ia32_movrssi", + "mwaitx" => "__builtin_ia32_mwaitx", + "pclmulqdq" => "__builtin_ia32_pclmulqdq128", + "pclmulqdq.256" => "__builtin_ia32_pclmulqdq256", + "pclmulqdq.512" => "__builtin_ia32_pclmulqdq512", + "prefetchrs" => "__builtin_ia32_prefetchrs", + "ptwrite32" => "__builtin_ia32_ptwrite32", + "ptwrite64" => "__builtin_ia32_ptwrite64", + "rdfsbase.32" => "__builtin_ia32_rdfsbase32", + "rdfsbase.64" => "__builtin_ia32_rdfsbase64", + "rdgsbase.32" => "__builtin_ia32_rdgsbase32", + "rdgsbase.64" => "__builtin_ia32_rdgsbase64", + "rdpid" => "__builtin_ia32_rdpid", + "rdpkru" => "__builtin_ia32_rdpkru", + "rdpmc" => "__builtin_ia32_rdpmc", + "rdpru" => "__builtin_ia32_rdpru", + "rdsspd" => "__builtin_ia32_rdsspd", + "rdsspq" => "__builtin_ia32_rdsspq", + "rdtsc" => "__builtin_ia32_rdtsc", + "rdtscp" => "__builtin_ia32_rdtscp", + "rstorssp" => "__builtin_ia32_rstorssp", + "saveprevssp" => "__builtin_ia32_saveprevssp", + "senduipi" => "__builtin_ia32_senduipi", + "serialize" => "__builtin_ia32_serialize", + "setssbsy" => "__builtin_ia32_setssbsy", + "sha1msg1" => "__builtin_ia32_sha1msg1", + "sha1msg2" => "__builtin_ia32_sha1msg2", + "sha1nexte" => "__builtin_ia32_sha1nexte", + "sha1rnds4" => "__builtin_ia32_sha1rnds4", + "sha256msg1" => "__builtin_ia32_sha256msg1", + "sha256msg2" => "__builtin_ia32_sha256msg2", + "sha256rnds2" => "__builtin_ia32_sha256rnds2", + "slwpcb" => "__builtin_ia32_slwpcb", + "sse.add.ss" => "__builtin_ia32_addss", + "sse.cmp.ps" => "__builtin_ia32_cmpps", + "sse.cmp.ss" => "__builtin_ia32_cmpss", + "sse.comieq.ss" => "__builtin_ia32_comieq", + "sse.comige.ss" => "__builtin_ia32_comige", + "sse.comigt.ss" => "__builtin_ia32_comigt", + "sse.comile.ss" => "__builtin_ia32_comile", + "sse.comilt.ss" => "__builtin_ia32_comilt", + "sse.comineq.ss" => "__builtin_ia32_comineq", + "sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", + "sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", + "sse.cvtss2si" => "__builtin_ia32_cvtss2si", + "sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", + "sse.cvttss2si" => "__builtin_ia32_cvttss2si", + "sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", + "sse.div.ss" => "__builtin_ia32_divss", + "sse.max.ps" => "__builtin_ia32_maxps", + "sse.max.ss" => "__builtin_ia32_maxss", + "sse.min.ps" => "__builtin_ia32_minps", + "sse.min.ss" => "__builtin_ia32_minss", + "sse.movmsk.ps" => "__builtin_ia32_movmskps", + "sse.mul.ss" => "__builtin_ia32_mulss", + "sse.rcp.ps" => "__builtin_ia32_rcpps", + "sse.rcp.ss" => "__builtin_ia32_rcpss", + "sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", + "sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", + "sse.sfence" => "__builtin_ia32_sfence", + "sse.sqrt.ps" => "__builtin_ia32_sqrtps", + "sse.sqrt.ss" => "__builtin_ia32_sqrtss", + "sse.storeu.ps" => "__builtin_ia32_storeups", + "sse.sub.ss" => "__builtin_ia32_subss", + "sse.ucomieq.ss" => "__builtin_ia32_ucomieq", + "sse.ucomige.ss" => "__builtin_ia32_ucomige", + "sse.ucomigt.ss" => "__builtin_ia32_ucomigt", + "sse.ucomile.ss" => "__builtin_ia32_ucomile", + "sse.ucomilt.ss" => "__builtin_ia32_ucomilt", + "sse.ucomineq.ss" => "__builtin_ia32_ucomineq", + "sse2.add.sd" => "__builtin_ia32_addsd", + "sse2.clflush" => "__builtin_ia32_clflush", + "sse2.cmp.pd" => "__builtin_ia32_cmppd", + "sse2.cmp.sd" => "__builtin_ia32_cmpsd", + "sse2.comieq.sd" => "__builtin_ia32_comisdeq", + "sse2.comige.sd" => "__builtin_ia32_comisdge", + "sse2.comigt.sd" => "__builtin_ia32_comisdgt", + "sse2.comile.sd" => "__builtin_ia32_comisdle", + "sse2.comilt.sd" => "__builtin_ia32_comisdlt", + "sse2.comineq.sd" => "__builtin_ia32_comisdneq", + "sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", + "sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", + "sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", + "sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", + "sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", + "sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", + "sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", + "sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", + "sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", + "sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", + "sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", + "sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", + "sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", + "sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", + "sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", + "sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", + "sse2.div.sd" => "__builtin_ia32_divsd", + "sse2.lfence" => "__builtin_ia32_lfence", + "sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", + "sse2.max.pd" => "__builtin_ia32_maxpd", + "sse2.max.sd" => "__builtin_ia32_maxsd", + "sse2.mfence" => "__builtin_ia32_mfence", + "sse2.min.pd" => "__builtin_ia32_minpd", + "sse2.min.sd" => "__builtin_ia32_minsd", + "sse2.movmsk.pd" => "__builtin_ia32_movmskpd", + "sse2.mul.sd" => "__builtin_ia32_mulsd", + "sse2.packssdw.128" => "__builtin_ia32_packssdw128", + "sse2.packsswb.128" => "__builtin_ia32_packsswb128", + "sse2.packuswb.128" => "__builtin_ia32_packuswb128", + "sse2.padds.b" => "__builtin_ia32_paddsb128", + "sse2.padds.w" => "__builtin_ia32_paddsw128", + "sse2.paddus.b" => "__builtin_ia32_paddusb128", + "sse2.paddus.w" => "__builtin_ia32_paddusw128", + "sse2.pause" => "__builtin_ia32_pause", + "sse2.pavg.b" => "__builtin_ia32_pavgb128", + "sse2.pavg.w" => "__builtin_ia32_pavgw128", + "sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", + "sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", + "sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", + "sse2.pmins.w" => "__builtin_ia32_pminsw128", + "sse2.pminu.b" => "__builtin_ia32_pminub128", + "sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", + "sse2.pmulh.w" => "__builtin_ia32_pmulhw128", + "sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", + "sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", + "sse2.psad.bw" => "__builtin_ia32_psadbw128", + "sse2.pshuf.d" => "__builtin_ia32_pshufd", + "sse2.pshufh.w" => "__builtin_ia32_pshufhw", + "sse2.pshufl.w" => "__builtin_ia32_pshuflw", + "sse2.psll.d" => "__builtin_ia32_pslld128", + "sse2.psll.dq" => "__builtin_ia32_pslldqi128", + "sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", + "sse2.psll.q" => "__builtin_ia32_psllq128", + "sse2.psll.w" => "__builtin_ia32_psllw128", + "sse2.pslli.d" => "__builtin_ia32_pslldi128", + "sse2.pslli.q" => "__builtin_ia32_psllqi128", + "sse2.pslli.w" => "__builtin_ia32_psllwi128", + "sse2.psra.d" => "__builtin_ia32_psrad128", + "sse2.psra.w" => "__builtin_ia32_psraw128", + "sse2.psrai.d" => "__builtin_ia32_psradi128", + "sse2.psrai.w" => "__builtin_ia32_psrawi128", + "sse2.psrl.d" => "__builtin_ia32_psrld128", + "sse2.psrl.dq" => "__builtin_ia32_psrldqi128", + "sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", + "sse2.psrl.q" => "__builtin_ia32_psrlq128", + "sse2.psrl.w" => "__builtin_ia32_psrlw128", + "sse2.psrli.d" => "__builtin_ia32_psrldi128", + "sse2.psrli.q" => "__builtin_ia32_psrlqi128", + "sse2.psrli.w" => "__builtin_ia32_psrlwi128", + "sse2.psubs.b" => "__builtin_ia32_psubsb128", + "sse2.psubs.w" => "__builtin_ia32_psubsw128", + "sse2.psubus.b" => "__builtin_ia32_psubusb128", + "sse2.psubus.w" => "__builtin_ia32_psubusw128", + "sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", + "sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", + "sse2.storel.dq" => "__builtin_ia32_storelv4si", + "sse2.storeu.dq" => "__builtin_ia32_storedqu", + "sse2.storeu.pd" => "__builtin_ia32_storeupd", + "sse2.sub.sd" => "__builtin_ia32_subsd", + "sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", + "sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", + "sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", + "sse2.ucomile.sd" => "__builtin_ia32_ucomisdle", + "sse2.ucomilt.sd" => "__builtin_ia32_ucomisdlt", + "sse2.ucomineq.sd" => "__builtin_ia32_ucomisdneq", + "sse3.addsub.pd" => "__builtin_ia32_addsubpd", + "sse3.addsub.ps" => "__builtin_ia32_addsubps", + "sse3.hadd.pd" => "__builtin_ia32_haddpd", + "sse3.hadd.ps" => "__builtin_ia32_haddps", + "sse3.hsub.pd" => "__builtin_ia32_hsubpd", + "sse3.hsub.ps" => "__builtin_ia32_hsubps", + "sse3.ldu.dq" => "__builtin_ia32_lddqu", + "sse3.monitor" => "__builtin_ia32_monitor", + "sse3.mwait" => "__builtin_ia32_mwait", + "sse41.blendpd" => "__builtin_ia32_blendpd", + "sse41.blendps" => "__builtin_ia32_blendps", + "sse41.blendvpd" => "__builtin_ia32_blendvpd", + "sse41.blendvps" => "__builtin_ia32_blendvps", + "sse41.dppd" => "__builtin_ia32_dppd", + "sse41.dpps" => "__builtin_ia32_dpps", + "sse41.extractps" => "__builtin_ia32_extractps128", + "sse41.insertps" => "__builtin_ia32_insertps128", + "sse41.movntdqa" => "__builtin_ia32_movntdqa", + "sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", + "sse41.packusdw" => "__builtin_ia32_packusdw128", + "sse41.pblendvb" => "__builtin_ia32_pblendvb128", + "sse41.pblendw" => "__builtin_ia32_pblendw128", + "sse41.phminposuw" => "__builtin_ia32_phminposuw128", + "sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", + "sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", + "sse41.pmaxud" => "__builtin_ia32_pmaxud128", + "sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", + "sse41.pminsb" => "__builtin_ia32_pminsb128", + "sse41.pminsd" => "__builtin_ia32_pminsd128", + "sse41.pminud" => "__builtin_ia32_pminud128", + "sse41.pminuw" => "__builtin_ia32_pminuw128", + "sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", + "sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", + "sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", + "sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", + "sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", + "sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", + "sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", + "sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", + "sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", + "sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", + "sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", + "sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", + "sse41.pmuldq" => "__builtin_ia32_pmuldq128", + "sse41.ptestc" => "__builtin_ia32_ptestc128", + "sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", + "sse41.ptestz" => "__builtin_ia32_ptestz128", + "sse41.round.pd" => "__builtin_ia32_roundpd", + "sse41.round.ps" => "__builtin_ia32_roundps", + "sse41.round.sd" => "__builtin_ia32_roundsd", + "sse41.round.ss" => "__builtin_ia32_roundss", + "sse42.crc32.32.16" => "__builtin_ia32_crc32hi", + "sse42.crc32.32.32" => "__builtin_ia32_crc32si", + "sse42.crc32.32.8" => "__builtin_ia32_crc32qi", + "sse42.crc32.64.64" => "__builtin_ia32_crc32di", + "sse42.pcmpestri128" => "__builtin_ia32_pcmpestri128", + "sse42.pcmpestria128" => "__builtin_ia32_pcmpestria128", + "sse42.pcmpestric128" => "__builtin_ia32_pcmpestric128", + "sse42.pcmpestrio128" => "__builtin_ia32_pcmpestrio128", + "sse42.pcmpestris128" => "__builtin_ia32_pcmpestris128", + "sse42.pcmpestriz128" => "__builtin_ia32_pcmpestriz128", + "sse42.pcmpestrm128" => "__builtin_ia32_pcmpestrm128", + "sse42.pcmpistri128" => "__builtin_ia32_pcmpistri128", + "sse42.pcmpistria128" => "__builtin_ia32_pcmpistria128", + "sse42.pcmpistric128" => "__builtin_ia32_pcmpistric128", + "sse42.pcmpistrio128" => "__builtin_ia32_pcmpistrio128", + "sse42.pcmpistris128" => "__builtin_ia32_pcmpistris128", + "sse42.pcmpistriz128" => "__builtin_ia32_pcmpistriz128", + "sse42.pcmpistrm128" => "__builtin_ia32_pcmpistrm128", + "sse4a.extrq" => "__builtin_ia32_extrq", + "sse4a.extrqi" => "__builtin_ia32_extrqi", + "sse4a.insertq" => "__builtin_ia32_insertq", + "sse4a.insertqi" => "__builtin_ia32_insertqi", + "sse4a.movnt.sd" => "__builtin_ia32_movntsd", + "sse4a.movnt.ss" => "__builtin_ia32_movntss", + "ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", + "ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", + "ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", + "ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", + "ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", + "ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", + "ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", + "ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", + "ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", + "ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", + "ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", + "ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", + "ssse3.psign.b.128" => "__builtin_ia32_psignb128", + "ssse3.psign.d.128" => "__builtin_ia32_psignd128", + "ssse3.psign.w.128" => "__builtin_ia32_psignw128", + "sttilecfg" => "__builtin_ia32_tile_storeconfig", + "stui" => "__builtin_ia32_stui", + "subborrow.u32" => "__builtin_ia32_subborrow_u32", + "subborrow.u64" => "__builtin_ia32_subborrow_u64", + "t2rpntlvwz0" => "__builtin_ia32_t2rpntlvwz0", + "t2rpntlvwz0rs" => "__builtin_ia32_t2rpntlvwz0rs", + "t2rpntlvwz0rst1" => "__builtin_ia32_t2rpntlvwz0rst1", + "t2rpntlvwz0t1" => "__builtin_ia32_t2rpntlvwz0t1", + "t2rpntlvwz1" => "__builtin_ia32_t2rpntlvwz1", + "t2rpntlvwz1rs" => "__builtin_ia32_t2rpntlvwz1rs", + "t2rpntlvwz1rst1" => "__builtin_ia32_t2rpntlvwz1rst1", + "t2rpntlvwz1t1" => "__builtin_ia32_t2rpntlvwz1t1", + "tbm.bextri.u32" => "__builtin_ia32_bextri_u32", + "tbm.bextri.u64" => "__builtin_ia32_bextri_u64", + "tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps", + "tcmmimfp16ps.internal" => "__builtin_ia32_tcmmimfp16ps_internal", + "tcmmrlfp16ps" => "__builtin_ia32_tcmmrlfp16ps", + "tcmmrlfp16ps.internal" => "__builtin_ia32_tcmmrlfp16ps_internal", + "tconjtcmmimfp16ps" => "__builtin_ia32_tconjtcmmimfp16ps", + "tconjtcmmimfp16ps.internal" => "__builtin_ia32_tconjtcmmimfp16ps_internal", + "tconjtfp16" => "__builtin_ia32_tconjtfp16", + "tconjtfp16.internal" => "__builtin_ia32_tconjtfp16_internal", + "tcvtrowd2ps" => "__builtin_ia32_tcvtrowd2ps", + "tcvtrowd2ps.internal" => "__builtin_ia32_tcvtrowd2ps_internal", + "tcvtrowps2bf16h" => "__builtin_ia32_tcvtrowps2bf16h", + "tcvtrowps2bf16h.internal" => "__builtin_ia32_tcvtrowps2bf16h_internal", + "tcvtrowps2bf16l" => "__builtin_ia32_tcvtrowps2bf16l", + "tcvtrowps2bf16l.internal" => "__builtin_ia32_tcvtrowps2bf16l_internal", + "tcvtrowps2phh" => "__builtin_ia32_tcvtrowps2phh", + "tcvtrowps2phh.internal" => "__builtin_ia32_tcvtrowps2phh_internal", + "tcvtrowps2phl" => "__builtin_ia32_tcvtrowps2phl", + "tcvtrowps2phl.internal" => "__builtin_ia32_tcvtrowps2phl_internal", + "tdpbf16ps" => "__builtin_ia32_tdpbf16ps", + "tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal", + "tdpbf8ps" => "__builtin_ia32_tdpbf8ps", + "tdpbf8ps.internal" => "__builtin_ia32_tdpbf8ps_internal", + "tdpbhf8ps" => "__builtin_ia32_tdpbhf8ps", + "tdpbhf8ps.internal" => "__builtin_ia32_tdpbhf8ps_internal", + "tdpbssd" => "__builtin_ia32_tdpbssd", + "tdpbssd.internal" => "__builtin_ia32_tdpbssd_internal", + "tdpbsud" => "__builtin_ia32_tdpbsud", + "tdpbsud.internal" => "__builtin_ia32_tdpbsud_internal", + "tdpbusd" => "__builtin_ia32_tdpbusd", + "tdpbusd.internal" => "__builtin_ia32_tdpbusd_internal", + "tdpbuud" => "__builtin_ia32_tdpbuud", + "tdpbuud.internal" => "__builtin_ia32_tdpbuud_internal", + "tdpfp16ps" => "__builtin_ia32_tdpfp16ps", + "tdpfp16ps.internal" => "__builtin_ia32_tdpfp16ps_internal", + "tdphbf8ps" => "__builtin_ia32_tdphbf8ps", + "tdphbf8ps.internal" => "__builtin_ia32_tdphbf8ps_internal", + "tdphf8ps" => "__builtin_ia32_tdphf8ps", + "tdphf8ps.internal" => "__builtin_ia32_tdphf8ps_internal", + "testui" => "__builtin_ia32_testui", + "tileloadd64" => "__builtin_ia32_tileloadd64", + "tileloadd64.internal" => "__builtin_ia32_tileloadd64_internal", + "tileloaddrs64" => "__builtin_ia32_tileloaddrs64", + "tileloaddrs64.internal" => "__builtin_ia32_tileloaddrs64_internal", + "tileloaddrst164" => "__builtin_ia32_tileloaddrst164", + "tileloaddrst164.internal" => "__builtin_ia32_tileloaddrst164_internal", + "tileloaddt164" => "__builtin_ia32_tileloaddt164", + "tileloaddt164.internal" => "__builtin_ia32_tileloaddt164_internal", + "tilemovrow" => "__builtin_ia32_tilemovrow", + "tilemovrow.internal" => "__builtin_ia32_tilemovrow_internal", + "tilerelease" => "__builtin_ia32_tilerelease", + "tilestored64" => "__builtin_ia32_tilestored64", + "tilestored64.internal" => "__builtin_ia32_tilestored64_internal", + "tilezero" => "__builtin_ia32_tilezero", + "tilezero.internal" => "__builtin_ia32_tilezero_internal", + "tmmultf32ps" => "__builtin_ia32_tmmultf32ps", + "tmmultf32ps.internal" => "__builtin_ia32_tmmultf32ps_internal", + "tpause" => "__builtin_ia32_tpause", + "ttcmmimfp16ps" => "__builtin_ia32_ttcmmimfp16ps", + "ttcmmimfp16ps.internal" => "__builtin_ia32_ttcmmimfp16ps_internal", + "ttcmmrlfp16ps" => "__builtin_ia32_ttcmmrlfp16ps", + "ttcmmrlfp16ps.internal" => "__builtin_ia32_ttcmmrlfp16ps_internal", + "ttdpbf16ps" => "__builtin_ia32_ttdpbf16ps", + "ttdpbf16ps.internal" => "__builtin_ia32_ttdpbf16ps_internal", + "ttdpfp16ps" => "__builtin_ia32_ttdpfp16ps", + "ttdpfp16ps.internal" => "__builtin_ia32_ttdpfp16ps_internal", + "ttmmultf32ps" => "__builtin_ia32_ttmmultf32ps", + "ttmmultf32ps.internal" => "__builtin_ia32_ttmmultf32ps_internal", + "ttransposed" => "__builtin_ia32_ttransposed", + "ttransposed.internal" => "__builtin_ia32_ttransposed_internal", + "umonitor" => "__builtin_ia32_umonitor", + "umwait" => "__builtin_ia32_umwait", + "urdmsr" => "__builtin_ia32_urdmsr", + "uwrmsr" => "__builtin_ia32_uwrmsr", + "vbcstnebf162ps128" => "__builtin_ia32_vbcstnebf162ps128", + "vbcstnebf162ps256" => "__builtin_ia32_vbcstnebf162ps256", + "vbcstnesh2ps128" => "__builtin_ia32_vbcstnesh2ps128", + "vbcstnesh2ps256" => "__builtin_ia32_vbcstnesh2ps256", + "vcvtneebf162ps128" => "__builtin_ia32_vcvtneebf162ps128", + "vcvtneebf162ps256" => "__builtin_ia32_vcvtneebf162ps256", + "vcvtneeph2ps128" => "__builtin_ia32_vcvtneeph2ps128", + "vcvtneeph2ps256" => "__builtin_ia32_vcvtneeph2ps256", + "vcvtneobf162ps128" => "__builtin_ia32_vcvtneobf162ps128", + "vcvtneobf162ps256" => "__builtin_ia32_vcvtneobf162ps256", + "vcvtneoph2ps128" => "__builtin_ia32_vcvtneoph2ps128", + "vcvtneoph2ps256" => "__builtin_ia32_vcvtneoph2ps256", + "vcvtneps2bf16128" => "__builtin_ia32_vcvtneps2bf16128", + "vcvtneps2bf16256" => "__builtin_ia32_vcvtneps2bf16256", + "vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", + "vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", + "vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", + "vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", + "vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi", + "vgf2p8affineinvqb.256" => "__builtin_ia32_vgf2p8affineinvqb_v32qi", + "vgf2p8affineinvqb.512" => "__builtin_ia32_vgf2p8affineinvqb_v64qi", + "vgf2p8affineqb.128" => "__builtin_ia32_vgf2p8affineqb_v16qi", + "vgf2p8affineqb.256" => "__builtin_ia32_vgf2p8affineqb_v32qi", + "vgf2p8affineqb.512" => "__builtin_ia32_vgf2p8affineqb_v64qi", + "vgf2p8mulb.128" => "__builtin_ia32_vgf2p8mulb_v16qi", + "vgf2p8mulb.256" => "__builtin_ia32_vgf2p8mulb_v32qi", + "vgf2p8mulb.512" => "__builtin_ia32_vgf2p8mulb_v64qi", + "vsha512msg1" => "__builtin_ia32_vsha512msg1", + "vsha512msg2" => "__builtin_ia32_vsha512msg2", + "vsha512rnds2" => "__builtin_ia32_vsha512rnds2", + "vsm3msg1" => "__builtin_ia32_vsm3msg1", + "vsm3msg2" => "__builtin_ia32_vsm3msg2", + "vsm3rnds2" => "__builtin_ia32_vsm3rnds2", + "vsm4key4128" => "__builtin_ia32_vsm4key4128", + "vsm4key4256" => "__builtin_ia32_vsm4key4256", + "vsm4key4512" => "__builtin_ia32_vsm4key4512", + "vsm4rnds4128" => "__builtin_ia32_vsm4rnds4128", + "vsm4rnds4256" => "__builtin_ia32_vsm4rnds4256", + "vsm4rnds4512" => "__builtin_ia32_vsm4rnds4512", + "wbinvd" => "__builtin_ia32_wbinvd", + "wbnoinvd" => "__builtin_ia32_wbnoinvd", + "wrfsbase.32" => "__builtin_ia32_wrfsbase32", + "wrfsbase.64" => "__builtin_ia32_wrfsbase64", + "wrgsbase.32" => "__builtin_ia32_wrgsbase32", + "wrgsbase.64" => "__builtin_ia32_wrgsbase64", + "wrpkru" => "__builtin_ia32_wrpkru", + "wrssd" => "__builtin_ia32_wrssd", + "wrssq" => "__builtin_ia32_wrssq", + "wrussd" => "__builtin_ia32_wrussd", + "wrussq" => "__builtin_ia32_wrussq", + "xabort" => "__builtin_ia32_xabort", + "xbegin" => "__builtin_ia32_xbegin", + "xend" => "__builtin_ia32_xend", + "xop.vfrcz.pd" => "__builtin_ia32_vfrczpd", + "xop.vfrcz.pd.256" => "__builtin_ia32_vfrczpd256", + "xop.vfrcz.ps" => "__builtin_ia32_vfrczps", + "xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", + "xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", + "xop.vfrcz.ss" => "__builtin_ia32_vfrczss", + "xop.vpcmov" => "__builtin_ia32_vpcmov", + "xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", + "xop.vpcomb" => "__builtin_ia32_vpcomb", + "xop.vpcomd" => "__builtin_ia32_vpcomd", + "xop.vpcomq" => "__builtin_ia32_vpcomq", + "xop.vpcomub" => "__builtin_ia32_vpcomub", + "xop.vpcomud" => "__builtin_ia32_vpcomud", + "xop.vpcomuq" => "__builtin_ia32_vpcomuq", + "xop.vpcomuw" => "__builtin_ia32_vpcomuw", + "xop.vpcomw" => "__builtin_ia32_vpcomw", + "xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", + "xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", + "xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", + "xop.vpermil2ps.256" => "__builtin_ia32_vpermil2ps256", + "xop.vphaddbd" => "__builtin_ia32_vphaddbd", + "xop.vphaddbq" => "__builtin_ia32_vphaddbq", + "xop.vphaddbw" => "__builtin_ia32_vphaddbw", + "xop.vphadddq" => "__builtin_ia32_vphadddq", + "xop.vphaddubd" => "__builtin_ia32_vphaddubd", + "xop.vphaddubq" => "__builtin_ia32_vphaddubq", + "xop.vphaddubw" => "__builtin_ia32_vphaddubw", + "xop.vphaddudq" => "__builtin_ia32_vphaddudq", + "xop.vphadduwd" => "__builtin_ia32_vphadduwd", + "xop.vphadduwq" => "__builtin_ia32_vphadduwq", + "xop.vphaddwd" => "__builtin_ia32_vphaddwd", + "xop.vphaddwq" => "__builtin_ia32_vphaddwq", + "xop.vphsubbw" => "__builtin_ia32_vphsubbw", + "xop.vphsubdq" => "__builtin_ia32_vphsubdq", + "xop.vphsubwd" => "__builtin_ia32_vphsubwd", + "xop.vpmacsdd" => "__builtin_ia32_vpmacsdd", + "xop.vpmacsdqh" => "__builtin_ia32_vpmacsdqh", + "xop.vpmacsdql" => "__builtin_ia32_vpmacsdql", + "xop.vpmacssdd" => "__builtin_ia32_vpmacssdd", + "xop.vpmacssdqh" => "__builtin_ia32_vpmacssdqh", + "xop.vpmacssdql" => "__builtin_ia32_vpmacssdql", + "xop.vpmacsswd" => "__builtin_ia32_vpmacsswd", + "xop.vpmacssww" => "__builtin_ia32_vpmacssww", + "xop.vpmacswd" => "__builtin_ia32_vpmacswd", + "xop.vpmacsww" => "__builtin_ia32_vpmacsww", + "xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", + "xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", + "xop.vpperm" => "__builtin_ia32_vpperm", + "xop.vprotb" => "__builtin_ia32_vprotb", + "xop.vprotbi" => "__builtin_ia32_vprotbi", + "xop.vprotd" => "__builtin_ia32_vprotd", + "xop.vprotdi" => "__builtin_ia32_vprotdi", + "xop.vprotq" => "__builtin_ia32_vprotq", + "xop.vprotqi" => "__builtin_ia32_vprotqi", + "xop.vprotw" => "__builtin_ia32_vprotw", + "xop.vprotwi" => "__builtin_ia32_vprotwi", + "xop.vpshab" => "__builtin_ia32_vpshab", + "xop.vpshad" => "__builtin_ia32_vpshad", + "xop.vpshaq" => "__builtin_ia32_vpshaq", + "xop.vpshaw" => "__builtin_ia32_vpshaw", + "xop.vpshlb" => "__builtin_ia32_vpshlb", + "xop.vpshld" => "__builtin_ia32_vpshld", + "xop.vpshlq" => "__builtin_ia32_vpshlq", + "xop.vpshlw" => "__builtin_ia32_vpshlw", + "xresldtrk" => "__builtin_ia32_xresldtrk", + "xsusldtrk" => "__builtin_ia32_xsusldtrk", + "xtest" => "__builtin_ia32_xtest", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + x86(name) + } + "xcore" => { + #[allow(non_snake_case)] + fn xcore(name: &str) -> &str { + match name { + // xcore + "bitrev" => "__builtin_bitrev", + "getid" => "__builtin_getid", + "getps" => "__builtin_getps", + "setps" => "__builtin_setps", + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } + } + xcore(name) + } + _ => unimplemented!("***** unsupported LLVM intrinsic {}", name), + } } diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs b/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs index 0eebd21001a..0b77694f115 100644 --- a/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs +++ b/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs @@ -1012,7 +1012,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function }; let func = cx.context.get_builtin_function(gcc_name); cx.functions.borrow_mut().insert(gcc_name.to_string(), func); - return func; + func } #[cfg(feature = "master")] @@ -1548,10 +1548,13 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.tcmmrlfp16ps" => "__builtin_trap", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py - _ => include!("archs.rs"), + _ => map_arch_intrinsic(name), }; let func = cx.context.get_target_builtin_function(gcc_name); cx.functions.borrow_mut().insert(gcc_name.to_string(), func); func } + +#[cfg(feature = "master")] +include!("archs.rs"); diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs b/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs index c921851b42b..09132c34aae 100644 --- a/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs +++ b/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs @@ -196,6 +196,95 @@ fn get_simple_function<'gcc, 'tcx>( )) } +fn get_simple_function_f128<'gcc, 'tcx>( + cx: &CodegenCx<'gcc, 'tcx>, + name: Symbol, +) -> Option<Function<'gcc>> { + if !cx.supports_f128_type { + return None; + } + + let f128_type = cx.type_f128(); + let func_name = match name { + sym::ceilf128 => "ceilf128", + sym::floorf128 => "floorf128", + sym::truncf128 => "truncf128", + sym::roundf128 => "roundf128", + sym::round_ties_even_f128 => "roundevenf128", + sym::sqrtf128 => "sqrtf128", + _ => return None, + }; + Some(cx.context.new_function( + None, + FunctionType::Extern, + f128_type, + &[cx.context.new_parameter(None, f128_type, "a")], + func_name, + false, + )) +} + +fn get_simple_function_f128_2args<'gcc, 'tcx>( + cx: &CodegenCx<'gcc, 'tcx>, + name: Symbol, +) -> Option<Function<'gcc>> { + if !cx.supports_f128_type { + return None; + } + + let f128_type = cx.type_f128(); + let func_name = match name { + sym::maxnumf128 => "fmaxf128", + sym::minnumf128 => "fminf128", + _ => return None, + }; + Some(cx.context.new_function( + None, + FunctionType::Extern, + f128_type, + &[ + cx.context.new_parameter(None, f128_type, "a"), + cx.context.new_parameter(None, f128_type, "b"), + ], + func_name, + false, + )) +} + +fn f16_builtin<'gcc, 'tcx>( + cx: &CodegenCx<'gcc, 'tcx>, + name: Symbol, + args: &[OperandRef<'tcx, RValue<'gcc>>], +) -> RValue<'gcc> { + let f32_type = cx.type_f32(); + let builtin_name = match name { + sym::ceilf16 => "__builtin_ceilf", + sym::floorf16 => "__builtin_floorf", + sym::fmaf16 => "fmaf", + sym::maxnumf16 => "__builtin_fmaxf", + sym::minnumf16 => "__builtin_fminf", + sym::powf16 => "__builtin_powf", + sym::powif16 => { + let func = cx.context.get_builtin_function("__builtin_powif"); + let arg0 = cx.context.new_cast(None, args[0].immediate(), f32_type); + let args = [arg0, args[1].immediate()]; + let result = cx.context.new_call(None, func, &args); + return cx.context.new_cast(None, result, cx.type_f16()); + } + sym::roundf16 => "__builtin_roundf", + sym::round_ties_even_f16 => "__builtin_rintf", + sym::sqrtf16 => "__builtin_sqrtf", + sym::truncf16 => "__builtin_truncf", + _ => unreachable!(), + }; + + let func = cx.context.get_builtin_function(builtin_name); + let args: Vec<_> = + args.iter().map(|arg| cx.context.new_cast(None, arg.immediate(), f32_type)).collect(); + let result = cx.context.new_call(None, func, &args); + cx.context.new_cast(None, result, cx.type_f16()) +} + impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { fn codegen_intrinsic_call( &mut self, @@ -211,7 +300,9 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc let fn_args = instance.args; let simple = get_simple_intrinsic(self, name); - let simple_func = get_simple_function(self, name); + let simple_func = get_simple_function(self, name) + .or_else(|| get_simple_function_f128(self, name)) + .or_else(|| get_simple_function_f128_2args(self, name)); // FIXME(tempdragon): Re-enable `clippy::suspicious_else_formatting` if the following issue is solved: // https://github.com/rust-lang/rust-clippy/issues/12497 @@ -234,17 +325,55 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc &args.iter().map(|arg| arg.immediate()).collect::<Vec<_>>(), ) } - sym::fmaf16 => { - // TODO(antoyo): use the correct builtin for f16. - let func = self.cx.context.get_builtin_function("fmaf"); - let args: Vec<_> = args - .iter() - .map(|arg| { - self.cx.context.new_cast(self.location, arg.immediate(), self.cx.type_f32()) - }) - .collect(); - let result = self.cx.context.new_call(self.location, func, &args); - self.cx.context.new_cast(self.location, result, self.cx.type_f16()) + sym::ceilf16 + | sym::floorf16 + | sym::fmaf16 + | sym::maxnumf16 + | sym::minnumf16 + | sym::powf16 + | sym::powif16 + | sym::roundf16 + | sym::round_ties_even_f16 + | sym::sqrtf16 + | sym::truncf16 => f16_builtin(self, name, args), + sym::fmaf128 => { + let f128_type = self.cx.type_f128(); + let func = self.cx.context.new_function( + None, + FunctionType::Extern, + f128_type, + &[ + self.cx.context.new_parameter(None, f128_type, "a"), + self.cx.context.new_parameter(None, f128_type, "b"), + self.cx.context.new_parameter(None, f128_type, "c"), + ], + "fmaf128", + false, + ); + self.cx.context.new_call( + self.location, + func, + &args.iter().map(|arg| arg.immediate()).collect::<Vec<_>>(), + ) + } + sym::powif128 => { + let f128_type = self.cx.type_f128(); + let func = self.cx.context.new_function( + None, + FunctionType::Extern, + f128_type, + &[ + self.cx.context.new_parameter(None, f128_type, "a"), + self.cx.context.new_parameter(None, self.int_type, "b"), + ], + "__powitf2", + false, + ); + self.cx.context.new_call( + self.location, + func, + &args.iter().map(|arg| arg.immediate()).collect::<Vec<_>>(), + ) } sym::is_val_statically_known => { let a = args[0].immediate(); @@ -526,7 +655,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc fn type_checked_load( &mut self, - _llvtable: Self::Value, + _vtable: Self::Value, _vtable_byte_offset: u64, _typeid: Self::Value, ) -> Self::Value { @@ -622,23 +751,23 @@ impl<'gcc, 'tcx> ArgAbiExt<'gcc, 'tcx> for ArgAbi<'tcx, Ty<'tcx>> { // We instead thus allocate some scratch space... let scratch_size = cast.size(bx); let scratch_align = cast.align(bx); - let llscratch = bx.alloca(scratch_size, scratch_align); - bx.lifetime_start(llscratch, scratch_size); + let scratch = bx.alloca(scratch_size, scratch_align); + bx.lifetime_start(scratch, scratch_size); // ... where we first store the value... - rustc_codegen_ssa::mir::store_cast(bx, cast, val, llscratch, scratch_align); + rustc_codegen_ssa::mir::store_cast(bx, cast, val, scratch, scratch_align); // ... and then memcpy it to the intended destination. bx.memcpy( dst.val.llval, self.layout.align.abi, - llscratch, + scratch, scratch_align, bx.const_usize(self.layout.size.bytes()), MemFlags::empty(), ); - bx.lifetime_end(llscratch, scratch_size); + bx.lifetime_end(scratch, scratch_size); } } else { OperandValue::Immediate(val).store(bx, dst); diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs b/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs index 82ef0d0b13a..6f6bc93b8b2 100644 --- a/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs +++ b/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs @@ -1081,7 +1081,9 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( let (_, element_ty1) = args[1].layout.ty.simd_size_and_type(bx.tcx()); let (_, element_ty2) = args[2].layout.ty.simd_size_and_type(bx.tcx()); let (pointer_count, underlying_ty) = match *element_ty1.kind() { - ty::RawPtr(p_ty, mutbl) if p_ty == in_elem && mutbl == hir::Mutability::Mut => { + ty::RawPtr(p_ty, mutability) + if p_ty == in_elem && mutability == hir::Mutability::Mut => + { (ptr_count(element_ty1), non_ptr(element_ty1)) } _ => { diff --git a/compiler/rustc_codegen_gcc/src/lib.rs b/compiler/rustc_codegen_gcc/src/lib.rs index dbecbc42618..aa57655921d 100644 --- a/compiler/rustc_codegen_gcc/src/lib.rs +++ b/compiler/rustc_codegen_gcc/src/lib.rs @@ -3,10 +3,12 @@ * TODO(antoyo): support #[inline] attributes. * TODO(antoyo): support LTO (gcc's equivalent to Full LTO is -flto -flto-partition=one — https://documentation.suse.com/sbp/all/html/SBP-GCC-10/index.html). * For Thin LTO, this might be helpful: +// cspell:disable-next-line * In gcc 4.6 -fwhopr was removed and became default with -flto. The non-whopr path can still be executed via -flto-partition=none. * Or the new incremental LTO (https://www.phoronix.com/news/GCC-Incremental-LTO-Patches)? * - * Maybe some missing optizations enabled by rustc's LTO is in there: https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html + * Maybe some missing optimizations enabled by rustc's LTO is in there: https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html +// cspell:disable-next-line * Like -fipa-icf (should be already enabled) and maybe -fdevirtualize-at-ltrans. * TODO: disable debug info always being emitted. Perhaps this slows down things? * @@ -206,7 +208,7 @@ impl CodegenBackend for GccCodegenBackend { #[cfg(not(feature = "master"))] { let temp_dir = TempDir::new().expect("cannot create temporary directory"); - let temp_file = temp_dir.into_path().join("result.asm"); + let temp_file = temp_dir.keep().join("result.asm"); let check_context = Context::default(); check_context.set_print_errors_to_stderr(false); let _int128_ty = check_context.new_c_type(CType::UInt128t); @@ -430,10 +432,11 @@ impl WriteBackendMethods for GccCodegenBackend { ) -> Result<ModuleCodegen<Self::Module>, FatalError> { back::write::link(cgcx, dcx, modules) } + fn autodiff( _cgcx: &CodegenContext<Self>, _module: &ModuleCodegen<Self::Module>, - _diff_fncs: Vec<AutoDiffItem>, + _diff_functions: Vec<AutoDiffItem>, _config: &ModuleConfig, ) -> Result<(), FatalError> { unimplemented!() @@ -494,12 +497,14 @@ fn target_config(sess: &Session, target_info: &LockedTargetInfo) -> TargetConfig return false; } target_info.cpu_supports(feature) + // cSpell:disable /* adx, aes, avx, avx2, avx512bf16, avx512bitalg, avx512bw, avx512cd, avx512dq, avx512er, avx512f, avx512fp16, avx512ifma, avx512pf, avx512vbmi, avx512vbmi2, avx512vl, avx512vnni, avx512vp2intersect, avx512vpopcntdq, bmi1, bmi2, cmpxchg16b, ermsb, f16c, fma, fxsr, gfni, lzcnt, movbe, pclmulqdq, popcnt, rdrand, rdseed, rtm, sha, sse, sse2, sse3, sse4.1, sse4.2, sse4a, ssse3, tbm, vaes, vpclmulqdq, xsave, xsavec, xsaveopt, xsaves */ + // cSpell:enable }) .map(Symbol::intern) .collect() @@ -508,13 +513,16 @@ fn target_config(sess: &Session, target_info: &LockedTargetInfo) -> TargetConfig let target_features = f(false); let unstable_target_features = f(true); + let has_reliable_f16 = target_info.supports_target_dependent_type(CType::Float16); + let has_reliable_f128 = target_info.supports_target_dependent_type(CType::Float128); + TargetConfig { target_features, unstable_target_features, // There are no known bugs with GCC support for f16 or f128 - has_reliable_f16: true, - has_reliable_f16_math: true, - has_reliable_f128: true, - has_reliable_f128_math: true, + has_reliable_f16, + has_reliable_f16_math: has_reliable_f16, + has_reliable_f128, + has_reliable_f128_math: has_reliable_f128, } } diff --git a/compiler/rustc_codegen_gcc/src/type_.rs b/compiler/rustc_codegen_gcc/src/type_.rs index 4e0a250b550..15a0206607e 100644 --- a/compiler/rustc_codegen_gcc/src/type_.rs +++ b/compiler/rustc_codegen_gcc/src/type_.rs @@ -302,13 +302,13 @@ impl<'gcc, 'tcx> BaseTypeCodegenMethods for CodegenCx<'gcc, 'tcx> { #[cfg_attr(feature = "master", allow(unused_mut))] fn type_array(&self, ty: Type<'gcc>, mut len: u64) -> Type<'gcc> { #[cfg(not(feature = "master"))] - if let Some(struct_type) = ty.is_struct() { - if struct_type.get_field_count() == 0 { - // NOTE: since gccjit only supports i32 for the array size and libcore's tests uses a - // size of usize::MAX in test_binary_search, we workaround this by setting the size to - // zero for ZSTs. - len = 0; - } + if let Some(struct_type) = ty.is_struct() + && struct_type.get_field_count() == 0 + { + // NOTE: since gccjit only supports i32 for the array size and libcore's tests uses a + // size of usize::MAX in test_binary_search, we workaround this by setting the size to + // zero for ZSTs. + len = 0; } self.context.new_array_type(None, ty, len) diff --git a/compiler/rustc_codegen_gcc/src/type_of.rs b/compiler/rustc_codegen_gcc/src/type_of.rs index 5745acce6fe..093f902bc3d 100644 --- a/compiler/rustc_codegen_gcc/src/type_of.rs +++ b/compiler/rustc_codegen_gcc/src/type_of.rs @@ -217,7 +217,7 @@ impl<'tcx> LayoutGccExt<'tcx> for TyAndLayout<'tcx> { let ty = match *self.ty.kind() { // NOTE: we cannot remove this match like in the LLVM codegen because the call // to fn_ptr_backend_type handle the on-stack attribute. - // TODO(antoyo): find a less hackish way to hande the on-stack attribute. + // TODO(antoyo): find a less hackish way to handle the on-stack attribute. ty::FnPtr(sig_tys, hdr) => cx .fn_ptr_backend_type(cx.fn_abi_of_fn_ptr(sig_tys.with(hdr), ty::List::empty())), _ => self.scalar_gcc_type_at(cx, scalar, Size::ZERO), diff --git a/compiler/rustc_codegen_gcc/tests/failing-ui-tests.txt b/compiler/rustc_codegen_gcc/tests/failing-ui-tests.txt index 0a01a661c35..d931f0d3b5e 100644 --- a/compiler/rustc_codegen_gcc/tests/failing-ui-tests.txt +++ b/compiler/rustc_codegen_gcc/tests/failing-ui-tests.txt @@ -1,26 +1,12 @@ tests/ui/allocator/no_std-alloc-error-handler-custom.rs tests/ui/allocator/no_std-alloc-error-handler-default.rs tests/ui/asm/may_unwind.rs -tests/ui/functions-closures/parallel-codegen-closures.rs -tests/ui/linkage-attr/linkage1.rs -tests/ui/lto/dylib-works.rs -tests/ui/sepcomp/sepcomp-cci.rs -tests/ui/sepcomp/sepcomp-extern.rs -tests/ui/sepcomp/sepcomp-fns-backwards.rs -tests/ui/sepcomp/sepcomp-fns.rs -tests/ui/sepcomp/sepcomp-statics.rs tests/ui/asm/x86_64/may_unwind.rs -tests/ui/panics/catch-unwind-bang.rs tests/ui/drop/dynamic-drop-async.rs tests/ui/cfg/cfg-panic-abort.rs -tests/ui/drop/repeat-drop.rs -tests/ui/coroutine/panic-drops-resume.rs -tests/ui/fmt/format-args-capture.rs -tests/ui/coroutine/panic-drops.rs tests/ui/intrinsics/panic-uninitialized-zeroed.rs tests/ui/iterators/iter-sum-overflow-debug.rs tests/ui/iterators/iter-sum-overflow-overflow-checks.rs -tests/ui/mir/mir_calls_to_shims.rs tests/ui/mir/mir_drop_order.rs tests/ui/mir/mir_let_chains_drop_order.rs tests/ui/oom_unwind.rs @@ -31,27 +17,15 @@ tests/ui/unwind-no-uwtable.rs tests/ui/parser/unclosed-delimiter-in-dep.rs tests/ui/consts/missing_span_in_backtrace.rs tests/ui/drop/dynamic-drop.rs -tests/ui/issues/issue-43853.rs -tests/ui/issues/issue-47364.rs -tests/ui/macros/rfc-2011-nicer-assert-messages/assert-without-captures-does-not-create-unnecessary-code.rs -tests/ui/rfcs/rfc-1857-stabilize-drop-order/drop-order.rs tests/ui/rfcs/rfc-2091-track-caller/std-panic-locations.rs tests/ui/simd/issue-17170.rs tests/ui/simd/issue-39720.rs -tests/ui/alloc-error/default-alloc-error-hook.rs -tests/ui/coroutine/panic-safe.rs tests/ui/issues/issue-14875.rs tests/ui/issues/issue-29948.rs -tests/ui/panics/nested_panic_caught.rs tests/ui/process/println-with-broken-pipe.rs tests/ui/lto/thin-lto-inlines2.rs -tests/ui/lto/weak-works.rs -tests/ui/panic-runtime/lto-abort.rs -tests/ui/lto/thin-lto-inlines.rs -tests/ui/lto/thin-lto-global-allocator.rs -tests/ui/lto/msvc-imp-present.rs +tests/ui/panic-runtime/lto-abort.rs tests/ui/lto/lto-thin-rustc-loads-linker-plugin.rs -tests/ui/lto/all-crates.rs tests/ui/async-await/deep-futures-are-freeze.rs tests/ui/coroutine/resume-after-return.rs tests/ui/simd/masked-load-store.rs @@ -59,15 +33,11 @@ tests/ui/simd/repr_packed.rs tests/ui/async-await/in-trait/dont-project-to-specializable-projection.rs tests/ui/consts/try-operator.rs tests/ui/coroutine/unwind-abort-mix.rs -tests/ui/type-alias-impl-trait/rpit_tait_equality_in_canonical_query.rs -tests/ui/impl-trait/equality-in-canonical-query.rs tests/ui/consts/issue-miri-1910.rs -tests/ui/mir/mir_heavy_promoted.rs tests/ui/consts/const_cmp_type_id.rs tests/ui/consts/issue-73976-monomorphic.rs tests/ui/consts/issue-94675.rs tests/ui/traits/const-traits/const-drop-fail.rs -tests/ui/traits/const-traits/const-drop.rs tests/ui/runtime/on-broken-pipe/child-processes.rs tests/ui/sanitizer/cfi/assoc-ty-lifetime-issue-123053.rs tests/ui/sanitizer/cfi/async-closures.rs @@ -85,14 +55,9 @@ tests/ui/sanitizer/cfi/can-reveal-opaques.rs tests/ui/sanitizer/kcfi-mangling.rs tests/ui/statics/const_generics.rs tests/ui/backtrace/dylib-dep.rs -tests/ui/errors/pic-linker.rs tests/ui/delegation/fn-header.rs -tests/ui/consts/zst_no_llvm_alloc.rs tests/ui/consts/const-eval/parse_ints.rs -tests/ui/simd/intrinsic/generic-arithmetic-pass.rs tests/ui/simd/intrinsic/generic-as.rs -tests/ui/backtrace/backtrace.rs -tests/ui/lifetimes/tail-expr-lock-poisoning.rs tests/ui/runtime/rt-explody-panic-payloads.rs tests/ui/codegen/equal-pointers-unequal/as-cast/inline1.rs tests/ui/codegen/equal-pointers-unequal/as-cast/inline2.rs @@ -108,4 +73,9 @@ tests/ui/codegen/equal-pointers-unequal/strict-provenance/segfault.rs tests/ui/codegen/equal-pointers-unequal/strict-provenance/zero.rs tests/ui/simd/simd-bitmask-notpow2.rs tests/ui/codegen/StackColoring-not-blowup-stack-issue-40883.rs +tests/ui/numbers-arithmetic/u128-as-f32.rs +tests/ui/lto/all-crates.rs tests/ui/uninhabited/uninhabited-transparent-return-abi.rs +tests/ui/coroutine/panic-drops-resume.rs +tests/ui/coroutine/panic-drops.rs +tests/ui/coroutine/panic-safe.rs diff --git a/compiler/rustc_codegen_gcc/tests/lang_tests_common.rs b/compiler/rustc_codegen_gcc/tests/lang_tests_common.rs index bdcf14b4b26..9abe97b1087 100644 --- a/compiler/rustc_codegen_gcc/tests/lang_tests_common.rs +++ b/compiler/rustc_codegen_gcc/tests/lang_tests_common.rs @@ -57,10 +57,10 @@ pub fn main_inner(profile: Profile) { #[cfg(not(feature = "master"))] fn filter(filename: &Path) -> bool { - if let Some(filename) = filename.to_str() { - if filename.ends_with("gep.rs") { - return false; - } + if let Some(filename) = filename.to_str() + && filename.ends_with("gep.rs") + { + return false; } rust_filter(filename) } diff --git a/compiler/rustc_codegen_gcc/tests/run/packed_u128.rs b/compiler/rustc_codegen_gcc/tests/run/packed_u128.rs new file mode 100644 index 00000000000..b7cc6e21023 --- /dev/null +++ b/compiler/rustc_codegen_gcc/tests/run/packed_u128.rs @@ -0,0 +1,31 @@ +// Compiler: +// +// Run-time: +// status: 0 + +#![feature(no_core)] +#![no_std] +#![no_core] +#![no_main] + +extern crate mini_core; +use intrinsics::black_box; +use mini_core::*; +#[repr(packed(1))] +pub struct ScalarInt { + data: u128, + size: u8, +} +#[inline(never)] +#[no_mangle] +fn read_data(a: &ScalarInt) { + black_box(a.data); +} + +#[no_mangle] +extern "C" fn main(argc: i32, _argv: *const *const u8) -> i32 { + let data = + [black_box(ScalarInt { data: 0, size: 1 }), black_box(ScalarInt { data: 0, size: 1 })]; + read_data(&data[1]); + 0 +} diff --git a/compiler/rustc_codegen_gcc/tools/cspell_dicts/rust.txt b/compiler/rustc_codegen_gcc/tools/cspell_dicts/rust.txt new file mode 100644 index 00000000000..379cbd77eef --- /dev/null +++ b/compiler/rustc_codegen_gcc/tools/cspell_dicts/rust.txt @@ -0,0 +1,2 @@ +lateout +repr diff --git a/compiler/rustc_codegen_gcc/tools/cspell_dicts/rustc_codegen_gcc.txt b/compiler/rustc_codegen_gcc/tools/cspell_dicts/rustc_codegen_gcc.txt new file mode 100644 index 00000000000..31023e50ffa --- /dev/null +++ b/compiler/rustc_codegen_gcc/tools/cspell_dicts/rustc_codegen_gcc.txt @@ -0,0 +1,75 @@ +aapcs +addo +archs +ashl +ashr +cgcx +clzll +cmse +codegened +csky +ctlz +ctpop +cttz +ctzll +flto +fmaximumf +fmuladd +fmuladdf +fminimumf +fmul +fptosi +fptosui +fptoui +fwrapv +gimple +hrtb +immediates +liblto +llbb +llcx +llextra +llfn +lgcc +llmod +llresult +llret +ltrans +llty +llval +llvals +loong +lshr +masm +maximumf +maxnumf +mavx +mcmodel +minimumf +minnumf +monomorphization +monomorphizations +monomorphized +monomorphizing +movnt +mulo +nvptx +pointee +powitf +reassoc +riscv +rlib +roundevenf +rustc +sitofp +sizet +spir +subo +sysv +tbaa +uitofp +unord +uninlined +utrunc +xabort +zext diff --git a/compiler/rustc_codegen_gcc/tools/generate_intrinsics.py b/compiler/rustc_codegen_gcc/tools/generate_intrinsics.py index 181f1e501a4..ed0ebf00719 100644 --- a/compiler/rustc_codegen_gcc/tools/generate_intrinsics.py +++ b/compiler/rustc_codegen_gcc/tools/generate_intrinsics.py @@ -168,25 +168,39 @@ def update_intrinsics(llvm_path, llvmint, llvmint2): os.path.dirname(os.path.abspath(__file__)), "../src/intrinsic/archs.rs", ) + # A hashmap of all architectures. This allows us to first match on the architecture, and then on the intrinsics. + # This speeds up the comparison, and makes our code considerably smaller. + # Since all intrinsic names start with "llvm.", we skip that prefix. print("Updating content of `{}`...".format(output_file)) with open(output_file, "w", encoding="utf8") as out: out.write("// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py`\n") out.write("// DO NOT EDIT IT!\n") - out.write("match name {\n") + out.write("/// Translate a given LLVM intrinsic name to an equivalent GCC one.\n") + out.write("fn map_arch_intrinsic(name:&str)->&str{\n") + out.write('let Some(name) = name.strip_prefix("llvm.") else { unimplemented!("***** unsupported LLVM intrinsic {}", name) };\n') + out.write('let Some((arch, name)) = name.split_once(\'.\') else { unimplemented!("***** unsupported LLVM intrinsic {}", name) };\n') + out.write("match arch {\n") for arch in archs: if len(intrinsics[arch]) == 0: continue + out.write("\"{}\" => {{ #[allow(non_snake_case)] fn {}(name: &str) -> &str {{ match name {{".format(arch,arch)) intrinsics[arch].sort(key=lambda x: (x[0], x[2])) out.write(' // {}\n'.format(arch)) for entry in intrinsics[arch]: + llvm_name = entry[0].removeprefix("llvm."); + llvm_name = llvm_name.removeprefix(arch); + llvm_name = llvm_name.removeprefix("."); if entry[2] is True: # if it is a duplicate - out.write(' // [DUPLICATE]: "{}" => "{}",\n'.format(entry[0], entry[1])) + out.write(' // [DUPLICATE]: "{}" => "{}",\n'.format(llvm_name, entry[1])) elif "_round_mask" in entry[1]: - out.write(' // [INVALID CONVERSION]: "{}" => "{}",\n'.format(entry[0], entry[1])) + out.write(' // [INVALID CONVERSION]: "{}" => "{}",\n'.format(llvm_name, entry[1])) else: - out.write(' "{}" => "{}",\n'.format(entry[0], entry[1])) - out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n') - out.write("}\n") + out.write(' "{}" => "{}",\n'.format(llvm_name, entry[1])) + out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n') + out.write("}} }} {}(name) }}\n,".format(arch)) + out.write(' _ => unimplemented!("***** unsupported LLVM architecture {}", name),\n') + out.write("}\n}") + subprocess.call(["rustfmt", output_file]) print("Done!") |