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| author | bors <bors@rust-lang.org> | 2025-02-25 02:24:40 +0000 |
|---|---|---|
| committer | bors <bors@rust-lang.org> | 2025-02-25 02:24:40 +0000 |
| commit | f5729cfed3c45e061e8a443677fc1d5ef9277df7 (patch) | |
| tree | c91747a4b57810c67589004322d9e46c5f099680 /compiler/rustc_codegen_llvm/src | |
| parent | 7d8c6e781d347e087c7d30ea393d7dcd725ed623 (diff) | |
| parent | 6c1f9592881b3e15bbd1157b45440e2bac289ed5 (diff) | |
| download | rust-f5729cfed3c45e061e8a443677fc1d5ef9277df7.tar.gz rust-f5729cfed3c45e061e8a443677fc1d5ef9277df7.zip | |
Auto merge of #137573 - compiler-errors:rollup-noq9yhp, r=compiler-errors
Rollup of 11 pull requests Successful merges: - #136522 (Remove `feature(dyn_compatible_for_dispatch)` from the compiler) - #137289 (Consolidate and improve error messaging for `CoerceUnsized` and `DispatchFromDyn`) - #137321 (Correct doc about `temp_dir()` behavior on Android) - #137417 (rustc_target: Add more RISC-V atomic-related features) - #137489 (remove `#[rustc_intrinsic_must_be_overridde]`) - #137530 (DWARF mixed versions with LTO on MIPS) - #137543 (std: Fix another new symlink test on Windows) - #137548 (Pass correct `TypingEnv` to `InlineAsmCtxt`) - #137550 (Don't immediately panic if dropck fails without returning errors) - #137552 (Update books) - #137556 (rename simd_shuffle_generic → simd_shuffle_const_generic) r? `@ghost` `@rustbot` modify labels: rollup
Diffstat (limited to 'compiler/rustc_codegen_llvm/src')
| -rw-r--r-- | compiler/rustc_codegen_llvm/src/intrinsic.rs | 2 | ||||
| -rw-r--r-- | compiler/rustc_codegen_llvm/src/llvm_util.rs | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs index dfbb5bc1731..56fae135e55 100644 --- a/compiler/rustc_codegen_llvm/src/intrinsic.rs +++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs @@ -1329,7 +1329,7 @@ fn generic_simd_intrinsic<'ll, 'tcx>( )); } - if name == sym::simd_shuffle_generic { + if name == sym::simd_shuffle_const_generic { let idx = fn_args[2].expect_const().to_value().valtree.unwrap_branch(); let n = idx.len() as u64; diff --git a/compiler/rustc_codegen_llvm/src/llvm_util.rs b/compiler/rustc_codegen_llvm/src/llvm_util.rs index b4b5d6a5b19..1fcb20e0d7b 100644 --- a/compiler/rustc_codegen_llvm/src/llvm_util.rs +++ b/compiler/rustc_codegen_llvm/src/llvm_util.rs @@ -281,6 +281,8 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea ("riscv32" | "riscv64", "zaamo") if get_version().0 < 19 => None, ("riscv32" | "riscv64", "zabha") if get_version().0 < 19 => None, ("riscv32" | "riscv64", "zalrsc") if get_version().0 < 19 => None, + ("riscv32" | "riscv64", "zama16b") if get_version().0 < 19 => None, + ("riscv32" | "riscv64", "zacas") if get_version().0 < 20 => None, // Enable the evex512 target feature if an avx512 target feature is enabled. ("x86", s) if s.starts_with("avx512") => { Some(LLVMFeature::with_dependency(s, TargetFeatureFoldStrength::EnableOnly("evex512"))) |