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authorMatthias Krüger <476013+matthiaskrgr@users.noreply.github.com>2025-08-27 07:45:55 +0200
committerGitHub <noreply@github.com>2025-08-27 07:45:55 +0200
commit7879cbbbfffc85bd7ecad79a623c618e608d98dc (patch)
treeafdec9bef763ffe59b5f399adcd16a813d631c10 /compiler/rustc_codegen_llvm
parent0c02bdc9016434f46d75b4be161a7e8d51b28bff (diff)
parentd47b5e4ab63df3774727e6dec542dade6ef22d9a (diff)
downloadrust-7879cbbbfffc85bd7ecad79a623c618e608d98dc.tar.gz
rust-7879cbbbfffc85bd7ecad79a623c618e608d98dc.zip
Rollup merge of #145078 - minxuanz:riscv-cacheline, r=samueltardieu
Fix wrong cache line size of riscv64

see https://go-review.googlesource.com/c/go/+/526659,  All of riscv CPU using 64B for cache-line size.
Diffstat (limited to 'compiler/rustc_codegen_llvm')
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