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authorTaiki Endo <te316e89@gmail.com>2024-11-29 00:24:36 +0900
committerTaiki Endo <te316e89@gmail.com>2024-11-29 00:24:36 +0900
commit0f8ebba54a8e41a9daccbbedae88e8798f4557c3 (patch)
tree6d566d32ae80069e6ce8ace413fbeb24e0617f3e /compiler/rustc_target/src/asm
parent9b4d7c6a40b328d212095c28670c629facf1557d (diff)
downloadrust-0f8ebba54a8e41a9daccbbedae88e8798f4557c3.tar.gz
rust-0f8ebba54a8e41a9daccbbedae88e8798f4557c3.zip
Support #[repr(simd)] types in input/output of PowerPC inline assembly
Diffstat (limited to 'compiler/rustc_target/src/asm')
-rw-r--r--compiler/rustc_target/src/asm/powerpc.rs6
1 files changed, 5 insertions, 1 deletions
diff --git a/compiler/rustc_target/src/asm/powerpc.rs b/compiler/rustc_target/src/asm/powerpc.rs
index aa8b26170be..a5a96b87e36 100644
--- a/compiler/rustc_target/src/asm/powerpc.rs
+++ b/compiler/rustc_target/src/asm/powerpc.rs
@@ -51,7 +51,11 @@ impl PowerPCInlineAsmRegClass {
                 }
             }
             Self::freg => types! { _: F32, F64; },
-            Self::vreg => &[],
+            // FIXME: vsx also supports integers and floats: https://github.com/rust-lang/rust/pull/131551#discussion_r1797651773
+            Self::vreg => types! {
+                altivec: VecI8(16), VecI16(8), VecI32(4), VecF32(4);
+                vsx: VecI64(2), VecF64(2);
+            },
             Self::cr | Self::xer => &[],
         }
     }