Add Vxworks RISC-V targets

3 files changed, 50 insertions, 0 deletions

diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
index f12e3e595ad..5a7d86991a2 100644
--- a/compiler/rustc_target/src/spec/mod.rs
+++ b/compiler/rustc_target/src/spec/mod.rs
@@ -1842,6 +1842,8 @@ supported_targets! {
     ("powerpc-wrs-vxworks", powerpc_wrs_vxworks),
     ("powerpc-wrs-vxworks-spe", powerpc_wrs_vxworks_spe),
     ("powerpc64-wrs-vxworks", powerpc64_wrs_vxworks),
+    ("riscv32-wrs-vxworks", riscv32_wrs_vxworks),
+    ("riscv64-wrs-vxworks", riscv64_wrs_vxworks),
 
     ("aarch64-kmc-solid_asp3", aarch64_kmc_solid_asp3),
     ("armv7a-kmc-solid_asp3-eabi", armv7a_kmc_solid_asp3_eabi),
diff --git a/compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs b/compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs
new file mode 100644
index 00000000000..4a6f7950b87
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs
@@ -0,0 +1,24 @@
+use crate::spec::{base, StackProbeType, Target, TargetOptions};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "riscv32".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: None,
+            tier: Some(3),
+            host_tools: Some(false),
+            std: None, // STD is a work in progress for this target arch
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
+        arch: "riscv32".into(),
+        options: TargetOptions {
+            cpu: "generic-rv32".into(),
+            llvm_abiname: "ilp32d".into(),
+            max_atomic_width: Some(32),
+            features: "+m,+a,+f,+d,+c,+zicsr".into(),
+            stack_probes: StackProbeType::Inline,
+            ..base::vxworks::opts()
+        },
+    }
+}
diff --git a/compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs b/compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs
new file mode 100644
index 00000000000..b0914871a64
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs
@@ -0,0 +1,24 @@
+use crate::spec::{base, StackProbeType, Target, TargetOptions};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "riscv64".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: None,
+            tier: Some(3),
+            host_tools: Some(false),
+            std: None, // STD is a work in progress for this target arch
+        },
+        pointer_width: 64,
+        data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(),
+        arch: "riscv64".into(),
+        options: TargetOptions {
+            cpu: "generic-rv64".into(),
+            llvm_abiname: "lp64d".into(),
+            max_atomic_width: Some(64),
+            features: "+m,+a,+f,+d,+c,+zicsr".into(),
+            stack_probes: StackProbeType::Inline,
+            ..base::vxworks::opts()
+        },
+    }
+}