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| author | Matthias Krüger <matthias.krueger@famsik.de> | 2022-12-24 00:31:41 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-24 00:31:41 +0100 |
| commit | d23cb738d255ca1a9834fbe87ba8700b3d7da23f (patch) | |
| tree | d821a3713007d0ed74b75c66b8df0fcca1d11e3e /compiler/rustc_target/src | |
| parent | e08dd9d998a697a8da791ee183db468e4de7aa72 (diff) | |
| parent | 1174aacf598d01b3e063668bb6ecd9c472688d02 (diff) | |
| download | rust-d23cb738d255ca1a9834fbe87ba8700b3d7da23f.tar.gz rust-d23cb738d255ca1a9834fbe87ba8700b3d7da23f.zip | |
Rollup merge of #105975 - jeremystucki:rustc-remove-needless-lifetimes, r=eholk
rustc: Remove needless lifetimes
Diffstat (limited to 'compiler/rustc_target/src')
| -rw-r--r-- | compiler/rustc_target/src/abi/call/loongarch.rs | 4 | ||||
| -rw-r--r-- | compiler/rustc_target/src/abi/call/riscv.rs | 4 | ||||
| -rw-r--r-- | compiler/rustc_target/src/spec/mod.rs | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/compiler/rustc_target/src/abi/call/loongarch.rs b/compiler/rustc_target/src/abi/call/loongarch.rs index d29b479de5d..4a2d39cc700 100644 --- a/compiler/rustc_target/src/abi/call/loongarch.rs +++ b/compiler/rustc_target/src/abi/call/loongarch.rs @@ -19,7 +19,7 @@ enum FloatConv { #[derive(Copy, Clone)] struct CannotUseFpConv; -fn is_loongarch_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool { +fn is_loongarch_aggregate<Ty>(arg: &ArgAbi<'_, Ty>) -> bool { match arg.layout.abi { Abi::Vector { .. } => true, _ => arg.layout.is_aggregate(), @@ -290,7 +290,7 @@ fn classify_arg<'a, Ty, C>( } } -fn extend_integer_width<'a, Ty>(arg: &mut ArgAbi<'a, Ty>, xlen: u64) { +fn extend_integer_width<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64) { if let Abi::Scalar(scalar) = arg.layout.abi { if let abi::Int(i, _) = scalar.primitive() { // 32-bit integers are always sign-extended diff --git a/compiler/rustc_target/src/abi/call/riscv.rs b/compiler/rustc_target/src/abi/call/riscv.rs index 1cb360f834e..34280d38e34 100644 --- a/compiler/rustc_target/src/abi/call/riscv.rs +++ b/compiler/rustc_target/src/abi/call/riscv.rs @@ -25,7 +25,7 @@ enum FloatConv { #[derive(Copy, Clone)] struct CannotUseFpConv; -fn is_riscv_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool { +fn is_riscv_aggregate<Ty>(arg: &ArgAbi<'_, Ty>) -> bool { match arg.layout.abi { Abi::Vector { .. } => true, _ => arg.layout.is_aggregate(), @@ -296,7 +296,7 @@ fn classify_arg<'a, Ty, C>( } } -fn extend_integer_width<'a, Ty>(arg: &mut ArgAbi<'a, Ty>, xlen: u64) { +fn extend_integer_width<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64) { if let Abi::Scalar(scalar) = arg.layout.abi { if let abi::Int(i, _) = scalar.primitive() { // 32-bit integers are always sign-extended diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index be994eda14c..988cd401f40 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -1319,7 +1319,7 @@ pub struct Target { } impl Target { - pub fn parse_data_layout<'a>(&'a self) -> Result<TargetDataLayout, TargetDataLayoutErrors<'a>> { + pub fn parse_data_layout(&self) -> Result<TargetDataLayout, TargetDataLayoutErrors<'_>> { let mut dl = TargetDataLayout::parse_from_llvm_datalayout_string(&self.data_layout)?; // Perform consistency checks against the Target information. |
