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| author | Folkert de Vries <folkert@folkertdev.nl> | 2025-07-10 16:17:07 +0200 |
|---|---|---|
| committer | Folkert de Vries <folkert@folkertdev.nl> | 2025-07-15 20:20:46 +0200 |
| commit | f6f6715990a8cb49fbbaf83e65fd884e0d63d17d (patch) | |
| tree | d16d1c1aa5dc4d9f0a49586b4ef7856a029ece09 /library/stdarch/crates | |
| parent | f8de93acbe41241d6a17c6ba9cba663f9588fe43 (diff) | |
| download | rust-f6f6715990a8cb49fbbaf83e65fd884e0d63d17d.tar.gz rust-f6f6715990a8cb49fbbaf83e65fd884e0d63d17d.zip | |
s390x: fix tests that matched on prefix of instruction
Diffstat (limited to 'library/stdarch/crates')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/s390x/vector.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/library/stdarch/crates/core_arch/src/s390x/vector.rs b/library/stdarch/crates/core_arch/src/s390x/vector.rs index 63205f13ccc..a09a27a029c 100644 --- a/library/stdarch/crates/core_arch/src/s390x/vector.rs +++ b/library/stdarch/crates/core_arch/src/s390x/vector.rs @@ -2265,14 +2265,14 @@ mod sealed { #[inline] #[target_feature(enable = "vector")] - #[cfg_attr(test, assert_instr("vlbb"))] + #[cfg_attr(test, assert_instr(vlbb))] unsafe fn test_vec_load_bndry(ptr: *const i32) -> MaybeUninit<vector_signed_int> { vector_signed_int::vec_load_bndry::<512>(ptr) } #[inline] #[target_feature(enable = "vector")] - #[cfg_attr(test, assert_instr(vst))] + #[cfg_attr(test, assert_instr(vstl))] unsafe fn test_vec_store_len(vector: vector_signed_int, ptr: *mut i32, byte_count: u32) { vector.vec_store_len(ptr, byte_count) } @@ -2798,11 +2798,11 @@ mod sealed { } test_impl! { vec_vmal_ib(a: vector_signed_char, b: vector_signed_char, c: vector_signed_char) -> vector_signed_char [simd_mladd, vmalb ] } - test_impl! { vec_vmal_ih(a: vector_signed_short, b: vector_signed_short, c: vector_signed_short) -> vector_signed_short[simd_mladd, vmalh ] } + test_impl! { vec_vmal_ih(a: vector_signed_short, b: vector_signed_short, c: vector_signed_short) -> vector_signed_short[simd_mladd, vmalhw ] } test_impl! { vec_vmal_if(a: vector_signed_int, b: vector_signed_int, c: vector_signed_int) -> vector_signed_int [simd_mladd, vmalf ] } test_impl! { vec_vmal_ub(a: vector_unsigned_char, b: vector_unsigned_char, c: vector_unsigned_char) -> vector_unsigned_char [simd_mladd, vmalb ] } - test_impl! { vec_vmal_uh(a: vector_unsigned_short, b: vector_unsigned_short, c: vector_unsigned_short) -> vector_unsigned_short[simd_mladd, vmalh ] } + test_impl! { vec_vmal_uh(a: vector_unsigned_short, b: vector_unsigned_short, c: vector_unsigned_short) -> vector_unsigned_short[simd_mladd, vmalhw ] } test_impl! { vec_vmal_uf(a: vector_unsigned_int, b: vector_unsigned_int, c: vector_unsigned_int) -> vector_unsigned_int [simd_mladd, vmalf ] } impl_mul!([VectorMladd vec_mladd] vec_vmal_ib (vector_signed_char, vector_signed_char, vector_signed_char) -> vector_signed_char ); |
