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authorPatrick Walton <pcwalton@mimiga.net>2013-03-22 18:52:04 -0700
committerPatrick Walton <pcwalton@mimiga.net>2013-03-26 21:29:34 -0700
commit142dbd65da9ae168c198162f0e1eec1c960e91f5 (patch)
treed403258aa9f4b33b7695a08100ce5454d49584b0 /src/libcore
parent46d4cc12d1f2b1c7b13d19ae88d123523e3e3964 (diff)
downloadrust-142dbd65da9ae168c198162f0e1eec1c960e91f5.tar.gz
rust-142dbd65da9ae168c198162f0e1eec1c960e91f5.zip
librustc: Remove all uses of the old `[T * N]` fixed-length vector syntax
Diffstat (limited to 'src/libcore')
-rw-r--r--src/libcore/cleanup.rs10
-rw-r--r--src/libcore/hash.rs6
-rw-r--r--src/libcore/libc.rs8
-rw-r--r--src/libcore/num/strconv.rs10
-rw-r--r--src/libcore/rt/context.rs6
-rw-r--r--src/libcore/sys.rs2
-rw-r--r--src/libcore/trie.rs2
-rw-r--r--src/libcore/vec.rs2
8 files changed, 24 insertions, 22 deletions
diff --git a/src/libcore/cleanup.rs b/src/libcore/cleanup.rs
index 66eeb339700..3beb1add3ea 100644
--- a/src/libcore/cleanup.rs
+++ b/src/libcore/cleanup.rs
@@ -38,12 +38,12 @@ struct MemoryRegion { priv opaque: () }
 #[cfg(target_arch="x86")]
 #[cfg(target_arch="arm")]
 struct Registers {
-    data: [u32 * 16]
+    data: [u32, ..16]
 }
 
 #[cfg(target_arch="mips")]
 struct Registers {
-    data: [u32 * 32]
+    data: [u32, ..32]
 }
 
 #[cfg(target_arch="x86")]
@@ -52,12 +52,12 @@ struct Registers {
 struct Context {
     regs: Registers,
     next: *Context,
-    pad: [u32 * 3]
+    pad: [u32, ..3]
 }
 
 #[cfg(target_arch="x86_64")]
 struct Registers {
-    data: [u64 * 22]
+    data: [u64, ..22]
 }
 
 #[cfg(target_arch="x86_64")]
@@ -80,7 +80,7 @@ struct Task {
     // Public fields
     refcount: intptr_t,                 // 0
     id: TaskID,                         // 4
-    pad: [u32 * 2],                     // 8
+    pad: [u32, ..2],                    // 8
     ctx: Context,                       // 16
     stack_segment: *StackSegment,       // 96
     runtime_sp: uintptr_t,              // 100
diff --git a/src/libcore/hash.rs b/src/libcore/hash.rs
index c1e9e658df0..7b3b49b7ee9 100644
--- a/src/libcore/hash.rs
+++ b/src/libcore/hash.rs
@@ -162,7 +162,7 @@ struct SipState {
     mut v1: u64,
     mut v2: u64,
     mut v3: u64,
-    mut tail: [u8 * 8], // unprocessed bytes
+    mut tail: [u8, ..8], // unprocessed bytes
     mut ntail: uint,  // how many bytes in tail are valid
 }
 
@@ -369,7 +369,7 @@ impl Streaming for SipState {
 
 #[test]
 pub fn test_siphash() {
-    let vecs : [[u8 * 8] * 64] = [
+    let vecs : [[u8, ..8], ..64] = [
         [ 0x31, 0x0e, 0x0e, 0xdd, 0x47, 0xdb, 0x6f, 0x72, ],
         [ 0xfd, 0x67, 0xdc, 0x93, 0xc5, 0x39, 0xf8, 0x74, ],
         [ 0x5a, 0x4f, 0xa9, 0xd9, 0x09, 0x80, 0x6c, 0x0d, ],
@@ -443,7 +443,7 @@ pub fn test_siphash() {
     let stream_inc = &State(k0,k1);
     let stream_full = &State(k0,k1);
 
-    fn to_hex_str(r:  &[u8 * 8]) -> ~str {
+    fn to_hex_str(r:  &[u8, ..8]) -> ~str {
         let mut s = ~"";
         for vec::each(*r) |b| {
             s += uint::to_str_radix(*b as uint, 16u);
diff --git a/src/libcore/libc.rs b/src/libcore/libc.rs
index 47eece81ce1..084437354fb 100644
--- a/src/libcore/libc.rs
+++ b/src/libcore/libc.rs
@@ -342,7 +342,7 @@ pub mod types {
                     st_mtime_nsec: c_long,
                     st_ctime: time_t,
                     st_ctime_nsec: c_long,
-                    __unused: [c_long * 3],
+                    __unused: [c_long, ..3],
                 }
             }
             pub mod posix08 {
@@ -430,7 +430,7 @@ pub mod types {
                     st_lspare: int32_t,
                     st_birthtime: time_t,
                     st_birthtime_nsec: c_long,
-                    __unused: [uint8_t * 2],
+                    __unused: [uint8_t, ..2],
                 }
             }
             pub mod posix08 {
@@ -631,7 +631,7 @@ pub mod types {
                     st_flags: uint32_t,
                     st_gen: uint32_t,
                     st_lspare: int32_t,
-                    st_qspare: [int64_t * 2],
+                    st_qspare: [int64_t, ..2],
                 }
             }
             pub mod posix08 {
@@ -712,7 +712,7 @@ pub mod types {
                     st_flags: uint32_t,
                     st_gen: uint32_t,
                     st_lspare: int32_t,
-                    st_qspare: [int64_t * 2],
+                    st_qspare: [int64_t, ..2],
                 }
             }
             pub mod posix08 {
diff --git a/src/libcore/num/strconv.rs b/src/libcore/num/strconv.rs
index ce6c015c131..5299203eb42 100644
--- a/src/libcore/num/strconv.rs
+++ b/src/libcore/num/strconv.rs
@@ -132,10 +132,12 @@ impl_NumStrConv_Integer!(u64)
 
 
 // Special value strings as [u8] consts.
-static inf_buf:          [u8*3] = ['i' as u8, 'n' as u8, 'f' as u8];
-static positive_inf_buf: [u8*4] = ['+' as u8, 'i' as u8, 'n' as u8, 'f' as u8];
-static negative_inf_buf: [u8*4] = ['-' as u8, 'i' as u8, 'n' as u8, 'f' as u8];
-static nan_buf:          [u8*3] = ['N' as u8, 'a' as u8, 'N' as u8];
+static inf_buf:          [u8, ..3] = ['i' as u8, 'n' as u8, 'f' as u8];
+static positive_inf_buf: [u8, ..4] = ['+' as u8, 'i' as u8, 'n' as u8,
+                                      'f' as u8];
+static negative_inf_buf: [u8, ..4] = ['-' as u8, 'i' as u8, 'n' as u8,
+                                      'f' as u8];
+static nan_buf:          [u8, ..3] = ['N' as u8, 'a' as u8, 'N' as u8];
 
 /**
  * Converts a number to its string representation as a byte vector.
diff --git a/src/libcore/rt/context.rs b/src/libcore/rt/context.rs
index 527acd4d1b1..7237fe118d8 100644
--- a/src/libcore/rt/context.rs
+++ b/src/libcore/rt/context.rs
@@ -123,7 +123,7 @@ fn initialize_call_frame(regs: &mut Registers, fptr: *c_void, arg: *c_void, sp:
 }
 
 #[cfg(target_arch = "x86_64")]
-type Registers = [uint * 22];
+type Registers = [uint, ..22];
 
 #[cfg(target_arch = "x86_64")]
 fn new_regs() -> ~Registers { ~[0, .. 22] }
@@ -157,7 +157,7 @@ fn initialize_call_frame(regs: &mut Registers, fptr: *c_void, arg: *c_void, sp:
 }
 
 #[cfg(target_arch = "arm")]
-type Registers = [uint * 32];
+type Registers = [uint, ..32];
 
 #[cfg(target_arch = "arm")]
 fn new_regs() -> ~Registers { ~[0, .. 32] }
@@ -175,7 +175,7 @@ fn initialize_call_frame(regs: &mut Registers, fptr: *c_void, arg: *c_void, sp:
 }
 
 #[cfg(target_arch = "mips")]
-type Registers = [uint * 32];
+type Registers = [uint, ..32];
 
 #[cfg(target_arch = "mips")]
 fn new_regs() -> ~Registers { ~[0, .. 32] }
diff --git a/src/libcore/sys.rs b/src/libcore/sys.rs
index 706cb10dba9..69991259cf2 100644
--- a/src/libcore/sys.rs
+++ b/src/libcore/sys.rs
@@ -194,7 +194,7 @@ pub mod tests {
 
     #[test]
     pub fn nonzero_size_of_basic() {
-        type Z = [i8 * 0];
+        type Z = [i8, ..0];
         fail_unless!(size_of::<Z>() == 0u);
         fail_unless!(nonzero_size_of::<Z>() == 1u);
         fail_unless!(nonzero_size_of::<uint>() == size_of::<uint>());
diff --git a/src/libcore/trie.rs b/src/libcore/trie.rs
index 012e0055674..4c4be33ea17 100644
--- a/src/libcore/trie.rs
+++ b/src/libcore/trie.rs
@@ -223,7 +223,7 @@ pub impl TrieSet {
 
 struct TrieNode<T> {
     count: uint,
-    children: [Child<T> * SIZE]
+    children: [Child<T>, ..SIZE]
 }
 
 impl<T> TrieNode<T> {
diff --git a/src/libcore/vec.rs b/src/libcore/vec.rs
index afacffb92c9..256b4c4922e 100644
--- a/src/libcore/vec.rs
+++ b/src/libcore/vec.rs
@@ -2636,7 +2636,7 @@ mod tests {
 
     #[test]
     fn test_len_divzero() {
-        type Z = [i8 * 0];
+        type Z = [i8, ..0];
         let v0 : &[Z] = &[];
         let v1 : &[Z] = &[[]];
         let v2 : &[Z] = &[[], []];