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| author | Michal Sudwoj <msudwoj@student.ethz.ch> | 2020-05-22 14:38:46 +0200 |
|---|---|---|
| committer | Michal Sudwoj <msudwoj@student.ethz.ch> | 2020-05-24 08:20:40 +0200 |
| commit | baa801a92900d1a44ab5efb005b4bbb0353af206 (patch) | |
| tree | 28d2798ba9f793f4505daac72bdb45bcb69a61fd /src/librustc_codegen_llvm/asm.rs | |
| parent | d77f73e8818453afd513f96e98cf7e0c889cdbd9 (diff) | |
| download | rust-baa801a92900d1a44ab5efb005b4bbb0353af206.tar.gz rust-baa801a92900d1a44ab5efb005b4bbb0353af206.zip | |
Minor fixes, as requested in PR review
Diffstat (limited to 'src/librustc_codegen_llvm/asm.rs')
| -rw-r--r-- | src/librustc_codegen_llvm/asm.rs | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/librustc_codegen_llvm/asm.rs b/src/librustc_codegen_llvm/asm.rs index fe4cd16c1f5..f3b46dd322a 100644 --- a/src/librustc_codegen_llvm/asm.rs +++ b/src/librustc_codegen_llvm/asm.rs @@ -414,8 +414,6 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String { InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h", InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r", InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l", - InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg32) => "f", - InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg64) => "d", InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r", InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f", InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r", @@ -512,8 +510,6 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(), InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(), InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(), - InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg32) => cx.type_f32(), - InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::freg64) => cx.type_f64(), InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(), InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(), InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) |