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authorRichard Diamond <wichard@vitalitystudios.com>2018-07-18 22:05:08 -0500
committerRichard Diamond <wichard@vitalitystudios.com>2018-08-23 14:31:10 -0500
commit66e8e1953e25a8d9e86e2e3fef88cc178a9cea02 (patch)
treef13711411e4cf5497f5252652b1b5e187b6eab63 /src/librustc_codegen_llvm/builder.rs
parentbfddedee37d69a4d2180f8c5e7dba000762618e9 (diff)
downloadrust-66e8e1953e25a8d9e86e2e3fef88cc178a9cea02.tar.gz
rust-66e8e1953e25a8d9e86e2e3fef88cc178a9cea02.zip
Fix an AMDGPU related load bit range metadata assertion.
Diffstat (limited to 'src/librustc_codegen_llvm/builder.rs')
-rw-r--r--src/librustc_codegen_llvm/builder.rs8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/librustc_codegen_llvm/builder.rs b/src/librustc_codegen_llvm/builder.rs
index cfbc2ab9007..e3526a5a2ee 100644
--- a/src/librustc_codegen_llvm/builder.rs
+++ b/src/librustc_codegen_llvm/builder.rs
@@ -496,6 +496,14 @@ impl Builder<'a, 'll, 'tcx> {
 
 
     pub fn range_metadata(&self, load: &'ll Value, range: Range<u128>) {
+        if self.sess().target.target.arch == "amdgpu" {
+            // amdgpu/LLVM does something weird and thinks a i64 value is
+            // split into a v2i32, halving the bitwidth LLVM expects,
+            // tripping an assertion. So, for now, just disable this
+            // optimization.
+            return;
+        }
+
         unsafe {
             let llty = val_ty(load);
             let v = [