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| author | Scott McMurray <scottmcm@users.noreply.github.com> | 2022-03-05 23:51:10 -0800 |
|---|---|---|
| committer | Scott McMurray <scottmcm@users.noreply.github.com> | 2022-03-10 01:19:02 -0800 |
| commit | 54408f096377190a7faf67cb7ef4eda6e1ed4700 (patch) | |
| tree | 7677ca8c72b99562057f8b1f18b8e83d1c48667e /src/test/codegen | |
| parent | b5a54d8777f00141954527a118715b1a36981b73 (diff) | |
| download | rust-54408f096377190a7faf67cb7ef4eda6e1ed4700.tar.gz rust-54408f096377190a7faf67cb7ef4eda6e1ed4700.zip | |
short-circuit the easy cases in `is_copy_modulo_regions`
This change is somewhat extensive, since it affects MIR -- since this is called to determine Copy vs Move -- so any test that's `no_core` needs to actually have the normal `impl`s it uses.
Diffstat (limited to 'src/test/codegen')
| -rw-r--r-- | src/test/codegen/abi-sysv64.rs | 1 | ||||
| -rw-r--r-- | src/test/codegen/abi-x86-interrupt.rs | 1 | ||||
| -rw-r--r-- | src/test/codegen/frame-pointer.rs | 2 | ||||
| -rw-r--r-- | src/test/codegen/riscv-abi/riscv64-lp64-lp64f-lp64d-abi.rs | 8 |
4 files changed, 11 insertions, 1 deletions
diff --git a/src/test/codegen/abi-sysv64.rs b/src/test/codegen/abi-sysv64.rs index bb910d573b3..dfc31227908 100644 --- a/src/test/codegen/abi-sysv64.rs +++ b/src/test/codegen/abi-sysv64.rs @@ -13,6 +13,7 @@ trait Sized {} #[lang = "copy"] trait Copy {} +impl Copy for i64 {} // CHECK: define x86_64_sysvcc i64 @has_sysv64_abi #[no_mangle] diff --git a/src/test/codegen/abi-x86-interrupt.rs b/src/test/codegen/abi-x86-interrupt.rs index 119004d261d..d612f603e4f 100644 --- a/src/test/codegen/abi-x86-interrupt.rs +++ b/src/test/codegen/abi-x86-interrupt.rs @@ -13,6 +13,7 @@ trait Sized {} #[lang = "copy"] trait Copy {} +impl Copy for i64 {} // CHECK: define x86_intrcc i64 @has_x86_interrupt_abi #[no_mangle] diff --git a/src/test/codegen/frame-pointer.rs b/src/test/codegen/frame-pointer.rs index 367591dcb96..f7c02d47939 100644 --- a/src/test/codegen/frame-pointer.rs +++ b/src/test/codegen/frame-pointer.rs @@ -17,7 +17,7 @@ trait Sized { } #[lang="copy"] trait Copy { } - +impl Copy for u32 {} // CHECK: define i32 @peach{{.*}}[[PEACH_ATTRS:\#[0-9]+]] { diff --git a/src/test/codegen/riscv-abi/riscv64-lp64-lp64f-lp64d-abi.rs b/src/test/codegen/riscv-abi/riscv64-lp64-lp64f-lp64d-abi.rs index faf81b5ae76..7f0f678062a 100644 --- a/src/test/codegen/riscv-abi/riscv64-lp64-lp64f-lp64d-abi.rs +++ b/src/test/codegen/riscv-abi/riscv64-lp64-lp64f-lp64d-abi.rs @@ -10,6 +10,14 @@ trait Sized {} #[lang = "copy"] trait Copy {} +impl Copy for bool {} +impl Copy for i8 {} +impl Copy for u8 {} +impl Copy for i32 {} +impl Copy for i64 {} +impl Copy for u64 {} +impl Copy for f32 {} +impl Copy for f64 {} // CHECK: define void @f_void() #[no_mangle] |