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authorFolkert <folkert@folkertdev.nl>2024-05-11 21:16:38 +0200
committerFolkert <folkert@folkertdev.nl>2024-05-11 21:58:25 +0200
commit4a4535a57cef0182d516888f1abb5d4a9ec84fdc (patch)
treea82dac497730b516281d15be59e621dfa23d9e87 /src
parent9e4e8054882de9e0f9496e415eecd5205a52f0e7 (diff)
downloadrust-4a4535a57cef0182d516888f1abb5d4a9ec84fdc.tar.gz
rust-4a4535a57cef0182d516888f1abb5d4a9ec84fdc.zip
add `llvm.x86.avx2.permd` intrinsic
Diffstat (limited to 'src')
-rw-r--r--src/intrinsics/llvm_x86.rs15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/intrinsics/llvm_x86.rs b/src/intrinsics/llvm_x86.rs
index 8df83c706a1..f0c48884745 100644
--- a/src/intrinsics/llvm_x86.rs
+++ b/src/intrinsics/llvm_x86.rs
@@ -374,6 +374,21 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
                 }
             }
         }
+        "llvm.x86.avx2.permd" => {
+            // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutevar8x32_epi32
+            intrinsic_args!(fx, args => (a, idx); intrinsic);
+
+            for j in 0..=7 {
+                let index = idx.value_typed_lane(fx, fx.tcx.types.u32, j).load_scalar(fx);
+                let index = fx.bcx.ins().uextend(fx.pointer_type, index);
+                let value = a.value_lane_dyn(fx, index).load_scalar(fx);
+                ret.place_typed_lane(fx, fx.tcx.types.u32, j).to_ptr().store(
+                    fx,
+                    value,
+                    MemFlags::trusted(),
+                );
+            }
+        }
         "llvm.x86.avx2.vperm2i128"
         | "llvm.x86.avx.vperm2f128.ps.256"
         | "llvm.x86.avx.vperm2f128.pd.256" => {