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| author | Caiweiran <cai.weiran.zte.com.cn> | 2025-07-23 11:23:36 +0000 |
|---|---|---|
| committer | Caiweiran <cai.weiran.zte.com.cn> | 2025-07-23 11:23:36 +0000 |
| commit | 2e49c52855c6a726d4f42705fe42d3c237f14b32 (patch) | |
| tree | e3128c6c06e5f78bc5b9fb2d9b9cd74d1a73349d /tests/codegen-llvm/const-vector.rs | |
| parent | a7a1618e6c835f1f00940ad72203d05808209a0d (diff) | |
| download | rust-2e49c52855c6a726d4f42705fe42d3c237f14b32.tar.gz rust-2e49c52855c6a726d4f42705fe42d3c237f14b32.zip | |
Fix tests/codegen-llvm/const-vector.rs test failure on riscv64
Diffstat (limited to 'tests/codegen-llvm/const-vector.rs')
| -rw-r--r-- | tests/codegen-llvm/const-vector.rs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/codegen-llvm/const-vector.rs b/tests/codegen-llvm/const-vector.rs index a2249f4fff7..f4307492341 100644 --- a/tests/codegen-llvm/const-vector.rs +++ b/tests/codegen-llvm/const-vector.rs @@ -15,6 +15,7 @@ #![feature(arm_target_feature)] #![feature(mips_target_feature)] #![allow(non_camel_case_types)] +#![feature(riscv_target_feature)] #[path = "../auxiliary/minisimd.rs"] mod minisimd; @@ -42,6 +43,7 @@ extern "unadjusted" { #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] pub fn do_call() { unsafe { // CHECK: call void @test_i8x2(<2 x i8> <i8 32, i8 64> |