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| author | Trevor Gross <t.gross35@gmail.com> | 2025-07-26 01:15:07 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-26 01:15:07 -0500 |
| commit | a262dadc4022b86592ca9b62642413bcf3e9b117 (patch) | |
| tree | e4631871038b1ad04ddfc3449db006380d56b977 /tests/codegen-llvm | |
| parent | e30017ba3e770f6c636ad51099f0ea6139b9d415 (diff) | |
| parent | 2e49c52855c6a726d4f42705fe42d3c237f14b32 (diff) | |
| download | rust-a262dadc4022b86592ca9b62642413bcf3e9b117.tar.gz rust-a262dadc4022b86592ca9b62642413bcf3e9b117.zip | |
Rollup merge of #144341 - CaiWeiran:const-vector_test, r=wesleywiser
Enable const-vector.rs test on RISC-V (riscv64) This PR replaces [#144283](https://github.com/rust-lang/rust/pull/144283) to resolve merge conflicts. This PR adds support for running the `tests/codegen/const-vector.rs` test on the RISC-V (riscv64) architecture. Previously, this test would fail on RISC-V targets due to architecture-specific code generation issues. This patch modifies the test to ensure compatibility while preserving its intent. The change has been tested locally using `./x test` on a riscv64 target, and the test now passes as expected. ### Notes: - This change is scoped specifically to improve RISC-V compatibility. - It does not affect behavior or test results on other architectures.
Diffstat (limited to 'tests/codegen-llvm')
| -rw-r--r-- | tests/codegen-llvm/const-vector.rs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/codegen-llvm/const-vector.rs b/tests/codegen-llvm/const-vector.rs index a2249f4fff7..f4307492341 100644 --- a/tests/codegen-llvm/const-vector.rs +++ b/tests/codegen-llvm/const-vector.rs @@ -15,6 +15,7 @@ #![feature(arm_target_feature)] #![feature(mips_target_feature)] #![allow(non_camel_case_types)] +#![feature(riscv_target_feature)] #[path = "../auxiliary/minisimd.rs"] mod minisimd; @@ -42,6 +43,7 @@ extern "unadjusted" { #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] pub fn do_call() { unsafe { // CHECK: call void @test_i8x2(<2 x i8> <i8 32, i8 64> |