diff options
| -rw-r--r-- | crates/core_simd/src/reduction.rs | 66 |
1 files changed, 44 insertions, 22 deletions
diff --git a/crates/core_simd/src/reduction.rs b/crates/core_simd/src/reduction.rs index db0640aae79..e79a185816b 100644 --- a/crates/core_simd/src/reduction.rs +++ b/crates/core_simd/src/reduction.rs @@ -2,7 +2,8 @@ use crate::simd::intrinsics::{ simd_reduce_add_ordered, simd_reduce_and, simd_reduce_max, simd_reduce_min, simd_reduce_mul_ordered, simd_reduce_or, simd_reduce_xor, }; -use crate::simd::{LaneCount, Simd, SupportedLaneCount}; +use crate::simd::{LaneCount, Simd, SimdElement, SupportedLaneCount}; +use core::ops::{BitAnd, BitOr, BitXor}; macro_rules! impl_integer_reductions { { $scalar:ty } => { @@ -22,27 +23,6 @@ macro_rules! impl_integer_reductions { unsafe { simd_reduce_mul_ordered(self, 1) } } - /// Horizontal bitwise "and". Returns the cumulative bitwise "and" across the lanes of - /// the vector. - #[inline] - pub fn horizontal_and(self) -> $scalar { - unsafe { simd_reduce_and(self) } - } - - /// Horizontal bitwise "or". Returns the cumulative bitwise "or" across the lanes of - /// the vector. - #[inline] - pub fn horizontal_or(self) -> $scalar { - unsafe { simd_reduce_or(self) } - } - - /// Horizontal bitwise "xor". Returns the cumulative bitwise "xor" across the lanes of - /// the vector. - #[inline] - pub fn horizontal_xor(self) -> $scalar { - unsafe { simd_reduce_xor(self) } - } - /// Horizontal maximum. Returns the maximum lane in the vector. #[inline] pub fn horizontal_max(self) -> $scalar { @@ -121,3 +101,45 @@ macro_rules! impl_float_reductions { impl_float_reductions! { f32 } impl_float_reductions! { f64 } + +impl<T, const LANES: usize> Simd<T, LANES> +where + Self: BitAnd<Self, Output = Self>, + T: SimdElement + BitAnd<T, Output = T>, + LaneCount<LANES>: SupportedLaneCount, +{ + /// Horizontal bitwise "and". Returns the cumulative bitwise "and" across the lanes of + /// the vector. + #[inline] + pub fn horizontal_and(self) -> T { + unsafe { simd_reduce_and(self) } + } +} + +impl<T, const LANES: usize> Simd<T, LANES> +where + Self: BitOr<Self, Output = Self>, + T: SimdElement + BitOr<T, Output = T>, + LaneCount<LANES>: SupportedLaneCount, +{ + /// Horizontal bitwise "or". Returns the cumulative bitwise "or" across the lanes of + /// the vector. + #[inline] + pub fn horizontal_or(self) -> T { + unsafe { simd_reduce_or(self) } + } +} + +impl<T, const LANES: usize> Simd<T, LANES> +where + Self: BitXor<Self, Output = Self>, + T: SimdElement + BitXor<T, Output = T>, + LaneCount<LANES>: SupportedLaneCount, +{ + /// Horizontal bitwise "xor". Returns the cumulative bitwise "xor" across the lanes of + /// the vector. + #[inline] + pub fn horizontal_xor(self) -> T { + unsafe { simd_reduce_xor(self) } + } +} |