diff options
26 files changed, 522 insertions, 836 deletions
diff --git a/library/stdarch/.github/workflows/rustc-pull.yml b/library/stdarch/.github/workflows/rustc-pull.yml new file mode 100644 index 00000000000..6b90d8a500f --- /dev/null +++ b/library/stdarch/.github/workflows/rustc-pull.yml @@ -0,0 +1,22 @@ +# Perform a subtree sync (pull) using the josh-sync tool once every few days (or on demand). +name: rustc-pull + +on: + workflow_dispatch: + schedule: + # Run at 04:00 UTC every Monday and Thursday + - cron: '0 4 * * 1,4' + +jobs: + pull: + if: github.repository == 'rust-lang/stdarch' + uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main + with: + # https://rust-lang.zulipchat.com/#narrow/channel/208962-t-libs.2Fstdarch/topic/Subtree.20sync.20automation/with/528461782 + zulip-stream-id: 208962 + zulip-bot-email: "stdarch-ci-bot@rust-lang.zulipchat.com" + pr-base-branch: master + branch-name: rustc-pull + secrets: + zulip-api-token: ${{ secrets.ZULIP_API_TOKEN }} + token: ${{ secrets.GITHUB_TOKEN }} diff --git a/library/stdarch/Cargo.lock b/library/stdarch/Cargo.lock index 4bdd423270c..a30743925d9 100644 --- a/library/stdarch/Cargo.lock +++ b/library/stdarch/Cargo.lock @@ -73,20 +73,20 @@ version = "0.1.0" dependencies = [ "proc-macro2", "quote", - "syn 2.0.102", + "syn 2.0.104", ] [[package]] name = "autocfg" -version = "1.4.0" +version = "1.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ace50bade8e6234aa140d9a2f552bbee1db4d353f69b8217bc503490fc1a9f26" +checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "cc" -version = "1.2.26" +version = "1.2.29" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "956a5e21988b87f372569b66183b78babf23ebc2e744b733e4350a752c4dafac" +checksum = "5c1599538de2394445747c8cf7935946e3cc27e9625f889d979bfb2aaf569362" dependencies = [ "shlex", ] @@ -128,7 +128,7 @@ dependencies = [ "heck", "proc-macro2", "quote", - "syn 2.0.102", + "syn 2.0.104", ] [[package]] @@ -338,9 +338,9 @@ dependencies = [ [[package]] name = "indexmap" -version = "2.9.0" +version = "2.10.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "cea70ddb795996207ad57735b50c5982d8844f38ba9ee5f1aedcfb708a2aa11e" +checksum = "fe4cd85333e22411419a0bcae1297d25e58c9443848b11dc6a86fefe8c78a661" dependencies = [ "equivalent", "hashbrown 0.15.4", @@ -403,9 +403,9 @@ checksum = "bbd2bcb4c963f2ddae06a2efc7e9f3591312473c50c6685e1f298068316e66fe" [[package]] name = "libc" -version = "0.2.172" +version = "0.2.174" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d750af042f7ef4f724306de029d18836c26c1765a54a6a3f094cbd23a7267ffa" +checksum = "1171693293099992e19cddea4e8b849964e9846f4acee11b3948bcc337be8776" [[package]] name = "linked-hash-map" @@ -624,7 +624,7 @@ checksum = "5b0276cf7f2c73365f7157c8123c21cd9a50fbbd844757af28ca1f5925fc2a00" dependencies = [ "proc-macro2", "quote", - "syn 2.0.102", + "syn 2.0.104", ] [[package]] @@ -685,7 +685,7 @@ version = "0.1.0" dependencies = [ "proc-macro2", "quote", - "syn 2.0.102", + "syn 2.0.104", ] [[package]] @@ -741,7 +741,7 @@ dependencies = [ "quote", "serde", "serde_json", - "syn 2.0.102", + "syn 2.0.104", ] [[package]] @@ -779,9 +779,9 @@ dependencies = [ [[package]] name = "syn" -version = "2.0.102" +version = "2.0.104" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f6397daf94fa90f058bd0fd88429dd9e5738999cca8d701813c80723add80462" +checksum = "17b6f705963418cdb9927482fa304bc562ece2fdd4f616084c50b7023b435a40" dependencies = [ "proc-macro2", "quote", @@ -837,7 +837,7 @@ version = "0.113.3" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "286049849b5a5bd09a8773171be96824afabffc7cc3df6caaf33a38db6cd07ae" dependencies = [ - "indexmap 2.9.0", + "indexmap 2.10.0", "semver", ] @@ -944,20 +944,20 @@ dependencies = [ [[package]] name = "zerocopy" -version = "0.8.25" +version = "0.8.26" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a1702d9583232ddb9174e01bb7c15a2ab8fb1bc6f227aa1233858c351a3ba0cb" +checksum = "1039dd0d3c310cf05de012d8a39ff557cb0d23087fd44cad61df08fc31907a2f" dependencies = [ "zerocopy-derive", ] [[package]] name = "zerocopy-derive" -version = "0.8.25" +version = "0.8.26" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "28a6e20d751156648aa063f3800b706ee209a32c0b4d9f24be3d980b01be55ef" +checksum = "9ecf5b4cc5364572d7f4c329661bcc82724222973f2cab6f050a4e5c22f75181" dependencies = [ "proc-macro2", "quote", - "syn 2.0.102", + "syn 2.0.104", ] diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 319cef2b1a1..31618d39b94 100644 --- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -13125,14 +13125,7 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v1f64" - )] - fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; - } - unsafe { _vmaxnm_f64(a, b) } + unsafe { simd_fmax(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"] @@ -13141,14 +13134,7 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v2f64" - )] - fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - unsafe { _vmaxnmq_f64(a, b) } + unsafe { simd_fmax(a, b) } } #[doc = "Floating-point Maximum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"] @@ -13157,14 +13143,7 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnm))] pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.f16" - )] - fn _vmaxnmh_f16(a: f16, b: f16) -> f16; - } - unsafe { _vmaxnmh_f16(a, b) } + f16::max(a, b) } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"] @@ -13173,14 +13152,7 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmv_f16(a: float16x4_t) -> f16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnmv.f16.v4f16" - )] - fn _vmaxnmv_f16(a: float16x4_t) -> f16; - } - unsafe { _vmaxnmv_f16(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"] @@ -13189,14 +13161,7 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnmv.f16.v8f16" - )] - fn _vmaxnmvq_f16(a: float16x8_t) -> f16; - } - unsafe { _vmaxnmvq_f16(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"] @@ -13205,14 +13170,7 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vmaxnmv_f32(a: float32x2_t) -> f32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32" - )] - fn _vmaxnmv_f32(a: float32x2_t) -> f32; - } - unsafe { _vmaxnmv_f32(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"] @@ -13221,14 +13179,7 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64" - )] - fn _vmaxnmvq_f64(a: float64x2_t) -> f64; - } - unsafe { _vmaxnmvq_f64(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"] @@ -13237,14 +13188,7 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmv))] pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32" - )] - fn _vmaxnmvq_f32(a: float32x4_t) -> f32; - } - unsafe { _vmaxnmvq_f32(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"] @@ -13333,14 +13277,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] pub fn vmaxv_s8(a: int8x8_t) -> i8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxv.i8.v8i8" - )] - fn _vmaxv_s8(a: int8x8_t) -> i8; - } - unsafe { _vmaxv_s8(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"] @@ -13349,14 +13286,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] pub fn vmaxvq_s8(a: int8x16_t) -> i8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxv.i8.v16i8" - )] - fn _vmaxvq_s8(a: int8x16_t) -> i8; - } - unsafe { _vmaxvq_s8(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"] @@ -13365,14 +13295,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] pub fn vmaxv_s16(a: int16x4_t) -> i16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxv.i16.v4i16" - )] - fn _vmaxv_s16(a: int16x4_t) -> i16; - } - unsafe { _vmaxv_s16(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"] @@ -13381,14 +13304,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] pub fn vmaxvq_s16(a: int16x8_t) -> i16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxv.i16.v8i16" - )] - fn _vmaxvq_s16(a: int16x8_t) -> i16; - } - unsafe { _vmaxvq_s16(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"] @@ -13397,14 +13313,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] pub fn vmaxv_s32(a: int32x2_t) -> i32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxv.i32.v2i32" - )] - fn _vmaxv_s32(a: int32x2_t) -> i32; - } - unsafe { _vmaxv_s32(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"] @@ -13413,14 +13322,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] pub fn vmaxvq_s32(a: int32x4_t) -> i32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smaxv.i32.v4i32" - )] - fn _vmaxvq_s32(a: int32x4_t) -> i32; - } - unsafe { _vmaxvq_s32(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"] @@ -13429,14 +13331,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] pub fn vmaxv_u8(a: uint8x8_t) -> u8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxv.i8.v8i8" - )] - fn _vmaxv_u8(a: uint8x8_t) -> u8; - } - unsafe { _vmaxv_u8(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"] @@ -13445,14 +13340,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] pub fn vmaxvq_u8(a: uint8x16_t) -> u8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxv.i8.v16i8" - )] - fn _vmaxvq_u8(a: uint8x16_t) -> u8; - } - unsafe { _vmaxvq_u8(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"] @@ -13461,14 +13349,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] pub fn vmaxv_u16(a: uint16x4_t) -> u16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxv.i16.v4i16" - )] - fn _vmaxv_u16(a: uint16x4_t) -> u16; - } - unsafe { _vmaxv_u16(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"] @@ -13477,14 +13358,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] pub fn vmaxvq_u16(a: uint16x8_t) -> u16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxv.i16.v8i16" - )] - fn _vmaxvq_u16(a: uint16x8_t) -> u16; - } - unsafe { _vmaxvq_u16(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"] @@ -13493,14 +13367,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] pub fn vmaxv_u32(a: uint32x2_t) -> u32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxv.i32.v2i32" - )] - fn _vmaxv_u32(a: uint32x2_t) -> u32; - } - unsafe { _vmaxv_u32(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"] @@ -13509,14 +13376,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] pub fn vmaxvq_u32(a: uint32x4_t) -> u32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umaxv.i32.v4i32" - )] - fn _vmaxvq_u32(a: uint32x4_t) -> u32; - } - unsafe { _vmaxvq_u32(a) } + unsafe { simd_reduce_max(a) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"] @@ -13573,14 +13433,7 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v1f64" - )] - fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; - } - unsafe { _vminnm_f64(a, b) } + unsafe { simd_fmin(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"] @@ -13589,14 +13442,7 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v2f64" - )] - fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - unsafe { _vminnmq_f64(a, b) } + unsafe { simd_fmin(a, b) } } #[doc = "Floating-point Minimum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"] @@ -13605,14 +13451,7 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnm))] pub fn vminnmh_f16(a: f16, b: f16) -> f16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.f16" - )] - fn _vminnmh_f16(a: f16, b: f16) -> f16; - } - unsafe { _vminnmh_f16(a, b) } + f16::min(a, b) } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"] @@ -13621,14 +13460,7 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnmv))] pub fn vminnmv_f16(a: float16x4_t) -> f16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnmv.f16.v4f16" - )] - fn _vminnmv_f16(a: float16x4_t) -> f16; - } - unsafe { _vminnmv_f16(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"] @@ -13637,14 +13469,7 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnmv))] pub fn vminnmvq_f16(a: float16x8_t) -> f16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnmv.f16.v8f16" - )] - fn _vminnmvq_f16(a: float16x8_t) -> f16; - } - unsafe { _vminnmvq_f16(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"] @@ -13653,14 +13478,7 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 { #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmv_f32(a: float32x2_t) -> f32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32" - )] - fn _vminnmv_f32(a: float32x2_t) -> f32; - } - unsafe { _vminnmv_f32(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"] @@ -13669,14 +13487,7 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 { #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmvq_f64(a: float64x2_t) -> f64 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64" - )] - fn _vminnmvq_f64(a: float64x2_t) -> f64; - } - unsafe { _vminnmvq_f64(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"] @@ -13685,14 +13496,7 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 { #[cfg_attr(test, assert_instr(fminnmv))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vminnmvq_f32(a: float32x4_t) -> f32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32" - )] - fn _vminnmvq_f32(a: float32x4_t) -> f32; - } - unsafe { _vminnmvq_f32(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"] @@ -13781,14 +13585,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] pub fn vminv_s8(a: int8x8_t) -> i8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminv.i8.v8i8" - )] - fn _vminv_s8(a: int8x8_t) -> i8; - } - unsafe { _vminv_s8(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"] @@ -13797,14 +13594,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] pub fn vminvq_s8(a: int8x16_t) -> i8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminv.i8.v16i8" - )] - fn _vminvq_s8(a: int8x16_t) -> i8; - } - unsafe { _vminvq_s8(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"] @@ -13813,14 +13603,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] pub fn vminv_s16(a: int16x4_t) -> i16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminv.i16.v4i16" - )] - fn _vminv_s16(a: int16x4_t) -> i16; - } - unsafe { _vminv_s16(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"] @@ -13829,14 +13612,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] pub fn vminvq_s16(a: int16x8_t) -> i16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminv.i16.v8i16" - )] - fn _vminvq_s16(a: int16x8_t) -> i16; - } - unsafe { _vminvq_s16(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"] @@ -13845,14 +13621,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] pub fn vminv_s32(a: int32x2_t) -> i32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminv.i32.v2i32" - )] - fn _vminv_s32(a: int32x2_t) -> i32; - } - unsafe { _vminv_s32(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"] @@ -13861,14 +13630,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] pub fn vminvq_s32(a: int32x4_t) -> i32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.sminv.i32.v4i32" - )] - fn _vminvq_s32(a: int32x4_t) -> i32; - } - unsafe { _vminvq_s32(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"] @@ -13877,14 +13639,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] pub fn vminv_u8(a: uint8x8_t) -> u8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminv.i8.v8i8" - )] - fn _vminv_u8(a: uint8x8_t) -> u8; - } - unsafe { _vminv_u8(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"] @@ -13893,14 +13648,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] pub fn vminvq_u8(a: uint8x16_t) -> u8 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminv.i8.v16i8" - )] - fn _vminvq_u8(a: uint8x16_t) -> u8; - } - unsafe { _vminvq_u8(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"] @@ -13909,14 +13657,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] pub fn vminv_u16(a: uint16x4_t) -> u16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminv.i16.v4i16" - )] - fn _vminv_u16(a: uint16x4_t) -> u16; - } - unsafe { _vminv_u16(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"] @@ -13925,14 +13666,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] pub fn vminvq_u16(a: uint16x8_t) -> u16 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminv.i16.v8i16" - )] - fn _vminvq_u16(a: uint16x8_t) -> u16; - } - unsafe { _vminvq_u16(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"] @@ -13941,14 +13675,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] pub fn vminv_u32(a: uint32x2_t) -> u32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminv.i32.v2i32" - )] - fn _vminv_u32(a: uint32x2_t) -> u32; - } - unsafe { _vminv_u32(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"] @@ -13957,14 +13684,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] pub fn vminvq_u32(a: uint32x4_t) -> u32 { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.uminv.i32.v4i32" - )] - fn _vminvq_u32(a: uint32x4_t) -> u32; - } - unsafe { _vminvq_u32(a) } + unsafe { simd_reduce_min(a) } } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"] diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 4bf926c3569..03d14086070 100644 --- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -27918,15 +27918,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v4f16" - )] - fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; - } - unsafe { _vmaxnm_f16(a, b) } + unsafe { simd_fmax(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"] @@ -27940,15 +27932,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v8f16" - )] - fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; - } - unsafe { _vmaxnmq_f16(a, b) } + unsafe { simd_fmax(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] @@ -27969,15 +27953,7 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v2f32" - )] - fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vmaxnm_f32(a, b) } + unsafe { simd_fmax(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] @@ -27998,15 +27974,7 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fmaxnm.v4f32" - )] - fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - unsafe { _vmaxnmq_f32(a, b) } + unsafe { simd_fmax(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"] @@ -28410,15 +28378,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v4f16" - )] - fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; - } - unsafe { _vminnm_f16(a, b) } + unsafe { simd_fmin(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"] @@ -28432,15 +28392,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v8f16" - )] - fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; - } - unsafe { _vminnmq_f16(a, b) } + unsafe { simd_fmin(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] @@ -28461,15 +28413,7 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v2f32" - )] - fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - unsafe { _vminnm_f32(a, b) } + unsafe { simd_fmin(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] @@ -28490,15 +28434,7 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.fminnm.v4f32" - )] - fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - unsafe { _vminnmq_f32(a, b) } + unsafe { simd_fmin(a, b) } } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] diff --git a/library/stdarch/crates/core_arch/src/core_arch_docs.md b/library/stdarch/crates/core_arch/src/core_arch_docs.md index bfa1b722886..6aea2b46184 100644 --- a/library/stdarch/crates/core_arch/src/core_arch_docs.md +++ b/library/stdarch/crates/core_arch/src/core_arch_docs.md @@ -193,6 +193,7 @@ others at: * [`powerpc64`] * [`nvptx`] * [`wasm32`] +* [`loongarch32`] * [`loongarch64`] * [`s390x`] @@ -208,6 +209,7 @@ others at: [`powerpc64`]: ../../core/arch/powerpc64/index.html [`nvptx`]: ../../core/arch/nvptx/index.html [`wasm32`]: ../../core/arch/wasm32/index.html +[`loongarch32`]: ../../core/arch/loongarch32/index.html [`loongarch64`]: ../../core/arch/loongarch64/index.html [`s390x`]: ../../core/arch/s390x/index.html diff --git a/library/stdarch/crates/core_arch/src/loongarch32/mod.rs b/library/stdarch/crates/core_arch/src/loongarch32/mod.rs new file mode 100644 index 00000000000..fb05450373c --- /dev/null +++ b/library/stdarch/crates/core_arch/src/loongarch32/mod.rs @@ -0,0 +1,47 @@ +//! `LoongArch32` intrinsics + +use crate::arch::asm; + +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.loongarch.cacop.w"] + fn __cacop(a: i32, b: i32, c: i32); + #[link_name = "llvm.loongarch.csrrd.w"] + fn __csrrd(a: i32) -> i32; + #[link_name = "llvm.loongarch.csrwr.w"] + fn __csrwr(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.csrxchg.w"] + fn __csrxchg(a: i32, b: i32, c: i32) -> i32; +} + +/// Generates the cache operation instruction +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn cacop<const IMM12: i32>(a: i32, b: i32) { + static_assert_simm_bits!(IMM12, 12); + __cacop(a, b, IMM12); +} + +/// Reads the CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn csrrd<const IMM14: i32>() -> i32 { + static_assert_uimm_bits!(IMM14, 14); + __csrrd(IMM14) +} + +/// Writes the CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 { + static_assert_uimm_bits!(IMM14, 14); + __csrwr(a, IMM14) +} + +/// Exchanges the CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 { + static_assert_uimm_bits!(IMM14, 14); + __csrxchg(a, b, IMM14) +} diff --git a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs index b1704bbb48d..3f1bfbcd0e1 100644 --- a/library/stdarch/crates/core_arch/src/loongarch64/mod.rs +++ b/library/stdarch/crates/core_arch/src/loongarch64/mod.rs @@ -1,4 +1,4 @@ -//! `LoongArch` intrinsics +//! `LoongArch64` intrinsics mod lasx; mod lsx; @@ -20,82 +20,24 @@ pub unsafe fn rdtime_d() -> (i64, isize) { (val, tid) } -/// Reads the lower 32-bit stable counter value and the counter ID -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn rdtimel_w() -> (i32, isize) { - let val: i32; - let tid: isize; - asm!("rdtimel.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)); - (val, tid) -} - -/// Reads the upper 32-bit stable counter value and the counter ID -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn rdtimeh_w() -> (i32, isize) { - let val: i32; - let tid: isize; - asm!("rdtimeh.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)); - (val, tid) -} - #[allow(improper_ctypes)] unsafe extern "unadjusted" { - #[link_name = "llvm.loongarch.crc.w.b.w"] - fn __crc_w_b_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crc.w.h.w"] - fn __crc_w_h_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crc.w.w.w"] - fn __crc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.crc.w.d.w"] fn __crc_w_d_w(a: i64, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.b.w"] - fn __crcc_w_b_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.h.w"] - fn __crcc_w_h_w(a: i32, b: i32) -> i32; - #[link_name = "llvm.loongarch.crcc.w.w.w"] - fn __crcc_w_w_w(a: i32, b: i32) -> i32; #[link_name = "llvm.loongarch.crcc.w.d.w"] fn __crcc_w_d_w(a: i64, b: i32) -> i32; #[link_name = "llvm.loongarch.cacop.d"] fn __cacop(a: i64, b: i64, c: i64); - #[link_name = "llvm.loongarch.dbar"] - fn __dbar(a: i32); - #[link_name = "llvm.loongarch.ibar"] - fn __ibar(a: i32); - #[link_name = "llvm.loongarch.movgr2fcsr"] - fn __movgr2fcsr(a: i32, b: i32); - #[link_name = "llvm.loongarch.movfcsr2gr"] - fn __movfcsr2gr(a: i32) -> i32; #[link_name = "llvm.loongarch.csrrd.d"] fn __csrrd(a: i32) -> i64; #[link_name = "llvm.loongarch.csrwr.d"] fn __csrwr(a: i64, b: i32) -> i64; #[link_name = "llvm.loongarch.csrxchg.d"] fn __csrxchg(a: i64, b: i64, c: i32) -> i64; - #[link_name = "llvm.loongarch.iocsrrd.b"] - fn __iocsrrd_b(a: i32) -> i32; - #[link_name = "llvm.loongarch.iocsrrd.h"] - fn __iocsrrd_h(a: i32) -> i32; - #[link_name = "llvm.loongarch.iocsrrd.w"] - fn __iocsrrd_w(a: i32) -> i32; #[link_name = "llvm.loongarch.iocsrrd.d"] fn __iocsrrd_d(a: i32) -> i64; - #[link_name = "llvm.loongarch.iocsrwr.b"] - fn __iocsrwr_b(a: i32, b: i32); - #[link_name = "llvm.loongarch.iocsrwr.h"] - fn __iocsrwr_h(a: i32, b: i32); - #[link_name = "llvm.loongarch.iocsrwr.w"] - fn __iocsrwr_w(a: i32, b: i32); #[link_name = "llvm.loongarch.iocsrwr.d"] fn __iocsrwr_d(a: i64, b: i32); - #[link_name = "llvm.loongarch.break"] - fn __break(a: i32); - #[link_name = "llvm.loongarch.cpucfg"] - fn __cpucfg(a: i32) -> i32; - #[link_name = "llvm.loongarch.syscall"] - fn __syscall(a: i32); #[link_name = "llvm.loongarch.asrtle.d"] fn __asrtle(a: i64, b: i64); #[link_name = "llvm.loongarch.asrtgt.d"] @@ -104,35 +46,6 @@ unsafe extern "unadjusted" { fn __lddir(a: i64, b: i64) -> i64; #[link_name = "llvm.loongarch.ldpte.d"] fn __ldpte(a: i64, b: i64); - #[link_name = "llvm.loongarch.frecipe.s"] - fn __frecipe_s(a: f32) -> f32; - #[link_name = "llvm.loongarch.frecipe.d"] - fn __frecipe_d(a: f64) -> f64; - #[link_name = "llvm.loongarch.frsqrte.s"] - fn __frsqrte_s(a: f32) -> f32; - #[link_name = "llvm.loongarch.frsqrte.d"] - fn __frsqrte_d(a: f64) -> f64; -} - -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn crc_w_b_w(a: i32, b: i32) -> i32 { - __crc_w_b_w(a, b) -} - -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn crc_w_h_w(a: i32, b: i32) -> i32 { - __crc_w_h_w(a, b) -} - -/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn crc_w_w_w(a: i32, b: i32) -> i32 { - __crc_w_w_w(a, b) } /// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) @@ -145,27 +58,6 @@ pub unsafe fn crc_w_d_w(a: i64, b: i32) -> i32 { /// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) #[inline] #[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn crcc_w_b_w(a: i32, b: i32) -> i32 { - __crcc_w_b_w(a, b) -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn crcc_w_h_w(a: i32, b: i32) -> i32 { - __crcc_w_h_w(a, b) -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn crcc_w_w_w(a: i32, b: i32) -> i32 { - __crcc_w_w_w(a, b) -} - -/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] pub unsafe fn crcc_w_d_w(a: i64, b: i32) -> i32 { __crcc_w_d_w(a, b) } @@ -178,38 +70,6 @@ pub unsafe fn cacop<const IMM12: i64>(a: i64, b: i64) { __cacop(a, b, IMM12); } -/// Generates the memory barrier instruction -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn dbar<const IMM15: i32>() { - static_assert_uimm_bits!(IMM15, 15); - __dbar(IMM15); -} - -/// Generates the instruction-fetch barrier instruction -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn ibar<const IMM15: i32>() { - static_assert_uimm_bits!(IMM15, 15); - __ibar(IMM15); -} - -/// Moves data from a GPR to the FCSR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) { - static_assert_uimm_bits!(IMM5, 5); - __movgr2fcsr(IMM5, a); -} - -/// Moves data from a FCSR to the GPR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn movfcsr2gr<const IMM5: i32>() -> i32 { - static_assert_uimm_bits!(IMM5, 5); - __movfcsr2gr(IMM5) -} - /// Reads the CSR #[inline] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -234,27 +94,6 @@ pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 { __csrxchg(a, b, IMM14) } -/// Reads the 8-bit IO-CSR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn iocsrrd_b(a: i32) -> i32 { - __iocsrrd_b(a) -} - -/// Reads the 16-bit IO-CSR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn iocsrrd_h(a: i32) -> i32 { - __iocsrrd_h(a) -} - -/// Reads the 32-bit IO-CSR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn iocsrrd_w(a: i32) -> i32 { - __iocsrrd_w(a) -} - /// Reads the 64-bit IO-CSR #[inline] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -262,27 +101,6 @@ pub unsafe fn iocsrrd_d(a: i32) -> i64 { __iocsrrd_d(a) } -/// Writes the 8-bit IO-CSR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn iocsrwr_b(a: i32, b: i32) { - __iocsrwr_b(a, b) -} - -/// Writes the 16-bit IO-CSR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn iocsrwr_h(a: i32, b: i32) { - __iocsrwr_h(a, b) -} - -/// Writes the 32-bit IO-CSR -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn iocsrwr_w(a: i32, b: i32) { - __iocsrwr_w(a, b) -} - /// Writes the 64-bit IO-CSR #[inline] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -290,29 +108,6 @@ pub unsafe fn iocsrwr_d(a: i64, b: i32) { __iocsrwr_d(a, b) } -/// Generates the breakpoint instruction -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn brk<const IMM15: i32>() { - static_assert_uimm_bits!(IMM15, 15); - __break(IMM15); -} - -/// Reads the CPU configuration register -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn cpucfg(a: i32) -> i32 { - __cpucfg(a) -} - -/// Generates the syscall instruction -#[inline] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn syscall<const IMM15: i32>() { - static_assert_uimm_bits!(IMM15, 15); - __syscall(IMM15); -} - /// Generates the less-than-or-equal asseration instruction #[inline] #[unstable(feature = "stdarch_loongarch", issue = "117427")] @@ -342,35 +137,3 @@ pub unsafe fn lddir<const B: i64>(a: i64) -> i64 { pub unsafe fn ldpte<const B: i64>(a: i64) { __ldpte(a, B) } - -/// Calculate the approximate single-precision result of 1.0 divided -#[inline] -#[target_feature(enable = "frecipe")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn frecipe_s(a: f32) -> f32 { - __frecipe_s(a) -} - -/// Calculate the approximate double-precision result of 1.0 divided -#[inline] -#[target_feature(enable = "frecipe")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn frecipe_d(a: f64) -> f64 { - __frecipe_d(a) -} - -/// Calculate the approximate single-precision result of dividing 1.0 by the square root -#[inline] -#[target_feature(enable = "frecipe")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn frsqrte_s(a: f32) -> f32 { - __frsqrte_s(a) -} - -/// Calculate the approximate double-precision result of dividing 1.0 by the square root -#[inline] -#[target_feature(enable = "frecipe")] -#[unstable(feature = "stdarch_loongarch", issue = "117427")] -pub unsafe fn frsqrte_d(a: f64) -> f64 { - __frsqrte_d(a) -} diff --git a/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs b/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs new file mode 100644 index 00000000000..da716ffd279 --- /dev/null +++ b/library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs @@ -0,0 +1,244 @@ +//! `Shared LoongArch` intrinsics + +use crate::arch::asm; + +/// Reads the lower 32-bit stable counter value and the counter ID +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn rdtimel_w() -> (i32, isize) { + let val: i32; + let tid: isize; + asm!("rdtimel.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)); + (val, tid) +} + +/// Reads the upper 32-bit stable counter value and the counter ID +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn rdtimeh_w() -> (i32, isize) { + let val: i32; + let tid: isize; + asm!("rdtimeh.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)); + (val, tid) +} + +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.loongarch.crc.w.b.w"] + fn __crc_w_b_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crc.w.h.w"] + fn __crc_w_h_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crc.w.w.w"] + fn __crc_w_w_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.b.w"] + fn __crcc_w_b_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.h.w"] + fn __crcc_w_h_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.crcc.w.w.w"] + fn __crcc_w_w_w(a: i32, b: i32) -> i32; + #[link_name = "llvm.loongarch.dbar"] + fn __dbar(a: i32); + #[link_name = "llvm.loongarch.ibar"] + fn __ibar(a: i32); + #[link_name = "llvm.loongarch.movgr2fcsr"] + fn __movgr2fcsr(a: i32, b: i32); + #[link_name = "llvm.loongarch.movfcsr2gr"] + fn __movfcsr2gr(a: i32) -> i32; + #[link_name = "llvm.loongarch.iocsrrd.b"] + fn __iocsrrd_b(a: i32) -> i32; + #[link_name = "llvm.loongarch.iocsrrd.h"] + fn __iocsrrd_h(a: i32) -> i32; + #[link_name = "llvm.loongarch.iocsrrd.w"] + fn __iocsrrd_w(a: i32) -> i32; + #[link_name = "llvm.loongarch.iocsrwr.b"] + fn __iocsrwr_b(a: i32, b: i32); + #[link_name = "llvm.loongarch.iocsrwr.h"] + fn __iocsrwr_h(a: i32, b: i32); + #[link_name = "llvm.loongarch.iocsrwr.w"] + fn __iocsrwr_w(a: i32, b: i32); + #[link_name = "llvm.loongarch.break"] + fn __break(a: i32); + #[link_name = "llvm.loongarch.cpucfg"] + fn __cpucfg(a: i32) -> i32; + #[link_name = "llvm.loongarch.syscall"] + fn __syscall(a: i32); + #[link_name = "llvm.loongarch.frecipe.s"] + fn __frecipe_s(a: f32) -> f32; + #[link_name = "llvm.loongarch.frecipe.d"] + fn __frecipe_d(a: f64) -> f64; + #[link_name = "llvm.loongarch.frsqrte.s"] + fn __frsqrte_s(a: f32) -> f32; + #[link_name = "llvm.loongarch.frsqrte.d"] + fn __frsqrte_d(a: f64) -> f64; +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn crc_w_b_w(a: i32, b: i32) -> i32 { + __crc_w_b_w(a, b) +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn crc_w_h_w(a: i32, b: i32) -> i32 { + __crc_w_h_w(a, b) +} + +/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320) +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn crc_w_w_w(a: i32, b: i32) -> i32 { + __crc_w_w_w(a, b) +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn crcc_w_b_w(a: i32, b: i32) -> i32 { + __crcc_w_b_w(a, b) +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn crcc_w_h_w(a: i32, b: i32) -> i32 { + __crcc_w_h_w(a, b) +} + +/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78) +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn crcc_w_w_w(a: i32, b: i32) -> i32 { + __crcc_w_w_w(a, b) +} + +/// Generates the memory barrier instruction +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn dbar<const IMM15: i32>() { + static_assert_uimm_bits!(IMM15, 15); + __dbar(IMM15); +} + +/// Generates the instruction-fetch barrier instruction +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn ibar<const IMM15: i32>() { + static_assert_uimm_bits!(IMM15, 15); + __ibar(IMM15); +} + +/// Moves data from a GPR to the FCSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) { + static_assert_uimm_bits!(IMM5, 5); + __movgr2fcsr(IMM5, a); +} + +/// Moves data from a FCSR to the GPR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn movfcsr2gr<const IMM5: i32>() -> i32 { + static_assert_uimm_bits!(IMM5, 5); + __movfcsr2gr(IMM5) +} + +/// Reads the 8-bit IO-CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn iocsrrd_b(a: i32) -> i32 { + __iocsrrd_b(a) +} + +/// Reads the 16-bit IO-CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn iocsrrd_h(a: i32) -> i32 { + __iocsrrd_h(a) +} + +/// Reads the 32-bit IO-CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn iocsrrd_w(a: i32) -> i32 { + __iocsrrd_w(a) +} + +/// Writes the 8-bit IO-CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn iocsrwr_b(a: i32, b: i32) { + __iocsrwr_b(a, b) +} + +/// Writes the 16-bit IO-CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn iocsrwr_h(a: i32, b: i32) { + __iocsrwr_h(a, b) +} + +/// Writes the 32-bit IO-CSR +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn iocsrwr_w(a: i32, b: i32) { + __iocsrwr_w(a, b) +} + +/// Generates the breakpoint instruction +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn brk<const IMM15: i32>() { + static_assert_uimm_bits!(IMM15, 15); + __break(IMM15); +} + +/// Reads the CPU configuration register +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn cpucfg(a: i32) -> i32 { + __cpucfg(a) +} + +/// Generates the syscall instruction +#[inline] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn syscall<const IMM15: i32>() { + static_assert_uimm_bits!(IMM15, 15); + __syscall(IMM15); +} + +/// Calculate the approximate single-precision result of 1.0 divided +#[inline] +#[target_feature(enable = "frecipe")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn frecipe_s(a: f32) -> f32 { + __frecipe_s(a) +} + +/// Calculate the approximate double-precision result of 1.0 divided +#[inline] +#[target_feature(enable = "frecipe")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn frecipe_d(a: f64) -> f64 { + __frecipe_d(a) +} + +/// Calculate the approximate single-precision result of dividing 1.0 by the square root +#[inline] +#[target_feature(enable = "frecipe")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn frsqrte_s(a: f32) -> f32 { + __frsqrte_s(a) +} + +/// Calculate the approximate double-precision result of dividing 1.0 by the square root +#[inline] +#[target_feature(enable = "frecipe")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub unsafe fn frsqrte_d(a: f64) -> f64 { + __frsqrte_d(a) +} diff --git a/library/stdarch/crates/core_arch/src/mod.rs b/library/stdarch/crates/core_arch/src/mod.rs index f6e959efd47..2105cca1b43 100644 --- a/library/stdarch/crates/core_arch/src/mod.rs +++ b/library/stdarch/crates/core_arch/src/mod.rs @@ -16,6 +16,9 @@ mod riscv_shared; ))] mod arm_shared; +#[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64", doc))] +mod loongarch_shared; + mod simd; #[doc = include_str!("core_arch_docs.md")] @@ -271,13 +274,25 @@ pub mod arch { pub use crate::core_arch::nvptx::*; } - /// Platform-specific intrinsics for the `loongarch` platform. + /// Platform-specific intrinsics for the `loongarch32` platform. + /// + /// See the [module documentation](../index.html) for more details. + #[cfg(any(target_arch = "loongarch32", doc))] + #[doc(cfg(target_arch = "loongarch32"))] + #[unstable(feature = "stdarch_loongarch", issue = "117427")] + pub mod loongarch32 { + pub use crate::core_arch::loongarch_shared::*; + pub use crate::core_arch::loongarch32::*; + } + + /// Platform-specific intrinsics for the `loongarch64` platform. /// /// See the [module documentation](../index.html) for more details. #[cfg(any(target_arch = "loongarch64", doc))] #[doc(cfg(target_arch = "loongarch64"))] #[unstable(feature = "stdarch_loongarch", issue = "117427")] pub mod loongarch64 { + pub use crate::core_arch::loongarch_shared::*; pub use crate::core_arch::loongarch64::*; } @@ -334,6 +349,10 @@ mod powerpc64; #[doc(cfg(target_arch = "nvptx64"))] mod nvptx; +#[cfg(any(target_arch = "loongarch32", doc))] +#[doc(cfg(target_arch = "loongarch32"))] +mod loongarch32; + #[cfg(any(target_arch = "loongarch64", doc))] #[doc(cfg(target_arch = "loongarch64"))] mod loongarch64; diff --git a/library/stdarch/crates/core_arch/src/s390x/vector.rs b/library/stdarch/crates/core_arch/src/s390x/vector.rs index 1cd33c3554b..63205f13ccc 100644 --- a/library/stdarch/crates/core_arch/src/s390x/vector.rs +++ b/library/stdarch/crates/core_arch/src/s390x/vector.rs @@ -1181,6 +1181,20 @@ mod sealed { impl_vec_trait! { [VectorOrc vec_orc]+ 2c (orc) } + // Z vector intrinsic C23 math.h LLVM IR ISO/IEC 60559 operation inexact vfidb parameters + // + // vec_rint rint llvm.rint roundToIntegralExact yes 0, 0 + // vec_roundc nearbyint llvm.nearbyint n/a no 4, 0 + // vec_floor / vec_roundm floor llvm.floor roundToIntegralTowardNegative no 4, 7 + // vec_ceil / vec_roundp ceil llvm.ceil roundToIntegralTowardPositive no 4, 6 + // vec_trunc / vec_roundz trunc llvm.trunc roundToIntegralTowardZero no 4, 5 + // vec_round roundeven llvm.roundeven roundToIntegralTiesToEven no 4, 4 + // n/a round llvm.round roundToIntegralTiesAway no 4, 1 + + // `simd_round_ties_even` is implemented as `llvm.rint`. + test_impl! { vec_rint_f32 (a: vector_float) -> vector_float [simd_round_ties_even, "vector-enhancements-1" vfisb] } + test_impl! { vec_rint_f64 (a: vector_double) -> vector_double [simd_round_ties_even, vfidb] } + test_impl! { vec_roundc_f32 (a: vector_float) -> vector_float [nearbyint_v4f32, "vector-enhancements-1" vfisb] } test_impl! { vec_roundc_f64 (a: vector_double) -> vector_double [nearbyint_v2f64, vfidb] } @@ -1189,9 +1203,6 @@ mod sealed { test_impl! { vec_round_f32 (a: vector_float) -> vector_float [roundeven_v4f32, _] } test_impl! { vec_round_f64 (a: vector_double) -> vector_double [roundeven_v2f64, _] } - test_impl! { vec_rint_f32 (a: vector_float) -> vector_float [simd_round_ties_even, "vector-enhancements-1" vfisb] } - test_impl! { vec_rint_f64 (a: vector_double) -> vector_double [simd_round_ties_even, vfidb] } - #[unstable(feature = "stdarch_s390x", issue = "135681")] pub trait VectorRoundc { unsafe fn vec_roundc(self) -> Self; diff --git a/library/stdarch/crates/intrinsic-test/src/arm/config.rs b/library/stdarch/crates/intrinsic-test/src/arm/config.rs index cee80374ae9..9a7b37253d1 100644 --- a/library/stdarch/crates/intrinsic-test/src/arm/config.rs +++ b/library/stdarch/crates/intrinsic-test/src/arm/config.rs @@ -114,7 +114,6 @@ pub const AARCH_CONFIGURATIONS: &str = r#" #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))] #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_dotprod))] #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))] -#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sha3))] #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))] #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))] #![feature(fmt_helpers_for_derive)] diff --git a/library/stdarch/crates/intrinsic-test/src/arm/mod.rs b/library/stdarch/crates/intrinsic-test/src/arm/mod.rs index 6aaa49ff97f..1a66ed4268d 100644 --- a/library/stdarch/crates/intrinsic-test/src/arm/mod.rs +++ b/library/stdarch/crates/intrinsic-test/src/arm/mod.rs @@ -104,7 +104,7 @@ impl SupportedArchitectureTest for ArmArchitectureTest { } fn compare_outputs(&self) -> bool { - if let Some(ref toolchain) = self.cli_options.toolchain { + if self.cli_options.toolchain.is_some() { let intrinsics_name_list = self .intrinsics .iter() @@ -113,8 +113,7 @@ impl SupportedArchitectureTest for ArmArchitectureTest { compare_outputs( &intrinsics_name_list, - toolchain, - &self.cli_options.c_runner, + &self.cli_options.runner, &self.cli_options.target, ) } else { diff --git a/library/stdarch/crates/intrinsic-test/src/common/cli.rs b/library/stdarch/crates/intrinsic-test/src/common/cli.rs index 1d572723008..beae6a4b044 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/cli.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/cli.rs @@ -60,7 +60,7 @@ pub struct ProcessedCli { pub filename: PathBuf, pub toolchain: Option<String>, pub cpp_compiler: Option<String>, - pub c_runner: String, + pub runner: String, pub target: String, pub linker: Option<String>, pub cxx_toolchain_dir: Option<String>, @@ -70,7 +70,7 @@ pub struct ProcessedCli { impl ProcessedCli { pub fn new(cli_options: Cli) -> Self { let filename = cli_options.input; - let c_runner = cli_options.runner.unwrap_or_default(); + let runner = cli_options.runner.unwrap_or_default(); let target = cli_options.target; let linker = cli_options.linker; let cxx_toolchain_dir = cli_options.cxx_toolchain_dir; @@ -102,7 +102,7 @@ impl ProcessedCli { Self { toolchain, cpp_compiler, - c_runner, + runner, target, linker, cxx_toolchain_dir, diff --git a/library/stdarch/crates/intrinsic-test/src/common/compare.rs b/library/stdarch/crates/intrinsic-test/src/common/compare.rs index 9e0cbe8cd6a..f16d83b0264 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/compare.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/compare.rs @@ -2,26 +2,24 @@ use super::cli::FailureReason; use rayon::prelude::*; use std::process::Command; -pub fn compare_outputs( - intrinsic_name_list: &Vec<String>, - toolchain: &str, - runner: &str, - target: &str, -) -> bool { +pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target: &str) -> bool { + fn runner_command(runner: &str) -> Command { + let mut it = runner.split_whitespace(); + let mut cmd = Command::new(it.next().unwrap()); + cmd.args(it); + + cmd + } + let intrinsics = intrinsic_name_list .par_iter() .filter_map(|intrinsic_name| { - let c = Command::new("sh") - .arg("-c") - .arg(format!("{runner} ./c_programs/{intrinsic_name}")) + let c = runner_command(runner) + .arg(format!("./c_programs/{intrinsic_name}")) .output(); - let rust = Command::new("sh") - .current_dir("rust_programs") - .arg("-c") - .arg(format!( - "cargo {toolchain} run --target {target} --bin {intrinsic_name} --release", - )) + let rust = runner_command(runner) + .arg(format!("target/{target}/release/{intrinsic_name}")) .env("RUSTFLAGS", "-Cdebuginfo=0") .output(); @@ -42,8 +40,8 @@ pub fn compare_outputs( if !rust.status.success() { error!( "Failed to run Rust program for intrinsic {intrinsic_name}\nstdout: {stdout}\nstderr: {stderr}", - stdout = std::str::from_utf8(&rust.stdout).unwrap_or(""), - stderr = std::str::from_utf8(&rust.stderr).unwrap_or(""), + stdout = String::from_utf8_lossy(&rust.stdout), + stderr = String::from_utf8_lossy(&rust.stderr), ); return Some(FailureReason::RunRust(intrinsic_name.clone())); } diff --git a/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs b/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs index 52bccaf905c..0e4a95ab528 100644 --- a/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs +++ b/library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs @@ -2,7 +2,6 @@ use itertools::Itertools; use rayon::prelude::*; use std::collections::BTreeMap; use std::fs::File; -use std::io::Write; use std::process::Command; use super::argument::Argument; @@ -23,8 +22,8 @@ pub fn format_rust_main_template( ) -> String { format!( r#"{notices}#![feature(simd_ffi)] -#![feature(link_llvm_intrinsics)] #![feature(f16)] +#![allow(unused)] {configurations} {definitions} @@ -38,6 +37,42 @@ fn main() {{ ) } +fn write_cargo_toml(w: &mut impl std::io::Write, binaries: &[String]) -> std::io::Result<()> { + writeln!( + w, + concat!( + "[package]\n", + "name = \"intrinsic-test-programs\"\n", + "version = \"{version}\"\n", + "authors = [{authors}]\n", + "license = \"{license}\"\n", + "edition = \"2018\"\n", + "[workspace]\n", + "[dependencies]\n", + "core_arch = {{ path = \"../crates/core_arch\" }}", + ), + version = env!("CARGO_PKG_VERSION"), + authors = env!("CARGO_PKG_AUTHORS") + .split(":") + .format_with(", ", |author, fmt| fmt(&format_args!("\"{author}\""))), + license = env!("CARGO_PKG_LICENSE"), + )?; + + for binary in binaries { + writeln!( + w, + concat!( + "[[bin]]\n", + "name = \"{binary}\"\n", + "path = \"{binary}/main.rs\"\n", + ), + binary = binary, + )?; + } + + Ok(()) +} + pub fn compile_rust_programs( binaries: Vec<String>, toolchain: Option<&str>, @@ -45,56 +80,20 @@ pub fn compile_rust_programs( linker: Option<&str>, ) -> bool { let mut cargo = File::create("rust_programs/Cargo.toml").unwrap(); - cargo - .write_all( - format!( - r#"[package] -name = "intrinsic-test-programs" -version = "{version}" -authors = [{authors}] -license = "{license}" -edition = "2018" -[workspace] -[dependencies] -core_arch = {{ path = "../crates/core_arch" }} -{binaries}"#, - version = env!("CARGO_PKG_VERSION"), - authors = env!("CARGO_PKG_AUTHORS") - .split(":") - .format_with(", ", |author, fmt| fmt(&format_args!("\"{author}\""))), - license = env!("CARGO_PKG_LICENSE"), - binaries = binaries - .iter() - .map(|binary| { - format!( - r#"[[bin]] -name = "{binary}" -path = "{binary}/main.rs""#, - ) - }) - .collect::<Vec<_>>() - .join("\n") - ) - .into_bytes() - .as_slice(), - ) - .unwrap(); - - let toolchain = match toolchain { - None => return true, - Some(t) => t, - }; + write_cargo_toml(&mut cargo, &binaries).unwrap(); /* If there has been a linker explicitly set from the command line then * we want to set it via setting it in the RUSTFLAGS*/ - let cargo_command = format!("cargo {toolchain} build --target {target} --release"); + let mut cargo_command = Command::new("cargo"); + cargo_command.current_dir("rust_programs"); - let mut command = Command::new("sh"); - command - .current_dir("rust_programs") - .arg("-c") - .arg(cargo_command); + if let Some(toolchain) = toolchain { + if !toolchain.is_empty() { + cargo_command.arg(toolchain); + } + } + cargo_command.args(["build", "--target", target, "--release"]); let mut rust_flags = "-Cdebuginfo=0".to_string(); if let Some(linker) = linker { @@ -102,11 +101,11 @@ path = "{binary}/main.rs""#, rust_flags.push_str(linker); rust_flags.push_str(" -C link-args=-static"); - command.env("CPPFLAGS", "-fuse-ld=lld"); + cargo_command.env("CPPFLAGS", "-fuse-ld=lld"); } - command.env("RUSTFLAGS", rust_flags); - let output = command.output(); + cargo_command.env("RUSTFLAGS", rust_flags); + let output = cargo_command.output(); if let Ok(output) = output { if output.status.success() { diff --git a/library/stdarch/crates/intrinsic-test/src/main.rs b/library/stdarch/crates/intrinsic-test/src/main.rs index 054138a0dba..538f317a297 100644 --- a/library/stdarch/crates/intrinsic-test/src/main.rs +++ b/library/stdarch/crates/intrinsic-test/src/main.rs @@ -30,12 +30,15 @@ fn main() { let test_environment = test_environment_result.unwrap(); + info!("building C binaries"); if !test_environment.build_c_file() { std::process::exit(2); } + info!("building Rust binaries"); if !test_environment.build_rust_file() { std::process::exit(3); } + info!("comaparing outputs"); if !test_environment.compare_outputs() { std::process::exit(1); } diff --git a/library/stdarch/crates/simd-test-macro/src/lib.rs b/library/stdarch/crates/simd-test-macro/src/lib.rs index aa36cb928a4..b18e2d6b63e 100644 --- a/library/stdarch/crates/simd-test-macro/src/lib.rs +++ b/library/stdarch/crates/simd-test-macro/src/lib.rs @@ -62,7 +62,7 @@ pub fn simd_test( maybe_riscv if maybe_riscv.starts_with("riscv") => "is_riscv_feature_detected", "powerpc" | "powerpcle" => "is_powerpc_feature_detected", "powerpc64" | "powerpc64le" => "is_powerpc64_feature_detected", - "loongarch64" => "is_loongarch_feature_detected", + "loongarch32" | "loongarch64" => "is_loongarch_feature_detected", "s390x" => "is_s390x_feature_detected", t => panic!("unknown target: {t}"), }; diff --git a/library/stdarch/crates/std_detect/README.md b/library/stdarch/crates/std_detect/README.md index 091f5542e0e..edc90d319a1 100644 --- a/library/stdarch/crates/std_detect/README.md +++ b/library/stdarch/crates/std_detect/README.md @@ -55,7 +55,7 @@ crate from working on applications in which `std` is not available. application. * Linux/Android: - * `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `loongarch64`, `s390x`: + * `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `loongarch{32,64}`, `s390x`: `std_detect` supports these on Linux by querying ELF auxiliary vectors (using `getauxval` when available), and if that fails, by querying `/proc/self/auxv`. * `arm64`: partial support for doing run-time feature detection by directly diff --git a/library/stdarch/crates/std_detect/src/detect/arch/loongarch.rs b/library/stdarch/crates/std_detect/src/detect/arch/loongarch.rs index e9d68f6a9bf..68fc600fa8e 100644 --- a/library/stdarch/crates/std_detect/src/detect/arch/loongarch.rs +++ b/library/stdarch/crates/std_detect/src/detect/arch/loongarch.rs @@ -2,7 +2,7 @@ features! { @TARGET: loongarch; - @CFG: target_arch = "loongarch64"; + @CFG: any(target_arch = "loongarch32", target_arch = "loongarch64"); @MACRO_NAME: is_loongarch_feature_detected; @MACRO_ATTRS: /// Checks if `loongarch` feature is enabled. diff --git a/library/stdarch/crates/std_detect/src/detect/arch/mod.rs b/library/stdarch/crates/std_detect/src/detect/arch/mod.rs index d5a13acc028..b0be554ed89 100644 --- a/library/stdarch/crates/std_detect/src/detect/arch/mod.rs +++ b/library/stdarch/crates/std_detect/src/detect/arch/mod.rs @@ -49,7 +49,7 @@ cfg_if! { } else if #[cfg(target_arch = "mips64")] { #[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")] pub use mips64::*; - } else if #[cfg(target_arch = "loongarch64")] { + } else if #[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64"))] { #[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")] pub use loongarch::*; } else if #[cfg(target_arch = "s390x")] { diff --git a/library/stdarch/crates/std_detect/src/detect/mod.rs b/library/stdarch/crates/std_detect/src/detect/mod.rs index 8fd3d957932..a9e9709c1f6 100644 --- a/library/stdarch/crates/std_detect/src/detect/mod.rs +++ b/library/stdarch/crates/std_detect/src/detect/mod.rs @@ -103,6 +103,7 @@ pub fn features() -> impl Iterator<Item = (&'static str, bool)> { target_arch = "powerpc64", target_arch = "mips", target_arch = "mips64", + target_arch = "loongarch32", target_arch = "loongarch64", target_arch = "s390x", ))] { diff --git a/library/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs b/library/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs index c30379ff065..54f52aa7533 100644 --- a/library/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs +++ b/library/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs @@ -80,6 +80,7 @@ pub(crate) fn auxv() -> Result<AuxVec, ()> { target_arch = "riscv64", target_arch = "mips", target_arch = "mips64", + target_arch = "loongarch32", target_arch = "loongarch64", ))] { @@ -182,6 +183,7 @@ fn auxv_from_buf(buf: &[usize]) -> Result<AuxVec, ()> { target_arch = "riscv64", target_arch = "mips", target_arch = "mips64", + target_arch = "loongarch32", target_arch = "loongarch64", ))] { diff --git a/library/stdarch/crates/std_detect/src/detect/os/linux/mod.rs b/library/stdarch/crates/std_detect/src/detect/os/linux/mod.rs index 8c689d0b1f0..9accd41717b 100644 --- a/library/stdarch/crates/std_detect/src/detect/os/linux/mod.rs +++ b/library/stdarch/crates/std_detect/src/detect/os/linux/mod.rs @@ -51,7 +51,7 @@ cfg_if::cfg_if! { } else if #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] { mod powerpc; pub(crate) use self::powerpc::detect_features; - } else if #[cfg(target_arch = "loongarch64")] { + } else if #[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64"))] { mod loongarch; pub(crate) use self::loongarch::detect_features; } else if #[cfg(target_arch = "s390x")] { diff --git a/library/stdarch/crates/std_detect/tests/macro_trailing_commas.rs b/library/stdarch/crates/std_detect/tests/macro_trailing_commas.rs index fa3a23c7968..2fee0abdd57 100644 --- a/library/stdarch/crates/std_detect/tests/macro_trailing_commas.rs +++ b/library/stdarch/crates/std_detect/tests/macro_trailing_commas.rs @@ -11,6 +11,7 @@ target_arch = "s390x", target_arch = "riscv32", target_arch = "riscv64", + target_arch = "loongarch32", target_arch = "loongarch64" ), feature(stdarch_internal) @@ -30,7 +31,7 @@ feature(stdarch_riscv_feature_detection) )] #![cfg_attr( - target_arch = "loongarch64", + any(target_arch = "loongarch32", target_arch = "loongarch64"), feature(stdarch_loongarch_feature_detection) )] @@ -45,6 +46,7 @@ target_arch = "s390x", target_arch = "riscv32", target_arch = "riscv64", + target_arch = "loongarch32", target_arch = "loongarch64" ))] #[macro_use] @@ -65,8 +67,8 @@ fn aarch64() { } #[test] -#[cfg(target_arch = "loongarch64")] -fn loongarch64() { +#[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64"))] +fn loongarch() { let _ = is_loongarch_feature_detected!("lsx"); let _ = is_loongarch_feature_detected!("lsx",); } diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index 8fa33e5bb33..b20c1b3c36b 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -6580,7 +6580,6 @@ intrinsics: arch: aarch64,arm64ec - - name: "vmaxnm{neon_type.no}" doc: Floating-point Maximum Number (vector) arguments: ["a: {neon_type}", "b: {neon_type}"] @@ -6592,11 +6591,7 @@ intrinsics: - float64x1_t - float64x2_t compose: - - LLVMLink: - name: "fmaxnm.{neon_type}" - links: - - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" - arch: aarch64,arm64ec + - FnCall: [simd_fmax, [a, b]] - name: "vmaxnmh_{type}" @@ -6611,11 +6606,7 @@ intrinsics: types: - f16 compose: - - LLVMLink: - name: "vmaxh.{neon_type}" - links: - - link: "llvm.aarch64.neon.fmaxnm.{type}" - arch: aarch64,arm64ec + - FnCall: ["f16::max", [a, b]] - name: "vminnmh_{type}" @@ -6630,11 +6621,7 @@ intrinsics: types: - f16 compose: - - LLVMLink: - name: "vminh.{neon_type}" - links: - - link: "llvm.aarch64.neon.fminnm.{type}" - arch: aarch64,arm64ec + - FnCall: ["f16::min", [a, b]] - name: "vmaxnmv{neon_type[0].no}" @@ -6648,11 +6635,7 @@ intrinsics: - [float32x2_t, f32] - [float64x2_t, f64] compose: - - LLVMLink: - name: "fmaxnmv.{neon_type[0]}" - links: - - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_max, [a]] - name: "vmaxnmv{neon_type[0].no}" doc: Floating-point maximum number across vector @@ -6664,11 +6647,7 @@ intrinsics: types: - [float32x4_t, f32] compose: - - LLVMLink: - name: "fmaxnmv.{neon_type[0]}" - links: - - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_max, [a]] - name: "vmaxnmv{neon_type[0].no}" @@ -6684,11 +6663,7 @@ intrinsics: - [float16x4_t, f16] - [float16x8_t, f16] compose: - - LLVMLink: - name: "fmaxnmv.{neon_type[0]}" - links: - - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_max, [a]] - name: "vminnmv{neon_type[0].no}" @@ -6704,11 +6679,7 @@ intrinsics: - [float16x4_t, f16] - [float16x8_t, f16] compose: - - LLVMLink: - name: "fminnmv.{neon_type[0]}" - links: - - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_min, [a]] - name: "vmaxv{neon_type[0].no}" @@ -6814,11 +6785,7 @@ intrinsics: - float64x1_t - float64x2_t compose: - - LLVMLink: - name: "fminnm.{neon_type}" - links: - - link: "llvm.aarch64.neon.fminnm.{neon_type}" - arch: aarch64,arm64ec + - FnCall: [simd_fmin, [a, b]] - name: "vminnmv{neon_type[0].no}" doc: "Floating-point minimum number across vector" @@ -6832,11 +6799,7 @@ intrinsics: - [float32x2_t, "f32"] - [float64x2_t, "f64"] compose: - - LLVMLink: - name: "vminnmv.{neon_type[0]}" - links: - - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_min, [a]] - name: "vminnmv{neon_type[0].no}" doc: "Floating-point minimum number across vector" @@ -6849,11 +6812,7 @@ intrinsics: types: - [float32x4_t, "f32"] compose: - - LLVMLink: - name: "vminnmv.{neon_type[0]}" - links: - - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_min, [a]] - name: "vmovl_high{neon_type[0].noq}" doc: Vector move @@ -13322,11 +13281,7 @@ intrinsics: - [int16x8_t, i16, 'smaxv'] - [int32x4_t, i32, 'smaxv'] compose: - - LLVMLink: - name: "vmaxv{neon_type[0].no}" - links: - - link: "llvm.aarch64.neon.smaxv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_max, [a]] - name: "vmaxv{neon_type[0].no}" doc: "Horizontal vector max." @@ -13344,11 +13299,7 @@ intrinsics: - [uint16x8_t, u16, 'umaxv'] - [uint32x4_t, u32, 'umaxv'] compose: - - LLVMLink: - name: "vmaxv{neon_type[0].no}" - links: - - link: "llvm.aarch64.neon.umaxv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_max, [a]] - name: "vmaxv{neon_type[0].no}" doc: "Horizontal vector max." @@ -13385,11 +13336,7 @@ intrinsics: - [int16x8_t, i16, 'sminv'] - [int32x4_t, i32, 'sminv'] compose: - - LLVMLink: - name: "vminv{neon_type[0].no}" - links: - - link: "llvm.aarch64.neon.sminv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_min, [a]] - name: "vminv{neon_type[0].no}" doc: "Horizontal vector min." @@ -13407,11 +13354,7 @@ intrinsics: - [uint16x8_t, u16, 'uminv'] - [uint32x4_t, u32, 'uminv'] compose: - - LLVMLink: - name: "vminv{neon_type[0].no}" - links: - - link: "llvm.aarch64.neon.uminv.{type[1]}.{neon_type[0]}" - arch: aarch64,arm64ec + - FnCall: [simd_reduce_min, [a]] - name: "vminv{neon_type[0].no}" doc: "Horizontal vector min." diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 58c26ae4f80..e0667228d2e 100644 --- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -7223,13 +7223,7 @@ intrinsics: - float32x2_t - float32x4_t compose: - - LLVMLink: - name: "fmaxnm.{neon_type}" - links: - - link: "llvm.arm.neon.vmaxnm.{neon_type}" - arch: arm - - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" - arch: aarch64,arm64ec + - FnCall: [simd_fmax, [a, b]] - name: "vmaxnm{neon_type.no}" @@ -7247,13 +7241,7 @@ intrinsics: - float16x4_t - float16x8_t compose: - - LLVMLink: - name: "fmaxnm.{neon_type}" - links: - - link: "llvm.arm.neon.vmaxnm.{neon_type}" - arch: arm - - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" - arch: aarch64,arm64ec + - FnCall: [simd_fmax, [a, b]] - name: "vminnm{neon_type.no}" @@ -7271,13 +7259,7 @@ intrinsics: - float16x4_t - float16x8_t compose: - - LLVMLink: - name: "fminnm.{neon_type}" - links: - - link: "llvm.arm.neon.vminnm.{neon_type}" - arch: arm - - link: "llvm.aarch64.neon.fminnm.{neon_type}" - arch: aarch64,arm64ec + - FnCall: [simd_fmin, [a, b]] - name: "vmin{neon_type.no}" @@ -7388,13 +7370,7 @@ intrinsics: - float32x2_t - float32x4_t compose: - - LLVMLink: - name: "fminnm.{neon_type}" - links: - - link: "llvm.arm.neon.vminnm.{neon_type}" - arch: arm - - link: "llvm.aarch64.neon.fminnm.{neon_type}" - arch: aarch64,arm64ec + - FnCall: [simd_fmin, [a, b]] - name: "vpadd{neon_type.no}" doc: Floating-point add pairwise |