diff options
Diffstat (limited to 'compiler/rustc_target/src')
9 files changed, 37 insertions, 16 deletions
diff --git a/compiler/rustc_target/src/callconv/loongarch.rs b/compiler/rustc_target/src/callconv/loongarch.rs index c779720f97b..27b41cc09ed 100644 --- a/compiler/rustc_target/src/callconv/loongarch.rs +++ b/compiler/rustc_target/src/callconv/loongarch.rs @@ -334,7 +334,7 @@ where Ty: TyAbiInterface<'a, C> + Copy, C: HasDataLayout + HasTargetSpec, { - let xlen = cx.data_layout().pointer_size.bits(); + let xlen = cx.data_layout().pointer_size().bits(); let flen = match &cx.target_spec().llvm_abiname[..] { "ilp32f" | "lp64f" => 32, "ilp32d" | "lp64d" => 64, @@ -369,7 +369,7 @@ where Ty: TyAbiInterface<'a, C> + Copy, C: HasDataLayout + HasTargetSpec, { - let grlen = cx.data_layout().pointer_size.bits(); + let grlen = cx.data_layout().pointer_size().bits(); for arg in fn_abi.args.iter_mut() { if arg.is_ignore() { diff --git a/compiler/rustc_target/src/callconv/mips.rs b/compiler/rustc_target/src/callconv/mips.rs index 6162267a0d0..48a01da865b 100644 --- a/compiler/rustc_target/src/callconv/mips.rs +++ b/compiler/rustc_target/src/callconv/mips.rs @@ -10,7 +10,7 @@ where ret.extend_integer_width_to(32); } else { ret.make_indirect(); - *offset += cx.data_layout().pointer_size; + *offset += cx.data_layout().pointer_size(); } } diff --git a/compiler/rustc_target/src/callconv/mod.rs b/compiler/rustc_target/src/callconv/mod.rs index 71cc2a45563..ab3271220eb 100644 --- a/compiler/rustc_target/src/callconv/mod.rs +++ b/compiler/rustc_target/src/callconv/mod.rs @@ -733,7 +733,7 @@ impl<'a, Ty> FnAbi<'a, Ty> { } if arg_idx.is_none() - && arg.layout.size > Primitive::Pointer(AddressSpace::DATA).size(cx) * 2 + && arg.layout.size > Primitive::Pointer(AddressSpace::ZERO).size(cx) * 2 && !matches!(arg.layout.backend_repr, BackendRepr::SimdVector { .. }) { // Return values larger than 2 registers using a return area @@ -792,7 +792,7 @@ impl<'a, Ty> FnAbi<'a, Ty> { let size = arg.layout.size; if arg.layout.is_sized() - && size <= Primitive::Pointer(AddressSpace::DATA).size(cx) + && size <= Primitive::Pointer(AddressSpace::ZERO).size(cx) { // We want to pass small aggregates as immediates, but using // an LLVM aggregate type for this leads to bad optimizations, diff --git a/compiler/rustc_target/src/callconv/riscv.rs b/compiler/rustc_target/src/callconv/riscv.rs index 6a2038f9381..a06f54d60e7 100644 --- a/compiler/rustc_target/src/callconv/riscv.rs +++ b/compiler/rustc_target/src/callconv/riscv.rs @@ -418,7 +418,7 @@ where "ilp32d" | "lp64d" => 64, _ => 0, }; - let xlen = cx.data_layout().pointer_size.bits(); + let xlen = cx.data_layout().pointer_size().bits(); let mut avail_gprs = 8; let mut avail_fprs = 8; @@ -448,7 +448,7 @@ where Ty: TyAbiInterface<'a, C> + Copy, C: HasDataLayout + HasTargetSpec, { - let xlen = cx.data_layout().pointer_size.bits(); + let xlen = cx.data_layout().pointer_size().bits(); for arg in fn_abi.args.iter_mut() { if arg.is_ignore() { diff --git a/compiler/rustc_target/src/callconv/sparc.rs b/compiler/rustc_target/src/callconv/sparc.rs index 6162267a0d0..48a01da865b 100644 --- a/compiler/rustc_target/src/callconv/sparc.rs +++ b/compiler/rustc_target/src/callconv/sparc.rs @@ -10,7 +10,7 @@ where ret.extend_integer_width_to(32); } else { ret.make_indirect(); - *offset += cx.data_layout().pointer_size; + *offset += cx.data_layout().pointer_size(); } } diff --git a/compiler/rustc_target/src/callconv/x86.rs b/compiler/rustc_target/src/callconv/x86.rs index bdf116ff303..918b71c80c4 100644 --- a/compiler/rustc_target/src/callconv/x86.rs +++ b/compiler/rustc_target/src/callconv/x86.rs @@ -219,7 +219,7 @@ where // SSE ABI. We prefer this over integer registers as float scalars need to be in SSE // registers for float operations, so that's the best place to pass them around. fn_abi.ret.cast_to(Reg { kind: RegKind::Vector, size: fn_abi.ret.layout.size }); - } else if fn_abi.ret.layout.size <= Primitive::Pointer(AddressSpace::DATA).size(cx) { + } else if fn_abi.ret.layout.size <= Primitive::Pointer(AddressSpace::ZERO).size(cx) { // Same size or smaller than pointer, return in an integer register. fn_abi.ret.cast_to(Reg { kind: RegKind::Integer, size: fn_abi.ret.layout.size }); } else { diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index 7a49f004072..4bc0d88a910 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -725,7 +725,7 @@ impl ToJson for LinkSelfContainedComponents { } bitflags::bitflags! { - /// The `-Z linker-features` components that can individually be enabled or disabled. + /// The `-C linker-features` components that can individually be enabled or disabled. /// /// They are feature flags intended to be a more flexible mechanism than linker flavors, and /// also to prevent a combinatorial explosion of flavors whenever a new linker feature is @@ -756,7 +756,7 @@ bitflags::bitflags! { rustc_data_structures::external_bitflags_debug! { LinkerFeatures } impl LinkerFeatures { - /// Parses a single `-Z linker-features` well-known feature, not a set of flags. + /// Parses a single `-C linker-features` well-known feature, not a set of flags. pub fn from_str(s: &str) -> Option<LinkerFeatures> { Some(match s { "cc" => LinkerFeatures::CC, @@ -765,6 +765,17 @@ impl LinkerFeatures { }) } + /// Return the linker feature name, as would be passed on the CLI. + /// + /// Returns `None` if the bitflags aren't a singular component (but a mix of multiple flags). + pub fn as_str(self) -> Option<&'static str> { + Some(match self { + LinkerFeatures::CC => "cc", + LinkerFeatures::LLD => "lld", + _ => return None, + }) + } + /// Returns whether the `lld` linker feature is enabled. pub fn is_lld_enabled(self) -> bool { self.contains(LinkerFeatures::LLD) @@ -2198,7 +2209,10 @@ pub struct TargetMetadata { impl Target { pub fn parse_data_layout(&self) -> Result<TargetDataLayout, TargetDataLayoutErrors<'_>> { - let mut dl = TargetDataLayout::parse_from_llvm_datalayout_string(&self.data_layout)?; + let mut dl = TargetDataLayout::parse_from_llvm_datalayout_string( + &self.data_layout, + self.options.default_address_space, + )?; // Perform consistency checks against the Target information. if dl.endian != self.endian { @@ -2209,9 +2223,10 @@ impl Target { } let target_pointer_width: u64 = self.pointer_width.into(); - if dl.pointer_size.bits() != target_pointer_width { + let dl_pointer_size: u64 = dl.pointer_size().bits(); + if dl_pointer_size != target_pointer_width { return Err(TargetDataLayoutErrors::InconsistentTargetPointerWidth { - pointer_size: dl.pointer_size.bits(), + pointer_size: dl_pointer_size, target: self.pointer_width, }); } @@ -2650,6 +2665,11 @@ pub struct TargetOptions { /// Whether the target supports XRay instrumentation. pub supports_xray: bool, + /// The default address space for this target. When using LLVM as a backend, most targets simply + /// use LLVM's default address space (0). Some other targets, such as CHERI targets, use a + /// custom default address space (in this specific case, `200`). + pub default_address_space: rustc_abi::AddressSpace, + /// Whether the targets supports -Z small-data-threshold small_data_threshold_support: SmallDataThresholdSupport, } @@ -2878,6 +2898,7 @@ impl Default for TargetOptions { entry_name: "main".into(), entry_abi: CanonAbi::C, supports_xray: false, + default_address_space: rustc_abi::AddressSpace::ZERO, small_data_threshold_support: SmallDataThresholdSupport::DefaultForArch, } } diff --git a/compiler/rustc_target/src/spec/targets/mips64_unknown_linux_muslabi64.rs b/compiler/rustc_target/src/spec/targets/mips64_unknown_linux_muslabi64.rs index fd509503053..f95ce756354 100644 --- a/compiler/rustc_target/src/spec/targets/mips64_unknown_linux_muslabi64.rs +++ b/compiler/rustc_target/src/spec/targets/mips64_unknown_linux_muslabi64.rs @@ -5,7 +5,7 @@ use crate::spec::{Target, TargetMetadata, TargetOptions, base}; pub(crate) fn target() -> Target { let mut base = base::linux_musl::opts(); base.cpu = "mips64r2".into(); - base.features = "+mips64r2".into(); + base.features = "+mips64r2,+xgot".into(); base.max_atomic_width = Some(64); Target { // LLVM doesn't recognize "muslabi64" yet. diff --git a/compiler/rustc_target/src/spec/targets/mips64el_unknown_linux_muslabi64.rs b/compiler/rustc_target/src/spec/targets/mips64el_unknown_linux_muslabi64.rs index aa087b1a35a..d42e097b0fd 100644 --- a/compiler/rustc_target/src/spec/targets/mips64el_unknown_linux_muslabi64.rs +++ b/compiler/rustc_target/src/spec/targets/mips64el_unknown_linux_muslabi64.rs @@ -3,7 +3,7 @@ use crate::spec::{Target, TargetMetadata, TargetOptions, base}; pub(crate) fn target() -> Target { let mut base = base::linux_musl::opts(); base.cpu = "mips64r2".into(); - base.features = "+mips64r2".into(); + base.features = "+mips64r2,+xgot".into(); base.max_atomic_width = Some(64); // FIXME(compiler-team#422): musl targets should be dynamically linked by default. base.crt_static_default = true; |