1 files changed, 320 insertions, 0 deletions
diff --git a/library/stdarch/crates/intrinsic-test/missing_arm.txt b/library/stdarch/crates/intrinsic-test/missing_arm.txt
new file mode 100644
index 00000000000..04c09a27d90
--- /dev/null
+++ b/library/stdarch/crates/intrinsic-test/missing_arm.txt
@@ -0,0 +1,320 @@
+# Not implemented in stdarch yet
+vbfdot_f32
+vbfdot_lane_f32
+vbfdot_laneq_f32
+vbfdotq_f32
+vbfdotq_lane_f32
+vbfdotq_laneq_f32
+vbfmlalbq_f32
+vbfmlalbq_lane_f32
+vbfmlalbq_laneq_f32
+vbfmlaltq_f32
+vbfmlaltq_lane_f32
+vbfmlaltq_laneq_f32
+vbfmmlaq_f32
+
+# Implemented in Clang and stdarch for A64 only even though CSV claims A32 support
+vaddq_p64
+vbsl_p64
+vbslq_p64
+vceq_p64
+vceqq_p64
+vceqz_p64
+vceqzq_p64
+vcombine_p64
+vcopy_lane_p64
+vcopy_laneq_p64
+vcopyq_lane_p64
+vcopyq_laneq_p64
+vcreate_p64
+vdup_lane_p64
+vdup_n_p64
+vdupq_lane_p64
+vdupq_n_p64
+vext_p64
+vextq_p64
+vget_high_p64
+vget_lane_p64
+vget_low_p64
+vgetq_lane_p64
+vmovn_high_s16
+vmovn_high_s32
+vmovn_high_s64
+vmovn_high_u16
+vmovn_high_u32
+vmovn_high_u64
+vmull_high_p64
+vmull_p64
+vreinterpret_p16_p64
+vreinterpret_p64_f32
+vreinterpret_p64_p16
+vreinterpret_p64_p8
+vreinterpret_p64_s16
+vreinterpret_p64_s32
+vreinterpret_p64_s8
+vreinterpret_p64_u16
+vreinterpret_p64_u32
+vreinterpret_p64_u64
+vreinterpret_p64_u8
+vreinterpret_p8_p64
+vreinterpretq_f64_u64
+vreinterpretq_p128_f32
+vreinterpretq_p128_p16
+vreinterpretq_p128_p8
+vreinterpretq_p128_s16
+vreinterpretq_p128_s32
+vreinterpretq_p128_s64
+vreinterpretq_p128_s8
+vreinterpretq_p128_u16
+vreinterpretq_p128_u32
+vreinterpretq_p128_u64
+vreinterpretq_p128_u8
+vreinterpretq_p16_p64
+vreinterpretq_p64_f32
+vreinterpretq_p64_p16
+vreinterpretq_p64_p8
+vreinterpretq_p64_s16
+vreinterpretq_p64_s32
+vreinterpretq_p64_s64
+vreinterpretq_p64_s8
+vreinterpretq_p64_u16
+vreinterpretq_p64_u32
+vreinterpretq_p64_u64
+vreinterpretq_p64_u8
+vreinterpretq_p8_p64
+vreinterpretq_s16_p64
+vreinterpretq_s32_p64
+vreinterpretq_s64_p64
+vreinterpretq_s8_p64
+vreinterpretq_u16_p64
+vreinterpretq_u32_p64
+vreinterpretq_u64_p64
+vreinterpretq_u8_p64
+vreinterpret_s16_p64
+vreinterpret_s32_p64
+vreinterpret_s64_p64
+vreinterpret_s8_p64
+vreinterpret_u16_p64
+vreinterpret_u32_p64
+vreinterpret_u64_p64
+vreinterpret_u8_p64
+vrndn_f64
+vrndnq_f64
+vset_lane_p64
+vsetq_lane_p64
+vsli_n_p64
+vsliq_n_p64
+vsri_n_p64
+vsriq_n_p64
+vtst_p64
+vtstq_p64
+vaddh_f16
+vsubh_f16
+vabsh_f16
+vdivh_f16
+vmulh_f16
+vfmsh_f16
+vfmah_f16
+vminnmh_f16
+vmaxnmh_f16
+vrndh_f16
+vrndnh_f16
+vrndih_f16
+vrndah_f16
+vrndph_f16
+vrndmh_f16
+vrndxh_f16
+vsqrth_f16
+vnegh_f16
+vcvth_f16_s32
+vcvth_s32_f16
+vcvth_n_f16_s32
+vcvth_n_s32_f16
+vcvth_f16_u32
+vcvth_u32_f16
+vcvth_n_f16_u32
+vcvth_n_u32_f16
+vcvtah_s32_f16
+vcvtah_u32_f16
+vcvtmh_s32_f16
+vcvtmh_u32_f16
+vcvtpq_s16_f16
+vcvtpq_u16_f16
+vcvtp_s16_f16
+vcvtp_u16_f16
+vcvtph_s32_f16
+vcvtph_u32_f16
+vcvtnh_u32_f16
+vcvtnh_s32_f16
+vfmlsl_low_f16
+vfmlslq_low_f16
+vfmlsl_high_f16
+vfmlslq_high_f16
+vfmlsl_lane_high_f16
+vfmlsl_laneq_high_f16
+vfmlslq_lane_high_f16
+vfmlslq_laneq_high_f16
+vfmlsl_lane_low_f16
+vfmlsl_laneq_low_f16
+vfmlslq_lane_low_f16
+vfmlslq_laneq_low_f16
+vfmlal_low_f16
+vfmlalq_low_f16
+vfmlal_high_f16
+vfmlalq_high_f16
+vfmlal_lane_low_f16
+vfmlal_laneq_low_f16
+vfmlalq_lane_low_f16
+vfmlalq_laneq_low_f16
+vfmlal_lane_high_f16
+vfmlal_laneq_high_f16
+vfmlalq_lane_high_f16
+vfmlalq_laneq_high_f16
+vreinterpret_f16_p64
+vreinterpretq_f16_p64
+vreinterpret_p64_f16
+vreinterpretq_p64_f16
+vreinterpret_p128_f16
+vreinterpretq_p128_f16
+
+# Present in Clang header but triggers an ICE due to lack of backend support.
+vcmla_f32
+vcmla_lane_f32
+vcmla_laneq_f32
+vcmla_rot180_f32
+vcmla_rot180_lane_f32
+vcmla_rot180_laneq_f32
+vcmla_rot270_f32
+vcmla_rot270_lane_f32
+vcmla_rot270_laneq_f32
+vcmla_rot90_f32
+vcmla_rot90_lane_f32
+vcmla_rot90_laneq_f32
+vcmlaq_f32
+vcmlaq_lane_f32
+vcmlaq_laneq_f32
+vcmlaq_rot180_f32
+vcmlaq_rot180_lane_f32
+vcmlaq_rot180_laneq_f32
+vcmlaq_rot270_f32
+vcmlaq_rot270_lane_f32
+vcmlaq_rot270_laneq_f32
+vcmlaq_rot90_f32
+vcmlaq_rot90_lane_f32
+vcmlaq_rot90_laneq_f32
+vcmla_f16
+vcmlaq_f16
+vcmla_laneq_f16
+vcmla_lane_f16
+vcmla_laneq_f16
+vcmlaq_lane_f16
+vcmlaq_laneq_f16
+vcmla_rot90_f16
+vcmlaq_rot90_f16
+vcmla_rot180_f16
+vcmlaq_rot180_f16
+vcmla_rot270_f16
+vcmlaq_rot270_f16
+vcmla_rot90_lane_f16
+vcmla_rot90_laneq_f16
+vcmlaq_rot90_lane_f16
+vcmlaq_rot90_laneq_f16
+vcmla_rot180_lane_f16
+vcmla_rot180_laneq_f16
+vcmlaq_rot180_lane_f16
+vcmlaq_rot180_laneq_f16
+vcmla_rot270_lane_f16
+vcmla_rot270_laneq_f16
+vcmlaq_rot270_lane_f16
+vcmlaq_rot270_laneq_f16
+
+# Implemented in stdarch for A64 only, Clang support both A32/A64
+vadd_s64
+vadd_u64
+vcaddq_rot270_f32
+vcaddq_rot90_f32
+vcadd_rot270_f32
+vcadd_rot90_f32
+vcvtaq_s32_f32
+vcvtaq_u32_f32
+vcvta_s32_f32
+vcvta_u32_f32
+vcvtmq_s32_f32
+vcvtmq_u32_f32
+vcvtm_s32_f32
+vcvtm_u32_f32
+vcvtnq_s32_f32
+vcvtnq_u32_f32
+vcvtn_s32_f32
+vcvtn_u32_f32
+vcvtpq_s32_f32
+vcvtpq_u32_f32
+vcvtp_s32_f32
+vcvtp_u32_f32
+vqdmulh_lane_s16
+vqdmulh_lane_s32
+vqdmulhq_lane_s16
+vqdmulhq_lane_s32
+vrnda_f32
+vrnda_f32
+vrndaq_f32
+vrndaq_f32
+vrnd_f32
+vrnd_f32
+vrndi_f32
+vrndi_f32
+vrndiq_f32
+vrndiq_f32
+vrndm_f32
+vrndm_f32
+vrndmq_f32
+vrndmq_f32
+vrndns_f32
+vrndp_f32
+vrndpq_f32
+vrndq_f32
+vrndq_f32
+vrndx_f32
+vrndxq_f32
+vrnda_f16
+vrnda_f16
+vrndaq_f16
+vrndaq_f16
+vrnd_f16
+vrnd_f16
+vrndi_f16
+vrndi_f16
+vrndiq_f16
+vrndiq_f16
+vrndm_f16
+vrndm_f16
+vrndmq_f16
+vrndmq_f16
+vrndns_f16
+vrndp_f16
+vrndpq_f16
+vrndq_f16
+vrndx_f16
+vrndxq_f16
+vpmin_f16
+vpmax_f16
+vcaddq_rot270_f16
+vcaddq_rot90_f16
+vcadd_rot270_f16
+vcadd_rot90_f16
+vcvtm_s16_f16
+vcvtmq_s16_f16
+vcvtm_u16_f16
+vcvtmq_u16_f16
+vcvtaq_s16_f16
+vcvtaq_u16_f16
+vcvtnq_s16_f16
+vcvtnq_u16_f16
+vcvtn_s16_f16
+vcvtn_u16_f16
+vcvtaq_s16_f16
+vcvtaq_u16_f16
+vcvta_s16_f16
+vcvta_u16_f16
+vceqz_f16
+vceqzq_f16