diff options
Diffstat (limited to 'library/stdarch/crates/std_detect/src')
| -rw-r--r-- | library/stdarch/crates/std_detect/src/detect/arch/riscv.rs | 45 |
1 files changed, 21 insertions, 24 deletions
diff --git a/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs b/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs index e0673165ab7..ed7ea86815a 100644 --- a/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs +++ b/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs @@ -44,34 +44,31 @@ features! { /// * Zifencei: `"zifencei"` /// * Zihintpause: `"zihintpause"` /// * Zihpm: `"zihpm"` - /// * Zk: `"zk"` - /// * Zbkb: `"zbkb"` - /// * Zbkc: `"zbkc"` - /// * Zbkx: `"zbkx"` - /// * Zkn: `"zkn"` - /// * Zknd: `"zknd"` - /// * Zkne: `"zkne"` - /// * Zknh: `"zknh"` - /// * Zkr: `"zkr"` - /// * Zks: `"zks"` - /// * Zksed: `"zksed"` - /// * Zksh: `"zksh"` - /// * Zkt: `"zkt"` - /// - /// There's also bases and extensions marked as standard instruction set, - /// but they are in frozen or draft state. These instruction sets are also - /// reserved by this macro and can be detected in the future platforms. - /// - /// Frozen RISC-V instruction sets: - /// /// * Zfh: `"zfh"` - /// * Zfhmin: `"zfhmin"` + /// * Zfhmin: `"zfhmin"` /// * Zfinx: `"zfinx"` /// * Zdinx: `"zdinx"` /// * Zhinx: `"zhinx"` - /// * Zhinxmin: `"zhinxmin"` + /// * Zhinxmin: `"zhinxmin"` + /// * Zbkb: `"zbkb"` + /// * Zbkc: `"zbkc"` + /// * Zbkx: `"zbkx"` + /// * Zk: `"zk"` + /// * Zkn: `"zkn"` + /// * Zknd: `"zknd"` + /// * Zkne: `"zkne"` + /// * Zknh: `"zknh"` + /// * Zkr: `"zkr"` + /// * Zks: `"zks"` + /// * Zksed: `"zksed"` + /// * Zksh: `"zksh"` + /// * Zkt: `"zkt"` /// * Ztso: `"ztso"` /// + /// There's also bases and extensions marked as standard instruction set, + /// but they are in frozen or draft state. These instruction sets are also + /// reserved by this macro and can be detected in the future platforms. + /// /// Draft RISC-V instruction sets: /// /// * RV128I: `"rv128i"` @@ -81,11 +78,11 @@ features! { /// /// Defined by Privileged Specification: /// - /// * Supervisor: `"s"` + /// * *Supervisor-Level ISA* (not "S" extension): `"s"` + /// * H (hypervisor): `"h"` /// * Svnapot: `"svnapot"` /// * Svpbmt: `"svpbmt"` /// * Svinval: `"svinval"` - /// * Hypervisor: `"h"` /// /// [ISA manual]: https://github.com/riscv/riscv-isa-manual/ #[stable(feature = "riscv_ratified", since = "1.78.0")] |