diff options
Diffstat (limited to 'tests/codegen')
| -rw-r--r-- | tests/codegen/alloc-optimisation.rs | 2 | ||||
| -rw-r--r-- | tests/codegen/asm/s390x-clobbers.rs | 2 | ||||
| -rw-r--r-- | tests/codegen/box-uninit-bytes.rs | 2 | ||||
| -rw-r--r-- | tests/codegen/dealloc-no-unwind.rs | 2 | ||||
| -rw-r--r-- | tests/codegen/iter-repeat-n-trivial-drop.rs | 2 | ||||
| -rw-r--r-- | tests/codegen/slice-is-ascii.rs | 2 | ||||
| -rw-r--r-- | tests/codegen/vec-calloc.rs | 2 | ||||
| -rw-r--r-- | tests/codegen/vec-optimizes-away.rs | 2 |
8 files changed, 8 insertions, 8 deletions
diff --git a/tests/codegen/alloc-optimisation.rs b/tests/codegen/alloc-optimisation.rs index 8abeecf8550..19f14647c1d 100644 --- a/tests/codegen/alloc-optimisation.rs +++ b/tests/codegen/alloc-optimisation.rs @@ -5,7 +5,7 @@ pub fn alloc_test(data: u32) { // CHECK-LABEL: @alloc_test // CHECK-NEXT: start: - // CHECK-NEXT: {{.*}} load volatile i8, ptr @__rust_no_alloc_shim_is_unstable, align 1 + // CHECK-NEXT: {{.*}} load volatile i8, ptr @{{.*}}__rust_no_alloc_shim_is_unstable, align 1 // CHECK-NEXT: ret void let x = Box::new(data); drop(x); diff --git a/tests/codegen/asm/s390x-clobbers.rs b/tests/codegen/asm/s390x-clobbers.rs index cbb6630553c..0ba22a32abf 100644 --- a/tests/codegen/asm/s390x-clobbers.rs +++ b/tests/codegen/asm/s390x-clobbers.rs @@ -1,6 +1,6 @@ //@ add-core-stubs //@ revisions: s390x -//@[s390x] compile-flags: --target s390x-unknown-linux-gnu +//@[s390x] compile-flags: --target s390x-unknown-linux-gnu -C target-cpu=z10 //@[s390x] needs-llvm-components: systemz #![crate_type = "rlib"] diff --git a/tests/codegen/box-uninit-bytes.rs b/tests/codegen/box-uninit-bytes.rs index 3b83ef3e250..0cc01148595 100644 --- a/tests/codegen/box-uninit-bytes.rs +++ b/tests/codegen/box-uninit-bytes.rs @@ -41,6 +41,6 @@ pub fn box_lotsa_padding() -> Box<LotsaPadding> { // Hide the `allocalign` attribute in the declaration of __rust_alloc // from the CHECK-NOT above, and also verify the attributes got set reasonably. -// CHECK: declare {{(dso_local )?}}noalias noundef ptr @__rust_alloc(i{{[0-9]+}} noundef, i{{[0-9]+}} allocalign noundef) unnamed_addr [[RUST_ALLOC_ATTRS:#[0-9]+]] +// CHECK: declare {{(dso_local )?}}noalias noundef ptr @{{.*}}__rust_alloc(i{{[0-9]+}} noundef, i{{[0-9]+}} allocalign noundef) unnamed_addr [[RUST_ALLOC_ATTRS:#[0-9]+]] // CHECK-DAG: attributes [[RUST_ALLOC_ATTRS]] = { {{.*}} allockind("alloc,uninitialized,aligned") allocsize(0) {{(uwtable )?}}"alloc-family"="__rust_alloc" {{.*}} } diff --git a/tests/codegen/dealloc-no-unwind.rs b/tests/codegen/dealloc-no-unwind.rs index c560d7a9932..68597817d6f 100644 --- a/tests/codegen/dealloc-no-unwind.rs +++ b/tests/codegen/dealloc-no-unwind.rs @@ -18,7 +18,7 @@ impl Drop for A { #[no_mangle] pub fn a(a: Box<i32>) { // CHECK-LABEL: define{{.*}}void @a - // CHECK: call void @__rust_dealloc + // CHECK: call void @{{.*}}__rust_dealloc // CHECK-NEXT: call void @foo let _a = A; drop(a); diff --git a/tests/codegen/iter-repeat-n-trivial-drop.rs b/tests/codegen/iter-repeat-n-trivial-drop.rs index 4dab499a8a5..3bb942d11d5 100644 --- a/tests/codegen/iter-repeat-n-trivial-drop.rs +++ b/tests/codegen/iter-repeat-n-trivial-drop.rs @@ -47,7 +47,7 @@ pub fn iter_repeat_n_next(it: &mut std::iter::RepeatN<NotCopy>) -> Option<NotCop #[no_mangle] // CHECK-LABEL: @vec_extend_via_iter_repeat_n pub fn vec_extend_via_iter_repeat_n() -> Vec<u8> { - // CHECK: %[[ADDR:.+]] = tail call {{(noalias )?}}noundef dereferenceable_or_null(1234) ptr @__rust_alloc(i64 noundef {{(range\(i64 1, 0\) )?}}1234, i64 noundef {{(range\(i64 1, -9223372036854775807\) )?}}1) + // CHECK: %[[ADDR:.+]] = tail call {{(noalias )?}}noundef dereferenceable_or_null(1234) ptr @{{.*}}__rust_alloc(i64 noundef {{(range\(i64 1, 0\) )?}}1234, i64 noundef {{(range\(i64 1, -9223372036854775807\) )?}}1) // CHECK: tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(1234) %[[ADDR]], i8 42, i64 1234, let n = 1234_usize; diff --git a/tests/codegen/slice-is-ascii.rs b/tests/codegen/slice-is-ascii.rs index b1e97154609..67537c871a0 100644 --- a/tests/codegen/slice-is-ascii.rs +++ b/tests/codegen/slice-is-ascii.rs @@ -1,5 +1,5 @@ //@ only-x86_64 -//@ compile-flags: -C opt-level=3 +//@ compile-flags: -C opt-level=3 -C target-cpu=x86-64 #![crate_type = "lib"] /// Check that the fast-path of `is_ascii` uses a `pmovmskb` instruction. diff --git a/tests/codegen/vec-calloc.rs b/tests/codegen/vec-calloc.rs index 2e2769ce130..d1c320ead01 100644 --- a/tests/codegen/vec-calloc.rs +++ b/tests/codegen/vec-calloc.rs @@ -177,6 +177,6 @@ pub fn vec_option_i32(n: usize) -> Vec<Option<i32>> { } // Ensure that __rust_alloc_zeroed gets the right attributes for LLVM to optimize it away. -// CHECK: declare noalias noundef ptr @__rust_alloc_zeroed(i64 noundef, i64 allocalign noundef) unnamed_addr [[RUST_ALLOC_ZEROED_ATTRS:#[0-9]+]] +// CHECK: declare noalias noundef ptr @{{.*}}__rust_alloc_zeroed(i64 noundef, i64 allocalign noundef) unnamed_addr [[RUST_ALLOC_ZEROED_ATTRS:#[0-9]+]] // CHECK-DAG: attributes [[RUST_ALLOC_ZEROED_ATTRS]] = { {{.*}} allockind("alloc,zeroed,aligned") allocsize(0) uwtable "alloc-family"="__rust_alloc" {{.*}} } diff --git a/tests/codegen/vec-optimizes-away.rs b/tests/codegen/vec-optimizes-away.rs index 39d5c1614c8..f6ed2898bda 100644 --- a/tests/codegen/vec-optimizes-away.rs +++ b/tests/codegen/vec-optimizes-away.rs @@ -5,7 +5,7 @@ pub fn sum_me() -> i32 { // CHECK-LABEL: @sum_me // CHECK-NEXT: {{^.*:$}} - // CHECK-NEXT: {{.*}} load volatile i8, ptr @__rust_no_alloc_shim_is_unstable, align 1 + // CHECK-NEXT: {{.*}} load volatile i8, ptr @{{.*}}__rust_no_alloc_shim_is_unstable, align 1 // CHECK-NEXT: ret i32 6 vec![1, 2, 3].iter().sum::<i32>() } |