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2023-10-31Enums in offset_of: update based on est31, scottmcm & llogiq reviewGeorge Bateman-17/+12
2023-10-31Support enum variants in offset_of!George Bateman-8/+16
2023-10-25implement C ABI lowering for CSKYdirreke-8/+30
2023-10-13Format all the let chains in compilerMichael Goulet-1/+2
2023-10-02Implement Deref<LayoutS> for LayoutLukas Wirth-0/+7
2023-10-02Add VariantIdx backLukas Wirth-4/+21
2023-10-02Move FieldIdx and Layout to rustc_targetLukas Wirth-0/+82
2023-10-02Bring back generic FieldIdxLukas Wirth-2/+2
2023-09-20rustc_target/loongarch: Fix passing of transparent unions with only one ↵WANG Rui-0/+11
non-ZST member This ensures that `MaybeUninit<T>` has the same ABI as `T` when passed through an `extern "C"` function. Fixes https://github.com/rust-lang/rust/issues/115509
2023-09-19rustc_target/riscv: Fix passing of transparent unions with only one non-ZST ↵msizanoen-0/+19
member This ensures that `MaybeUninit<T>` has the same ABI as `T` when passed through an `extern "C"` function. Fixes https://github.com/rust-lang/rust/issues/115481.
2023-09-17Rollup merge of #115654 - RalfJung:pass-mode-cast, r=compiler-errorsDylan DPC-27/+37
improve PassMode docs
2023-09-15special case `TyAndLayout` debug implBoxy-3/+38
2023-09-15clarify PassMode::Indirect as wellRalf Jung-18/+19
2023-09-15explain PassMode::CastRalf Jung-9/+18
2023-09-12add helper method for finding the one non-1-ZST fieldRalf Jung-0/+21
2023-09-10fix homogeneous_aggregate not ignoring some 1-ZSTRalf Jung-4/+9
2023-09-08turns out Layout has some more things to worry about -- move ABI comparison ↵Ralf Jung-1/+10
into helper function like is_bool, and some special magic extra fields
2023-09-08the wasm ABI behavior is a bugRalf Jung-2/+9
2023-09-08accept some differences for rustc_abi(assert_eq), so that we can test more ↵Ralf Jung-0/+48
things to be compatible
2023-09-07extend comments around PassMode::DirectRalf Jung-1/+3
2023-08-26Use `preserve_mostcc` for `extern "rust-cold"`Scott McMurray-7/+4
As experimentation in 115242 has shown looks better than `coldcc`. And *don't* use a different convention for cold on Windows, because that actually ends up making things worse. cc tracking issue 97544
2023-08-14Update compiler/rustc_target/src/abi/call/csky.rsDirreck-1/+1
Co-authored-by: bjorn3 <17426603+bjorn3@users.noreply.github.com>
2023-08-14add a csky-unknown-linux-gnuabiv2 targetDirreke-0/+33
2023-08-10Auto merge of #114614 - RalfJung:offset-of-sanity, r=cjgillotbors-1/+6
offset_of: guard against invalid use (with unsized fields)
2023-08-08feat: `riscv-interrupt-{m,s}` calling conventionsSeth Pellegrino-0/+25
Similar to prior support added for the mips430, avr, and x86 targets this change implements the rough equivalent of clang's [`__attribute__((interrupt))`][clang-attr] for riscv targets, enabling e.g. ```rust static mut CNT: usize = 0; pub extern "riscv-interrupt-m" fn isr_m() { unsafe { CNT += 1; } } ``` to produce highly effective assembly like: ```asm pub extern "riscv-interrupt-m" fn isr_m() { 420003a0: 1141 addi sp,sp,-16 unsafe { CNT += 1; 420003a2: c62a sw a0,12(sp) 420003a4: c42e sw a1,8(sp) 420003a6: 3fc80537 lui a0,0x3fc80 420003aa: 63c52583 lw a1,1596(a0) # 3fc8063c <_ZN12esp_riscv_rt3CNT17hcec3e3a214887d53E.0> 420003ae: 0585 addi a1,a1,1 420003b0: 62b52e23 sw a1,1596(a0) } } 420003b4: 4532 lw a0,12(sp) 420003b6: 45a2 lw a1,8(sp) 420003b8: 0141 addi sp,sp,16 420003ba: 30200073 mret ``` (disassembly via `riscv64-unknown-elf-objdump -C -S --disassemble ./esp32c3-hal/target/riscv32imc-unknown-none-elf/release/examples/gpio_interrupt`) This outcome is superior to hand-coded interrupt routines which, lacking visibility into any non-assembly body of the interrupt handler, have to be very conservative and save the [entire CPU state to the stack frame][full-frame-save]. By instead asking LLVM to only save the registers that it uses, we defer the decision to the tool with the best context: it can more accurately account for the cost of spills if it knows that every additional register used is already at the cost of an implicit spill. At the LLVM level, this is apparently [implemented by] marking every register as "[callee-save]," matching the semantics of an interrupt handler nicely (it has to leave the CPU state just as it found it after its `{m|s}ret`). This approach is not suitable for every interrupt handler, as it makes no attempt to e.g. save the state in a user-accessible stack frame. For a full discussion of those challenges and tradeoffs, please refer to [the interrupt calling conventions RFC][rfc]. Inside rustc, this implementation differs from prior art because LLVM does not expose the "all-saved" function flavor as a calling convention directly, instead preferring to use an attribute that allows for differentiating between "machine-mode" and "superivsor-mode" interrupts. Finally, some effort has been made to guide those who may not yet be aware of the differences between machine-mode and supervisor-mode interrupts as to why no `riscv-interrupt` calling convention is exposed through rustc, and similarly for why `riscv-interrupt-u` makes no appearance (as it would complicate future LLVM upgrades). [clang-attr]: https://clang.llvm.org/docs/AttributeReference.html#interrupt-risc-v [full-frame-save]: https://github.com/esp-rs/esp-riscv-rt/blob/9281af2ecffe13e40992917316f36920c26acaf3/src/lib.rs#L440-L469 [implemented by]: https://github.com/llvm/llvm-project/blob/b7fb2a3fec7c187d58a6d338ab512d9173bca987/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp#L61-L67 [callee-save]: https://github.com/llvm/llvm-project/blob/973f1fe7a8591c7af148e573491ab68cc15b6ecf/llvm/lib/Target/RISCV/RISCVCallingConv.td#L30-L37 [rfc]: https://github.com/rust-lang/rfcs/pull/3246
2023-08-08offset_of: guard against invalid use (with unsized fields)Ralf Jung-1/+6
2023-07-21Revert "Auto merge of #113166 - moulins:ref-niches-initial, r=oli-obk"David Tolnay-5/+1
This reverts commit 557359f92512ca88b62a602ebda291f17a953002, reversing changes made to 1e6c09a803fd543a98bfbe1624d697a55300a786.
2023-07-21Auto merge of #113922 - matthiaskrgr:rollup-90cj2vv, r=matthiaskrgrbors-21/+0
Rollup of 4 pull requests Successful merges: - #113887 (new solver: add a separate cache for coherence) - #113910 (Add FnPtr ty to SMIR) - #113913 (error/E0691: include alignment in error message) - #113914 (rustc_target: drop duplicate code) r? `@ghost` `@rustbot` modify labels: rollup
2023-07-21rustc_target: drop duplicate codeDavid Rheinsberg-21/+0
Drop duplicate helper methods on `Layout`, which are already implemented on `LayoutS`. Note that `Layout` has a `Deref` implementation to `LayoutS`, so all accessors are automatically redirected. The methods are identical and have been copied to `rustc_abi` in: commit 390a637e296ccfaac4c6abd1291b0523e8a8e00b Author: hamidreza kalbasi <hamidrezakalbasi@protonmail.com> Date: Mon Nov 7 00:36:11 2022 +0330 move things from rustc_target::abi to rustc_abi This commit left behind the original implementation. Drop it now. Signed-off-by: David Rheinsberg <david@readahead.eu>
2023-07-21Don't treat ref. fields with non-null niches as `dereferenceable_or_null`Moulins-1/+5
2023-07-18support for mips32r6 as a target_arch valuechenx97-1/+1
2023-07-18merge patternschenx97-2/+1
2023-07-18support for mips64r6 as a target_arch valuechenx97-0/+1
2023-07-14i686-windows: make requested alignment > 4 special case apply transitivelyErik Desjardins-4/+4
2023-07-10aarch64-linux: properly handle 128bit aligned aggregatesErik Desjardins-36/+44
2023-07-10repr(align) <= 4 should still be byvalErik Desjardins-2/+6
2023-07-10move has_repr to layout, handle repr(transparent) properlyErik Desjardins-15/+2
2023-07-10i686-windows: pass arguments with requested alignment > 4 indirectlyErik Desjardins-4/+33
2023-07-10implement vector-containing aggregate alignment for x86 darwinErik Desjardins-31/+51
2023-07-10rustc_target: Add alignment to indirectly-passed by-value types, correcting thePatrick Walton-13/+47
alignment of `byval` on x86 in the process. Commit 88e4d2c2918428d55e34cd57c11279ea839c8822 from five years ago removed support for alignment on indirectly-passed arguments because of problems with the `i686-pc-windows-msvc` target. Unfortunately, the `memcpy` optimizations I recently added to LLVM 16 depend on this to forward `memcpy`s. This commit attempts to fix the problems with `byval` parameters on that target and now correctly adds the `align` attribute. The problem is summarized in [this comment] by @eddyb. Briefly, 32-bit x86 has special alignment rules for `byval` parameters: for the most part, their alignment is forced to 4. This is not well-documented anywhere but in the Clang source. I looked at the logic in Clang `TargetInfo.cpp` and tried to replicate it here. The relevant methods in that file are `X86_32ABIInfo::getIndirectResult()` and `X86_32ABIInfo::getTypeStackAlignInBytes()`. The `align` parameter attribute for `byval` parameters in LLVM must match the platform ABI, or miscompilations will occur. Note that this doesn't use the approach suggested by eddyb, because I felt it was overkill to store the alignment in `on_stack` when special handling is really only needed for 32-bit x86. As a side effect, this should fix #80127, because it will make the `align` parameter attribute for `byval` parameters match the platform ABI on LLVM x86-64. [this comment]: https://github.com/rust-lang/rust/pull/80822#issuecomment-829985417
2023-07-03abi: avoid ice for non-ffi-safe fn ptrsDavid Wood-4/+6
Remove an `unwrap` that assumed FFI-safe types in foreign fn-ptr types. Signed-off-by: David Wood <david.wood@huawei.com>
2023-06-02Auto merge of #112198 - compiler-errors:rollup-o2xe4of, r=compiler-errorsbors-1/+1
Rollup of 7 pull requests Successful merges: - #111670 (Require that const param tys implement `ConstParamTy`) - #111914 (CFI: Fix cfi with async: transform_ty: unexpected GeneratorWitness(Bi…) - #112030 (Migrate `item_trait_alias` to Askama) - #112150 (Support 128-bit atomics on all x86_64 Apple targets) - #112174 (Fix broken link) - #112190 (Improve comments on `TyCtxt` and `GlobalCtxt`.) - #112193 (Check tuple elements are `Sized` in `offset_of`) Failed merges: - #112071 (Group rfcs tests) r? `@ghost` `@rustbot` modify labels: rollup
2023-06-02Fix broken linkcui fliter-1/+1
Signed-off-by: cui fliter <imcusg@gmail.com>
2023-06-01Use translatable diagnostics in `rustc_const_eval`Deadbeef-11/+0
2023-05-11Rollup merge of #111375 - rcvalle:rust-cfi-fix-106547, r=bjorn3Michael Goulet-4/+4
CFI: Fix SIGILL reached via trait objects Fix #106547 by transforming the concrete self into a reference to a trait object before emitting type metadata identifiers for trait methods.
2023-05-09CFI: Fix SIGILL reached via trait objectsRamon de C Valle-4/+4
Fix #106547 by transforming the concrete self into a reference to a trait object before emitting type metadata identifiers for trait methods.
2023-05-07Use smaller ints for bitflagsNilstrieb-1/+1
2023-04-21offset_ofDrMeepster-0/+15
2023-04-17Spelling - compilerJosh Soref-1/+1
* account * achieved * advising * always * ambiguous * analysis * annotations * appropriate * build * candidates * cascading * category * character * clarification * compound * conceptually * constituent * consts * convenience * corresponds * debruijn * debug * debugable * debuggable * deterministic * discriminant * display * documentation * doesn't * ellipsis * erroneous * evaluability * evaluate * evaluation * explicitly * fallible * fulfill * getting * has * highlighting * illustrative * imported * incompatible * infringing * initialized * into * intrinsic * introduced * javascript * liveness * metadata * monomorphization * nonexistent * nontrivial * obligation * obligations * offset * opaque * opportunities * opt-in * outlive * overlapping * paragraph * parentheses * poisson * precisely * predecessors * predicates * preexisting * propagated * really * reentrant * referent * responsibility * rustonomicon * shortcircuit * simplifiable * simplifications * specify * stabilized * structurally * suggestibility * translatable * transmuting * two * unclosed * uninhabited * visibility * volatile * workaround Signed-off-by: Josh Soref <2119212+jsoref@users.noreply.github.com>
2023-04-10Fix typos in compilerDaniPopes-1/+1
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