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2021-03-14Address review commentsAmanieu d'Antras-7/+7
2021-03-13Always lower asm! to valid HIRAmanieu d'Antras-0/+14
2021-02-21New pass to deduplicate blocksSimon Vandel Sillesen-5/+38
2020-12-10Use Symbol for inline asm register class namesArlie Davis-29/+22
This takes care of one "FIXME": // FIXME: use direct symbol comparison for register class names Instead of using string literals, this uses Symbol for register class names.
2020-12-01Add wasm32 support to inline asmGus Caplan-0/+67
2020-11-12Rollup merge of #78950 - khyperia:spirv-asm, r=AmanieuMara Bos-0/+67
Add asm register information for SPIR-V As discussed in [zulip](https://rust-lang.zulipchat.com/#narrow/stream/182449-t-compiler.2Fhelp/topic/Defining.20asm!.20for.20new.20architecture), we at [rust-gpu](https://github.com/EmbarkStudios/rust-gpu) would like to support `asm!` for our SPIR-V backend. However, we cannot do so purely without frontend support: [this match](https://github.com/rust-lang/rust/blob/d4ea0b3e46a0303d5802b632e88ba1ba84d9d16f/compiler/rustc_target/src/asm/mod.rs#L185) fails and so `asm!` is not supported ([error reported here](https://github.com/rust-lang/rust/blob/d4ea0b3e46a0303d5802b632e88ba1ba84d9d16f/compiler/rustc_ast_lowering/src/expr.rs#L1095)). To resolve this, we need to stub out register information for SPIR-V to support getting the `asm!` content all the way to [`AsmBuilderMethods::codegen_inline_asm`](https://doc.rust-lang.org/nightly/nightly-rustc/rustc_codegen_ssa/traits/trait.AsmBuilderMethods.html#tymethod.codegen_inline_asm), at which point the rust-gpu backend can do all the parsing and codegen that is needed. This is a pretty weird PR - adding support for a backend that isn't in-tree feels pretty gross to me, but I don't see an easy way around this. ``@Amanieu`` said I should submit it anyway, so, here we are! Let me know if this needs to go through a more formal process (MCP?) and what I should do to help this along. I based this off the [wasm asm PR](https://github.com/rust-lang/rust/pull/78684), which unfortunately this PR conflicts with that one quite a bit, sorry for any merge conflict pain :( --- Some open questions: - What do we call the register class? Some context, SPIR-V is an SSA-based IR, there are "instructions" that create IDs (referred to as `<id>` in the spec), which can be referenced by other instructions. So, `reg` isn't exactly accurate, they're SSA IDs, not re-assignable registers. - What happens when a SPIR-V register gets to the LLVM backend? Right now it's a `bug!`, but should that be a `sess.fatal()`? I'm not sure if it's even possible to reach that point, maybe there's a check that prevents the `spirv` target from even reaching that codepath.
2020-11-11Change capitalization of Spirv to SpirVkhyperia-18/+18
This matches the capitalization of RiscV
2020-11-11Add asm register information for SPIR-Vkhyperia-0/+67
2020-11-08Collapse all uses of `target.options.foo` into `target.foo`Vadim Petrochenkov-1/+1
with an eye on merging `TargetOptions` into `Target`. `TargetOptions` as a separate structure is mostly an implementation detail of `Target` construction, all its fields logically belong to `Target` and available from `Target` through `Deref` impls.
2020-10-30Fix even more clippy warningsJoshua Nelson-4/+1
2020-10-04Removes reg aliases since there are many ABIs: o32/n32/n64Lzu Tao-32/+32
2020-10-04Add asm! support for mips64Lzu Tao-7/+12
2020-10-04mips32: Add f64 hard-float supportLzu Tao-1/+1
co-authored-by: Amanieu <amanieu@gmail.com>
2020-09-27Add MIPS asm! supportLzu Tao-0/+157
This patch also: * Add soft-float supports: only f32 * zero-extend i8/i16 to i32 because MIPS only supports register-length arithmetic. * Update table in asm! chapter in unstable book.
2020-08-30mv compiler to compiler/mark-0/+1719