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2023-10-20s/generator/coroutine/Oli Scherer-2/+2
2023-10-20s/Generator/Coroutine/Oli Scherer-1/+1
2023-07-22Merge commit '1eded3619d0e55d57521a259bf27a03906fdfad0' into ↵bjorn3-1/+31
sync_cg_clif-2023-07-22
2023-06-15Merge commit '8830dccd1d4c74f1f69b0d3bd982a3f1fcde5807' into ↵bjorn3-0/+68
sync_cg_clif-2023-06-15
2023-04-29Merge commit 'ef07e8e60f994ec014d049a95591426fb92ebb79' into ↵bjorn3-5/+22
sync_cg_clif-2023-04-29
2023-03-15Merge commit 'dec0daa8f6d0a0e1c702f169abb6bf3eee198c67' into ↵bjorn3-2/+3
sync_cg_clif-2023-03-15
2022-12-14Merge commit '2bb3996244cf1b89878da9e39841e9f6bf061602' into ↵bjorn3-0/+2
sync_cg_clif-2022-12-14
2022-09-27Stabilize bench_black_boxUrgau-1/+1
2022-07-25Merge commit 'c19edfd71a1d0ddef86c2c67fdb40718d40a72b4' into ↵bjorn3-0/+19
sync_cg_clif-2022-07-25
2022-04-22Merge commit 'f2cdd4a78d89c009342197cf5844a21f8aa813df' into ↵bjorn3-1/+5
sync_cg_clif-2022-04-22
2021-07-07Merge commit '3a31c6d8272c14388a34622193baf553636fe470' into ↵bjorn3-2/+0
sync_cg_clif-2021-07-07
2021-05-27Merge commit '40dd3e2b7089b5e96714e064b731f6dbf17c61a9' into ↵bjorn3-15/+1
sync_cg_clif-2021-05-27
2021-04-30Sync rustc_codegen_cranelift 'ddd4ce25535cf71203ba3700896131ce55fde795'Erin Power-0/+3
2020-12-27Merge commit 'dbee13661efa269cb4cd57bb4c6b99a19732b484' into ↵bjorn3-0/+2
sync_cg_clif-2020-12-27
2020-11-27Merge commit '5988bbd24aa87732bfa1d111ba00bcdaa22c481a' into ↵bjorn3-0/+1
sync_cg_clif-2020-11-27
2020-11-03Merge commit '03f01bbe901d60b71cf2c5ec766aef5e532ab79d' into ↵bjorn3-7/+7
update_cg_clif-2020-11-01
2020-08-20Don't test x86_64 simd on archs other than x86_64bjorn3-0/+14
2020-08-15Emulate the cpuid arch intrinsicbjorn3-0/+2
2020-08-08Enable simd insert and extract testsbjorn3-3/+2
Working since rust-lang/stdarch#876 Fixes #666
2020-07-19Implement simd_insertbjorn3-0/+9
2020-07-16Add test for SwitchInt on 128bit integersbjorn3-0/+11
2020-07-03Test signed 128bit discriminantsbjorn3-0/+8
2020-06-20Implement checked_mulbjorn3-0/+23
Fixes #6
2020-06-20Use Cranelift legalization for icmp.i128bjorn3-0/+6
The previous translation was wrong for signed 128bit comparisions This fixes several libcore tests
2020-06-20Implement #[link_section]bjorn3-0/+2
Fixes #1047
2020-04-18Sync fn_sig_for_fn_abi with upstream for generator resume argsbjorn3-2/+6
Fixes #970
2020-03-04Rustup to rustc 1.43.0-nightly (4ad624882 2020-03-03)bjorn3-1/+1
2020-02-26Tls supportbjorn3-0/+4
2019-11-24Run libcore testsbjorn3-0/+4
2019-11-16Fix signed cast to 128bit integerbjorn3-1/+6
2019-11-09Rustup to rustc 1.40.0-nightly (9e346646e 2019-11-08)bjorn3-0/+2
2019-08-21Fix float -> u/i128 castbjorn3-9/+12
The original test casts were optimized away by rustc, so cg_clif never saw them. cc #668
2019-08-21Implement u/i128 <-> float castsbjorn3-0/+11
Fixes #668
2019-08-20Implement saturating_{add,sub} intrinsicsbjorn3-0/+5
2019-08-19Implement pow{f32,f64} intrinsicsbjorn3-0/+1
2019-08-19Implement copysign{f32,f64} intrinsicsbjorn3-0/+1
2019-08-16Workaround for missing `#[rustc_args_required_const(..)]` supportbjorn3-0/+16
cc #666
2019-08-14Cast rhs to lhs type for shl and shrbjorn3-0/+2
2019-08-12Fix some warningsbjorn3-8/+6
2019-08-12Implement log2{f32,f64} intrinsicsbjorn3-0/+1
2019-08-05Implement simd_extractbjorn3-0/+7
2019-08-01Test mutex lockingbjorn3-0/+3
2019-07-31Fix simd_castbjorn3-0/+13
2019-07-30Implement some float simd intrinsicsbjorn3-8/+33
2019-07-29Fix _mm_movemask_epi8bjorn3-0/+3
The order of iteration was wrong
2019-07-29Implement llvm.x86.avx2.pmovmskb llvm intrinsicbjorn3-0/+27
2019-07-29Implement and test simd_shuffle*bjorn3-2/+50
2019-07-29[WIP] simd_shuffle*bjorn3-0/+2
2019-07-29Fix simd comparisonbjorn3-0/+4
2019-07-29Emulate some simd intrinsicsbjorn3-0/+16
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