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2025-09-22Auto merge of #146683 - clarfonthey:safe-intrinsics, r=RalfJung,Amanieubors-20/+20
Mark float intrinsics with no preconditions as safe Note: for ease of reviewing, the list of safe intrinsics is sorted in the first commit, and then safe intrinsics are added in the second commit. All *recently added* float intrinsics have been correctly marked as safe to call due to the fact that they have no preconditions. This adds the remaining float intrinsics which are safe to call to the safe intrinsic list, and removes the unsafe blocks around their calls. --- Side note: this may want a try run before being added to the queue, since I'm not sure if there's any tier-2 code that uses these intrinsics that might not be tested on the usual PR flow. We've already uncovered a few places in subtrees that do this, and it's worth double-checking before clogging up the queue.
2025-09-21Mark float intrinsics with no preconditions as safeltdk-20/+20
2025-09-15Merge pull request #1921 from a4lg/riscv-inline-asm-general-improvementsSayantan Chakraborty-51/+215
RISC-V: Improvements of inline assembly uses
2025-09-15Merge pull request #1919 from sayantn/fix-vreinterpretFolkert de Vries-9286/+6
Remove big-endian swizzles from `vreinterpret`
2025-09-14RISC-V: Improvements of inline assembly usesTsukasa OI-51/+215
This commit performs various improvements (better register allocation, less register clobbering on the worst case and better readability) of RISC-V inline assembly use cases. Note that it does not change the `p` module (which defines the "P" extension draft instructions but very likely to change). 1. Use `lateout` as possible. Unlike `out(reg)` and `in(reg)` pair, `lateout(reg)` and `in(reg)` can share the same register because they state that the late-output register is written after all the reads are performed. It can improve register allocation. 2. Add `preserves_flags` option as possible. While RISC-V doesn't have _regular_ condition codes, RISC-V inline assembly in the Rust language assumes that some registers (mainly vector state registers) may be overwritten by default. By adding `preserves_flags` to the intrinsics corresponding instructions without overwriting them, it can minimize register clobbering on the worst case. 3. Use trailing semicolon. As `asm!` declares an action and it doesn't return a value by itself, it would be better to have trailing semicolon to denote that an `asm!` call is effectively a statement. 4. Make most of `asm!` calls multi-lined. `rustfmt` makes some simple (yet long) `asm!` calls multi-lined but it does not perform formatting of complex `asm!` calls with inputs and/or outputs. To keep consistency, it makes most of the `asm!` calls multi-lined.
2025-09-12stdarch-gen-arm: Make Clippy happyTsukasa OI-1/+1
2025-09-12intrinsic-test: Make Clippy happyTsukasa OI-2/+2
2025-09-11Merge pull request #1918 from a4lg/riscv-aes64im-lower-requirementsSayantan Chakraborty-1/+1
RISC-V: "Lower" requirements of `aes64im`
2025-09-12Remove big-endian swizzles from `vreinterpret`sayantn-9286/+6
2025-09-11RISC-V: "Lower" requirements of `aes64im`Tsukasa OI-1/+1
This instruction is incorrectly categorized as the same one as `aes64ks1i` and `aes64ks2` (that should require `zkne || zknd` but currently require `zkne && zknd`) but `aes64im` only requires the Zknd extension. This commit fixes the category of this intrinsic (lowering the requirements from the Rust perspective but it does not actually lower it from the RISC-V perspective).
2025-09-10loongarch: Align intrinsic signatures with LLVMWANG Rui-16/+20
2025-09-07move target-specific definitions into constantsFolkert de Vries-38/+36
2025-09-07move `build_c_file` and `build_rust_file` into `SupportedArchitectureTest`Folkert de Vries-143/+143
2025-09-07remove `trait IntrinsicDefinition`Folkert de Vries-54/+28
2025-09-07move `print_result_c` into the traitFolkert de Vries-83/+75
2025-09-07move `print_result_c` into the inner intrinsic typeFolkert de Vries-22/+30
2025-09-07move more constants into `SupportedArchitectureTest`Folkert de Vries-28/+53
2025-09-07move platform headers into `SupportedArchitectureTest`Folkert de Vries-2/+5
2025-09-07move `compare_outputs` implementation into `SupportedArchitectureTest` ↵Folkert de Vries-40/+47
definition
2025-09-06s390x: use the new `u128::funnel_shl`Folkert de Vries-15/+5
2025-09-03Merge pull request #1911 from nikic/remove-hackFolkert de Vries-12/+4
Remove some llvm workarounds
2025-09-03RISC-V: Lower requirements of `clmul` and `clmulh`Tsukasa OI-2/+2
They don't need full "Zbc" extension but only its subset: the "Zbkc" extension. Since the compiler implies `zbkc` from `zbc`, it's safe to use `#[target_feature(enable = "zbkc")]`.
2025-09-02Remove some llvm workaroundsNikita Popov-12/+4
2025-08-29use `llvm.roundeven` on armFolkert de Vries-14/+6
2025-08-21Merge pull request #1903 from folkertdev/s390x-llvm-21-fixesAmanieu d'Antras-93/+130
`s390x` llvm 21 improvements
2025-08-21use `simd_saturating_{add, sub}` on neonFolkert de Vries-316/+48
2025-08-20Merge pull request #1901 from folkertdev/wasm-read-unalignedAmanieu d'Antras-24/+14
wasm: use `{read, write}_unaligned` methods
2025-08-20Merge pull request #1899 from dpaoliello/arm64ecFolkert de Vries-4/+821
Add testing for Arm64EC Windows
2025-08-20s390x: link to a missed optimizationFolkert de Vries-0/+3
2025-08-20s390x: implement `vec_sld` using `fshl`Folkert de Vries-9/+46
2025-08-20s390x: implement `vec_subc_u128` using `overflowing_sub`Folkert de Vries-6/+4
2025-08-20s390x: implement `vec_mulo` using `core::intrinsics::simd`Folkert de Vries-36/+32
2025-08-20wasm: use `{read, write}_unaligned` methodsFolkert de Vries-24/+14
2025-08-20s390x: implement `vec_mule` using `core::intrinsics::simd`Folkert de Vries-38/+47
2025-08-20s390x: add `assert_instr` for `vec_extend`Folkert de Vries-6/+3
2025-08-20s390x: add `assert_instr` for `vec_round`Folkert de Vries-4/+2
2025-08-20s390x: define `unpack_low` using `core::intrinsics::simd`Folkert de Vries-9/+8
2025-08-20Adjust immediate for vrndscalepd testsNikita Popov-2/+2
The immediate here encodes both the rounding mode (in the low bits) and the scale (in the high bits). Make sure the scale is non-zero.
2025-08-20Work around selection failure without avx512vlNikita Popov-4/+12
2025-08-20Add missing avx512vl target featuresNikita Popov-188/+188
2025-08-20Use intrinsics for some s390x operationsNikita Popov-3/+10
2025-08-20Drop no longer needed feature gatesNikita Popov-2/+0
2025-08-14Stabilize `sse4a` and `tbm` target featuressayantn-2/+0
- remove some stabilized target features from `gate.rs`
2025-08-10Add testing for Arm64EC WindowsDaniel Paoliello-4/+821
2025-08-05use `IntoIterator` for the `add_flags` methodsFolkert de Vries-10/+11
2025-08-05Merge pull request #1895 from ↵Folkert de Vries-52/+50
madhav-madhusoodanan/intrinsic-test-intrinsictype-cleanup `intrinsic-test`: Cleaning the `IntrinsicType` struct and related functionalities
2025-08-05chore: moved chunk_info to `common` and code cleanupMadhav Madhusoodanan-35/+34
2025-08-05feat: cleaned the IntrinsicType struct and associated functions.Madhav Madhusoodanan-27/+26
Changes: 1. Removed `from_c` from the IntrinsicType definition. 2. Moved the `from_c` arm-specific definition to an ArmIntrinsicType-specific impl block
2025-08-03Merge pull request #1889 from rust-lang/rustc-pullFolkert de Vries-0/+10
Rustc pull update
2025-08-03feat: Added another variant of the Constraint enumMadhav Madhusoodanan-6/+13
generated by cgit-pink 1.4.1-3-g733a5 (git 2.37.1) at 2025-10-30 15:38:58 +0000