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2025-03-16let's not use `&mut` until we get confirmation it's OKFolkert de Vries-8/+8
2025-03-16add `vec_cmprg_or_0_idx_cc` and `vec_cmpnrg_or_0_idx_cc`Folkert de Vries-0/+30
2025-03-16add `vec_cmprg_or_0_idx` and `vec_cmpnrg_or_0_idx`Folkert de Vries-24/+100
2025-03-16add `vec_cmprg_cc` and friendsFolkert de Vries-0/+40
2025-03-16add `vec_cmprg_idx` and `vec_cmpnrg_idx`Folkert de Vries-0/+36
2025-03-16add `vec_cmpnrg`Folkert de Vries-4/+34
2025-03-16add `vec_cmprg`Folkert de Vries-8/+97
2025-03-16add `vec_sld`, `vec_sldb`, `vec_sldw` and `vec_srdb`Folkert de Vries-0/+165
2025-03-16add `vec_msum_u128`Folkert de Vries-0/+45
2025-03-16add `vec_cp_until_zero` and `vec_cp_until_zero_cc`Folkert de Vries-0/+115
2025-03-16add `vec_signed` and `vec_unsigned`Folkert de Vries-0/+68
2025-03-16add `vec_extend_s64`Folkert de Vries-0/+88
2025-03-16add `vec_double` and `vec_float`Folkert de Vries-0/+158
2025-03-16add `vec_search_string_cc` and `vec_search_string_until_zero_cc`Folkert de Vries-0/+159
2025-03-16add `vec_test_mask`Folkert de Vries-0/+71
2025-03-16add `vec_fp_test_data_class`Folkert de Vries-0/+125
2025-03-16add `vec_scatter`Folkert de Vries-2/+66
2025-03-16add `vec_sel`Folkert de Vries-0/+77
2025-03-16add `vec_bperm_u128`Folkert de Vries-0/+25
2025-03-16add `vec_gather_element`Folkert de Vries-0/+123
2025-03-16add `vec_nmadd`Folkert de Vries-0/+49
2025-03-16add `vec_gfmsum_accum` and `vec_gfmsum_accum_128`Folkert de Vries-0/+67
2025-03-16add `vec_gfmsum_128`Folkert de Vries-0/+29
2025-03-16add `vec_gfmsum`Folkert de Vries-0/+37
2025-03-16clarify fixme waiting for a newer llvm versionFolkert de Vries-1/+2
2025-03-16add `vec_nmsub`Folkert de Vries-4/+50
2025-03-16add `vec_mule`Folkert de Vries-0/+81
2025-03-16add `vec_add_u128`, `vec_addc_u128`, `vec_adde_u128` and `vec_addce_u128`Folkert de Vries-1/+122
2025-03-16add `vec_checksum`Folkert de Vries-0/+17
2025-03-16add `vec_avg`Folkert de Vries-0/+42
2025-03-16add `vec_unpackh` and `vec_unpackl`Folkert de Vries-3/+129
2025-03-16correct name of signed splat functionsFolkert de Vries-4/+4
2025-03-16test `vec_rl`Folkert de Vries-5/+5
2025-03-16add `vec_madd` and `vec_msub`Folkert de Vries-0/+63
2025-03-16add `vec_packs_cc` and `vec_packsu_cc`Folkert de Vries-6/+104
2025-03-16add `vec_pack`, `vec_packs` and `vec_packsu`Folkert de Vries-0/+182
2025-03-16add `vec_load_bndry`, `__lcbb` and `vec_load_pair`Folkert de Vries-3/+102
2025-03-16add `vec_load_len_r` and `vec_store_len_r`Folkert de Vries-0/+22
2025-03-16add `vec_load_len` and `vec_store_len`Folkert de Vries-0/+56
2025-03-16add `vec_xl` and `vec_xst`Folkert de Vries-0/+148
2025-03-16add `vec_reve`Folkert de Vries-0/+15
2025-03-16Document safety conditions of simd shiftsAlex Crichton-0/+40
2025-03-16Fix rustfmtAlex Crichton-1/+3
2025-03-16wasm32: Fix undefined behavior with shift intrinsicsAlex Crichton-15/+13
This commit fixes an issue where simd shift intrinsic in LLVM are undefined behavior if the shift amount is larger than the bit width of the lane. While in WebAssembly the corresponding instructions are defined as masking out the upper bits we need to represent that explicitly in LLVM IR to ensure that the semantics remain defined. cc rust-lang/rust#137941
2025-03-16Update SDE mirror to ci-mirrors.rust-lang.orgSayantan Chakraborty-3/+4
This is to combat the spurious CI failures in emulated run. Also helps with updatability and compatibility - it will work even if Intel changes the link
2025-03-06Don't field-project (`.0`) into SIMD typesScott McMurray-11/+54
2025-03-05feat - FEAT_LUT neon instrinsicsJames Barford-Evans-1/+1606
2025-03-04add unstable for faminmaxJames Barford-Evans-8/+8
2025-03-04mark FEAT_FAMINMAX intrinsics as safeJames Barford-Evans-28/+14
2025-03-04armV7 does not need faminmax flagJames Barford-Evans-1/+0
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