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2019-10-25FormattingThomas Lively-1/+2
2019-10-25Re-enable Emscripten's exception handling supportThomas Lively-1/+5
Passes LLVM codegen and Emscripten link-time flags for exception handling if and only if the panic strategy is `unwind`. Sets the default panic strategy for Emscripten targets to `unwind`. Re-enables tests that depend on unwinding support for Emscripten, including `should_panic` tests.
2019-10-16Upgrade Emscripten targets to use upstream LLVM backendThomas Lively-2/+1
- Compatible with Emscripten 1.38.46-upstream or later upstream. - Refactors the Emscripten target spec to share code with other wasm targets. - Replaces the old incorrect wasm32 C call ABI with the correct one, preserving the old one as wasm32_bindgen_compat for wasm-bindgen compatibility. - Updates the varargs ABI used by Emscripten and deletes the old one. - Removes the obsolete wasm32-experimental-emscripten target. - Uses EMCC_CFLAGS on CI to avoid the timeout problems with #63649.
2019-10-05Revert "Auto merge of #63649 - tlively:emscripten-upstream-upgrade, ↵Tyler Mandry-1/+2
r=alexcrichton" This reverts commit 7870050796e5904a0fc85ecbe6fa6dde1cfe0c91, reversing changes made to 2e7244807a7878f6eca3eb7d97ae9b413aa49014.
2019-10-04Upgrade Emscripten targets to use upstream LLVM backendThomas Lively-2/+1
- Refactors the Emscripten target spec to share code with other wasm targets. - Replaces the incorrect wasm32 C call ABI with the old asmjs version, which is correct for both wasm32 and JS. - Updates the varargs ABI used by Emscripten and deletes the old one. - Removes the obsolete wasm32-experimental-emscripten target. - Temporarily makes Emscripten targets use panic=abort by default because supporting unwinding will require an LLVM patch.
2019-07-22add support for hexagon-unknown-linux-muslBrian Cain-1/+1
2019-05-13Pass a `Symbol` to `check_name`, `emit_feature_err`, and related functions.Nicholas Nethercote-67/+68
2019-04-23Add f16c target_featuregnzlbg-0/+1
2019-04-19Rollup merge of #60097 - cuviper:llvm8-mergefunc-use-aliases, r=rkruppeMazdak Farrokhzad-1/+1
Use -mergefunc-use-aliases for any LLVM >= 8 This functionality is not specific to Rust's LLVM, but any starting in LLVM 8.0, as noted in <https://github.com/rust-lang/rust/pull/56358#discussion_r237702197>. cc @nikic r? @rkruppe
2019-04-18Use -mergefunc-use-aliases for any LLVM >= 8Josh Stone-1/+1
2019-04-17whitelist rtm x86 cpu featuretyler-0/+1
2019-02-18librustc_codegen_llvm => 2018Taiki Endo-2/+2
2019-02-14Whitelist the ARM v8 target-featuregnzlbg-0/+1
2019-02-13Whitelist the ARM v6 target-featuregnzlbg-0/+1
2019-01-30Add MOVBE featureJethro Beekman-0/+1
2019-01-24Implement optimize(size) and optimize(speed)Simonas Kazlauskas-3/+3
2019-01-05Add a target option "merge-functions" taking values in ("disabled",Peter Jin-1/+9
"trampolines", or "aliases (the default)) to allow targets to opt out of the MergeFunctions LLVM pass. Also add a corresponding -Z option with the same name and values. This works around: https://github.com/rust-lang/rust/issues/57356 Motivation: Basically, the problem is that the MergeFunctions pass, which rustc currently enables by default at -O2 and -O3, and `extern "ptx-kernel"` functions (specific to the NVPTX target) are currently not compatible with each other. If the MergeFunctions pass is allowed to run, rustc can generate invalid PTX assembly (i.e. a PTX file that is not accepted by the native PTX assembler ptxas). Therefore we would like a way to opt out of the MergeFunctions pass, which is what our target option does. Related work: The current behavior of rustc is to enable MergeFunctions at -O2 and -O3, and also to enable the use of function aliases within MergeFunctions. MergeFunctions both with and without function aliases is incompatible with the NVPTX target. clang's "solution" is to have a "-fmerge-functions" flag that opts in to the MergeFunctions pass, but it is not enabled by default.
2018-12-25Remove licensesMark Rousskov-10/+0
2018-12-21Enable emission of alignment attrs for pointer paramsNikita Popov-0/+4
Instead disable creation of assumptions during inlining using an LLVM opt flag. The -Z arg-align-attributes option which previously controlled this behavior is removed.
2018-12-14rustc: Add the `cmpxchg16b` target feature on x86/x86_64Alex Crichton-0/+2
This appears to be called `cx16` in LLVM and a few other locations, but the Intel Intrinsic Guide doesn't have a name for this and the CPU manual from Intel only mentions `cmpxchg16b`, so that's the name chosen here.
2018-12-12x86: Add the `adx` target feature to whitelistAlex Crichton-0/+1
Requested in rust-lang-nursery/stdsimd#322 this is hopefully the first step!
2018-11-30Enable -mergefunc-use-aliasesNikita Popov-0/+3
If the Rust LLVM fork is used, enable the -mergefunc-use-aliases flag, which will create aliases for merged functions, rather than inserting a call from one to the other. A number of codegen tests needed to be adjusted, because functions that previously fell below the thunk limit are now being merged. Merging is prevented either using -C no-prepopulate-passes, or by making the functions non-identical. I expect that this is going to break something, somewhere, because it isn't able to deal with aliases properly, but we won't find out until we try :) This fixes #52651.
2018-11-11Fix typos.Bruce Mitchener-1/+1
2018-11-10Auto merge of #55650 - nikic:funnel-shift, r=nagisabors-0/+4
Implement rotate using funnel shift on LLVM >= 7 Implement the rotate_left and rotate_right operations using llvm.fshl and llvm.fshr if they are available (LLVM >= 7). Originally I wanted to expose the funnel_shift_left and funnel_shift_right intrinsics and implement rotate_left and rotate_right on top of them. However, emulation of funnel shifts requires emitting a conditional to check for zero shift amount, which is not necessary for rotates. I was uncomfortable doing that here, as I don't want to rely on LLVM to optimize away that conditional (and for variable rotates, I'm not sure it can). We should revisit that question when we raise our minimum version requirement to LLVM 7 and don't need emulation code anymore. Fixes #52457.
2018-11-08Disable wasm32 features on emscriptenNikita Popov-1/+2
These are only supported by the native wasm32 backend.
2018-11-03Implement rotate using funnel shift on LLVM >= 7Nikita Popov-0/+4
Implement the rotate_left and rotate_right operations using llvm.fshl and llvm.fshr if they are available (LLVM >= 7). Originally I wanted to expose the funnel_shift_left and funnel_shift_right intrinsics and implement rotate_left and rotate_right on top of them. However, emulation of funnel shifts requires emitting a conditional to check for zero shift amount, which is not necessary for rotates. I was uncomfortable doing that here, as I don't want to rely on LLVM to optimize away that conditional (and for variable rotates, I'm not sure it can). We should revisit that question when we raise our minimum version requirement to LLVM 7 and don't need emulation code anymore.
2018-10-12exit with status code 101 on fatal LLVM errorAndy Russell-0/+2
Fixes #54992.
2018-10-08codegen_llvm: improve allocationsljedrz-2/+3
2018-09-05Auto merge of #53878 - alexcrichton:wasm-atomics-feature, r=eddybbors-0/+1
rustc: Prepare the `atomics` feature for wasm This commit adds a few changes for atomic instructions on the `wasm32-unknown-unknown` target. Atomic instructions are not yet stable in WebAssembly itself but there are multiple implementations and LLVM has support for the proposed instruction set, so let's work on exposing it! Here there are a few inclusions: * The `atomics` feature was whitelisted for LLVM, allowing code in Rust to enable/disable/gate on this. * The `singlethread` option is turned off for wasm when the `atomics` feature is enabled. This means that by default wasm won't be lowering with atomics, but when atomics are enabled globally we'll turn off single-threaded mode to actually codegen atomics. This probably isn't what we'll want in the long term but for now it should work. * Finally the maximum atomic width is increased to 64 to reflect the current wasm spec.
2018-09-03whitelist some ARM featuresJorge Aparicio-0/+4
2018-08-31rustc: Prepare the `atomics` feature for wasmAlex Crichton-0/+1
This commit adds a few changes for atomic instructions on the `wasm32-unknown-unknown` target. Atomic instructions are not yet stable in WebAssembly itself but there are multiple implementations and LLVM has support for the proposed instruction set, so let's work on exposing it! Here there are a few inclusions: * The `atomics` feature was whitelisted for LLVM, allowing code in Rust to enable/disable/gate on this. * The `singlethread` option is turned off for wasm when the `atomics` feature is enabled. This means that by default wasm won't be lowering with atomics, but when atomics are enabled globally we'll turn off single-threaded mode to actually codegen atomics. This probably isn't what we'll want in the long term but for now it should work. * Finally the maximum atomic width is increased to 64 to reflect the current wasm spec.
2018-08-28Fix warnings about the `native` target-cpuAlex Crichton-0/+18
This fixes a regression from #53031 where specifying `-C target-cpu=native` is printing a lot of warnings from LLVM about `native` being an unknown CPU. It turns out that `native` is indeed an unknown CPU and we have to perform a mapping to an actual CPU name, but this mapping is only performed in one location rather than all locations we inform LLVM about the target CPU. This commit centralizes the mapping of `native` to LLVM's value of the native CPU, ensuring that all locations we inform LLVM about the `target-cpu` it's never `native`. Closes #53322
2018-08-08Add wasm32 simd128 target featuregnzlbg-0/+6
2018-07-30rustc_llvm: move to rustc_codegen_llvm::llvm.Irina Popa-1/+1
2018-07-25ARM: expose `rclass` and `dsp` target featuresPaolo Teti-0/+2
- `dsp`: the subtarget supports the DSP (saturating arith. and such) instructions - `rclass`: target is a Cortex-R Both features are useful to support ARM MCUs on `coresimd`. Note: Cortex-R52 is the first Armv8-R with `neon` support
2018-07-06ARM: expose the "mclass" target featureJorge Aparicio-0/+1
2018-05-17Rename trans to codegen everywhere.Irina Popa-0/+255
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