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2023-12-18Merge commit '21b06c1beb9bb59369ffd652f5d617bcf6952e05' into sync-from-raLaurențiu Nicola-21/+19
2023-12-11Merge commit '457b966b171b09a7e57acb710fbca29a4b3526f0' into sync-from-raLaurențiu Nicola-485/+1056
2023-12-04Merge commit 'e402c494b7c7d94a37c6d789a216187aaf9ccd3e' into sync-from-raLaurențiu Nicola-23/+214
2023-11-27Merge commit '237712fa314237e428e7ef2ab83b979f928a43a1' into sync-from-raLaurențiu Nicola-8/+115
2023-11-16Merge commit '141fc695dca1df7cfc3c9803972ec19bb178dcbc' into sync-from-raLaurențiu Nicola-4/+26
2023-11-08Merge commit '3b7c7f97e4a7bb253a8d398ee4f8346f6cf2817b' into sync-from-raLaurențiu Nicola-19/+299
2023-09-18Merge commit '258b15c506a2d3ad862fd17ae24eaf272443f477' into sync-from-raLaurențiu Nicola-70/+107
2023-08-21Merge commit '9b3d03408c66749d56466bb09baf2a7177deb6ce' into sync-from-raLaurențiu Nicola-75/+635
2023-08-14fix the wrong number in const KNOWN_ARCHdirreke-1/+1
2023-08-14add a csky-unknown-linux-gnuabiv2 targetDirreke-0/+1
2023-08-08feat: `riscv-interrupt-{m,s}` calling conventionsSeth Pellegrino-0/+2
Similar to prior support added for the mips430, avr, and x86 targets this change implements the rough equivalent of clang's [`__attribute__((interrupt))`][clang-attr] for riscv targets, enabling e.g. ```rust static mut CNT: usize = 0; pub extern "riscv-interrupt-m" fn isr_m() { unsafe { CNT += 1; } } ``` to produce highly effective assembly like: ```asm pub extern "riscv-interrupt-m" fn isr_m() { 420003a0: 1141 addi sp,sp,-16 unsafe { CNT += 1; 420003a2: c62a sw a0,12(sp) 420003a4: c42e sw a1,8(sp) 420003a6: 3fc80537 lui a0,0x3fc80 420003aa: 63c52583 lw a1,1596(a0) # 3fc8063c <_ZN12esp_riscv_rt3CNT17hcec3e3a214887d53E.0> 420003ae: 0585 addi a1,a1,1 420003b0: 62b52e23 sw a1,1596(a0) } } 420003b4: 4532 lw a0,12(sp) 420003b6: 45a2 lw a1,8(sp) 420003b8: 0141 addi sp,sp,16 420003ba: 30200073 mret ``` (disassembly via `riscv64-unknown-elf-objdump -C -S --disassemble ./esp32c3-hal/target/riscv32imc-unknown-none-elf/release/examples/gpio_interrupt`) This outcome is superior to hand-coded interrupt routines which, lacking visibility into any non-assembly body of the interrupt handler, have to be very conservative and save the [entire CPU state to the stack frame][full-frame-save]. By instead asking LLVM to only save the registers that it uses, we defer the decision to the tool with the best context: it can more accurately account for the cost of spills if it knows that every additional register used is already at the cost of an implicit spill. At the LLVM level, this is apparently [implemented by] marking every register as "[callee-save]," matching the semantics of an interrupt handler nicely (it has to leave the CPU state just as it found it after its `{m|s}ret`). This approach is not suitable for every interrupt handler, as it makes no attempt to e.g. save the state in a user-accessible stack frame. For a full discussion of those challenges and tradeoffs, please refer to [the interrupt calling conventions RFC][rfc]. Inside rustc, this implementation differs from prior art because LLVM does not expose the "all-saved" function flavor as a calling convention directly, instead preferring to use an attribute that allows for differentiating between "machine-mode" and "superivsor-mode" interrupts. Finally, some effort has been made to guide those who may not yet be aware of the differences between machine-mode and supervisor-mode interrupts as to why no `riscv-interrupt` calling convention is exposed through rustc, and similarly for why `riscv-interrupt-u` makes no appearance (as it would complicate future LLVM upgrades). [clang-attr]: https://clang.llvm.org/docs/AttributeReference.html#interrupt-risc-v [full-frame-save]: https://github.com/esp-rs/esp-riscv-rt/blob/9281af2ecffe13e40992917316f36920c26acaf3/src/lib.rs#L440-L469 [implemented by]: https://github.com/llvm/llvm-project/blob/b7fb2a3fec7c187d58a6d338ab512d9173bca987/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp#L61-L67 [callee-save]: https://github.com/llvm/llvm-project/blob/973f1fe7a8591c7af148e573491ab68cc15b6ecf/llvm/lib/Target/RISCV/RISCVCallingConv.td#L30-L37 [rfc]: https://github.com/rust-lang/rfcs/pull/3246
2023-08-07Merge commit 'baee6b338b0ea076cd7a9f18d47f175dd2ba0e5d' into sync-from-raLaurențiu Nicola-2/+42
2023-07-17Merge commit '37f84c101bca43b11027f30ab0c2852f9325bc3d' into sync-from-raLaurențiu Nicola-8/+8
2023-06-19Merge commit 'cd3bf9fe51676b520c546460e6d8919b8c8ff99f' into sync-from-raLaurențiu Nicola-5/+225
2023-06-05Merge commit 'aa9bc8612514d216f84eec218dfd19ab83f3598a' into sync-from-raLaurențiu Nicola-268/+1168
2023-03-20:arrow_up: rust-analyzerLaurențiu Nicola-22/+167
2023-03-13Auto merge of #109069 - lnicola:rust-analyzer-2023-03-13, r=lnicolabors-14/+77
:arrow_up: `rust-analyzer` r? `@ghost`
2023-03-13:arrow_up: rust-analyzerLaurențiu Nicola-14/+77
2023-03-12Remove uses of `box_syntax` in rustc and toolsclubby789-2/+2
2023-02-20:arrow_up: rust-analyzerLaurențiu Nicola-241/+501
2023-02-13:arrow_up: rust-analyzerLaurențiu Nicola-110/+272
2023-01-09:arrow_up: rust-analyzerarcnmx-170/+538
Merge commit '368e0bb32f1178cf162c2ce5f7e10b7ae211eb26'
2022-11-23:arrow_up: rust-analyzerLaurențiu Nicola-23/+178
2022-11-09:arrow_up: rust-analyzerLaurențiu Nicola-4/+25
2022-10-18:arrow_up: rust-analyzerLaurențiu Nicola-975/+1167
2022-10-11:arrow_up: rust-analyzerLaurențiu Nicola-23/+28
2022-09-20:arrow_up: rust-analyzerLaurențiu Nicola-244/+80
2022-09-13:arrow_up: rust-analyzerLaurențiu Nicola-0/+59
2022-09-06:arrow_up: rust-analyzerLaurențiu Nicola-7/+55
2022-08-30:arrow_up: rust-analyzerLaurențiu Nicola-16/+41
2022-08-23:arrow_up: rust-analyzerLaurențiu Nicola-47/+99
2022-08-16:arrow_up: rust-analyzerLaurențiu Nicola-126/+159
2022-08-02:arrow_up: rust-analyzerLaurențiu Nicola-180/+400
2022-07-26Merge commit 'e36a20c24f35a4cee82bbdc600289104c9237c22' into ↵Amos Wenger-3/+38
ra-sync-and-pms-component
2022-07-24Add 'src/tools/rust-analyzer/' from commit ↵Amos Wenger-0/+21737
'977e12a0bdc3e329af179ef3a9d466af9eb613bb' git-subtree-dir: src/tools/rust-analyzer git-subtree-mainline: 3c98486a0cdb6d92f0fca34ffb1fd46c0e498653 git-subtree-split: 977e12a0bdc3e329af179ef3a9d466af9eb613bb
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