rust - https://github.com/rust-lang/rust

Age	Commit message (Collapse)	Author	Lines
2025-09-22	Rollup merge of #146831 - taiki-e:powerpc-clobber, r=Amanieu	Stuart Cook	-4/+4
	Support ctr and lr as clobber-only registers in PowerPC inline assembly Follow-up to rust-lang/rust#131341. CTR and LR are marked as volatile in all ABIs, but I skipped them in rust-lang/rust#131341 due to they are currently marked as reserved. https://github.com/rust-lang/rust/blob/dd7fda570040e8a736f7d8bc28ddd1b444aabc82/compiler/rustc_target/src/asm/powerpc.rs#L209-L212 However, they are actually only unusable as input/output of inline assembly, and should be fine to support as clobber-only registers as discussed in [#t-compiler > ppc/ppc64 inline asm support](https://rust-lang.zulipchat.com/#narrow/channel/131828-t-compiler/topic/ppc.2Fppc64.20inline.20asm.20support/with/540413845). r? ````@Amanieu```` or ````@workingjubilee```` cc ````@programmerjake```` ````@rustbot```` label +O-PowerPC +A-inline-assembly
2025-09-21	emit attribute for readonly non-pure inline assembly	Folkert de Vries	-0/+48

2025-09-21	Support ctr and lr as clobber-only registers in PowerPC inline assembly	Taiki Endo	-4/+4

2025-09-15	rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list	Tsukasa OI	-1/+1
	Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register in the reference, it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
2025-07-22	Rename `tests/codegen` into `tests/codegen-llvm`	Guillaume Gomez	-0/+927