From f414715ebfda201f91f80ef9f28d9923d614d1c4 Mon Sep 17 00:00:00 2001 From: Tim Neumann Date: Sun, 6 Nov 2022 19:03:22 +0000 Subject: LLVM 16: Update RISCV data layout --- compiler/rustc_codegen_llvm/src/context.rs | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'compiler/rustc_codegen_llvm/src') diff --git a/compiler/rustc_codegen_llvm/src/context.rs b/compiler/rustc_codegen_llvm/src/context.rs index 79ddfd884df..c22ec128dac 100644 --- a/compiler/rustc_codegen_llvm/src/context.rs +++ b/compiler/rustc_codegen_llvm/src/context.rs @@ -158,6 +158,10 @@ pub unsafe fn create_module<'ll>( if sess.target.arch == "s390x" { target_data_layout = target_data_layout.replace("-v128:64", ""); } + + if sess.target.arch == "riscv64" { + target_data_layout = target_data_layout.replace("-n32:64-", "-n64-"); + } } // Ensure the data-layout values hardcoded remain the defaults. -- cgit 1.4.1-3-g733a5