From c5b92649291d43a93ccd11f61557d7ae77651512 Mon Sep 17 00:00:00 2001 From: est31 Date: Wed, 17 Feb 2021 10:22:29 +0100 Subject: Replace vec![] calls with slice literals There is no need to create vec's here --- compiler/rustc_codegen_llvm/src/asm.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'compiler/rustc_codegen_llvm/src') diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index 4aa25aae747..26815de403f 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -61,9 +61,9 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> { // Default per-arch clobbers // Basically what clang does let arch_clobbers = match &self.sess().target.arch[..] { - "x86" | "x86_64" => vec!["~{dirflag}", "~{fpsr}", "~{flags}"], - "mips" | "mips64" => vec!["~{$1}"], - _ => Vec::new(), + "x86" | "x86_64" => &["~{dirflag}", "~{fpsr}", "~{flags}"][..], + "mips" | "mips64" => &["~{$1}"], + _ => &[], }; let all_constraints = ia -- cgit 1.4.1-3-g733a5