From 80b74d397fffc9deaafd2b44552ba3a9107b4d5b Mon Sep 17 00:00:00 2001
From: daxpedda <daxpedda@gmail.com>
Date: Sat, 13 Jul 2024 00:10:33 +0200
Subject: Implement a implicit target feature mechanism

---
 compiler/rustc_codegen_llvm/src/llvm_util.rs | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'compiler/rustc_codegen_llvm/src')

diff --git a/compiler/rustc_codegen_llvm/src/llvm_util.rs b/compiler/rustc_codegen_llvm/src/llvm_util.rs
index dc21b92a95f..af8a9be1ccb 100644
--- a/compiler/rustc_codegen_llvm/src/llvm_util.rs
+++ b/compiler/rustc_codegen_llvm/src/llvm_util.rs
@@ -646,6 +646,22 @@ pub(crate) fn global_llvm_features(sess: &Session, diagnostics: bool) -> Vec<Str
         }
     }
 
+    // This is a workaround for a LLVM bug that doesn't implicitly enable
+    // `simd128` when `relaxed-simd` is.
+    // See <https://github.com/llvm/llvm-project/pull/99803>, which didn't make
+    // it into a released version of LLVM yet.
+    //
+    // This doesn't use the "implicit target feature" system because it is only
+    // used for function attributes in other targets, which fixes this bug as
+    // well on the function attribute level.
+    if sess.target.families.contains(&"wasm".into()) {
+        if features.iter().any(|f| f == "+relaxed-simd")
+            && !features.iter().any(|f| f == "+simd128")
+        {
+            features.push("+simd128".into());
+        }
+    }
+
     if diagnostics && let Some(f) = check_tied_features(sess, &featsmap) {
         sess.dcx().emit_err(TargetFeatureDisableOrEnable {
             features: f,
-- 
cgit 1.4.1-3-g733a5