From 8affef2ccba424f37445f6df6592426600d00a31 Mon Sep 17 00:00:00 2001 From: Ralf Jung Date: Mon, 18 Jul 2022 09:48:20 -0400 Subject: add intrinsic to access vtable size and align --- compiler/rustc_codegen_llvm/src/intrinsic.rs | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'compiler/rustc_codegen_llvm/src') diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs index 9f364749287..01e276ac902 100644 --- a/compiler/rustc_codegen_llvm/src/intrinsic.rs +++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs @@ -363,6 +363,20 @@ impl<'ll, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'_, 'll, 'tcx> { return; } + sym::vtable_size | sym::vtable_align => { + let ptr = args[0].immediate(); + let layout = self.layout_of(self.tcx.types.usize); + let type_ = self.backend_type(layout); + let offset = match name { + sym::vtable_size => 1, + sym::vtable_align => 2, + _ => bug!(), + }; + let offset = self.const_int(type_, offset); + let vtable_field_ptr = self.inbounds_gep(type_, ptr, &[offset]); + self.load(type_, vtable_field_ptr, layout.align.abi) + } + _ if name.as_str().starts_with("simd_") => { match generic_simd_intrinsic(self, name, callee_ty, args, ret_ty, llret_ty, span) { Ok(llval) => llval, -- cgit 1.4.1-3-g733a5