From 91ef03bf2f545f10db008d0ad54c3d197f539895 Mon Sep 17 00:00:00 2001 From: Eduardo Sánchez Muñoz Date: Tue, 3 Oct 2023 18:14:01 +0200 Subject: Fix typos `*ucom` → `ucom*` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/tools/miri/src/shims/x86/sse.rs | 2 +- src/tools/miri/src/shims/x86/sse2.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/tools/miri/src/shims/x86/sse.rs b/src/tools/miri/src/shims/x86/sse.rs index de1e695b6d1..0e51a73d091 100644 --- a/src/tools/miri/src/shims/x86/sse.rs +++ b/src/tools/miri/src/shims/x86/sse.rs @@ -141,7 +141,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>: let left = this.read_scalar(&this.project_index(&left, 0)?)?.to_f32()?; let right = this.read_scalar(&this.project_index(&right, 0)?)?.to_f32()?; - // The difference between the com* and *ucom variants is signaling + // The difference between the com* and ucom* variants is signaling // of exceptions when either argument is a quiet NaN. We do not // support accessing the SSE status register from miri (or from Rust, // for that matter), so we treat equally both variants. diff --git a/src/tools/miri/src/shims/x86/sse2.rs b/src/tools/miri/src/shims/x86/sse2.rs index 2ef6a9b59ed..a27d37d0fff 100644 --- a/src/tools/miri/src/shims/x86/sse2.rs +++ b/src/tools/miri/src/shims/x86/sse2.rs @@ -637,7 +637,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>: let left = this.read_scalar(&this.project_index(&left, 0)?)?.to_f64()?; let right = this.read_scalar(&this.project_index(&right, 0)?)?.to_f64()?; - // The difference between the com* and *ucom variants is signaling + // The difference between the com* and ucom* variants is signaling // of exceptions when either argument is a quiet NaN. We do not // support accessing the SSE status register from miri (or from Rust, // for that matter), so we treat equally both variants. -- cgit 1.4.1-3-g733a5