From 298ec5258f8e5f1211734bcb43c89aa184d3ca1b Mon Sep 17 00:00:00 2001 From: Wesley Wiser Date: Wed, 23 Aug 2023 13:31:38 -0400 Subject: Disable MIR SROA optimization by default Turn off the MIR SROA optimization by default to prevent incorrect debuginfo generation and rustc ICEs caused by invalid LLVM IR being created. Related to #115113 --- .../pre-codegen/mem_replace.mem_replace.PreCodegen.after.mir | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'tests/mir-opt/pre-codegen/mem_replace.mem_replace.PreCodegen.after.mir') diff --git a/tests/mir-opt/pre-codegen/mem_replace.mem_replace.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/mem_replace.mem_replace.PreCodegen.after.mir index dde7a618881..f8f4f5b9959 100644 --- a/tests/mir-opt/pre-codegen/mem_replace.mem_replace.PreCodegen.after.mir +++ b/tests/mir-opt/pre-codegen/mem_replace.mem_replace.PreCodegen.after.mir @@ -15,18 +15,20 @@ fn mem_replace(_1: &mut u32, _2: u32) -> u32 { scope 7 (inlined std::ptr::write::) { debug dst => _4; debug src => _2; + let mut _6: *mut u32; scope 8 { scope 9 (inlined std::ptr::write::runtime::) { - debug dst => _4; + debug dst => _6; } } } } scope 4 (inlined std::ptr::read::) { debug src => _3; + let mut _5: *const u32; scope 5 { scope 6 (inlined std::ptr::read::runtime::) { - debug src => _3; + debug src => _5; } } } @@ -36,11 +38,15 @@ fn mem_replace(_1: &mut u32, _2: u32) -> u32 { bb0: { StorageLive(_3); _3 = &raw const (*_1); + StorageLive(_5); _0 = (*_3); + StorageDead(_5); StorageDead(_3); StorageLive(_4); _4 = &raw mut (*_1); + StorageLive(_6); (*_4) = _2; + StorageDead(_6); StorageDead(_4); return; } -- cgit 1.4.1-3-g733a5