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| author | beetrees <b@beetr.ee> | 2024-06-27 22:18:04 +0100 |
|---|---|---|
| committer | beetrees <b@beetr.ee> | 2024-07-01 17:39:30 +0100 |
| commit | 0f643c449aea5060de03a0b8fe8288cd1c861e0d (patch) | |
| tree | 92a70e27de933611bb18371b3147ab372a95095d | |
| parent | 0e1c832dbd08c90497d46978eda7da5acd467c4e (diff) | |
| download | rust-0f643c449aea5060de03a0b8fe8288cd1c861e0d.tar.gz rust-0f643c449aea5060de03a0b8fe8288cd1c861e0d.zip | |
Ensure tests don't fail on i586 in CI
| -rw-r--r-- | tests/assembly/x86-return-float.rs | 5 | ||||
| -rw-r--r-- | tests/ui/abi/numbers-arithmetic/return-float.rs | 90 |
2 files changed, 52 insertions, 43 deletions
diff --git a/tests/assembly/x86-return-float.rs b/tests/assembly/x86-return-float.rs index 270aea2475f..c4a2c1ad44e 100644 --- a/tests/assembly/x86-return-float.rs +++ b/tests/assembly/x86-return-float.rs @@ -1,5 +1,10 @@ //@ assembly-output: emit-asm //@ only-x86 +// FIXME(#114479): LLVM miscompiles loading and storing `f32` and `f64` when SSE is disabled. +// There's no compiletest directive to ignore a test on i586 only, so just always explicitly enable +// SSE2. +// Use the same target CPU as `i686` so that LLVM orders the instructions in the same order. +//@ compile-flags: -Ctarget-feature=+sse2 -Ctarget-cpu=pentium4 // Force frame pointers to make ASM more consistent between targets //@ compile-flags: -O -C force-frame-pointers //@ filecheck-flags: --implicit-check-not fld --implicit-check-not fst diff --git a/tests/ui/abi/numbers-arithmetic/return-float.rs b/tests/ui/abi/numbers-arithmetic/return-float.rs index 3b025b763f1..66a6d66911d 100644 --- a/tests/ui/abi/numbers-arithmetic/return-float.rs +++ b/tests/ui/abi/numbers-arithmetic/return-float.rs @@ -4,50 +4,54 @@ // Test that floats (in particular signalling NaNs) are losslessly returned from functions. fn main() { - let bits_f32 = std::hint::black_box([ - 4.2_f32.to_bits(), - f32::INFINITY.to_bits(), - f32::NEG_INFINITY.to_bits(), - f32::NAN.to_bits(), - // These two masks cover all the mantissa bits. One of them is a signalling NaN, the other - // is quiet. - // Similar to the masks in `test_float_bits_conv` in library/std/src/f32/tests.rs - f32::NAN.to_bits() ^ 0x002A_AAAA, - f32::NAN.to_bits() ^ 0x0055_5555, - // Same as above but with the sign bit flipped. - f32::NAN.to_bits() ^ 0x802A_AAAA, - f32::NAN.to_bits() ^ 0x8055_5555, - ]); - for bits in bits_f32 { - assert_eq!(identity(f32::from_bits(bits)).to_bits(), bits); - // Test types that are returned as scalar pairs. - assert_eq!(identity((f32::from_bits(bits), 42)).0.to_bits(), bits); - assert_eq!(identity((42, f32::from_bits(bits))).1.to_bits(), bits); - let (a, b) = identity((f32::from_bits(bits), f32::from_bits(bits))); - assert_eq!((a.to_bits(), b.to_bits()), (bits, bits)); - } + // FIXME(#114479): LLVM miscompiles loading and storing `f32` and `f64` when SSE is disabled on + // x86. + if cfg!(not(all(target_arch = "x86", not(target_feature = "sse2")))) { + let bits_f32 = std::hint::black_box([ + 4.2_f32.to_bits(), + f32::INFINITY.to_bits(), + f32::NEG_INFINITY.to_bits(), + f32::NAN.to_bits(), + // These two masks cover all the mantissa bits. One of them is a signalling NaN, the + // other is quiet. + // Similar to the masks in `test_float_bits_conv` in library/std/src/f32/tests.rs + f32::NAN.to_bits() ^ 0x002A_AAAA, + f32::NAN.to_bits() ^ 0x0055_5555, + // Same as above but with the sign bit flipped. + f32::NAN.to_bits() ^ 0x802A_AAAA, + f32::NAN.to_bits() ^ 0x8055_5555, + ]); + for bits in bits_f32 { + assert_eq!(identity(f32::from_bits(bits)).to_bits(), bits); + // Test types that are returned as scalar pairs. + assert_eq!(identity((f32::from_bits(bits), 42)).0.to_bits(), bits); + assert_eq!(identity((42, f32::from_bits(bits))).1.to_bits(), bits); + let (a, b) = identity((f32::from_bits(bits), f32::from_bits(bits))); + assert_eq!((a.to_bits(), b.to_bits()), (bits, bits)); + } - let bits_f64 = std::hint::black_box([ - 4.2_f64.to_bits(), - f64::INFINITY.to_bits(), - f64::NEG_INFINITY.to_bits(), - f64::NAN.to_bits(), - // These two masks cover all the mantissa bits. One of them is a signalling NaN, the other - // is quiet. - // Similar to the masks in `test_float_bits_conv` in library/std/src/f64/tests.rs - f64::NAN.to_bits() ^ 0x000A_AAAA_AAAA_AAAA, - f64::NAN.to_bits() ^ 0x0005_5555_5555_5555, - // Same as above but with the sign bit flipped. - f64::NAN.to_bits() ^ 0x800A_AAAA_AAAA_AAAA, - f64::NAN.to_bits() ^ 0x8005_5555_5555_5555, - ]); - for bits in bits_f64 { - assert_eq!(identity(f64::from_bits(bits)).to_bits(), bits); - // Test types that are returned as scalar pairs. - assert_eq!(identity((f64::from_bits(bits), 42)).0.to_bits(), bits); - assert_eq!(identity((42, f64::from_bits(bits))).1.to_bits(), bits); - let (a, b) = identity((f64::from_bits(bits), f64::from_bits(bits))); - assert_eq!((a.to_bits(), b.to_bits()), (bits, bits)); + let bits_f64 = std::hint::black_box([ + 4.2_f64.to_bits(), + f64::INFINITY.to_bits(), + f64::NEG_INFINITY.to_bits(), + f64::NAN.to_bits(), + // These two masks cover all the mantissa bits. One of them is a signalling NaN, the + // other is quiet. + // Similar to the masks in `test_float_bits_conv` in library/std/src/f64/tests.rs + f64::NAN.to_bits() ^ 0x000A_AAAA_AAAA_AAAA, + f64::NAN.to_bits() ^ 0x0005_5555_5555_5555, + // Same as above but with the sign bit flipped. + f64::NAN.to_bits() ^ 0x800A_AAAA_AAAA_AAAA, + f64::NAN.to_bits() ^ 0x8005_5555_5555_5555, + ]); + for bits in bits_f64 { + assert_eq!(identity(f64::from_bits(bits)).to_bits(), bits); + // Test types that are returned as scalar pairs. + assert_eq!(identity((f64::from_bits(bits), 42)).0.to_bits(), bits); + assert_eq!(identity((42, f64::from_bits(bits))).1.to_bits(), bits); + let (a, b) = identity((f64::from_bits(bits), f64::from_bits(bits))); + assert_eq!((a.to_bits(), b.to_bits()), (bits, bits)); + } } } |
