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| author | Tsukasa OI <floss_rust@irq.a4lg.com> | 2025-09-15 02:16:34 +0000 |
|---|---|---|
| committer | Tsukasa OI <floss_rust@irq.a4lg.com> | 2025-09-15 02:16:34 +0000 |
| commit | 5ebdec5ac2908b0bae42adbe451beeadbe8fa5de (patch) | |
| tree | 03efdce305a499f55c7a29990a9cb4a340c4917a | |
| parent | 52618eb338609df44978b0ca4451ab7941fd1c7a (diff) | |
| download | rust-5ebdec5ac2908b0bae42adbe451beeadbe8fa5de.tar.gz rust-5ebdec5ac2908b0bae42adbe451beeadbe8fa5de.zip | |
rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list
Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register in the reference, it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
| -rw-r--r-- | compiler/rustc_codegen_llvm/src/asm.rs | 1 | ||||
| -rw-r--r-- | tests/codegen-llvm/asm/riscv-clobbers.rs | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index 38c1d3b53e8..b79176e9098 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -240,6 +240,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> { } InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => { constraints.extend_from_slice(&[ + "~{fflags}".to_string(), "~{vtype}".to_string(), "~{vl}".to_string(), "~{vxsat}".to_string(), diff --git a/tests/codegen-llvm/asm/riscv-clobbers.rs b/tests/codegen-llvm/asm/riscv-clobbers.rs index e55b6731098..0f235ddcdcc 100644 --- a/tests/codegen-llvm/asm/riscv-clobbers.rs +++ b/tests/codegen-llvm/asm/riscv-clobbers.rs @@ -17,7 +17,7 @@ extern crate minicore; use minicore::*; // CHECK-LABEL: @flags_clobber -// CHECK: call void asm sideeffect "", "~{vtype},~{vl},~{vxsat},~{vxrm}"() +// CHECK: call void asm sideeffect "", "~{fflags},~{vtype},~{vl},~{vxsat},~{vxrm}"() #[no_mangle] pub unsafe fn flags_clobber() { asm!("", options(nostack, nomem)); |