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| author | Kor Nielsen <kor@google.com> | 2023-04-26 23:56:55 -0700 |
|---|---|---|
| committer | Kor Nielsen <kor@google.com> | 2023-04-27 00:22:41 -0700 |
| commit | 08f7e32a6ec132649aee2b586a9356a95320c5d8 (patch) | |
| tree | d329673dfef03e167a479f9141e2d55340f5447a | |
| parent | adaac6b166df57ea5a20d56e4cce503b55aca927 (diff) | |
| download | rust-08f7e32a6ec132649aee2b586a9356a95320c5d8.tar.gz rust-08f7e32a6ec132649aee2b586a9356a95320c5d8.zip | |
Support RISC-V unaligned-scalar-mem target feature
This adds `unaligned-scalar-mem` as an allowed RISC-V target feature. Some RISC-V cores support unaligned access to memory without trapping. On such cores, the compiler could significantly improve code-size and performance when using functions like core::ptr::read_unaligned<u32> by emitting a single load or store instruction with an unaligned address, rather than a long sequence of byte load/store/bitmanip instructions. Enabling the `unaligned-scalar-mem` target feature allows LLVM to do this optimization. Fixes #110883
| -rw-r--r-- | compiler/rustc_codegen_ssa/src/target_features.rs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs index 611dd3d1cd1..df3d0811879 100644 --- a/compiler/rustc_codegen_ssa/src/target_features.rs +++ b/compiler/rustc_codegen_ssa/src/target_features.rs @@ -252,6 +252,7 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[ ("f", Some(sym::riscv_target_feature)), ("m", Some(sym::riscv_target_feature)), ("relax", Some(sym::riscv_target_feature)), + ("unaligned-scalar-mem", Some(sym::riscv_target_feature)), ("v", Some(sym::riscv_target_feature)), ("zba", Some(sym::riscv_target_feature)), ("zbb", Some(sym::riscv_target_feature)), |