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| author | Augie Fackler <augie@google.com> | 2024-04-17 15:05:29 -0400 |
|---|---|---|
| committer | Augie Fackler <augie@google.com> | 2024-04-17 16:15:24 -0400 |
| commit | 22b704bac4779d773cf9e641c0b0c3e17352dc3a (patch) | |
| tree | 11aca638f7aac38fb30025d3137022d0c5058ea4 | |
| parent | 00ed4edb44ccc76d8cc992ef9f9f4634ea6d0e82 (diff) | |
| download | rust-22b704bac4779d773cf9e641c0b0c3e17352dc3a.tar.gz rust-22b704bac4779d773cf9e641c0b0c3e17352dc3a.zip | |
llvm: update riscv target feature to match LLVM 19
In llvm/llvm-project@9067070d91e9d8cdd8509ffa56a076f08a3d7281 they ended up largely reverting llvm/llvm-project@e81796671890b59c110f8e41adc7ca26f8484d20. This means the change we did in rust-lang/rust@b378059e6b2573c5356423fa31d184a89a3b6029 is now only corrct for LLVM 18...so we have to adjust again. @rustbot label: +llvm-main
| -rw-r--r-- | compiler/rustc_codegen_llvm/src/llvm_util.rs | 7 | ||||
| -rw-r--r-- | compiler/rustc_target/src/target_features.rs | 2 | ||||
| -rw-r--r-- | tests/ui/abi/riscv-discoverability-guidance.rs | 4 | ||||
| -rw-r--r-- | tests/ui/check-cfg/well-known-values.stderr | 2 |
4 files changed, 8 insertions, 7 deletions
diff --git a/compiler/rustc_codegen_llvm/src/llvm_util.rs b/compiler/rustc_codegen_llvm/src/llvm_util.rs index c9e62e504ae..5552b381025 100644 --- a/compiler/rustc_codegen_llvm/src/llvm_util.rs +++ b/compiler/rustc_codegen_llvm/src/llvm_util.rs @@ -270,9 +270,10 @@ pub fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> LLVMFeature<'a> { "sve2-bitperm", TargetFeatureFoldStrength::EnableOnly("neon"), ), - // The unaligned-scalar-mem feature was renamed to fast-unaligned-access. - ("riscv32" | "riscv64", "fast-unaligned-access") if get_version().0 <= 17 => { - LLVMFeature::new("unaligned-scalar-mem") + // In LLVM 18, `unaligned-scalar-mem` was merged with `unaligned-vector-mem` into a single feature called + // `fast-unaligned-access`. In LLVM 19, it was split back out. + ("riscv32" | "riscv64", "unaligned-scalar-mem") if get_version().0 == 18 => { + LLVMFeature::new("fast-unaligned-access") } // For LLVM 18, enable the evex512 target feature if a avx512 target feature is enabled. ("x86", s) if get_version().0 >= 18 && s.starts_with("avx512") => { diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index c003982278e..6b171af47de 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -279,9 +279,9 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Stability)] = &[ ("d", Unstable(sym::riscv_target_feature)), ("e", Unstable(sym::riscv_target_feature)), ("f", Unstable(sym::riscv_target_feature)), - ("fast-unaligned-access", Unstable(sym::riscv_target_feature)), ("m", Stable), ("relax", Unstable(sym::riscv_target_feature)), + ("unaligned-scalar-mem", Unstable(sym::riscv_target_feature)), ("v", Unstable(sym::riscv_target_feature)), ("zba", Stable), ("zbb", Stable), diff --git a/tests/ui/abi/riscv-discoverability-guidance.rs b/tests/ui/abi/riscv-discoverability-guidance.rs index a09a0edba85..1b189d907ba 100644 --- a/tests/ui/abi/riscv-discoverability-guidance.rs +++ b/tests/ui/abi/riscv-discoverability-guidance.rs @@ -2,9 +2,9 @@ //@ revisions: riscv32 riscv64 // //@ [riscv32] needs-llvm-components: riscv -//@ [riscv32] compile-flags: --target=riscv32i-unknown-none-elf -C target-feature=-fast-unaligned-access --crate-type=rlib +//@ [riscv32] compile-flags: --target=riscv32i-unknown-none-elf -C target-feature=-unaligned-scalar-mem --crate-type=rlib //@ [riscv64] needs-llvm-components: riscv -//@ [riscv64] compile-flags: --target=riscv64gc-unknown-none-elf -C target-feature=-fast-unaligned-access --crate-type=rlib +//@ [riscv64] compile-flags: --target=riscv64gc-unknown-none-elf -C target-feature=-unaligned-scalar-mem --crate-type=rlib #![no_core] #