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authorGuillaume Gomez <guillaume1.gomez@gmail.com>2022-09-09 15:36:36 +0200
committerGitHub <noreply@github.com>2022-09-09 15:36:36 +0200
commit3ec332fc82596e7f80311fa142035945729ce156 (patch)
tree7efe2a2b762a2ee61b14586a3ee3444b383d5a3c
parent6102ff18aedd16f69b66fe313e1dc77df254ac35 (diff)
parentd8b382105f1cb6faeb7e500481720d3433bf87ae (diff)
downloadrust-3ec332fc82596e7f80311fa142035945729ce156.tar.gz
rust-3ec332fc82596e7f80311fa142035945729ce156.zip
Rollup merge of #101495 - bjorn3:pause-no-sse2, r=Mark-Simulacrum
Compile spin_loop_hint as pause on x86 even without sse2 enabled

The x86 `pause` instruction was introduced with sse2, but because it is encoded as `rep nop`, it works just fine on cpu's without sse2 support. It just doesn't do anything.
-rw-r--r--library/core/src/hint.rs19
1 files changed, 8 insertions, 11 deletions
diff --git a/library/core/src/hint.rs b/library/core/src/hint.rs
index 20340d42962..764e2796202 100644
--- a/library/core/src/hint.rs
+++ b/library/core/src/hint.rs
@@ -160,19 +160,16 @@ pub const unsafe fn unreachable_unchecked() -> ! {
 #[inline]
 #[stable(feature = "renamed_spin_loop", since = "1.49.0")]
 pub fn spin_loop() {
-    #[cfg(all(any(target_arch = "x86", target_arch = "x86_64"), target_feature = "sse2"))]
+    #[cfg(target_arch = "x86")]
     {
-        #[cfg(target_arch = "x86")]
-        {
-            // SAFETY: the `cfg` attr ensures that we only execute this on x86 targets.
-            unsafe { crate::arch::x86::_mm_pause() };
-        }
+        // SAFETY: the `cfg` attr ensures that we only execute this on x86 targets.
+        unsafe { crate::arch::x86::_mm_pause() };
+    }
 
-        #[cfg(target_arch = "x86_64")]
-        {
-            // SAFETY: the `cfg` attr ensures that we only execute this on x86_64 targets.
-            unsafe { crate::arch::x86_64::_mm_pause() };
-        }
+    #[cfg(target_arch = "x86_64")]
+    {
+        // SAFETY: the `cfg` attr ensures that we only execute this on x86_64 targets.
+        unsafe { crate::arch::x86_64::_mm_pause() };
     }
 
     // RISC-V platform spin loop hint implementation